A multi-stage interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure and a preparation method thereof

Abstract

This invention discloses a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure and its fabrication method. The sensing structure, from the center outwards, includes a mass block, a cantilever beam, and an outer frame. The mass block and outer frame are concentrically arranged and connected by the hexagonal cantilever beam. The cantilever beam structure, from top to bottom, consists of a passivation layer, an upper electrode layer, a piezoelectric layer, a lower electrode layer, an insulating layer, an upper silicon layer, and a buried oxide layer, and is centrally symmetrically distributed. Gaps and partitions are etched into the lower electrode layer, piezoelectric layer, and upper electrode layer at the two connection ends and the middle position of the cantilever beam, forming multiple independent piezoelectric sensing units. The electrodes of each piezoelectric sensing unit are connected to external leads to achieve differential interconnection of the output charges of multiple sensing units. This invention enhances stress concentration at the cantilever beam connection ends through the hexagonal cantilever beam structure design and introduces structural partitioning to divide multiple piezoelectric sensing units and connect them in series, significantly improving output sensitivity.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano manufacturing and advanced sensing, specifically relating to a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure and its fabrication method. Background Technology

[0002] Health maintenance based on vibration monitoring data is an important means of fault diagnosis and preventive maintenance of mechanical equipment. As the core sensing component of vibration monitoring, vibration sensors have higher requirements for their performance in order to meet the application needs of complex and harsh environments.

[0003] Currently, mechanical equipment fault diagnosis mostly employs traditional bulk vibration sensors. However, bulk vibration sensors suffer from drawbacks such as large size, low integration, high power consumption, and limited anti-interference capabilities, restricting their application in large-scale, distributed, and highly interference-prone monitoring scenarios. With the continuous advancement of Micro-Electro-Mechanical Systems (MEMS) technology, miniature vibration sensors, with their advantages of miniaturization, low power consumption, high integration, and mass production, have become an important development direction in the field of fault diagnosis, providing a crucial technological pathway for the next generation of high-performance vibration sensors. Among them, piezoelectric MEMS vibration sensors, characterized by high reliability, excellent high-frequency response, and self-powered operation, can accurately capture weak vibration signals across a wide frequency range, providing a solution for achieving high-precision, high-reliability, and low-power vibration monitoring.

[0004] The performance of piezoelectric MEMS vibration sensors depends on their micro / nano structures and piezoelectric materials. The micro / nano structures of piezoelectric MEMS vibration sensors are mainly divided into cantilever beam-mass structures and annular diaphragm structures. The cantilever beam-mass structure allows for control of output performance by adjusting the number and shape of the cantilever beams and the electrode connection method, offering advantages such as high sensitivity and structural diversity. However, its fabrication process is relatively complex, and its structural stiffness is poor. The annular diaphragm structure offers advantages such as simple structure, high stiffness, and simple fabrication process, but its energy harvesting efficiency is lower. On the other hand, the piezoelectric materials commonly used in piezoelectric MEMS vibration sensors mainly include lead zirconate titanate, zinc oxide, and aluminum nitride. Lead zirconate titanate has a large piezoelectric coefficient, but its poor compatibility with MEMS processes and the presence of lead in its material system limit its application. Zinc oxide has advantages such as low loss and good compatibility with MEMS processes, but it may cause a shielding effect that leads to a decrease in the material's piezoelectric performance. Compared with lead zirconate titanate and zinc oxide, aluminum nitride has a smaller piezoelectric coefficient, but its piezoelectric coefficient can be significantly improved by doping with an appropriate amount of scandium. In addition, aluminum nitride also has advantages such as low dielectric loss, good temperature stability, and good compatibility with MEMS processes, showing great application prospects.

[0005] Despite significant progress in research on piezoelectric MEMS vibration sensors, their miniaturization limitations still present bottlenecks in areas such as high-frequency sensitivity, adaptability to complex environments, and long-term service stability. Therefore, developing piezoelectric MEMS vibration sensors with high sensitivity, wide bandwidth, and high environmental robustness through structural design and electrode layout optimization is of great importance. Summary of the Invention

[0006] To address the problems existing in the prior art, the purpose of this invention is to provide a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure and its fabrication method. This invention employs a hexagonal cantilever beam structure to suspend and support the mass block, increasing stress concentration at the cantilever beam connection points and thus enhancing the piezoelectric effect. Furthermore, the invention utilizes a structural partition design to increase the number of electrodes, and differential series connection of electrode leads enables the superposition of the potentials of all electrodes, increasing output sensitivity.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure includes an SOI substrate. A functional heterogeneous layer is disposed on the surface of the SOI substrate. The functional heterogeneous layer includes an insulating layer, a lower electrode layer, a piezoelectric layer, an upper electrode layer, and a passivation layer sequentially disposed on the upper silicon surface of the SOI substrate. The overall structure formed by the SOI substrate and the functional heterogeneous layer has a mass block, a cantilever beam, and an outer frame arranged sequentially from the center outwards. The mass block and the outer frame are concentrically arranged. Each side of the mass block is connected to the outer frame through the cantilever beam. The cantilever beam is hexagonal in shape, with a pair of opposite sides connected to both the mass block and the outer frame. The overall thickness of the mass block and the outer frame includes the thickness of the functional heterogeneous layer and... The SOI substrate and the cantilever beam have an overall thickness including the functional heterogeneous layer, the buried oxide layer of the SOI substrate, and the upper silicon layer. The end of the cantilever beam connected to the mass block and the end connected to the outer frame are provided with gaps that penetrate the lower electrode layer, the piezoelectric layer, and the upper electrode layer. The middle position of the cantilever beam has a partition gap that penetrates the lower electrode layer, the piezoelectric layer, and the upper electrode layer in a direction parallel to the gap. In the cantilever beam, the two partitions in the lower electrode layer (i.e., the lower outer electrode 7-1 and the lower inner electrode 7-2) and the two partitions in the upper electrode layer (i.e., the upper outer electrode 9-1 and the upper inner electrode 9-2) are connected to the corresponding pads of each partition through electrode leads. The pads are set on the passivation layer.

[0008] Preferably, the mass block is a regular hexagon, the outer frame is a square, and a pair of opposite sides of the mass block and the outer frame are parallel.

[0009] Preferably, the cantilever beam is a hexagon formed by the lower bases of two congruent isosceles trapezoids joined together, with the gap along the upper edge of the two congruent isosceles trapezoids and the partition gap along the lower edge of the two congruent isosceles trapezoids.

[0010] Preferably, the width of the gap is 4-6 μm.

[0011] Preferably, in the thickness direction of the cantilever beam, the partition gap includes a narrow partition gap and a wide partition gap, wherein the width of the narrow partition gap is smaller than the width of the wide partition gap, wherein the narrow partition gap penetrates the lower electrode layer and the piezoelectric layer, and the wide partition gap penetrates the upper electrode layer.

[0012] Preferably, the width of the narrow partition gap is 9-11 μm, and the width of the wide partition gap is 65-75 μm.

[0013] Preferably, in the cantilever beam, the lower electrode layer between the partition gap and the gap near the outer frame is designated as the lower outer electrode, the lower electrode layer between the partition gap and the gap near the mass block is designated as the lower inner electrode, the upper electrode layer between the partition gap and the gap near the outer frame is designated as the upper outer electrode, and the upper electrode layer between the partition gap and the gap near the mass block is designated as the upper inner electrode. The passivation layer surface is provided with lower outer electrode lead pads connected to the lower outer electrode, lower inner electrode lead pads connected to the lower inner electrode, and upper outer electrode lead pads connected to the upper outer electrode through a through-hole etching process. The upper layer outer electrode and the lower layer inner electrode lead pad are connected to the upper layer inner electrode. The lower layer outer electrode and the lower layer outer electrode lead pad are connected through the lower layer outer electrode lead. The lower layer inner electrode and the lower layer inner electrode lead pad are connected through the lower layer inner electrode lead. The upper layer outer electrode and the upper layer outer electrode lead pad are connected through the upper layer outer electrode lead. The upper layer inner electrode and the upper layer inner electrode lead pad are connected through the upper layer inner electrode lead. On the upper surface of the passivation layer, the upper layer outer electrode lead, lower layer outer electrode lead, lower layer inner electrode lead and upper layer inner electrode lead corresponding to each cantilever beam are arranged according to the positive and negative polarities of the output charge.

[0014] Preferably, the lower outer electrode leads and the lower inner electrode leads at adjacent positions are differentially connected in series through external lead bonding, and the upper outer electrode leads and the upper inner electrode leads at adjacent positions are differentially connected in series through external lead bonding. A pair of upper outer electrode leads and upper inner electrode leads are reserved for signal output, thereby realizing the superposition of the output potentials of all electrodes.

[0015] Preferably, the piezoelectric layer is an aluminum nitride scandium piezoelectric thin film, wherein the scandium doping amount is 10%-30% of the mass of aluminum nitride, and the piezoelectric layer thickness is 0.5-1.5 μm; the insulating layer and passivation layer material is silicon dioxide, and the insulating layer and passivation layer thickness is 0.2-0.5 μm; the lower electrode layer and upper electrode layer material is molybdenum, and the lower electrode layer and upper electrode layer thickness is 0.15-0.30 μm; the electrode lead material includes a chromium layer and a gold layer, the gold layer is located on the upper surface of the chromium layer, the chromium layer thickness is 25-35 nm, and the gold layer thickness is 0.25-0.35 μm.

[0016] The present invention also provides a method for fabricating a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure as described above, comprising the following steps: Step 1: An insulating layer is prepared sequentially on the SOI substrate using plasma-enhanced chemical deposition, followed by a lower electrode layer, a piezoelectric layer, and an upper electrode layer using magnetron sputtering. Step 2: The upper electrode layer, piezoelectric layer and lower electrode layer are sequentially etched and patterned using spin coating, photolithography and ion beam etching processes to complete the preparation of alignment marks, gaps and partition gaps; Step 3: A passivation layer is prepared using plasma-enhanced chemical deposition. The passivation layer and piezoelectric layer are then etched and patterned using spin coating, photolithography, and ion beam etching processes to complete the fabrication of the upper electrode lead hole and the lower electrode lead hole. The upper electrode lead hole extends to the upper electrode layer, and the lower electrode lead hole extends to the lower electrode layer. Step 4: Electrode leads are fabricated and patterned using spin coating, photolithography, magnetron sputtering, and lift-off processes to form electrode leads and pads; Step 5: Prepare an aluminum thin film as the upper masking layer using magnetron sputtering; Step 6: The upper masking layer, passivation layer, piezoelectric layer, lower electrode layer, insulating layer and upper silicon layer are sequentially etched and patterned using spin coating, photolithography, ion beam etching and inductively coupled plasma etching processes to complete the fabrication of the cantilever beam; Step 7: The silicon substrate and buried oxide layer are etched and patterned on the back side of the SOI substrate using spin coating, photolithography, inductively coupled plasma etching and reactive ion etching processes to complete the fabrication of the mass block and the outer frame; Step 8: Remove the upper masking layer using a wet etching process to obtain the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure.

[0017] The present invention has the following beneficial effects: This invention relates to a multi-level interconnected, highly sensitive piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure. Using an SOI substrate, an insulating layer, a lower electrode layer, a piezoelectric layer, an upper electrode layer, and a passivation layer are sequentially disposed on its surface, forming a functional heterogeneous layer. The sensing structure consists of a mass block, a cantilever beam, and an outer frame arranged concentrically from the center outwards. Each side of the mass block is connected to the outer frame via the hexagonal cantilever beam, and a pair of opposite sides of the cantilever beam are connected to both the mass block and the outer frame. The hexagonal geometry causes the force generated by vibration to concentrate stress at the connection points between the cantilever beam and the mass block / outer frame. Since the piezoelectric conversion efficiency of the piezoelectric layer is positively correlated with the applied stress, this stress concentration effectively enhances the charge separation effect of the piezoelectric layer, thereby improving the chip's ability to capture high-frequency, weak vibration signals. The overall thickness of the cantilever beam includes the functional heterogeneous layer, the buried oxide layer of the SOI substrate, and the upper silicon layer. The overall thickness of the mass block and the outer frame covers the functional heterogeneous layer and the entire SOI substrate. This thickness difference ensures the inertial displacement of the mass block while avoiding insufficient stiffness of the cantilever beam, achieving a balance between sensitivity and structural stability. Simultaneously, gaps penetrating the lower electrode layer, piezoelectric layer, and upper electrode layer are provided at both ends where the cantilever beam connects to the mass block and the outer frame. A partition gap parallel to this gap is also provided in the middle. This structure divides the piezoelectric layer and the upper and lower electrode layers on each cantilever beam into two equal sandwich-structure piezoelectric sensitive units, both located in stress concentration areas. By connecting the respective sections of the lower and upper electrode layers to the pads on the passivation layer via electrode leads, differential series interconnection of the sensitive units can be achieved. This allows the electrical signals generated by each sensitive unit to achieve potential superposition, further improving the chip's output sensitivity. Furthermore, this partition design does not compromise the overall structural integrity of the cantilever beam, ensuring the structural strength of the chip. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1(a) is a schematic diagram of the overall structure of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in an embodiment of the present invention. Figure 1(b) is a cross-sectional view of Figure 1(a); Figure 1(c) is an enlarged view of part A in Figure 1(b); Figure 1(d) is an enlarged view of part B in Figure 1(b); Figure 2This is a flowchart illustrating the fabrication process of a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in an embodiment of the present invention. Figure 3 This is a potential distribution diagram of the vibration sensing unit of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in an embodiment of the present invention. Figure 4 This is a schematic diagram of the electrode connections of a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in an embodiment of the present invention. Figure 5 The figures show a comparison of the structures of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure with those of a rectangular cantilever beam structure and an hourglass-shaped cantilever beam structure in the embodiments of the present invention. (a) is the chip structure diagram corresponding to the hexagonal cantilever beam structure, (b) is the chip structure diagram corresponding to the rectangular cantilever beam structure, and (c) is the chip structure diagram corresponding to the hourglass-shaped cantilever beam structure. Figure 6 The figures above are comparison diagrams of stress distribution of different cantilever beam structures based on the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip with hexagonal cantilever beam structure in the embodiments of the present invention. Among them, (a) is the stress distribution diagram corresponding to the hexagonal cantilever beam, (b) is the stress distribution diagram corresponding to the rectangular cantilever beam structure, and (c) is the stress distribution diagram corresponding to the hourglass-shaped cantilever beam. Figure 7 This is a comparison diagram of the output of a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure with piezoelectric vibration sensing chips based on a rectangular cantilever beam structure and an hourglass-shaped cantilever beam structure in an embodiment of the present invention. Figure 8 This is a comparison diagram of the single-electrode and multi-electrode differential series outputs of a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in an embodiment of the present invention. In the diagram: 1. Mass block, 2. Outer frame, 3. Silicon substrate, 4. Buried oxide layer, 5. Upper silicon layer, 6. Insulating layer, 7. Lower electrode layer, 7-1. Lower outer electrode, 7-2. Lower inner electrode, 8. Piezoelectric layer, 9. Upper electrode layer, 9-1. Upper outer electrode, 9-2. Upper inner electrode, 10. Passivation layer, 11. Upper outer electrode lead, 11-1. Upper outer electrode lead pad, 12. Lower outer electrode lead, 1 2-1-Lower layer outer electrode lead pad, 13-Lower layer inner electrode lead, 13-1-Lower layer inner electrode lead pad, 14-Upper layer inner electrode lead, 14-1-Upper layer inner electrode lead pad, 15-Cantilever beam, 16-Through hole, 17-Gap, 18-Separation gap, 18-1-Narrow separation gap, 18-2-Wide separation gap, 19-Upper electrode lead hole, 20-Lower electrode lead hole, 21-Upper masking layer. Detailed Implementation

[0020] To make the objectives, features, and advantages of the present invention more apparent and easier to understand, the technical solutions adopted in the present invention will be described more clearly and in detail below with reference to the accompanying drawings and embodiments.

[0021] This embodiment is based on a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip with a hexagonal cantilever beam structure, as shown in Figures 1(a)-1(d). It includes an SOI substrate consisting of a silicon substrate 3, a buried oxide layer 4, and an upper silicon layer 5 connected in sequence. The surface of the SOI substrate is provided with a functional heterogeneous layer consisting of an insulating layer 6, a lower electrode layer 7, a piezoelectric layer 8, an upper electrode layer 9, and a passivation layer 10 stacked in sequence. The overall structure formed by the SOI substrate and the functional heterogeneous layer has mass blocks arranged sequentially from the center outwards. 1. Cantilever beam 15 and outer frame 2. Mass block 1 is hexagonal in shape and outer frame 2 is square in shape. Mass block 1 and outer frame 2 are concentrically arranged. A pair of opposite sides of mass block 1 and outer frame 2 are parallel. Each side of mass block 1 is connected to outer frame 2 through a cantilever beam 15 to form six through holes 16. The shape of the six cantilever beams 15 is a hexagon formed by two congruent isosceles trapezoids with their lower bases connected. This ensures the structural rigidity while causing stress concentration at the two connection ends of the cantilever beams 15 in the working state. The overall thickness of the cantilever beam 15 includes the buried oxide layer 4, the upper silicon layer 5, and the functional heterostructure layer, and all the cantilever beams 15 are centrally symmetrically distributed; the silicon substrate 3 located below the cantilever beam 15 in the SOI substrate is a blank area (i.e., the silicon substrate 3 below the cantilever beam 15 needs to be removed, thus making the cantilever beam 15 suspended); the lower electrode layer 7, the piezoelectric layer 8, and the upper electrode layer 9 are etched with gaps 17 and partition gaps 18 at the two connecting ends and the middle position of the cantilever beam 15, respectively. The end of the cantilever beam 15 connected to the mass block 1 and the end connected to the outer frame 2 are provided with gaps 17 penetrating the lower electrode layer 7, the piezoelectric layer 8, and the upper electrode layer 9. The middle position of the cantilever beam 15 is provided with a partition gap 18 penetrating the lower electrode layer 7, the piezoelectric layer 8, and the upper electrode layer 9 in a direction parallel to the gap 17; The lower electrode layer 7 and the upper electrode layer 9 on the cantilever beam 15 are separated by gap 17 and partition gap 18 into a lower outer electrode 7-1, a lower inner electrode 7-2, an upper outer electrode 9-1, and an upper inner electrode 9-2. The lower outer electrode 7-1 is arranged on the cantilever beam 15 near the connection end of the outer frame 2, and the lower inner electrode 7-2 is arranged on the cantilever beam 15 near the connection end of the mass block 1. The polarization charge polarities of the lower outer electrode 7-1 and the lower inner electrode 7-2 are opposite. The upper outer electrode 9-1 is arranged on the cantilever beam 15 near the connection end of the outer frame 2, and the upper inner electrode 9-2 is arranged on the cantilever beam 15 near the connection end of the mass block 1. The polarization charge polarities of the upper outer electrode 9-1 and the upper inner electrode 9-2 are opposite, and the polarization charge polarities of the upper outer electrode 9-1 and the lower inner electrode 7-2 are the same.Referring to Figures 1(b)-1(d), the surface of the passivation layer 10 is provided with an upper external electrode lead 11 connected to the upper external electrode 9-1, a lower external electrode lead 12 connected to the lower external electrode 7-1, a lower internal electrode lead 13 connected to the lower internal electrode 7-2, and an upper internal electrode lead 14 connected to the upper internal electrode 9-2, arranged according to the polarity of the output charge being one positive and one negative. The lower external electrode lead 12 and the lower internal electrode lead 13 at adjacent positions are differentially connected in series through external lead bonding, and the upper external electrode lead 14 at adjacent positions is connected in series. The external electrode lead 11 and the upper inner electrode lead 14 are differentially connected in series through external lead bonding, and a pair of upper external electrode leads 11 and upper inner electrode leads 14 are reserved for signal output to realize the superposition of the output potential of all electrodes; the passivation layer 10 is also provided with upper external electrode lead pads 11-1, lower external electrode lead pads 12-1, lower inner electrode lead pads 13-1 and upper inner electrode lead pads 14-1 respectively connected to the upper external electrode lead 11, lower external electrode lead 12, lower inner electrode lead 13 and upper inner electrode lead 14.

[0022] As a preferred embodiment of the above scheme, in this embodiment, the six cantilever beams 15 are connected to the middle of the six sides of the mass block 1 and are arranged in a centrally symmetrical manner, which not only enhances the structural rigidity but also reduces lateral interference.

[0023] As a preferred embodiment of the above solution, in this embodiment, the gap 17 is provided along the upper base edge of two congruent isosceles trapezoids, and the width of the gap 17 is 4-6μm.

[0024] As a preferred embodiment of the above solution, in this embodiment, the partition gap 18 is set along the lower base edge of two congruent isosceles trapezoids. Each partition gap 18 consists of a narrow partition gap 18-1 that separates the lower electrode layer 7 and the piezoelectric layer 8 and a wide partition gap 18-2 that separates the upper electrode layer 9. This structural design prevents charge neutralization from occurring inside the lower electrode layer 7 and the upper electrode layer 9. The width of the narrow partition gap 18-1 is 9-11 μm, and the width of the wide partition gap 18-2 is 65-75 μm.

[0025] As a preferred embodiment of the above scheme, in this embodiment, the upper outer electrode lead 11 and the upper inner electrode lead 14 are connected to the upper outer electrode 9-1 and the upper inner electrode 9-2 respectively through the upper electrode lead hole 19, and the lower outer electrode lead 12 and the lower inner electrode lead 13 are connected to the lower outer electrode 7-1 and the lower inner electrode 7-2 respectively through the lower electrode lead hole 20. On the upper surface of the passivation layer 10, the upper outer electrode lead 11, the lower outer electrode lead 12, the lower inner electrode lead 13 and the upper inner electrode lead 14 are arranged in a positive and a negative polarity according to the output charge, and are arranged around the outer frame 2.

[0026] As a preferred embodiment of the above scheme, in this embodiment, the lower outer electrode lead 12 and the lower inner electrode lead 13 at adjacent positions are differentially connected in series through external lead bonding, and the upper outer electrode lead 11 and the upper inner electrode lead 14 at adjacent positions are differentially connected in series through external lead bonding. A pair of upper outer electrode leads 11 and upper inner electrode leads 14 are reserved for signal output, thereby realizing the superposition of the output potentials of all electrodes.

[0027] As a preferred embodiment of the above scheme, in this embodiment, the piezoelectric layer 8 is made of aluminum nitride scandium piezoelectric thin film and prepared by magnetron sputtering process. The scandium doping amount is 10%-30% of the mass of aluminum nitride, which makes the relative permittivity of the piezoelectric layer 8 change little while obtaining a higher piezoelectric coefficient, significantly improving the electromechanical coupling coefficient of the piezoelectric layer 8. The thickness of the piezoelectric layer 8 is 0.5-2 μm.

[0028] As a preferred embodiment of the above scheme, in this embodiment, the insulating layer 6 and the passivation layer 10 are made of silicon dioxide, and the thickness of the insulating layer 6 and the passivation layer 10 is 0.2-0.5 μm; the lower electrode layer 7 and the upper electrode layer 9 are made of molybdenum, and the thickness of the lower electrode layer 7 and the upper electrode layer 9 is 0.15-0.30 μm; the electrode lead material is a chromium / gold composite material, including a chromium layer and a gold layer, with the gold layer located on the upper surface of the chromium layer, the thickness of the chromium layer being 25-35 nm, and the thickness of the gold layer being 0.25-0.35 μm.

[0029] As a preferred option of the above scheme, refer to Figure 3 and Figure 4 Under load, the two connecting ends of the cantilever beam 15 exhibit a positive and negative potential distribution. The lower outer electrode 7-1, the lower inner electrode 7-2, the upper outer electrode 9-1, and the upper inner electrode 9-2 collect the charge generated by the piezoelectric layer 8 and form twelve sandwich-structured piezoelectric output sensitive units on the six cantilever beams 15. Through the electrode lead layout with alternating polarity and the differential series lead connection method, the potentials of each electrode can be superimposed and output to improve the output sensitivity.

[0030] As a preferred option of the above scheme, refer to Figure 5 and Figure 6 Compared with two other piezoelectric vibration sensing chips with the same cantilever beam area 15, the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on the hexagonal cantilever beam structure of this invention has a more prominent stress concentration effect at the connection end of the hexagonal cantilever beam 15, thus enhancing the piezoelectric effect.

[0031] Reference Figure 2The fabrication method of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure provided in the above embodiments of the present invention includes the following steps: Step 1: On the surface of the SOI substrate, an insulating layer 6 is prepared sequentially using plasma-enhanced chemical deposition, and a lower electrode layer 7, a piezoelectric layer 8, and an upper electrode layer 9 are prepared using magnetron sputtering. Step 2: The upper electrode layer 9, piezoelectric layer 8 and lower electrode layer 7 are sequentially etched and patterned using a homogenization, photolithography and ion beam etching process to complete the preparation of alignment marks, gaps 17 and partition gaps 18, and to form the lower outer electrode 7-1, lower inner electrode 7-1, upper outer electrode 9-1 and upper inner electrode 9-2. Step 3: A passivation layer 10 is prepared using plasma-enhanced chemical deposition to protect the upper electrode layer 9 from oxidation. The passivation layer 10 and the piezoelectric layer 8 are then etched and patterned using a spin coating, photolithography, and ion beam etching process to complete the fabrication of the upper electrode lead hole 19 and the lower electrode lead hole 20. The upper electrode lead hole 19 extends to the upper electrode layer 9, and the lower electrode lead hole 20 extends to the lower electrode layer 7. Step 4: Electrode leads are fabricated and patterned using a process of homogenization, photolithography, magnetron sputtering and lift-off to form an upper outer electrode lead 11, a lower outer electrode lead 12, a lower inner electrode lead 13 and an upper inner electrode lead 14. Step 5: An aluminum thin film is prepared using magnetron sputtering as the upper masking layer 21 for front structure protection; Step 6: The upper masking layer 21, passivation layer 10, piezoelectric layer 8, lower electrode layer 7, insulating layer 6 and upper silicon layer 5 are sequentially etched and patterned using homogenization, photolithography, ion beam etching and inductively coupled plasma etching processes to complete the fabrication of the cantilever beam 15. Step 7: The silicon substrate 3 and buried oxide layer 4 are etched and patterned on the back side of the SOI substrate using spin coating, photolithography, inductively coupled plasma etching and reactive ion etching processes to complete the fabrication of mass block 1 and outer frame 2. Step 8: Remove the upper masking layer 21 using a wet etching process to obtain the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure.

[0032] As a preferred option of the above scheme, refer to Figure 2 In the fabrication process of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure, after the patterned deposition of electrode leads is completed, a layer of aluminum is deposited on the upper surface of the structure for masking and protection, thereby improving the processing yield.

[0033] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application are described clearly and completely. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments.

[0034] Example As shown in Figure 1, this embodiment is based on a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip with a hexagonal cantilever beam structure. It adopts a hexagonal cantilever beam structure and structural isolation design. By enhancing stress concentration and differentially connecting the electrodes in series, the superposition output of the potentials of each electrode is realized, which significantly improves the output sensitivity.

[0035] Specifically, the mass block 1 and the outer frame 2 are formed by stacking a silicon substrate 3, a buried oxide layer 4, an upper silicon layer 5, an insulating layer 6, a lower electrode layer 7, a piezoelectric layer 8, an upper electrode layer 9, and a passivation layer 10. The mass block 1 has a regular hexagonal shape, and the outer frame 2 has a square shape. The side length of the mass block 1 is 420 μm, and the side length of the outer frame 2 is 2400 μm.

[0036] An insulating layer 6 is placed between the upper silicon layer 5 and the lower electrode layer 7 to block charge transfer between them. Considering that silicon dioxide has good adhesion to the upper silicon layer 5 and is insulating, the insulating layer 6 is preferably made of silicon dioxide and has a thickness of 0.3 μm.

[0037] The lower electrode layer 7 is placed between the insulating layer 6 and the piezoelectric layer 8, and includes a lower outer electrode 7-1 and a lower inner electrode 7-2, used to collect the charge on the lower surface of the piezoelectric layer 8. Considering the high lattice matching degree of molybdenum and scandium aluminum nitride, which can promote the high-quality growth of scandium aluminum nitride, the material of the lower electrode layer 7 is preferably molybdenum, with a thickness of 0.2 μm.

[0038] The piezoelectric layer 8 is positioned between the lower electrode layer 7 and the upper electrode layer 9, serving as the main functional layer of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure of this invention. Considering that doping aluminum nitride with scandium can improve the piezoelectric properties of the material, and that the fabrication of aluminum nitride scandium has high compatibility with MEMS processes, aluminum nitride scandium is preferably used as the material for the piezoelectric layer 8, with a thickness of 1 μm.

[0039] The upper electrode layer 9 is positioned between the piezoelectric layer 8 and the passivation layer 10, and includes an upper outer electrode 9-1 and an upper inner electrode 9-2, used to collect the charge on the upper surface of the piezoelectric layer 8. Considering the high lattice matching degree between molybdenum and scandium aluminum nitride, the upper electrode layer 9 is preferably made of molybdenum with a thickness of 0.2 μm.

[0040] A passivation layer 10 is placed on the upper surface of the upper electrode layer 9 to protect the upper electrode layer 9 from oxidation. Considering that silicon dioxide has good adhesion to molybdenum and a good passivation effect, the material of the passivation layer 10 is preferably silicon dioxide, with a thickness of 0.3 μm.

[0041] The upper external electrode lead 11, lower external electrode lead 12, lower internal electrode lead 13, and upper internal electrode lead 14 are arranged alternately on the upper surface of the passivation layer 10 according to the output polarity of positive and negative. They are connected to the upper electrode layer 9 and the lower electrode layer 7 through the upper electrode lead hole 19 and the lower electrode lead hole 20, so that the electrical signals of the upper external electrode 9-1, lower external electrode 7-1, lower internal electrode 7-2, and upper internal electrode 9-2 can be interconnected for output. Considering the high conductivity of gold and the adhesion of chromium, the materials of the upper external electrode lead 11, lower external electrode lead 12, lower internal electrode lead 13, and upper internal electrode lead 14 are preferably chromium and gold, with thicknesses of 30 nm (chromium) and 0.3 μm (gold), respectively.

[0042] The cantilever beam 15 is a hexagon formed by two identical isosceles trapezoids with their lower bases joined together. Considering the stress concentration of the reinforcement structure, the width of the two ends of the cantilever beam 15 is 252 μm, the width of the waist is 420 μm, and the length is 270 μm.

[0043] The gap 17 is used to separate the lower electrode layer 7, the piezoelectric layer 8 and the upper electrode layer 9 on the cantilever beam 15 to improve energy harvesting efficiency, and its width is 5 μm.

[0044] The partition gap 18 is used to divide the lower electrode layer 7, piezoelectric layer 8 and upper electrode layer 9 on the cantilever beam 15 into two equal parts to prevent charge neutralization. The width of the narrow gap 18-1 is 10 μm, and the width of the wide gap 18-2 is 70 μm.

[0045] like Figure 5 The diagram shows a structural comparison of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure of the present invention, and piezoelectric vibration sensing chips with similar structural dimensions based on rectangular and hourglass cantilever beam structures. The cantilever beams 15 of the three piezoelectric vibration sensing chips are hexagonal, rectangular, and hourglass-shaped, respectively, and have the same area. Figure 7 The diagram shows a comparison of the output of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in this embodiment, compared with piezoelectric vibration sensing chips based on rectangular and hourglass cantilever beam structures. The output voltage sensitivity of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on the hexagonal cantilever beam structure in this embodiment is 3.39 mV / g@5 kHz, the output voltage sensitivity of the piezoelectric vibration sensing chip based on the rectangular cantilever beam structure is 3.09 mV / g@5 kHz, and the output voltage sensitivity of the piezoelectric vibration sensing chip based on the hourglass cantilever beam structure is 2.86 mV / g@5 kHz. The comparison shows that the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on the hexagonal cantilever beam structure in this embodiment has superior output performance.

[0046] like Figure 8 As shown, in this embodiment, the single-electrode output voltage sensitivity of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure is 0.3mV / g@5kHz, and the multi-electrode differential series output voltage sensitivity is 3.39mV / g@5kHz. The comparison shows that the multi-electrode differential series configuration can effectively improve the chip's output sensitivity.

[0047] The performance parameters of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in this embodiment are as follows: a. Measurement range: 60g; b. Measurement accuracy: better than 5%FS; c. Operating bandwidth: 0.5~10kHz; d. Impact resistance: 5000g.

[0048] The working principle of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in this embodiment is as follows: During vibration monitoring, the lower end face of the outer frame 2 is installed perpendicular to the vibration direction of the device under test, and the mass block 1 is suspended and vibrates along with the device under test. Under the action of inertial force, the cantilever beam 15 undergoes bending strain and excites the piezoelectric layer 8 to generate a piezoelectric effect, generating polarization charges on the upper and lower surfaces of the piezoelectric layer 8. The lower outer electrode 7-1, the lower inner electrode 7-2, the upper outer electrode 9-1, and the upper inner electrode 9-2 are arranged on the surface of the piezoelectric layer 8 to collect the polarization charges, and output them differentially in series through the lower outer electrode lead 12, the lower inner electrode lead 13, the upper outer electrode lead 11, and the upper inner electrode lead 14. There is a corresponding relationship between the chip's output voltage and the vibration acceleration, thereby realizing real-time monitoring of the device's vibration state.

[0049] like Figure 2 The diagram shows the fabrication process flow of a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in an embodiment of the present invention. The detailed fabrication steps are as follows: Step a, Prepare SOI wafer: Use a 4-inch N-type 100 crystal double-sided polished SOI wafer. The resistivity of the upper silicon layer 5 is 1-10 Ω·cm and the thickness is 15±0.5 μm. The thickness of the buried oxide layer 4 is 1 μm. The resistivity of the silicon substrate 3 is 1-10 Ω·cm and the thickness is 475±10 μm. The total thickness of the SOI wafer is 501±10.5 μm. Step b, Preparation of silicon dioxide insulating layer 6: The surface impurities of the SOI wafer are removed by ultrasonication for 5 min in sequence with acetone, anhydrous ethanol and deionized water. The water stains remaining on the surface of the SOI wafer are dried with a nitrogen gun and dried at 120℃ for 10 min. Then, a 0.3 μm thick silicon dioxide film is grown on the upper surface of the upper silicon layer 5 of the SOI wafer as the insulating layer 6 of the wafer by plasma-enhanced chemical deposition process. The film growth rate is 1.75 nm / s and the growth environment temperature is 300℃. Step c, Preparation of molybdenum lower electrode layer 7: A 0.2 μm thick layer of molybdenum is grown on the upper surface of the insulating layer 6 using a magnetron sputtering process as the lower electrode layer 7 of the wafer; Step d: Preparation of aluminum scandium nitride piezoelectric layer 8: A 1 μm thick aluminum scandium nitride is deposited on the upper surface of the lower electrode layer 7 as the piezoelectric layer 8 of the wafer using a magnetron sputtering process; Step e: Fabrication and patterning of the molybdenum upper electrode layer 9: A 0.2 μm thick molybdenum layer is deposited on the upper surface of the piezoelectric layer 8 using magnetron sputtering as the upper electrode layer 9 of the wafer. A layer of AZ4620 photoresist (positive photoresist) is spin-coated onto the upper electrode layer 9 at a low speed of 500 rpm for 5 s and a high speed of 3000 rpm for 50 s, followed by soft baking at 120℃ for 10 min. Then, the wafer is exposed to light using the first mask (negative mask) for 15 s, transferred to a 0.73% sodium hydroxide developer solution, rinsed with deionized water, dried with a nitrogen gun, and hardened at 120℃ for 10 min to complete the development and pattern transfer. Finally, the 0.2 μm upper electrode layer 9 is etched and patterned using an ion beam etching process to form alignment marks, the upper outer electrode 9-1, and the upper inner electrode 9-2. Step f, Preparation of alignment marks, gap 17 and partition slit 18: Spin-coat a layer of AZ4620 photoresist (positive photoresist) on the upper surface of the wafer, set the rotation speed to low speed 500 rpm for 5 s, high speed 3000 rpm for 50 s, and soft bake at 120℃ for 10 min; then use a second mask (negative mask) for photolithography exposure for 10 s, transfer to 0.73% sodium hydroxide developer and soak for 40 s, clean with deionized water, blow dry the surface water stains of the wafer with a nitrogen gun, and harden at 120℃ for 10 min to complete the development pattern transfer; finally, use ion beam etching process to etch a 1 μm piezoelectric layer 8 and a 0.2 μm lower electrode layer 7 on the upper surface of the wafer and pattern them to form the lower outer electrode 7-1, lower inner electrode 7-2, gap 17 and partition slit 18, with an etching rate of 20 nm / min for aluminum scandium nitride and molybdenum; Step g, Preparation of silicon dioxide passivation layer 10: A 0.3 μm thick silicon dioxide film is formed on the upper surface of the wafer by plasma-enhanced chemical deposition as the passivation layer 10 of the wafer to protect the upper electrode layer 9 from oxidation. The film growth rate is 1.75 nm / s and the growth environment temperature is 300℃. Step h, preparing the lead holes: Spin-coating a layer of AZ4620 photoresist (positive photoresist) onto the upper surface of the wafer, setting the spin speed to low speed 500 rpm for 5 s and high speed 3000 rpm for 50 s, and then soft baking at 120℃ for 10 min; then photolithographic exposure using a third mask (negative mask) for 10 s, transferring to 0.73% sodium hydroxide developer and rinsing for 40 s, then rinsing with deionized water, drying the surface water stains of the wafer with a nitrogen gun, and hardening at 120℃ for 10 min to complete the development pattern transfer; finally, etching a 0.3 μm thick silicon dioxide layer on the upper surface of the wafer using ion beam etching process and patterning to form the upper electrode lead hole 19 and the preliminary lower electrode lead hole 20, with a silicon dioxide etching rate of 35.7 nm / min; Step i: Preparation of the lower electrode lead hole 22: Spin-coat a layer of AZ4620 photoresist (positive photoresist) on the upper surface of the wafer, set the rotation speed to low speed 500 rpm for 5 s, high speed 3000 rpm for 50 s, and soft bake at 120℃ for 10 min; then use the fourth mask (negative mask) for photolithography exposure for 10 s, transfer to 0.73% sodium hydroxide developer and soak for 40 s, then clean with deionized water, blow dry the surface water stains of the wafer with a nitrogen gun, and harden at 120℃ for 10 min to complete the development pattern transfer; finally, use ion beam etching process to etch a 1 μm piezoelectric layer 8 on the upper surface of the wafer and pattern it to form a complete lower electrode lead hole 22; Step j: Fabrication of chromium / gold electrode leads: Spin-coat a layer of AZ4620 photoresist (positive resist) onto the upper surface of the wafer, setting the spin speed to low 500 rpm for 5 s and high 3000 rpm for 50 s, and then soft bake at 120℃ for 10 min; then expose using the fifth mask (negative mask) for 10 s, transfer to 0.73% sodium hydroxide developer and soak for 40 s, rinse with deionized water, dry the surface of the wafer with a nitrogen gun, and harden at 120℃ for 10 min to complete the development and pattern transfer; finally, deposit a 0.3 μm thick gold layer on the upper surface of the wafer using magnetron sputtering (using 30... Using chromium metal of nm as the adhesion layer, i.e., first magnetron sputtering a chromium layer with a thickness of 30 nm, and then magnetron sputtering a gold layer with a thickness of 300 nm on the surface of the chromium layer, and then using a stripping process to complete the patterning, forming an upper outer electrode lead 11, a lower outer electrode lead 12, a lower inner electrode lead 13 and an upper inner electrode lead 14. Step k, Preparation of aluminum upper masking layer 21: A 0.4 μm thick aluminum layer is deposited on the upper surface of the wafer using a magnetron sputtering process as the upper masking layer 23 of the device, which is used to protect the front structure in subsequent processes; Step 1: Fabrication of cantilever beam 15: Spin-coat a layer of AZ4620 photoresist (positive photoresist) onto the upper surface of the wafer. Set the spin speed to low speed 500 rpm for 5 s and high speed 3000 rpm for 50 s, and then soft bake at 120℃ for 10 min. Then, use the sixth mask (negative mask) for photolithography exposure for 10 s, transfer to 0.73% sodium hydroxide developer and soak for 40 s. After rinsing with deionized water, dry the surface water stains of the wafer with a nitrogen gun and harden at 120℃ for 10 min to complete the development and pattern transfer. Finally, use ion beam etching to sequentially etch and pattern the upper mask layer 21, passivation layer 10, piezoelectric layer 8, lower electrode layer 7 and insulating layer 6 on the upper surface of the wafer. The etching rate of aluminum is 30 nm / min. Step m, Fabrication of cantilever beam 15: Based on step l, 15μm upper silicon layer 5 is etched and patterned using inductively coupled plasma etching process to complete the fabrication of cantilever beam 15; Step n, Preparation of mass block 1 and outer frame 2: Spin-coat a layer of AZ4620 photoresist (positive resist) on the lower surface of the wafer, with the spin speed set at low speed of 500 rpm for 5 s and high speed of 3000 rpm for 50 s, and then soft bake at 120℃ for 10 min; then use the seventh mask (negative mask) for photolithography exposure for 10 s, transfer to 0.73% sodium hydroxide developer and soak for 40 s, then clean with deionized water and blow dry the surface water stains of the wafer with a nitrogen gun, and harden at 120℃ for 10 min to complete the development and pattern transfer; finally, use inductively coupled plasma etching process to etch and pattern the 475 μm silicon substrate 3 on the lower surface of the wafer to form mass block 1 and outer frame 2; Step o, Preparation of via 16: Spin-coat a layer of AZ4620 photoresist (positive photoresist) on the lower surface of the wafer, setting the spin speed to low speed 500 rpm for 5 s and high speed 3000 rpm for 50 s, and then soft bake at 120℃ for 10 min; then use the 8th mask (negative mask) for photolithography exposure for 10 s, transfer to 0.73% sodium hydroxide developer and soak for 40 s, then clean with deionized water and blow dry the surface water stains of the wafer with a nitrogen gun, and harden at 120℃ for 10 min to complete the development and pattern transfer; finally, use reactive ion etching process to etch a 1 μm buried oxide layer 4 on the lower surface of the wafer and pattern it to form via 16; Step p, Removing the upper masking layer 21: The wafer is placed in an etching solution with a ratio of concentrated phosphoric acid, concentrated nitric acid and water of 16:1:4 and heated in an 80°C water bath. The upper masking layer 21 is removed by wet etching process, thus completing the fabrication of the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure in this embodiment.

[0050] In summary, the embodiments of this invention successfully fabricate a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure. This sensing chip exhibits high output sensitivity, enabling accurate monitoring of weak high-frequency vibration signals. Furthermore, the sensing chip demonstrates excellent temperature stability, making it of significant scientific and practical value for fault monitoring in complex and harsh environments. The multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure employs a structural partition design. Through etching gaps and partition slits, the lower electrode layer, piezoelectric layer, and upper electrode layer on each cantilever beam are divided into two equal parts and superimposed into two sandwich-structured piezoelectric output sensitive units arranged in the stress concentration area of ​​the cantilever beam. Connection via electrode leads allows for the superposition of all electrode potentials, further improving the output performance of the piezoelectric vibration sensing chip of this invention.

[0051] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure, characterized in that, The structure includes an SOI substrate, on the surface of which a functional heterogeneous layer is provided. The functional heterogeneous layer includes an insulating layer (6), a lower electrode layer (7), a piezoelectric layer (8), an upper electrode layer (9), and a passivation layer (10) sequentially disposed on the surface of the upper silicon layer (5) of the SOI substrate. The overall structure formed by the SOI substrate and the functional heterogeneous layer has a mass block (1), a cantilever beam (15), and an outer frame (2) arranged sequentially from the center outward. The mass block (1) and the outer frame (2) are concentrically arranged. Each side of the mass block (1) is connected to the outer frame (2) through the cantilever beam (15). The cantilever beam (15) is hexagonal in shape and a pair of opposite sides are connected to the mass block (1) and the outer frame (2) respectively. The overall thickness of the mass block (1) and the outer frame (2) includes the functional heterogeneous layer. The cantilever beam (15) has an overall thickness including the functional heterogeneous layer, the buried oxide layer (4) of the SOI substrate, and the upper silicon layer (5). The cantilever beam (15) is provided with a gap (17) that penetrates the lower electrode layer (7), the piezoelectric layer (8), and the upper electrode layer (9) at one end connected to the mass block (1) and the other end connected to the outer frame (2). The middle position of the cantilever beam (15) is provided with a partition gap (18) that penetrates the lower electrode layer (7), the piezoelectric layer (8), and the upper electrode layer (9) in a direction parallel to the gap (17). In the cantilever beam (15), the two partitions in the lower electrode layer (7) and the two partitions in the upper electrode layer (9) are connected to the corresponding pads of each partition through electrode leads. The pads are set on the passivation layer (10).

2. The multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure according to claim 1, characterized in that, The mass block (1) is a regular hexagon, and the outer frame (2) is a square. A pair of opposite sides of the mass block (1) and the outer frame (2) are parallel.

3. The multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure according to claim 1, characterized in that, The cantilever beam (15) is a hexagon formed by the lower bases of two congruent isosceles trapezoids joined together. The gap (17) is set along the upper base edge of the two congruent isosceles trapezoids, and the partition gap (18) is set along the lower base edge of the two congruent isosceles trapezoids.

4. A multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure according to claim 1 or 3, characterized in that, The width of the gap (17) is 4-6 μm.

5. A multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure according to claim 1 or 3, characterized in that, In the thickness direction of the cantilever beam (15), the partition gap (18) includes a narrow partition gap (18-1) and a wide partition gap (18-2). The width of the narrow partition gap (18-1) is smaller than the width of the wide partition gap (18-2). The narrow partition gap (18-1) penetrates the lower electrode layer (7) and the piezoelectric layer (8), and the wide partition gap (18-2) penetrates the upper electrode layer (9).

6. A multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure according to claim 5, characterized in that, The width of the narrow partition gap (18-1) is 9-11 μm, and the width of the wide partition gap (18-2) is 65-75 μm.

7. A multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure according to claim 1, characterized in that, In the cantilever beam (15), the lower electrode layer (7) between the partition gap (18) and the gap (17) near the outer frame (2) is denoted as the lower outer electrode (7-1), the lower electrode layer (7) between the partition gap (18) and the gap (17) near the mass block (1) is denoted as the lower inner electrode (7-2), and the upper electrode layer (9) between the partition gap (18) and the gap (17) near the outer frame (2) is denoted as the upper outer electrode (9-1). The upper electrode layer (9) between the partition gap (18) and the gap (17) near the mass block (1) is denoted as the upper inner electrode (9-2). The passivation layer (10) surface is provided with lower outer electrode lead pads (12-1) connected to the lower outer electrode (7-1), lower inner electrode lead pads (13-1) connected to the lower inner electrode (7-2), and upper outer electrode lead pads (9-1) connected to the upper outer electrode (9-1) through a through-hole etching process. The upper layer inner electrode pad (11-1) and the lower layer inner electrode pad (14-1) connected to the upper layer inner electrode (9-2) are connected. The lower layer outer electrode (7-1) and the lower layer outer electrode pad (12-1) are connected through the lower layer outer electrode lead (12). The lower layer inner electrode (7-2) and the lower layer inner electrode pad (13-1) are connected through the lower layer inner electrode lead (13). The upper layer outer electrode (9-1) and the upper layer outer electrode pad (14-1) are connected through the lower layer inner electrode lead (13). 1-1) The upper outer electrode leads (11) are connected, and the upper inner electrode (9-2) and the upper inner electrode lead pad (14-1) are connected through the upper inner electrode lead (14). On the upper surface of the passivation layer (10), the upper outer electrode leads (11), lower outer electrode leads (12), lower inner electrode leads (13) and upper inner electrode leads (14) corresponding to each cantilever beam (15) are arranged in a positive and a negative order according to the polarity of the output charge.

8. A multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure according to claim 7, characterized in that, The lower outer electrode lead (12) and the lower inner electrode lead (13) at adjacent positions are differentially connected in series through external lead bonding. The upper outer electrode lead (11) and the upper inner electrode lead (14) at adjacent positions are differentially connected in series through external lead bonding. A pair of upper outer electrode leads (11) and upper inner electrode leads (14) are reserved for signal output, thereby realizing the superposition of the output potential of all electrodes.

9. A multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure according to claim 1, characterized in that, The piezoelectric layer (8) is made of aluminum nitride scandium piezoelectric film, wherein the scandium doping amount is 10%-30% of the mass of aluminum nitride, and the thickness of the piezoelectric layer (8) is 0.5-1.5μm; the insulating layer (6) and passivation layer (10) are made of silicon dioxide, and the thickness of the insulating layer (6) and passivation layer (10) is 0.2-0.5μm; the lower electrode layer (7) and upper electrode layer (9) are made of molybdenum, and the thickness of the lower electrode layer (7) and upper electrode layer (9) is 0.15-0.30μm; the electrode lead material includes a chromium layer and a gold layer, the gold layer is located on the upper surface of the chromium layer, the thickness of the chromium layer is 25-35nm, and the thickness of the gold layer is 0.25-0.35μm.

10. A method for fabricating a multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure as described in any one of claims 1-9, characterized in that, Includes the following steps: Step 1: An insulating layer (6) is prepared sequentially on the SOI substrate using plasma-enhanced chemical deposition (PECD), followed by a lower electrode layer (7), a piezoelectric layer (8), and an upper electrode layer (9) prepared using magnetron sputtering. Step 2: The upper electrode layer (9), piezoelectric layer (8) and lower electrode layer (7) are sequentially etched and patterned using a homogenization, photolithography and ion beam etching process to complete the preparation of alignment marks, gaps (17) and partition gaps (18); Step 3: A passivation layer (10) is prepared using plasma-enhanced chemical deposition. The passivation layer (10) and the piezoelectric layer (8) are then etched and patterned using a spin coating, photolithography, and ion beam etching process to complete the fabrication of the upper electrode lead hole (19) and the lower electrode lead hole (20). The upper electrode lead hole (19) extends to the upper electrode layer (9), and the lower electrode lead hole (20) extends to the lower electrode layer (7). Step 4: Electrode leads are fabricated and patterned using spin coating, photolithography, magnetron sputtering, and lift-off processes to form electrode leads and pads; Step 5: Prepare an aluminum thin film as the upper masking layer using magnetron sputtering (21); Step 6: The upper masking layer (21), passivation layer (10), piezoelectric layer (8), lower electrode layer (7), insulating layer (6) and upper silicon layer (5) are sequentially etched and patterned using the processes of homogenization, photolithography, ion beam etching and inductively coupled plasma etching to complete the fabrication of the cantilever beam (15); Step 7: The silicon substrate (3) and buried oxide layer (4) are etched and patterned on the back side of the SOI substrate using a process of homogenization, photolithography, inductively coupled plasma etching and reactive ion etching to complete the fabrication of mass block (1) and outer frame (2); Step 8: Remove the upper masking layer (21) using a wet etching process to obtain the multi-level interconnected high-sensitivity piezoelectric vibration sensing chip based on a hexagonal cantilever beam structure.

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