An electric digital processing and identification system for data of an electric energy metering box

Abstract

The application relates to the technical field of electric digital data processing, and discloses an electric digital processing and identification system for electric energy metering box data, which comprises a time sequence feature extraction unit, a dead zone logic unit, a self-referencing difference logic unit, a discrete logic mapping unit and a state machine matching unit.The time sequence feature extraction unit acquires voltage and current sequences and extracts zero-crossing time stamps, and calculates dynamic time differences.The dead zone logic unit compares time intervals with a dead zone time threshold, and outputs an effective time difference sequence.The self-referencing difference logic unit calculates a numerical difference value by using a first sample value stored in a register and a second sample value in a current period, and further determines a discrete difference parameter.The discrete logic mapping unit converts the parameter into a single-byte state code according to a mapping matrix.The state machine matching unit aggregates the state code to generate a sequence array, and outputs an alarm signal by calculating a logical distance.The application eliminates common-mode drift components generated by temperature drift and fundamental frequency fluctuation by using numerical hedging of adjacent periods, improves identification accuracy, reduces calculation power consumption, and ensures monitoring timeliness.

Description

Technical Field

[0001] This invention relates to the field of electrical digital data processing technology, specifically to an electrical digital processing and identification system for electricity metering box data. Background Technology

[0002] Currently, smart nodes on the edge of the power distribution network monitor electricity usage by collecting and processing voltage and current data. The mainstream approach in this field adopts a signal sampling and feature extraction architecture to identify the operating status of equipment based on waveform parameters. However, the deployment environment of edge nodes is subject to electromagnetic interference and temperature differences, causing frequency drift in the underlying clock reference of the microprocessor. At the same time, the base frequency of the power distribution network is affected by load fluctuations and exhibits periodic fluctuations. These factors cause common-mode offset in the feature data extracted based on the absolute time reference, directly affecting the accuracy of anomaly identification. To suppress interference, conventional solutions introduce external temperature sensors to perform reference calibration or load multi-dimensional filters to track the offset. Such approaches increase the risk of hardware failure and increase processor instruction cycle consumption, causing logical blocking when the system processes high-frequency concurrent data. This creates an irreconcilable contradiction between identification accuracy and resource consumption.

[0003] Besides hardware architecture limitations, software processing strategies are insufficient in balancing computational energy efficiency and environmental stability. For example, Chinese invention patent CN111144230B discloses a time-domain load signal denoising method based on VMD, which achieves adaptive denoising of complex signals through variational mode decomposition. The underlying logic relies on complex variational iterative solutions and entropy statistics. For power metering edge nodes with limited computing resources and strict real-time requirements, the computational complexity increases the processor's dynamic power consumption. When faced with systemic common-mode drift caused by hardware temperature drift or power grid base frequency changes, it is difficult to quickly compensate through time-domain correlation.

[0004] Therefore, the technical problem to be solved by this invention is how to achieve an electrical digital processing mechanism that can offset the effects of clock drift and base frequency fluctuations under strict hardware constraints and has low instruction cycle loss. Summary of the Invention

[0005] This invention proposes an electronic digital processing and identification system for electricity metering box data, comprising: The timing feature extraction unit is used to acquire the voltage digital sequence and the current digital sequence, extract the first zero-crossing timestamp of the zero-crossing potential of the voltage signal and the second zero-crossing timestamp of the zero-crossing potential of the current signal, and calculate the dynamic time difference between the first zero-crossing timestamp and the second zero-crossing timestamp within the same AC cycle. The dead zone logic unit, which is connected to the timing feature extraction unit, is used to store the dead zone time threshold. It compares the time interval between two adjacent first zero-crossing timestamps with the dead zone time threshold. When the time interval is less than the dead zone time threshold, it deletes the next first zero-crossing timestamp and outputs the effective time difference sequence. The self-referenced differential logic unit is connected to the dead-zone logic unit and includes an internal register and an arithmetic logic module. The internal register is used to cache the first valid time difference of the previous AC cycle. The arithmetic logic module is used to obtain the second valid time difference of the current AC cycle, read the first valid time difference from the internal register, calculate the numerical difference between the second valid time difference and the first valid time difference, and generate a first-order discrete differential parameter. The internal register overwrites the first valid time difference according to the second valid time difference. The discrete logic mapping unit is used to store the mapping matrix, obtain the first-order discrete difference parameters, and output a single-byte integer status code according to the mapping matrix. The state machine matching unit is used to aggregate single-byte integer status codes in sequence to generate a one-dimensional status code sequence array, calculate the logical distance between the one-dimensional status code sequence array and the abnormal pattern feature vector, and output an identification alarm signal when the logical distance is less than the judgment threshold.

[0006] Preferably, in the self-referenced differential logic unit, the arithmetic logic module uses the numerical cancellation of the first sample value and the second sample value of adjacent AC cycles to eliminate the common-mode drift component caused by the temperature drift of the crystal oscillator inside the power metering box and the fundamental frequency fluctuation of the power grid, so that the numerical offset of the first-order discrete differential parameter reflects the transient change characteristics of the controlled load.

[0007] Preferably, the state machine matching unit has a built-in byte entropy monitoring module, which is used to calculate the distribution dispersion of each single-byte integer state code in the current one-dimensional state code sequence array. When the distribution dispersion is lower than the stable operating condition threshold, a sequence truncation instruction is output to reduce the preset number of single-byte integer state codes generated in the next sampling period.

[0008] Preferably, the dead-time logic unit shields high-frequency spurious pulses in the voltage digital sequence by using a dead-time threshold, so that the generated effective time difference sequence is driven only by the power frequency zero-crossing event, thereby reducing the computational load of the self-referenced differential logic unit.

[0009] Preferably, the mapping matrix defines multiple differential interval thresholds with asymmetric distribution of zero points. The discrete logic mapping unit determines the corresponding logic mapping path based on the positive and negative polarities of the first-order discrete differential parameters, which is used to distinguish the heterogeneous characteristic data generated by sudden increases and decreases in grid load.

[0010] Preferably, after the arithmetic logic module completes the difference calculation, it sends a synchronization trigger signal to the discrete logic mapping unit. The discrete logic mapping unit only retrieves the mapping matrix when it receives the synchronization trigger signal, so as to reduce the dynamic power consumption of the system.

[0011] Preferably, when the distribution dispersion is continuously lower than the stable operating condition threshold for a preset sleep duration, the byte entropy monitoring module sends a frequency reduction command to the timing feature extraction unit to increase the sampling step size of the voltage digital sequence and the current digital sequence.

[0012] Preferably, the internal register adopts a single-depth hardware buffer structure, which receives the output of the arithmetic logic module at the end of each AC cycle to complete the data shift, ensuring that the buffered sample value always remains the value of the previous adjacent cycle.

[0013] Preferably, the alarm signal identification includes anomaly type code and timing offset. The state machine matching unit determines the feature pattern index that generates the minimum logical distance in the one-dimensional state code sequence array as the anomaly type code and outputs it.

[0014] The beneficial effects of this invention are: 1. In the digital processing of data from the electricity metering box, the processing system eliminates common-mode interference from the environment through the coordinated operation of the timing feature extraction unit and the self-reference differential logic unit. The arithmetic logic unit calculates the integer difference of the effective time difference within adjacent AC cycles, so that the low-frequency offset caused by physical temperature drift or power grid base frequency fluctuations cancels each other out during the differential operation. This method utilizes the timing correlation between adjacent cycles and establishes a stable anomaly discrimination benchmark through the differential topology of the processor's internal instructions, so that the anomaly identification process is free from dependence on external physical sensors and environmental tracking compensation algorithms, ensuring the consistency of data discrimination under complex operating conditions.

[0015] 2. The discrete logic mapping unit converts the time difference information into a single-byte integer status code based on the differential interval threshold. Combined with the one-dimensional array comparison of the state machine matching unit, it achieves dimensionality reduction of the data. This processing path transforms the analysis of continuous analog electrical waveforms into pattern matching based on a low-bit-width integer array. Feature recognition can be completed using only the basic logic instruction set. This data processing structure effectively reduces the instruction execution cycle of the edge microprocessor, prevents computational overflow or recognition delay when high-frequency sampling data is concurrent, and improves the monitoring timeliness of the power metering box for abnormal events at the edge. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of the data feature extraction and differential recognition process for the electricity metering box of the present invention; Figure 2 This is a block diagram of the cascaded logic units of the data processing system for the electricity metering box of the present invention. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] A digital processing and identification system for electricity meter box data includes: The timing feature extraction unit is used to acquire the voltage digital sequence and the current digital sequence, extract the first zero-crossing timestamp of the zero-crossing potential of the voltage signal and the second zero-crossing timestamp of the zero-crossing potential of the current signal, and calculate the dynamic time difference between the first zero-crossing timestamp and the second zero-crossing timestamp within the same AC cycle. The dead zone logic unit, which is connected to the timing feature extraction unit, is used to store the dead zone time threshold. It compares the time interval between two adjacent first zero-crossing timestamps with the dead zone time threshold. When the time interval is less than the dead zone time threshold, it deletes the next first zero-crossing timestamp and outputs the effective time difference sequence. The self-referenced differential logic unit is connected to the dead-zone logic unit and includes an internal register and an arithmetic logic module. The internal register is used to cache the first valid time difference of the previous AC cycle. The arithmetic logic module is used to obtain the second valid time difference of the current AC cycle, read the first valid time difference from the internal register, calculate the numerical difference between the second valid time difference and the first valid time difference, and generate a first-order discrete differential parameter. The internal register overwrites the first valid time difference according to the second valid time difference. The discrete logic mapping unit is used to store the mapping matrix, obtain the first-order discrete difference parameters, and output a single-byte integer status code according to the mapping matrix.

[0020] The state machine matching unit is used to aggregate single-byte integer status codes in sequence to generate a one-dimensional status code sequence array, calculate the logical distance between the one-dimensional status code sequence array and the abnormal pattern feature vector, and output an identification alarm signal when the logical distance is less than the judgment threshold.

[0021] Preferably, in the self-referenced differential logic unit, the arithmetic logic module uses the numerical cancellation of the first sample value and the second sample value of adjacent AC cycles to eliminate the common-mode drift component caused by the temperature drift of the crystal oscillator inside the power metering box and the fundamental frequency fluctuation of the power grid, so that the numerical offset of the first-order discrete differential parameter reflects the transient change characteristics of the controlled load.

[0022] Preferably, the state machine matching unit has a built-in byte entropy monitoring module, which is used to calculate the distribution dispersion of each single-byte integer state code in the current one-dimensional state code sequence array. When the distribution dispersion is lower than the stable operating condition threshold, a sequence truncation instruction is output to reduce the preset number of single-byte integer state codes generated in the next sampling period.

[0023] Preferably, the dead-time logic unit shields high-frequency spurious pulses in the voltage digital sequence by using a dead-time threshold, so that the generated effective time difference sequence is driven only by the power frequency zero-crossing event, thereby reducing the computational load of the self-referenced differential logic unit.

[0024] Preferably, the mapping matrix defines multiple differential interval thresholds with asymmetric distribution of zero points. The discrete logic mapping unit determines the corresponding logic mapping path based on the positive and negative polarities of the first-order discrete differential parameters, which is used to distinguish the heterogeneous characteristic data generated by sudden increases and decreases in grid load.

[0025] Preferably, after the arithmetic logic module completes the difference calculation, it sends a synchronization trigger signal to the discrete logic mapping unit. The discrete logic mapping unit only retrieves the mapping matrix when it receives the synchronization trigger signal, so as to reduce the dynamic power consumption of the system.

[0026] Preferably, when the distribution dispersion is continuously lower than the stable operating condition threshold for a preset sleep duration, the byte entropy monitoring module sends a frequency reduction command to the timing feature extraction unit to increase the sampling step size of the voltage digital sequence and the current digital sequence.

[0027] Preferably, the internal register adopts a single-depth hardware buffer structure, which receives the output of the arithmetic logic module at the end of each AC cycle to complete the data shift, ensuring that the buffered sample value always remains the value of the previous adjacent cycle.

[0028] Preferably, the alarm signal identification includes anomaly type code and timing offset. The state machine matching unit determines the feature pattern index that generates the minimum logical distance in the one-dimensional state code sequence array as the anomaly type code and outputs it.

[0029] Example 1: In the operation of an energy metering box deployed in a high-load power distribution environment in an industrial park, the system faces electromagnetic pulse interference from the start-up and shutdown of large inductive loads and a temperature rise exceeding 55°C inside the cabinet during summer. Due to the frequency drift of the underlying crystal oscillator of the microprocessor inside the metering box at high temperatures, and the continuous low-frequency breathing effect of the local power grid base frequency between 49.8Hz and 50.2Hz caused by load fluctuations, traditional identification methods based on absolute time-domain thresholds generate false alarms due to reference offset. Furthermore, limited by the 100MHz processor power of the edge nodes, the system struggles to perform high-order floating-point operations. To address these challenges, the present invention provides an electronic digital processing and identification system for energy metering box data. During operation, the timing feature extraction unit acquires the voltage and current digital sequences continuously sampled from the distribution network side. It determines the first zero-crossing timestamp of the voltage signal zero-crossing potential and the second zero-crossing timestamp of the current signal zero-crossing potential through numerical comparison, and calculates the dynamic time difference between the first and second zero-crossing timestamps within the same AC cycle. The dead-time logic unit is connected to the timing feature extraction unit. This unit uses a stored 100μs dead-time threshold to compare the time interval between two adjacent first zero-crossing timestamps. When the time interval is less than the dead-time threshold, the next first zero-crossing timestamp is deleted, thereby shielding stray pulses generated by nonlinear loads in the voltage digital sequence and outputting an effective time difference sequence driven by the power frequency zero-crossing event.

[0030] The self-referenced differential logic unit is connected to the dead-time logic unit, and the first valid time difference of the previous AC cycle is cached through an internal register. The arithmetic logic module obtains the second effective time difference of the current communication cycle. And read the first valid time difference in the internal register. The numerical difference between the two is calculated to generate a first-order discrete difference parameter. In this differential topology, the hardware clock offset caused by ambient temperature difference and the frequency fluctuation caused by power grid load are equivalent to low-frequency common-mode deviation within adjacent 20ms electrical cycles, thus achieving offsetting elimination in the difference operation; the discrete logic mapping unit receives first-order discrete differential parameters. The system determines single-byte integer status codes corresponding to specific differential logic intervals based on the differential interval thresholds defined in the mapping matrix. These single-byte integer status codes, generated continuously, are aggregated into a one-dimensional status code sequence array by the state machine matching unit in a time sequence. The Hamming logic distance between this one-dimensional status code sequence array and the pre-loaded abnormal pattern feature vector is calculated. When the logic distance is less than the judgment threshold, an identification alarm signal is output. Through this processing path, the system transforms analog electrical signal identification into pattern matching based on a low-bit-width integer array, while maintaining the central processing unit (CPU) utilization rate below a certain threshold. Under the premise of eliminating dependence on external temperature sensor hardware, and when the power grid base frequency fluctuation exceeds Under Hz interference, a microsecond-level timing jitter event caused by insulation degradation of a power distribution branch was accurately identified, thus confirming the reliability of abnormal state identification.

[0031] Example 2: In a digital signal processing experiment simulating edge metering on the power distribution side, the experimental group used a processing system including a self-referenced differential logic unit, while the control group used an identification structure based on absolute threshold comparison. The experimental data came from a physical electrical signal acquisition platform with 24-bit high-resolution analog-to-digital conversion capability and a sampling rate set to 100kHz. To simulate industrial interference conditions, Gaussian white noise with a signal-to-noise ratio of 20dB was superimposed on the input voltage digital sequence, and the operating environment of the microprocessor crystal oscillator was heated from 25℃ to 60℃ by a constant temperature control box, resulting in a frequency temperature drift deviation of 0.05%; dead time threshold... The value is set to 100μs. This parameter depends on the sampling frequency and the spectral width of the high-frequency harmonic components of the power grid. The setting balances signal extraction precision with spike noise blocking effectiveness. The decision rule is that the dead time threshold must be greater than the harmonic period and less than 5% of the AC period. For the 5kHz harmonic components under operating conditions, 100μs is selected as the dead time threshold to isolate stray pulses. The dead time threshold determination procedure includes: acquiring the voltage digital sequence of the target power distribution environment under no-load conditions using an oscilloscope or data acquisition terminal, and statistically identifying the high-frequency stray pulse width within 200 consecutive AC cycles. The distribution is analyzed, and the maximum pulse width is extracted and set as the basic observation value. The basic observation value is multiplied by a safety factor of 1.2 to 1.5 to determine the dead-time threshold. This covers transient spikes generated by nonlinear loads and maintains them within a 5% frequency window of the AC cycle. An analog signal containing a preset frequency drift is input to the system, and the stability of the time difference sequence is observed. If the zero-point drift of the first-order discrete difference parameter is less than 1 μs within a frequency fluctuation range of ±0.5 Hz, parameter locking is completed. To ensure that the dead-time threshold remains effective in the system's low-power mode, when the timing feature extraction unit receives a frequency reduction command to increase the sampling step size... At this time, the internal hardware frequency divider will execute the lower limit clamping logic, forcibly limiting the increased target sampling step size to no more than half of the dead time threshold. For the aforementioned 100μs dead time threshold, the maximum sampling step size after frequency reduction is hard-constrained to no more than 50μs. The corresponding minimum sampling frequency of the analog-to-digital converter is limited to a baseline of no less than 20kHz, thereby physically ensuring that any real zero-crossing event can be captured by at least two consecutive discrete sampling points, avoiding the dead time comparison module losing its ability to determine the microsecond-level characteristics of the operating waveform due to excessive amplification of the sampling time scale.

[0032] During the test run, the timing feature extraction unit acquires the first zero-crossing timestamp of the voltage signal's zero-crossing potential, which is then processed by the arithmetic logic module according to the formula. Calculate the numerical difference between the effective time differences of adjacent AC cycles, where, The effective time difference for the current communication cycle. The first valid time difference of the previous AC cycle in the register buffer. For the generated first-order discrete differential parameters, observational data show that within a 10-minute observation window during which the crystal oscillator frequency drifts due to ambient temperature rise, the anomaly identification accuracy of the control group drops from 98.5% to 71.2% due to the cumulative offset of the first zero-crossing timestamp relative to the reference. The experimental group filters out the common-mode components generated by temperature drift through a numerical cancellation mechanism, and the output status code sequence remains stable, with the identification accuracy maintained above 99.1%, confirming the ability of this differential topology to suppress physical environmental disturbances.

[0033] To verify the rationality of the numerical range, an out-of-range control group was set up. When the dead time threshold was reduced to 5μs, high-frequency stray pulses in the voltage sequence frequently triggered pseudo-zero-crossing events, resulting in an increased computational load on the self-referenced differential logic unit and a large number of misjudgments in the recognition results. When the threshold was increased to 500μs, the zero-crossing potential of the voltage signal was truncated by the logic, resulting in the loss of the first-order discrete differential parameter. The value window before and after 100μs was verified as a working range that balances real-time performance and determinism. In the gradient verification stage, three noise intensities with signal-to-noise ratios of 20dB, 15dB, and 10dB were set respectively. The recognition rates of timing jitter caused by branch insulation degradation in the test group were 99.2%, 98.7%, and 97.6%, respectively. The data showed a slow downward trend with the increase of noise intensity, and no sudden failure occurred, confirming the stability and engineering feasibility of the system under harsh operating conditions.

[0034] Example 3: This example combines Figures 1 to 2 This document describes an electrical digital processing and identification system for electricity metering box data, such as... Figure 1As shown, the voltage digital sequence and current digital sequence are input in parallel to the timing feature extraction unit. This unit extracts the zero-crossing timestamp and calculates the dynamic time difference, then outputs the dynamic time difference to the dead-zone logic unit. The dead-zone logic unit compares the dead-zone time threshold and outputs the effective time difference, which in turn outputs the effective time difference sequence to the arithmetic logic module. Simultaneously, the internal register caches the effective time difference of the previous cycle and inputs the first effective time difference to the arithmetic logic module. The arithmetic logic module calculates the numerical difference to generate parameters and overwrites them with the second effective time difference, feeding them back to the internal register. The arithmetic logic module also outputs a first-order discrete difference parameter to the discrete logic mapping unit. Upon receiving this parameter, the discrete logic mapping unit retrieves the mapping matrix and outputs a single-byte status code. The generated single-byte integer status code is then input to the state machine matching unit. The state machine matching unit aggregates the status code sequence array and calculates the logical distance. When the logical distance is less than the judgment threshold, a one-way alarm signal is output. Figure 2 As shown, the system adopts a top-down unidirectional serial topology, including a timing feature extraction unit at the top. The output of the timing feature extraction unit is directly connected to the dead-zone logic unit, which is connected to the self-reference differential logic unit. The self-reference differential logic unit is connected downward to the discrete logic mapping unit in the data path, and the output of the discrete logic mapping unit is finally connected to the state machine matching unit.

[0035] Example 4: In intelligent building power distribution monitoring involving multiple types of variable frequency loads, the system faces high-frequency current distortion caused by nonlinear power electronic equipment. The transient characteristics generated by this distortion overlap with the branch insulation fault waveform in the time domain. Furthermore, the background noise energy in this condition fluctuates within a 15% range depending on the start and stop of electrical equipment within the building. This makes it difficult for the fixed-step feature mapping method to maintain recognition sensitivity while suppressing false alarms caused by noise fluctuations. The discrete logic mapping unit allocates a lookup table with a depth of 256 in the static random access memory, based on the first-order discrete differential parameter... The quantization step size divides the value range into 256 logical intervals, each corresponding to a unique single-byte integer status code. The arithmetic logic module will then acquire... The index is converted to an unsigned integer and points to the storage address of the lookup table, thus outputting an 8-bit status code; the mapping matrix construction procedure includes: collecting raw data of the controlled load under three typical operating conditions: steady-state operation, load surge, and load drop, and calculating the corresponding first-order discrete difference parameters. Based on the distribution characteristics of the probability density function on the number axis, multiple asymmetric discrete intervals are divided centered at zero in both positive and negative polarity directions, covering specific load variation intensities. These discrete intervals are used as index addresses, and unique single-byte integer status codes are written to the corresponding storage units to form a static lookup table. In actual debugging procedures, the load power is changed stepwise, and the system output status code sequence is recorded. If the status code transition is synchronized with the physical load action and the status code dispersion is lower than a preset value in steady state, the mapping matrix is ​​deemed to meet the engineering implementation requirements. When determining the specific isolation boundaries of the aforementioned discrete intervals, the arithmetic logic module divides the constructed positive and negative polarity probability density envelope curves... Instead of performing first-order partial derivative mathematical calculations, the system accurately captures the local extreme points where the slope of the curve density distribution changes abruptly, using these points as initial reference abscissas. With zero bias as the origin of integration, the system divides the probability integral area between adjacent abscissas into equal-amplitude infinitesimal elements based on the cumulative area of ​​the differential value change caused by each kilowatt load transition in the monitored power grid branch. The resulting function segmentation node sequence can then be directly defined as the absolute quantization threshold limit of the asymmetric discrete interval. During operation, the system continuously statistically analyzes the status code distribution characteristics over 1000 sampling periods. The byte entropy monitoring module calculates the entropy value of the current one-dimensional status code sequence array to characterize the background noise intensity, and uses the formula... Determine the judgment threshold; where, The threshold used to identify alarms This represents the statistical mean of logical distances over historical stable periods. The threshold value corresponds to the standard deviation of the sample, and varies with the standard deviation of the background noise. It automatically adjusts to changes.

[0036] The state machine matching unit stores 16 consecutively generated state codes into a first-in-first-out (FIFO) memory, forming a one-dimensional state code sequence array representing the current load characteristics. The arithmetic logic unit performs a bitwise XOR operation between this array and the abnormal mode feature vector stored in non-volatile memory. The Hamming logic distance between the two is determined by counting the number of logic 1s in the XOR result. If the Hamming logic distance is less than a judgment threshold for three consecutive electrical cycles, the determination is made. When the system generates an alarm signal, and under test conditions where background noise fluctuations reach 15%, this processing method maintains an accuracy rate of over 99.4%, achieving accurate extraction of transient anomalies under limited computing power; the discrete logic mapping unit processes first-order discrete differential parameters. When the polarity discrimination logic is executed, the threshold of the difference interval defined in the mapping matrix exhibits an asymmetric distribution characteristic with zero as the reference. When the arithmetic logic module calculates... When the value is positive, the system calls the lookup table subset corresponding to the positive fluctuation range to characterize the electrical fingerprint generated by the load surge, while when... When the value is negative, the system switches to the lookup table subset corresponding to the negative fluctuation range to handle the characteristic data generated by the sudden load reduction. In this processing method, since the transient response curves of the power grid during load increases and decreases are inherently heterogeneous, an asymmetric threshold boundary is set. to The system achieves decoupling and extraction of load variations of different natures in a single data conversion process, enabling the generated single-byte integer status code to accurately carry the polarity evolution information on the physical side.

[0037] Example 5: In the feature library construction phase before the newly developed power metering and identification system is put into operation, the generation of abnormal mode feature vectors originates from a controlled discrete state sequence extraction procedure. A nonlinear rectifier load and an inductive load are connected in the simulated power distribution branch. A 50Hz sine wave is output from a programmable AC power supply with added harmonic components. The first-order discrete differential parameter sequence under normal operating conditions is obtained through a timing feature extraction unit and a self-referenced differential logic unit. A micro-arc discharge event caused by poor contact is simulated by the action of a mechanical switch. The system captures 32 AC cycle data before and after the triggering time of this event and converts them into single-byte integer status codes. The arithmetic logic unit compares the normal sequence and the abnormal sequence and extracts a 16-byte code stream of statistical differences, which is defined as the fault feature index corresponding to the fault type. The data is then stored in non-volatile memory to complete the data filling of the abnormal pattern feature vector. During the feature extraction step, the arithmetic logic unit calculates the state transition variance of each single byte in the abnormal state sequence within 32 consecutive AC cycles and subtracts it from the stable basis variance of the corresponding position in the normal sequence to obtain a one-dimensional discrete difference feature array. The system uses a software sliding window algorithm to traverse the sequence along this difference array, sliding bit by bit with a fixed sliding window length of 16 bytes, continuously calculating the sum of the variance differences of all elements in the current window, locating the specific interval where the sum of variances reaches the global maximum value. Through the above-mentioned quantitative spatial sliding window and variance optimization logic, the 16-byte data segment with the most drastic difference amplitude and natural continuity in the time domain is extracted as the final fixed code stream.

[0038] When the system is first deployed and debugged in a specific industrial site, in order to determine the initial benchmark for the judgment threshold and offset the background noise difference at the installation site, the system starts a 24-hour online observation and calibration process. The processor continuously collects voltage and current digital sequences, and the byte entropy monitoring module calculates the probability distribution of the first-order discrete difference parameter after converting it into a single-byte integer status code every 1000 sampling cycles. The statistical mean of the logical distance is recorded by the arithmetic logic module. with standard deviation After calibration, according to the formula Determine the judgment threshold; where, This represents the statistical mean of logical distances over historical stable periods. The standard deviation of the corresponding sample is . This procedure establishes an anomaly detection baseline based on the harmonic noise level of a specific substation environment. This baseline is then used by the state machine matching unit to maintain the preset detection sensitivity when the ambient noise level fluctuates.

[0039] Example 6: In the pre-deployment calibration procedure for a specific power distribution condition, the generation of abnormal mode feature vectors originates from the fault fingerprint extraction path based on position weight stability assessment. The system acquires the original code stream sequence containing micro-arc features of poor contact, collected by the timing feature extraction unit, and determines the sequence length to be 1024 bytes. The arithmetic logic unit retrieves the first-order discrete difference parameter in the sequence through a sliding window. The system identifies the extreme points of mutations and uses them as the time-point alignment benchmark. It then performs bit-by-bit probability statistics on the aligned 32-cycle bitstream to determine the state stability coefficient of each bit. By selecting 16-byte data segments corresponding to the bits with the highest stability coefficients (top 5%), and using hash transformation to convert them into fixed-dimensional anomaly pattern feature vectors stored in static random access memory, the system completes the standardized encapsulation of fault fingerprints. In this data encapsulation and transformation, the system's hash function incorporates Locality Sensitive Hash (LSH) algorithm logic and a time-domain weighted masking system. In practice, the processing engine retains the temporal positions of the preferred bits within the original 32 cycles and sequentially adds base-decreasing temporal spatial weights to their sequence before pushing the weighted feature stream into the mapper. This mechanism ensures that the generated compressed fixed-length vector not only effectively reduces memory usage but also fully inherits the coherent jump patterns of physical events along the temporal edges, providing a solid feature preservation foundation for the system to subsequently use Hamming distance calculation to measure physical feature similarity.

[0040] When the system runs the online adaptive calibration process to determine the stable operating condition threshold that distinguishes between load mutations and background noise, the byte entropy monitoring module analyzes the bit distribution pattern of the one-dimensional status code sequence array in real time and applies the formula... Calculate the information entropy of the current data stream, where H is the calculated byte entropy. To determine the frequency of occurrence of the i-th type of status code within the observation and statistics unit, the system continuously records 500 sets of byte entropy values ​​during stable operation without abnormal input and extracts the upper envelope of its fluctuations as a criterion. When the real-time calculated byte entropy is consistently lower than 1.1 times the upper envelope and the dispersion of the Hamming logic distance is within ±2σ of the statistical mean, the decision logic gate outputs a stable signal. Subsequently, the preset aggregation quantity parameter of the single-byte integer status code is reduced to lower the processor core's operating frequency, achieving automated calibration of the decision logic in a dynamic environment. When the system decision gate triggers the reduction instruction for this aggregation quantity parameter, the monitoring routine of the underlying hardware abstraction layer synchronously captures the state transition of this software variable and rewrites the microprocessor's internal system control register (System Control Register) via the bus channel. Register sends a Dynamic Voltage and Frequency Adjustment (DVFS) mapping instruction to the phase-locked loop (PLL) oscillation circuit. In actual operation, the chip controller proportionally reduces the frequency multiplier configuration word of the PLL based on the reduced array aggregation length, so that the physical clock tick driving the central processing unit hardware core is deterministically reduced step by step. Thus, without changing the external hardware electrical structure, a cross-scale execution path from software logic parameters to physical dynamic power consumption reduction is opened up.

[0041] When the state machine matching unit outputs an alarm signal, it initiates an encoding mapping procedure. The arithmetic logic unit sorts the calculated Hamming logic distances and retrieves the abnormal pattern feature vector that produces the minimum logic distance. The system determines a unique feature pattern index based on the physical starting address of this vector in non-volatile memory and encapsulates it as an abnormal type code in the alarm signal. Simultaneously, the processor reads the deviation between the starting timestamp of the matching action triggered in the current one-dimensional state code sequence array and the preset reference period. Based on this deviation, it calculates the timing offset and outputs it synchronously as a subordinate parameter of the alarm signal. Through this signal generation method based on memory address index, the system provides the management terminal with structured digital insights containing fault attributes and precise timing, completing the information transformation closed loop from underlying bit comparison to application-layer decision support.

[0042] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A digital processing and identification system for electricity metering box data, characterized in that, include: The timing feature extraction unit is used to acquire the voltage digital sequence and the current digital sequence, extract the first zero-crossing timestamp of the zero-crossing potential of the voltage signal and the second zero-crossing timestamp of the zero-crossing potential of the current signal, and calculate the dynamic time difference between the first zero-crossing timestamp and the second zero-crossing timestamp within the same AC cycle. The dead zone logic unit, which is connected to the timing feature extraction unit, is used to store the dead zone time threshold. It compares the time interval between two adjacent first zero-crossing timestamps with the dead zone time threshold. When the time interval is less than the dead zone time threshold, it deletes the next first zero-crossing timestamp and outputs the effective time difference sequence. The self-referenced differential logic unit is connected to the dead-zone logic unit and includes an internal register and an arithmetic logic module. The internal register is used to cache the first valid time difference of the previous AC cycle. The arithmetic logic module is used to obtain the second valid time difference of the current AC cycle, read the first valid time difference from the internal register, calculate the numerical difference between the second valid time difference and the first valid time difference, and generate a first-order discrete differential parameter. The internal register overwrites the first valid time difference according to the second valid time difference. The discrete logic mapping unit is used to store the mapping matrix, obtain the first-order discrete difference parameters, and output a single-byte integer status code according to the mapping matrix. The state machine matching unit is used to aggregate single-byte integer status codes in sequence to generate a one-dimensional status code sequence array, calculate the logical distance between the one-dimensional status code sequence array and the abnormal pattern feature vector, and output an identification alarm signal when the logical distance is less than the judgment threshold.

2. The electrical digital processing and identification system for electricity metering box data according to claim 1, characterized in that, In the self-referenced differential logic unit, the arithmetic logic module uses the numerical cancellation of the first and second sample values ​​of adjacent AC cycles to eliminate the common-mode drift component caused by the temperature drift of the crystal oscillator inside the power metering box and the fluctuation of the grid fundamental frequency, so that the numerical offset of the first-order discrete differential parameter reflects the transient change characteristics of the controlled load.

3. The electrical digital processing and identification system for electricity metering box data according to claim 1, characterized in that, The state machine matching unit has a built-in byte entropy monitoring module, which is used to calculate the distribution dispersion of each single-byte integer state code in the current one-dimensional state code sequence array. When the distribution dispersion is lower than the stable operating condition threshold, a sequence truncation instruction is output to reduce the preset number of single-byte integer state codes generated in the next sampling period.

4. The electrical digital processing and identification system for electricity metering box data according to claim 1, characterized in that, The dead-time logic unit shields high-frequency spurious pulses in the voltage digital sequence by using a dead-time threshold, so that the generated effective time difference sequence is driven only by the power frequency zero-crossing event, thereby reducing the computational load of the self-referenced differential logic unit.

5. The electrical digital processing and identification system for electricity metering box data according to claim 1, characterized in that, The mapping matrix defines multiple differential interval thresholds with asymmetric distribution of zero points. The discrete logic mapping unit determines the corresponding logic mapping path based on the positive and negative polarities of the first-order discrete differential parameters, which is used to distinguish the heterogeneous characteristic data generated by sudden increases and decreases in power grid load.

6. The electrical digital processing and identification system for electricity metering box data according to claim 1, characterized in that, After completing the difference calculation, the arithmetic logic module sends a synchronization trigger signal to the discrete logic mapping unit. The discrete logic mapping unit only retrieves the mapping matrix when it receives the synchronization trigger signal, so as to reduce the dynamic power consumption of the system.

7. The electrical digital processing and identification system for electricity metering box data according to claim 3, characterized in that, When the distribution dispersion remains below the stable operating condition threshold for a preset sleep duration, the byte entropy monitoring module sends a frequency reduction command to the timing feature extraction unit to increase the sampling step size of the voltage digital sequence and the current digital sequence.

8. The electrical digital processing and identification system for electricity metering box data according to claim 1, characterized in that, The internal registers employ a single-depth hardware buffer structure, which receives the output of the arithmetic logic module at the end of each AC cycle to complete the data shift, ensuring that the buffered sample values ​​always remain the values ​​of the preceding adjacent cycles.

9. The electrical digital processing and identification system for electricity metering box data according to claim 1, characterized in that, The alarm signal identification includes the anomaly type code and the timing offset. The state machine matching unit determines the feature pattern index that generates the minimum logical distance in the one-dimensional state code sequence array as the anomaly type code and outputs it.

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