Dc-dc converter using parallel load point integrated circuit

Abstract

A converter includes a first stage connected to first and second input terminals and including a first-stage IC having a feedback terminal, a first half-bridge circuit and a second half-bridge circuit connected in parallel, each of the first and second half-bridge circuits including a half-bridge IC that receives a clock signal from the first stage, a transformer including a single magnetic core, a first primary winding extending around the single magnetic core and connected to the first half-bridge circuit, a second primary winding extending around the single magnetic core and connected to the second half-bridge circuit, and a secondary winding extending around the single magnetic core, a rectifier connected to the secondary winding, first and second output terminals connected to the rectifier, and a feedback circuit connected between the first output terminal and the feedback terminal of the first-stage IC.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 63 / 749,082, filed January 24, 2025. The entire contents of this application are incorporated herein by reference. Technical Field

[0003] This invention relates to converters. More specifically, this invention relates to DC-DC converters that use parallel-connected point-of-load (POL) integrated circuits (ICs) to achieve resonant operation. Background Technology

[0004] When higher currents are required, it is well known that the ICs, transformers, and electronic components in a DC-DC converter are scaled up. However, scaling up a DC-DC converter presents problems, including increasing the height of the transformer to accommodate the larger current, and the potential for reliability issues with larger ICs. Summary of the Invention

[0005] To overcome the aforementioned problems, an exemplary embodiment of the present invention provides a converter comprising a first stage and a second stage including half-bridge circuits, wherein each half-bridge circuit receives a clock signal from the first stage, and wherein the first stage receives a feedback signal from the second stage. Using multiple half-bridge circuits allows for the use of more reliable ICs and allows the primary windings to be wound around the same magnetic core, which allows for the use of smaller transformers.

[0006] According to an exemplary embodiment of the present invention, a converter includes a first input terminal and a second input terminal; a first stage connected to the first and second input terminals and including a first-stage integrated circuit (IC) including a feedback terminal; a first half-bridge circuit and a second half-bridge circuit connected in parallel and receiving an input voltage from the first stage, each of the first and second half-bridge circuits including a half-bridge IC receiving a clock signal from the first stage; a transformer including a single magnetic core, a first primary winding extending around the single magnetic core and connected to the first half-bridge circuit, a second primary winding extending around the single magnetic core and connected to the second half-bridge circuit, and a secondary winding extending around the single magnetic core; a rectifier connected to the secondary winding; a first output terminal and a second output terminal connected to the rectifier; and a feedback circuit connected between the first output terminal and the feedback terminal of the first-stage IC.

[0007] The half-bridge IC can be a non-resonant buck point-of-load IC that can receive the input voltage from the first stage and may include a feedback terminal and a switching output terminal. A voltage sensing circuit is connected to both the feedback terminal and the switching output terminal of the half-bridge IC. The voltage sensing circuit may include a voltage divider defined by a first resistor and a second resistor connected in series with each other; the first resistor may be directly connected to the switching output terminal of the half-bridge IC; and the node between the first and second resistors is connected to the feedback terminal of the half-bridge IC. The signal received from the voltage sensing circuit at the feedback terminal of the half-bridge IC allows the half-bridge IC to provide a 50% duty cycle or approximately 50% duty cycle.

[0008] The first stage can be a buck converter. The first-stage IC may include a switched output terminal that provides the input voltage. The feedback circuit may include an isolator, optocoupler, or signal isolator. The rectifier may include a full-bridge rectifier, a voltage doubler circuit, or a voltage quadrupler circuit. The magnetic core may have a toroidal, rectangular, elliptical, or EI-shaped form.

[0009] The above and other features, elements, characteristics, steps, and advantages of the invention will become more apparent from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 The converter can be used with Figure 2 The second level shown is used in conjunction with the first level.

[0011] Figure 2 The converter can be used with Figure 1 The second level is used in conjunction with the first level shown.

[0012] Figure 3 A converter including a first stage and a second stage is shown. The first stage includes a buck converter, and the second stage includes a parallel POL IC that receives a clock signal from the first stage.

[0013] Figure 4 The secondary circuit with a full-bridge rectifier is shown.

[0014] Figure 5 The secondary circuit with a full-bridge rectifier and an inductor is shown.

[0015] Figure 6 The secondary circuit with a quadrupole voltage multiplier is shown.

[0016] Figure 7 The secondary circuit with a voltage doubler circuit is shown.

[0017] Figure 8 The secondary circuit with another voltage doubler circuit is shown.

[0018] Figure 9 The primary circuit of the second stage of a converter with a capacitor voltage divider is shown.

[0019] Figure 10 The primary circuit of the second stage of a converter with a capacitive voltage divider and a resonant capacitor is shown.

[0020] Figure 11 It shows that it can be used with Figure 1 and Figure 2 An example of an isolator used with the converter shown. Detailed Implementation

[0021] Figure 1 and Figure 2 The first and second stages of the converter are shown. Figure 1 It shows the provision for Figure 2 The second level of input is the first level. Figure 3 A converter including a first stage connected to a second stage is shown. The second stage includes two half-bridge circuits connected in parallel, and includes a transformer connected between the two parallel half-bridge circuits, as well as a rectifier stage or rectifier. Although Figure 3 Two half-bridge circuits in the second stage are shown, but any number of half-bridge circuits can be used. The first stage includes input voltage terminals Vin+ and Vin- for receiving the input voltage, and the rectifier stage or rectifier includes output voltage terminals Vout+ and Vout- for providing the output voltage. Figure 3 The input voltage is shown to be from about 15V to about 18V, and the output voltage is about 5V with a power of about 50W, but any other values ​​can be used. Figure 3 The first level in can include Figure 1 The first level, and Figure 3 The second level can include Figure 2 The second level. Alternative sites, in Figure 3 In this context, different first levels and / or different second levels can be used.

[0022] exist Figure 3 In this process, the first-stage output voltage (i.e., the second-stage input voltage) can be adjusted using the feedback signal from the feedback circuit based on the second-stage output voltage. This can be achieved by using an isolator across the isolation boundary provided by the transformer (by...). Figure 3 (As shown by the dashed line in the diagram) to send the feedback signal of the feedback circuit, the isolator can be, for example, an optocoupler, an insulating signal isolator, etc. Figure 1 and Figure 2 It shows Figure 1 The feedback terminal FB of IC U3 is connected to Figure 2 The terminal FBSIGNAL is connected to the output voltage VOUT+. Figure 1 and Figure 2 Isolators are not shown in any of these diagrams, but it should be understood that isolators can be connected to... Figure 1 Between the feedback terminal FB and the terminal FB SIGNAL of IC U3, to cross the... Figure 2 The transformer TX1 provides the isolation boundary for sending feedback signals.

[0023] exist Figure 3 In this circuit, the clock signal of the IC in the half-bridge circuit can be connected to the first stage to synchronize the frequency and phase of the half-bridge circuit. For example, the first stage may include components that can provide a clock signal or a synchronization signal (provided by...). Figure 3 The first stage may include an IC (shown as a dashed line in the diagram), and the second stage may include an IC that receives a clock signal or synchronization signal that can be used to synchronize the frequency and phase of the half-bridge circuit. Alternatively, the half-bridge circuit IC may be connected to the output terminal of the IC in the first stage.

[0024] exist Figure 3 In this system, the transformer core can have a toroidal, rectangular, elliptical, or EI-shaped form, and the primary winding of each half-bridge circuit can be wound around the same core, allowing the use of small transformers even in high-power applications. The secondary winding can also be wound around the same core.

[0025] exist Figure 3 In this configuration, the rectifier stage or rectifier may include diodes and may include capacitors. For example, the rectifier stage may include, for instance, diodes, capacitor ... Figure 2 Diodes D2 and D5 are shown. However, as... Figures 4 to 8 As shown, other configurations are also possible. For example, the rectifier stage can be configured as follows: Figure 4 and Figure 5 The diagram shows four diodes D1, D2, D3, and D4 arranged in a full-bridge configuration, which can be used as follows: Figure 6 The diagram shows four capacitors C10, C11, C12, and C13 arranged in a quadrupole configuration and three diodes D5, D6, and D7, or as shown below. Figure 7 The diagram shows two capacitors C10 and C11 arranged to double the voltage, and two diodes D5 and D6.

[0026] exist Figure 3 In this process, the first-stage output voltage (which can also be the second-stage input voltage) can be adjusted by a feedback signal from a feedback circuit. This feedback signal is sent from the secondary side of the transformer via an isolator, which can include an optocoupler or any other signal isolator. The second stage can include two or more half-bridge circuits, which can include... Figure 2 POL IC U1. For example... Figure 3As shown, the IC in the half-bridge circuit can be connected to the clock signal of the first stage to synchronize frequency and phase. The transformer can include a magnetic core that can have any shape, including toroidal, rectangular, elliptical, and EI-shaped. The primary winding of each half-bridge circuit can be wound around the same magnetic core.

[0027] Figure 3 The first stage can be a buck converter. For example, Figure 3 The first level may include Figure 1 As the first stage of the pre-stabilization stage, and Figure 3 The second level may include Figure 2 The second level. Figure 2 A first half-bridge circuit, including a first IC U1, is shown connected in parallel with a second half-bridge circuit including a second IC U2. For example... Figure 3 As shown, the parallel-connected half-bridge circuit can be connected between the first stage (pre-regulator stage) and the transformer, and the rectifier stage is connected to the transformer.

[0028] Although larger ICs can handle greater current, the size of ICs is limited, currently around 5mm x 6mm, because as the size of ICs increases, losses and heat generation negatively impact the reliability of the ICs.

[0029] Figure 2 A possible second stage of the converter is shown. The second stage includes dividing the second stage into a primary side ( Figure 2 (left side) and secondary side ( Figure 2 The transformer TX1 (on the right side) consists of two primary windings P1 and P2 and two secondary windings S1 and S2. Figure 2 As shown, the primary windings P1 and P2 may include 6 turns, and the secondary windings S1 and S2 may include 14 turns. The primary windings P1 and P2 and the secondary windings S1 and S2 can have any number of turns. The primary windings P1 and P2 can be wound around the same magnetic core. The magnetic core can have any suitable shape, including, for example, a toroidal, rectangular, elliptical, or EI-shaped core. The secondary windings S1 and S2 can also be wound around the same magnetic core. The second stage may include two half-bridge circuits connected in parallel. Each half-bridge circuit may include IC U1 or IC U2 connected to the primary winding P1 or P2.

[0030] The primary side of the second stage includes IC U1, which contains one or more power switches, and IC U2, which also contains one or more power switches. Both IC U1 and IC U2 may include an input voltage terminal VIN; an enable terminal EN that turns IC U1 on when voltage is applied and turns it off when no voltage is applied; a switch output terminal SW connected to the output of one or more power switches; a feedback terminal FB that monitors the output of IC U1; a clock or synchronization terminal CLK; and a ground terminal GND. IC U1 and IC U2 may include unconnected terminals NC that are not connected to any other components of the converter. Unconnected terminals NC may be allowed to float.

[0031] The primary side of the second stage may include input terminals +input and -input connected to input capacitor C3. Input terminal +input and the first terminal of input capacitor C3 can be connected to input voltage terminal VIN and enable terminal EN. Input terminal -input and the second terminal of input capacitor C3 can be connected to ground terminal GND of IC U1 and IC U2. Switch output terminal SW of IC U1 can be connected to primary winding P1, and switch output terminal SW of IC U2 can be connected to primary winding P2. Primary winding P1 can be connected in series with capacitor C5, and primary winding P2 can be connected in series with capacitor C25.

[0032] The feedback terminal FB of IC U1 can be connected to the switching output terminal SW of IC U1. The feedback terminal FB of IC U1 can be connected to the switching output terminal SW of IC U1 before any inductor or LC filter connected to the switching output terminal of IC U1. For example... Figure 2 As shown, the feedback terminal FB of IC U1 can be connected to the switching output terminal SW of IC U1 via a voltage divider defined by resistors R6 and R7 connected in series across the switching output terminal SW and input terminal of IC U1. The feedback terminal FB of IC U2 can be connected to the switching output terminal SW of IC U2. The feedback terminal FB of IC U2 can be connected to the switching output terminal SW of IC U2 before any inductor or LC filter connected to the switching output terminal of IC U2. For example... Figure 2 As shown, the feedback terminal FB of IC U2 can be connected to the switch output terminal SW of IC U2 via a voltage divider defined by resistors R26 and R27 connected in series across the switch output terminal SW and input terminal of IC U2.

[0033] ICs U1 and U2 can be non-resonant buck POL ICs, which may include internal high-side power switches and internal low-side power switches connected in series with each other and connected to the input voltage. They may also include a forced continuous conduction mode (CCM) function that allows negative current to flow into the internal low-side switch. Some POL ICs include discontinuous conduction mode (DCM) under light load conditions to improve efficiency by preventing negative current. Typically, a POL IC detects negative current in the inductor by sensing the voltage drop in the low-side switch. Once the POL IC detects a negative voltage drop, the switch is turned off to prevent negative current from flowing into it. On the other hand, if a POL IC is used in an isolated half-bridge converter, the inductor current flow is negative in each cycle. If the POL IC includes a DCM function, preventing negative current through DCM control would cause the converter to malfunction. Based on the feedback signal of the output voltage, the non-resonant buck POL IC can regulate the output voltage by changing the duty cycle of the internal high-side power switch and the internal low-side power switch. An example of a usable non-resonant buck POL IC is the Texas Instruments TLV62568A, as described in its datasheet: Texas Instruments, "TLV6256xA 1-A, 2-A Buck Converter in SOT563 Package with Forced PWM Mode," revised March 2020, page 23, the entire contents of which are incorporated herein by reference. IC U1 and IC U2 do not need to include pulse frequency modulation (PFM) control under light load (or the ability to disable PFM control), pulse frequency hopping mode, or any light load efficiency enhancement features.

[0034] exist Figure 2In each half-bridge circuit, the feedback terminal FB is connected to the switch output terminal SW via a voltage sensing circuit that may include a voltage divider defined by resistors R6, R7 or R26, R27, wherein resistors R6, R26 may be connected directly to the switch output terminal SW and before any inductor or transformer winding receiving the output of the switch output terminal SW. The voltage divider defined by resistors R6, R7 or R26, R27 maintains the average voltage at the switch output terminal SW, thereby keeping the voltage at the feedback terminal FB constant. IC U1, IC U2 may include an internal operational amplifier (OP amp) (not shown) comprising a positive terminal connected to a reference voltage and a negative terminal connected to the node between resistors R6, R7 or R26, R27 via the feedback terminal FB. When the reference voltage applied to the positive terminal is the same as the voltage applied to the feedback terminal at the negative terminal, the positive and negative terminals of the internal OP amp can be considered virtually short-circuited. Connecting the feedback terminal FB to the switch output terminal SW enables the 50% duty cycle operation required for resonant operation. A precise 50% duty cycle is not required. An approximate 50% duty cycle (e.g., 47.5%–52.5%) can still be used to achieve resonant operation. Resonant operation avoids instability problems caused by LC filters with smaller gain and phase margins in the control loop, typically defined by the primary winding P1 and capacitor C5 or by the primary winding P2 and capacitor C25. LC filters defined by the primary winding P1 and capacitor C5 or by the primary winding P2 and capacitor C25 include a 180° phase shift and increased gain at the resonant frequency. If the gain of an LC filter defined by the primary winding P1 and capacitor C5 or by the primary winding P2 and capacitor C25 is too large at the 180° phase shift, the converter may oscillate. Using... Figure 2The non-resonant buck POL IC shown can eliminate or significantly reduce the influence of the LC filter defined by the primary winding P1 and capacitor C5, or by the primary winding P2 and capacitor C25, on the control of the converter. The switching frequency of IC U1 can be matched to the resonant frequency of the resonant circuit defined by the leakage inductance of the primary winding P1 and the capacitance of capacitor C5 by adjusting the values ​​of the leakage inductance of the primary winding P1 and the capacitance of capacitor C5. Similarly, the switching frequency of IC U2 can be matched to the resonant frequency of the resonant circuit defined by the leakage inductance of the primary winding P2 and the capacitance of capacitor C25 by adjusting the values ​​of the leakage inductance of the primary winding P2 and the capacitance of capacitor C25. The feedback terminal FB of IC U1 can be connected to the switch output terminal SW. The voltage across capacitor C5 is approximately 5V within manufacturing and / or measurement tolerances, and the output current Iout is approximately 0.2A within manufacturing and / or measurement tolerances. Similarly, the feedback terminal FB of IC U2 can be connected to the switch output terminal SW. The voltage across capacitor C25 is approximately 5V within manufacturing and / or measurement tolerances, and the output current Iout is approximately 0.2A within manufacturing and / or measurement tolerances. Within these tolerances, the load regulation of the second stage can be improved by approximately 12%.

[0035] The clock or synchronization terminal CLK of IC U1 and IC U2 in the second stage can be connected to the clock or synchronization terminal CLK of IC U3 in the first stage to synchronize the frequency and phase of the half-bridge circuit.

[0036] The signal from the switch output terminal SW can also be used instead of the signal from the clock or synchronization terminal CLK of IC U3. The signal provided by the switch output terminal SW is switched on and off at a specific frequency, and it can provide the same or similar information as the signal from the clock or synchronization terminal CLK. For example, the logic circuit connected to the clock or synchronization terminal CLK of IC U1 and IC U2 can withstand voltages up to approximately 5V. If the voltage of the signal provided by the switch output terminal SW does not exceed 5V, the switch output terminal SW of U3 can be directly connected to the clock or synchronization terminal CLK of IC U1 and IC U2. If the voltage of the signal provided by the switch output terminal SW sometimes exceeds 5V, a voltage divider can be used to reduce the voltage of the switch output terminal SW of U3, so that the reduced voltage can be connected to the clock or synchronization terminal CLK of IC U1 and IC U2.

[0037] The secondary side of the second stage may include rectifier diodes D2 and D5 and an output capacitor C1. The anode of diode D2 can be connected to one end of the secondary winding S1. The other end of the secondary winding S1 can be connected to one end of the secondary winding S2 to define a tap. The anode of diode D5 can be connected to the other end of the secondary winding S2. One end of the output capacitor C1 can be connected to the cathodes of diodes D2 and D5 and the output terminal Vout+, and the other end of the output capacitor C1 can be connected to the tap between the secondary windings S1 and S2 and the output terminal Vout-.

[0038] Figure 2 The output voltage VOUT+ of the second stage can be supplied as a feedback signal FB SIGNAL to Figure 1 The first stage. The feedback signal FB SIGNAL can be supplied to the feedback terminal FB of IC U3 to control the voltage supplied by the switch output terminal SW.

[0039] Figure 1 The converter can be used as a pre-regulator and Figure 2 The first stage can be used in conjunction with the second stage. The first stage can be used to reduce fluctuations in the input voltage supplied to the second stage. The first stage includes an IC U3 containing one or more power switches. IC U3 includes an input voltage terminal VIN; an enable terminal EN that turns IC U3 on when a voltage is applied and turns IC U3 off when no voltage is applied; a switch output terminal SW connected to the output of one or more power switches; a feedback terminal FB; a bootstrap terminal BST that can be connected to the switch output terminal SW via a capacitor C9; a clock or synchronization terminal CLK; and a ground terminal GND.

[0040] The first stage may include input terminals Vin+ and Vin- for receiving input voltage, and output terminals +input and -input connected to the second stage. Input terminals Vin+ and Vin- are connected to input capacitor C4. The first terminal of input terminal Vin+ and input capacitor C4 can be connected to the input voltage terminal VIN, and can be connected to the enable terminal EN via resistor R5. The second terminal of input terminal Vin+ and input capacitor C4 can be connected to the ground terminal GND and the output terminal -input. The switch output terminal SW can be connected to the output capacitor C2 and the output terminal +input via inductor L1. The feedback terminal FB can be connected to the output voltage terminal VOUT+ of the second stage via a voltage divider defined by resistors R13 and R18, which are connected in series between the output voltage terminal VOUT+ of the second stage and the input terminal VIN- of the first stage. Although... Figure 1 and Figure 2Although not shown, the connection between the feedback terminal FB of U3 and the output voltage terminal VOUT+ of the second stage can include an isolator. Any suitable isolator can be used. Figure 11 An example of an isolator is shown in the figure.

[0041] Figure 11 The isolator in the circuit includes an optocoupler U4 connected between the feedback terminal FB of U3 and the output voltage terminal VOUT+ of the second stage to provide isolation. A voltage divider defined by resistors R14 and R17 connected in series across the output voltage Vout+ and ground determines the output voltage Vout+ at the reference terminal R of the parallel regulator U5. Circuit operation can be stabilized using a compensation circuit including capacitor C12 connected in series between the cathode terminal K of the parallel regulator U5 and the node between resistors R14 and R17, and resistor R14. The current through resistor R16 can be regulated using a regulator circuit including resistors R11 and R12. The current through resistor R16 is limited by the gain of optocoupler U4, and the LED current of optocoupler U4 is determined by resistors R11 and R12 in the regulator circuit. Resistor R16 is connected to the second stage +input (i.e., the first stage +output) controlled by the feedback terminal FB of IC U3.

[0042] As explained above, the clock or synchronization terminal CLK of IC U3 can be connected to the clock or synchronization terminal CLK of IC U1 and IC U2.

[0043] IC U3 can be a step-down IC. IC U3 can accept a wide range of input voltages (e.g., from approximately 4.5V to approximately 24V within manufacturing and / or measurement tolerances) and can provide a fixed output voltage to the second stage (i.e., a fixed input voltage received by the second stage), allowing the second stage to maintain a 50% duty cycle, thus enabling resonant operation in the second stage. Allowing the second stage to maintain a 50% duty cycle eliminates the need for line adjustments in the second stage and enables a constant output voltage with a wide input voltage range. Furthermore, the output voltage accuracy can be set by adjusting both the transformer turns ratio and the output voltage of the second stage. The output voltage of the first stage (i.e., the input voltage of the second stage) can be precisely set by a voltage divider defined by resistors R13 and R18. Resistors R6 and R7 in the second stage can be adjusted according to the input voltage of the second stage to maintain a 50% duty cycle and thus achieve resonant operation.

[0044] The converters discussed above can use different primary and secondary circuits. Figures 4 to 10 Different examples of secondary and primary circuits that can be used are shown. Any combination of these primary and secondary circuits can be used in the converters discussed above. Additionally, Figures 4 to 8 The diodes in the circuit can be replaced with field-effect transistors (FETs) to improve efficiency.

[0045] Figure 4 The secondary circuit of a full-bridge rectifier with connections to the secondary winding S1 and the output capacitor C1 is shown. The full-bridge rectifier is defined by diodes D1, D2, D3, and D4. Resistor R1 represents the load. Figure 5 It shows the relationship with Figure 4 The secondary circuit is similar to that of the inductor L1, but the full-bridge rectifier is connected to the inductor L1. The cathodes of diodes D1 and D2 are connected to the inductor L1.

[0046] Figure 6 The secondary circuit is shown, including capacitors C10 to C13 arranged as a quaternary voltage multiplier and diodes D5 to D8. The quaternary voltage multiplier is connected to the output capacitor C1. Resistor R1 represents the load. Figure 7 The secondary circuit is shown, including capacitors C10 and C11 and diodes D5 and D6 arranged as a voltage doubler circuit. The voltage doubler circuit is connected to the output capacitor C1. Figure 8 The secondary circuit is shown, including capacitors C6 and C7 arranged as another voltage doubler circuit and diodes D1 and D3. Since only one capacitor is used, therefore... Figure 8 Compare Figure 7 It includes one less component, but when diode D3 is on, current only flows to capacitor C6. In contrast, Figure 7 This includes an additional capacitor, but when diode D5 is turned on, current flows not only into capacitor C11 but also out of capacitor C10. Therefore, Figure 7 The voltage multiplier circuit is more powerful than Figure 8 Double the pressure compared to Figure 8 It has twice the pressure, making it more expensive but more efficient.

[0047] Figure 9 The primary circuit of the second stage of a converter with a capacitive voltage divider is shown. The capacitive voltage divider includes capacitors C5 and C6 connected in series and across the input terminals +input and -input. The node between capacitors C5 and C6 is connected to the primary winding P1. When the low-side switch in IC U1 is turned on, current is received from both capacitors C5 and C6, rather than just from capacitor C5. Current sharing between capacitors C5 and C6 improves efficiency. Figure 10 It shows the relationship with Figure 9 The primary circuit of the second stage of the converter is similar to the primary circuit of the primary circuit in the converter. Figure 10 The primary circuit also includes a node connected between capacitors C5 and C6 and a resonant capacitor C3 for the primary winding P1.

[0048] It can be used with any boost converter technology, including, for example, LED boost converters and wireless charging technology. Figure 3 The converter in the middle.

[0049] It should be understood that the foregoing description is merely illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention. Accordingly, the invention is intended to encompass all such alternatives, modifications, and variations falling within the scope of the appended claims.

Claims

1. A converter, comprising: First input terminal and second input terminal; The first stage is connected to the first input terminal and the second input terminal, and includes a first-stage integrated circuit IC, wherein the first-stage IC includes a feedback terminal; The first half-bridge circuit and the second half-bridge circuit are connected in parallel and receive the input voltage from the first stage. Each of the first half-bridge circuit and the second half-bridge circuit includes a half-bridge IC that receives a clock signal from the first stage. Transformers, including: Single magnetic core; A first primary winding extends around the single magnetic core and is connected to the first half-bridge circuit; A second primary winding extends around the single magnetic core and is connected to the second half-bridge circuit; and The secondary winding extends around the single magnetic core; A rectifier is connected to the secondary winding; The first output terminal and the second output terminal are connected to the rectifier; and A feedback circuit is connected between the first output terminal and the feedback terminal of the first-stage IC.

2. The converter according to claim 1, wherein The half-bridge IC is a non-resonant buck point-of-load IC that receives the input voltage from the first stage and includes a feedback terminal and a switching output terminal; and The voltage sensing circuit is connected to the feedback terminal of the half-bridge IC and the switching output terminal of the half-bridge IC.

3. The converter according to claim 2, wherein The voltage sensing circuit includes a voltage divider defined by a first resistor and a second resistor connected in series with each other; The first resistor is directly connected to the switch output terminal of the half-bridge IC; and The node between the first resistor and the second resistor is connected to the feedback terminal of the half-bridge IC.

4. The converter according to claim 2, wherein, The signal received from the voltage sensing circuit by the feedback terminal of the half-bridge IC causes the half-bridge IC to provide a 50% duty cycle or approximately 50% duty cycle.

5. The converter according to any one of claims 1 to 4, wherein, The first stage is a buck converter.

6. The converter according to any one of claims 1 to 4, wherein, The first-stage IC includes a switch output terminal that provides the input voltage.

7. The converter according to any one of claims 1 to 4, wherein, The feedback circuit includes an isolator, an optocoupler, or a signal isolator.

8. The converter according to any one of claims 1 to 4, wherein, The rectifier includes a full-bridge rectifier, a doubler circuit, or a quadrupler circuit.

9. The converter according to any one of claims 1 to 4, wherein, The magnetic core has a ring, rectangular, elliptical or EI-shaped shape.

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