A low-inductance motor low-torque ripple control method based on dual-core function DSP

Abstract

The application discloses a low-inductance motor low-torque ripple control method based on a dual-core function DSP, relates to the technical field of low-inductance motor control, and relies on a main core of the dual-core function DSP and a CLA coprocessor function isolation division architecture, so that the main core only executes low-frequency overall tasks such as system initialization, bus communication and fault protection, the CLA coprocessor independently completes high-frequency operation of the whole motor control process, operation resources are completely isolated, the problem of operation congestion and interruption overflow is avoided from the root, 100kHz high-frequency PWM carrier frequency is determined in combination with the electrical bandwidth characteristics of the motor, the electrical bandwidth of 5k-15kHz of the low-inductance motor is accurately matched, the control signal can track the rapid change of the motor speed and current in real time, the motor driving jitter problem caused by insufficient carrier frequency is solved, and the carrier frequency comprehensively balances the motor control demand and power module loss, so that high-frequency stable control can be realized without additional improvement of chip computing power.

Description

Technical Field

[0001] This invention relates to the field of low-inductance motor control technology, specifically to a low-torque ripple control method for low-inductance motors based on a dual-core DSP. Background Technology

[0002] Low-inductance motors are widely used in high-end equipment due to their compact structure, low moment of inertia, and fast response speed. However, their inherent characteristics result in a very high rate of current change, which easily generates large current ripple. This leads to motor torque pulsation and increased operating noise, reducing motor stability and lifespan, and also affecting control accuracy. Existing servo drives are mostly general-purpose designs, primarily developed for high-inductance ordinary motors, and are not optimized for low-inductance characteristics, resulting in the following technical challenges: First, the electrical bandwidth of low-inductance motors is generally between 5k-15kHz, while the carrier frequency of existing servo drives is relatively low, making it impossible to track the rapid changes in speed and current of low-inductance motors in a timely manner, resulting in severe motor jitter. Increasing the control frequency is an effective way to reduce ripple, but the high-frequency operation that results in this is prone to competing for computing resources, leading to problems such as computational congestion, interrupt overflow, and control delay. Moreover, the computing power of the control chip is actually limited, so it is difficult to significantly increase the carrier frequency in engineering.

[0003] Second, existing control methods mostly employ software scheduling to trigger sampling and loop calculations. Software scheduling has inherent delays and cannot match the control requirements of rapid current changes in low-inductance motors, further exacerbating torque ripple and reducing control accuracy, thus becoming a key bottleneck restricting high-precision control of low-inductance motors.

[0004] Therefore, there is an urgent need for a control solution that addresses the core pain points of low-inductance motors, thereby reducing control delay and suppressing current ripple, and enabling smooth torque pulsation output from the motor. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a low-torque pulsation control method for low-inductance motors based on a dual-core DSP. This method addresses the issues of mismatch between the carrier frequency of existing servo drives and the electrical bandwidth of low-inductance motors, as well as the resource contention caused by high-frequency computation. It utilizes a functionally isolated architecture between the main core and the CLA coprocessor of the dual-core DSP. The main core performs only low-frequency tasks such as system initialization, bus communication, and fault protection, while the CLA coprocessor independently completes the high-frequency computation of the entire motor control process. This achieves complete isolation of computational resources, fundamentally avoiding computational congestion and interrupt overflow problems. Simultaneously, a 100kHz high-frequency PWM carrier frequency is determined based on the motor's electrical bandwidth characteristics, precisely matching the 5kHz-15kHz electrical bandwidth of the low-inductance motor. This allows the control signal to track rapid changes in motor speed and current in real time, completely resolving the motor drive jitter problem caused by insufficient carrier frequency. Furthermore, this carrier frequency comprehensively balances motor control requirements and power module losses, achieving stable high-frequency control without requiring additional chip computing power.

[0006] To solve the above-mentioned technical problems, this invention provides the following technical solution: a low-torque ripple control method for low-inductance motors based on a dual-core DSP, the specific steps of which are as follows: The steps of this method are as follows: S100: After the system is powered on and started, the main core of the dual-core DSP independently completes the initialization configuration of the hardware parameters and software programs of the entire system, establishing a unified hardware and software operating foundation for the system. After initialization, S200 is constructed to establish a parallel operation mechanism in which the main core of the dual-core DSP and the control law accelerator CLA coprocessor are completely isolated from each other, and the dedicated task boundaries of the main core and the CLA coprocessor are clearly defined, and the computing resources are completely isolated and called in parallel. The S300 and CLA coprocessors control the ePWM module of the dual-core DSP to generate a high-frequency PWM carrier signal that matches the electrical characteristics of the low-inductance motor. At the same time, the original dead-time compensation function of the ePWM module is enabled, and the matching dead-time parameters are configured to suppress current spikes and current ripples caused by the high current change rate of the low-inductance motor. The S400's cascaded hardware triggering mechanism, through the hardware logic execution of the dual-core DSP, triggers linkage without software scheduling intervention, achieving full synchronization of sampling, carrier, and loop control. After the S500 and CLA coprocessors complete the loop control calculations, they generate corresponding control signals, which are then converted into precise three-phase PWM drive signals by the ePWM module and output to the motor drive module. The motor drive module drives the low-inductance motor to run smoothly. The S600 control module's signal sampling and conditioning circuit collects real-time parameter signals such as the position of the low-inductance motor, and also collects current, voltage, and temperature signals from the motor drive module. The conditioned signals are then fed back to the main core to perform full-link monitoring of the low-inductance motor. S700: The main core checks whether it has received a run-end instruction from the host computer. If no run-end instruction is received, the main core continues to execute low-frequency, general-purpose tasks and loops back to S200 to continue execution. If a run-end instruction is received, the main core sends a stop instruction to the CLA coprocessor, controlling the CLA coprocessor to stop outputting control signals and controlling the system to stop in an orderly manner.

[0007] Furthermore, in S100, the initialization configuration includes: The AD sampling module is initialized, and the sampling channels, sampling accuracy, sampling triggering methods and sampling parameter ranges are configured, covering all parameter sampling configurations required for motor control and fault detection. ePWM module initialization, configuring the ePWM module's operating mode, counting period, output pin mapping, dead time, and triggering method, etc.; CLA coprocessor initialization: Configure the CLA coprocessor's control task mapping, running permissions, trigger sources, and memory space allocation, enabling the CLA coprocessor to have the hardware and software foundation for independent operation; Communication protocol initialization: Configure the communication parameters, data frame format, and interaction logic of the bus communication protocol integrated by the dual-core DSP, and complete the communication link configuration with the host computer.

[0008] Furthermore, in S200, the working principle of the parallel task mechanism is as follows: After the S100 system initialization configuration is completed, the main core of the dual-core DSP and the CLA coprocessor enter a completely isolated parallel running state, and perform data interaction through the shared memory of the dual-core DSP, without cross-occupancy of computing resources, wherein: The main core only undertakes low-frequency, overall planning tasks of the system. It communicates with the host computer via a communication interface module to receive instructions and upload status information. It processes data from the signal sampling and conditioning circuit in real time and continuously performs full-link fault protection tasks. It does not participate in any real-time calculations or execution operations of the low-inductance motor control. The CLA coprocessor, as the sole independent core for real-time control of low-inductance motors, independently undertakes high-frequency real-time dedicated tasks for low-inductance motor control, including motor running state machine management, three-level closed-loop control calculations of current loop, speed loop, and position loop, ePWM module control, and the entire process of control signal generation and output. It fully leverages the high-speed floating-point computing power of the CLA coprocessor and avoids high-frequency calculations from competing for system computing resources.

[0009] Furthermore, in S300, the method for determining the high-frequency PWM carrier frequency is as follows: Based on the stator resistance and stator inductance parameters of the low-inductance motor, the electrical bandwidth of the low-inductance motor is calculated. For low-inductance motors with an inductance value range of 30uH-300uH, the electrical bandwidth range is 5kHz-15kHz. According to the matching criterion that the carrier frequency is 5-10 times the electrical bandwidth, the carrier frequency is set to ≥50kHz. Considering the current ripple suppression requirements of the low-inductance motor, the switching loss limitation of the power module, and the hardware computing power of the dual-core DSP, the preferred high-frequency PWM carrier frequency is 100kHz, which satisfies the control requirements for torque ripple suppression of the low-inductance motor and keeps the switching loss of the power module within a reasonable range.

[0010] Furthermore, in S300, the working principle of the original dead-time compensation function is as follows: When the CLA coprocessor starts the ePWM module to generate a high-frequency PWM carrier signal, it enables the original dead-time compensation function built into the ePWM module of the dual-core DSP, configuring the dead time to be 50ns. The original dead-time compensation function inserts a matching dead time at the rising and falling edges of the PWM carrier signal through hardware logic to avoid shoot-through short circuit faults in the power switching devices of the upper and lower arms of the three-phase H-bridge of the motor drive module. At the same time, it compensates for the voltage output error caused by the dead time for the extremely high current change rate of the low-inductance motor under the high-frequency PWM carrier, thereby suppressing current distortion and current ripple from the root and reducing the torque pulsation of the low-inductance motor.

[0011] Furthermore, the working principle of the cascading hardware triggering mechanism in the S400 is as follows: The high-frequency PWM carrier signal generated by the ePWM module triggers the AD sampling module to start synchronous sampling through hardware pins. The sampling frequency is consistent with the high-frequency PWM carrier frequency, realizing hardware-level synchronization between AD sampling and PWM carrier. The sampling objects of the AD sampling module include the core operating parameters of the low-inductance motor, such as the three-phase current, bus voltage, power module temperature, and motor winding temperature. After the AD sampling module completes the sampling of all parameters, it sends a hardware trigger signal to the CLA coprocessor, which then starts the CLA coprocessor to execute the three-level closed-loop control operation of current loop, speed loop, and position loop. The entire process is carried out without any software scheduling intervention, relying entirely on the hardware logic of the dual-core DSP to achieve trigger linkage. This compresses the control delay from sampling to operation to less than 1μs, completely eliminating the inherent control delay caused by software scheduling and ensuring that the control signal can track the rapid current changes of the low-inductance motor in real time.

[0012] Furthermore, the execution flow of the three-level closed-loop control operation of the current loop-velocity loop-position loop is as follows: After receiving the hardware trigger signal, the CLA coprocessor executes three-level closed-loop control operations in the order of current loop, speed loop, and position loop. The current loop operation is performed, comparing the three-phase current parameters of the motor collected by the AD sampling module with the current setpoint, and generating a voltage control quantity through the PI regulator. The operation period of the current loop is consistent with the period of the high-frequency PWM carrier signal. The speed loop operation compares the real-time motor speed feedback value with the speed setpoint, and generates the current setpoint for the current loop through the PI regulator. The operation period of the speed loop is an integer multiple of the high-frequency PWM carrier period. The position loop operation is performed, comparing the real-time position feedback value of the motor with the position setpoint, and generating the speed setpoint value of the speed loop through the PI controller. The operation cycle of the position loop is an integer multiple of the operation cycle of the speed loop. After the calculation is completed, the CLA coprocessor generates the final control signal, which is used to generate the PWM drive signal.

[0013] Furthermore, the process of precise drive and closed-loop operation of the S500 motor is as follows: After the CLA coprocessor completes the three-level closed-loop control operation and generates the control signal, it performs space vector pulse width modulation calculation and converts the control signal into a three-phase PWM drive signal with the corresponding duty cycle. The CLA coprocessor transmits the three-phase PWM drive signal to the ePWM module through the control module, and outputs the three-phase PWM drive signal to the motor drive module through the output pin of the ePWM module; The motor drive module controls the on / off state of the three-phase H-bridge power switching devices based on the received three-phase PWM drive signal, and outputs the corresponding three-phase AC power to the low-inductance motor to drive the low-inductance motor to run.

[0014] Furthermore, the end-to-end fault protection task includes: the main core obtains the end-to-end operating parameters collected by the AD sampling module in real time through shared memory, and continuously monitors the abnormal states of the system such as overcurrent faults, overvoltage faults, overheating faults, and motor stall faults; when any fault state is detected, the main core sends a fault stop command to the CLA coprocessor. After receiving the fault stop command, the CLA coprocessor stops the output of the PWM drive signal, shuts down all power switching devices of the motor drive module, and executes the system's fast fault protection. At the same time, the main core uploads the fault code and fault parameters to the host computer through bus communication to complete the reporting and recording of the fault state.

[0015] Furthermore, the dual-core DSP includes, but is not limited to, DSP chips with a "main core + CLA" architecture.

[0016] Furthermore, the communication protocol includes either CAN communication or EtherCAT bus communication.

[0017] Compared with existing technologies, this low-torque ripple control method for low-inductance motors based on a dual-core DSP has the following advantages: I. This invention relies on a functionally isolated architecture between the main core of a dual-core DSP and the CLA coprocessor. The main core performs only low-frequency tasks such as system initialization, bus communication, and fault protection, while the CLA coprocessor independently completes the high-frequency calculations for the entire motor control process. This achieves complete isolation of computing resources, fundamentally avoiding computational congestion and interrupt overflow issues. At the same time, a 100kHz high-frequency PWM carrier frequency is determined based on the electrical bandwidth characteristics of the motor, precisely matching the 5k-15kHz electrical bandwidth of the low-inductance motor. This allows the control signal to track the rapid changes in motor speed and current in real time, completely solving the motor drive jitter problem caused by insufficient carrier frequency. Furthermore, this carrier frequency comprehensively balances the motor control requirements and power module losses, achieving high-frequency stable control without additional chip computing power.

[0018] II. This invention employs a cascaded hardware triggering mechanism that uses PWM hardware to trigger synchronous AD sampling and AD conversion to trigger CLA loop control. The entire triggering and linkage is achieved through DSP hardware logic without any software scheduling intervention, completely eliminating the control delay caused by software scheduling. This ensures full synchronization between sampling, carrier, and loop control. Simultaneously, it utilizes the ePWM dead-time compensation function of the dual-core DSP to insert precise dead time into the high-frequency PWM carrier signal, compensating for voltage output errors caused by dead time. This fundamentally suppresses current ripple caused by the high current change rate of low-inductance motors, solving the problems of torque pulsation and reduced control accuracy caused by the superposition of current ripple and control delay. This allows the control signal to accurately follow the rapid dynamic changes of motor current.

[0019] Third, this invention utilizes the hardware characteristics of a dual-core DSP to create a dedicated control scheme. The main core and the CLA coprocessor run in parallel and interact with each other through shared memory. This fully leverages the high-speed floating-point operation advantage of the CLA coprocessor, ensuring the continuity and stability of high-frequency motor control operations. Simultaneously, the main core can acquire motor operating parameters in real time, enabling full-link fault monitoring and rapid protection. This scheme requires no additional high-frequency drive, computation acceleration, or other hardware modules; all functions can be achieved solely through the DSP's built-in hardware resources. It also reduces the overall computing power requirements of the control chip. While addressing the core pain points of low-inductance motor control, it balances the engineering practicality and economy of the solution, adapting to high-precision control scenarios for various low-inductance motors and solving the problem of poor compatibility with general-purpose drivers.

[0020] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0022] Figure 1 This is a schematic diagram of the motor control hardware based on a dual-core DSP in an embodiment of the present invention; Figure 2 This is a block diagram showing the task division between the main core and CLA of the dual-core DSP in this embodiment of the invention; Figure 3 This is a flowchart of the motor control program based on a dual-core DSP in an embodiment of the present invention; In the diagram: 1. Control module; 2. Motor drive module; 3. Low inductance motor; 11. DSP; 12. Signal sampling and conditioning module; 13. Communication interface module; 14. Power supply module. Detailed Implementation

[0023] To better understand the above technical solutions, a detailed description of the solutions will be provided below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] To address the shortcomings of existing technologies in low-inductance motor control, such as the mismatch between carrier frequency and electrical bandwidth, inherent delays in software scheduling and triggering, and large current ripple caused by high-frequency computation preempting resources, this invention provides a low-torque ripple control method for low-inductance motors based on a dual-core DSP. This method utilizes a three-dimensional linkage logic—dual-core functional isolation and division of labor, coordinated high-frequency carrier and dead-time compensation, and fully synchronized hardware cascade triggering—to enable the control signal to track rapid current changes in the low-inductance motor in real time. This fundamentally suppresses current ripple, completely eliminates control delay, and achieves precise drive and stable operation of the low-inductance motor. This invention is primarily applied to high-precision control scenarios for low-inductance motors, such as coreless motors, and is suitable for fields with extremely high requirements for motor operational stability and control precision, such as precision manufacturing, aerospace, industrial robots, and high-end servo equipment. In these scenarios, the inherent characteristics of low-inductance motors result in extremely high current change rates. Traditional general-purpose servo drives are not optimized for low-inductance characteristics and cannot match the rapid changes in current and speed of the motor. This invention achieves complete isolation of computing resources by dividing tasks between the main core of a dual-core DSP and the CLA coprocessor. It sets a 100kHz high-frequency PWM carrier and enables ePWM original life and death zone compensation. It designs a hardware cascade triggering mechanism to achieve full synchronization of sampling, carrier and loop control, and builds a complete control system from system initialization, dual-core parallel operation to motor closed-loop drive and status monitoring.

[0025] This embodiment provides a low-torque ripple control method for low-inductance motors based on a dual-core DSP. It relies on a dual-core DSP chip with a main core and a control law accelerator (CLA) coprocessor. In this embodiment, the dual-core DSP chip is a DSP chip with a "main core + CLA" architecture, preferably the TMS320F28379D (F28379D) from Texas Instruments (TI). This chip integrates dual C28x cores and an independent CLA coprocessor, and features multiple high-synchronization ePWM modules, a 16-bit high-precision AD sampling module, and a multi-protocol bus communication interface. Other DSP chips with a core + CLA architecture are also available. In this embodiment, the low-inductance motor is preferably a coreless permanent magnet synchronous motor. The stator inductance of this type of motor ranges from tens to hundreds of μH, typically between 30 μH and 300 μH, making it a typical low-inductance motor widely used in high-precision servo drive scenarios.

[0026] The hardware architecture of the control system upon which this invention is based is as follows: Figure 1As shown, the control system includes a control module 1 and a motor drive module 2, forming a hardware link for core computation and power drive, jointly controlling the low-inductance motor 3. The control module 1, motor drive module 2, and low-inductance motor 3 are electrically connected in sequence. The control module 1 uses a dual-core DSP 11 as its core computational carrier and also integrates a signal sampling and conditioning circuit 12, a communication interface module 13, and a power supply module 14. The input terminals of the signal sampling and conditioning circuit 12 are electrically connected to the signal output terminals of the motor drive module 2 and the low-inductance motor 3, respectively, and the output terminal is electrically connected to the AD sampling pin of the dual-core DSP 11. This circuit collects operating parameters of the low-inductance motor 3, such as three-phase current, bus voltage, power module temperature, and motor winding temperature, and performs signal filtering, level matching, and other conditioning processes before transmitting the data to the dual-core DSP 11. The communication interface module 13 is electrically connected to the communication pin of the dual-core DSP 11 and also communicates with the host computer. The power supply module 14 is connected to the components in the control module 1 and the motor drive module 2, respectively, to provide a stable power supply for the entire system. The motor drive module 2 adopts a three-phase H-bridge power topology, and its power switching device preferably adopts gallium nitride (GaN) power transistors to adapt to the switching requirements of 100kHz high-frequency PWM carrier. Its control input terminal is electrically connected to the ePWM output pin of the dual-core DSP 11, and its power output terminal is electrically connected to the three-phase stator winding of the low-inductance motor 3, which is used to convert the PWM drive signal output by the dual-core DSP into three-phase AC power to drive the low-inductance motor 3.

[0027] The functional division of labor and parallel operation mechanism of the main core and CLA coprocessor of the dual-core DSP constructed in this invention is as follows: Figure 2 As shown, the two adopt a fully isolated parallel operation architecture, clearly defining dedicated task boundaries to achieve complete isolation and parallel access to computing resources, without cross-occupancy of computing resources. The main core of the dual-core DSP only undertakes low-frequency, system-wide coordination tasks, including system-wide hardware and software initialization configuration, bus communication with the host computer, and end-to-end operational status monitoring and fault protection. It does not participate in any real-time calculations or execution operations related to the low-inductance motor control. The CLA coprocessor, as the sole independent core for real-time control of the low-inductance motor, independently undertakes high-frequency, real-time tasks, including high-frequency PWM carrier signal generation, ePWM module parameter configuration, motor operating state machine management, three-level closed-loop control calculations (current loop, speed loop, and position loop), space vector pulse width modulation (SVPWM) calculation, and the entire process of control signal generation and output. This fully leverages the CLA coprocessor's single-cycle 32-bit high-speed floating-point computing power, avoiding high-frequency computation from preempting system computing resources.

[0028] The following combination Figure 3 The flowchart shown below provides a detailed explanation of the specific implementation steps of the control method of the present invention: System Initialization: After the system powers on, the main core of the dual-core DSP independently completes the initialization configuration of all system hardware parameters and software programs, establishing a unified hardware and software foundation for system operation. This initialization configuration is entirely completed independently by the main core; the CLA coprocessor remains in a waiting-to-start state during this step to avoid computational resource conflicts during initialization. The initialization configuration specifically includes: The AD sampling module is initialized. The main core configures the number of sampling channels, sampling accuracy, hardware-triggered synchronous sampling method, sampling parameter range and sampling filter parameters of the AD sampling module. At the same time, the sampling trigger source is configured as the hardware trigger signal of the ePWM module, and the software trigger permission is disabled to ensure that the sampling action is triggered only by hardware logic, covering all parameter sampling configurations required for motor control and fault detection. The ePWM module is initialized, and the main core configures key parameters such as the ePWM module's counting mode, PWM period, duty cycle, synchronization, dead time, and triggering. This ensures that the low-inductance motor control requirements are met and the hardware system is safe. It also enables synchronization between the ePWM module, ADC, and interrupts, allowing the entire control system to work together efficiently and accurately.

[0029] The CLA coprocessor is initialized, and the main core configures the CLA coprocessor's control task mapping, independent running permissions, hardware trigger source, and memory space allocation. Specifically, the real-time tasks of motor closed-loop control, ePWM module configuration, and PWM signal generation are mapped to the dedicated program storage space of the CLA coprocessor. The trigger source of the CLA coprocessor is configured as the sampling completion hardware signal of the AD sampling module. At the same time, dedicated local data memory and shared memory are allocated. The local data memory can only be accessed by the CLA coprocessor and is used to store intermediate data of real-time calculation. The shared memory can be accessed bidirectionally by the main core and the CLA coprocessor for the interaction of running parameters and instruction data between the two, so that the CLA coprocessor has the hardware and software foundation to run independently. Communication protocol initialization, main core configuration of dual-core DSP integrated CAN bus communication protocol communication baud rate, data frame format, interaction logic and fault retransmission mechanism.

[0030] The main core performs routine tasks: After initialization, the main core and the CLA coprocessor enter a completely isolated parallel running state. They interact via shared memory, with no cross-occupancy of computing resources. In this routine running state, the main core only executes low-frequency, coordination-specific tasks, including: The system interacts with the host computer via a communication interface module, receiving real-time control data such as running commands, speed / position setpoints, and end-of-run commands from the host computer. Simultaneously, it uploads real-time operating parameters of the low-inductance motor, system operating status, and fault codes to the host computer. It also acquires analog signals such as voltage and current collected by the AD sampling module in real-time through shared memory, continuously executing full-link fault protection tasks. Throughout the process, it does not participate in any real-time calculations or execution operations for the low-inductance motor control, thus avoiding interference from high-frequency real-time calculations on the main core's overall task management.

[0031] The CLA coprocessor starts running independently, serving as the sole independent core for real-time control of low-inductance motors. It begins executing high-frequency real-time dedicated tasks such as loop control, establishing the operational foundation for subsequent motor drive modules to control low-inductance motors.

[0032] High-frequency PWM in the ePWM module: After the CLA coprocessor starts, the ePWM module, which independently controls the dual-core DSP, generates a high-frequency PWM carrier signal that matches the electrical characteristics of the low-inductance motor. Simultaneously, the original dead-time compensation function of the ePWM module is enabled, and matching dead-time parameters are configured to suppress current spikes and ripples caused by the high current change rate of the low-inductance motor. The specific method for determining the high-frequency PWM carrier frequency in this step is as follows: Based on the stator resistance and stator inductance parameters of the low-inductance motor, the electrical bandwidth of the motor is calculated. Following the matching criterion that the carrier frequency should be 5-10 times the electrical bandwidth, the carrier frequency is set to ≥50kHz. Specific carrier frequencies, such as 100kHz, need to be determined comprehensively based on factors such as the current ripple suppression requirements of the low-inductance motor, the switching loss limitations of the power module, and the hardware computing power of the dual-core DSP. This ensures that the control requirements for torque ripple suppression of the low-inductance motor are met, allowing for real-time tracking of rapid changes in motor current, while also keeping the switching losses of the power module within a reasonable range.

[0033] While the CLA coprocessor starts the ePWM module to generate a high-frequency PWM carrier signal, it also enables the original dead-time compensation function built into the ePWM module of the dual-core DSP. The dead time is configured to be 50ns. The original dead-time compensation function inserts matching dead time at the rising and falling edges of the PWM carrier signal through hardware logic to avoid shoot-through short circuit faults in the power switching devices of the upper and lower arms of the three-phase H-bridge of the motor drive module. At the same time, for the extremely high current change rate of the low-inductance motor under the high-frequency PWM carrier, the hardware logic compensates for the voltage output error caused by the dead time in real time without the need for software calculation. This suppresses current distortion and current ripple at the source and reduces the torque pulsation of the low-inductance motor.

[0034] Triggering AD Sampling: A cascaded hardware triggering mechanism is constructed, in which ePWM carrier triggers AD sampling, and AD sampling completion triggers CLA loop operation. This mechanism utilizes the hardware logic of a dual-core DSP to execute the trigger linkage without any software scheduling intervention, achieving full synchronization of sampling, carrier, and loop control. The specific workflow of the cascaded hardware triggering mechanism is as follows: The high-frequency PWM carrier signal generated by the ePWM module sends a synchronization trigger signal to the AD sampling module through a hardware pin at the zero point of each carrier cycle, triggering the AD sampling module to start synchronous sampling. The sampling frequency is exactly the same as the high-frequency PWM carrier frequency, both being 100kHz, achieving hardware-level synchronization between AD sampling and the PWM carrier. The sampling objects of the AD sampling module include core operating parameters of the low-inductance motor such as three-phase current, bus voltage, power module temperature, and motor winding temperature. After sampling, the sampled data is immediately stored in shared memory for access by the main core and CLA coprocessor. After the AD sampling module completes the phase current sampling and analog-to-digital conversion of the motor drive module, it immediately sends a hardware trigger signal to the CLA coprocessor through hardware logic. This initiates the CLA coprocessor to execute the three-level closed-loop control operation of the current loop, speed loop, and position loop. The entire process is performed without any software scheduling intervention, relying entirely on the hardware logic of the dual-core DSP to achieve triggering and linkage. This compresses the control delay from sampling completion to operation initiation to less than 1μs, completely eliminating the inherent control delay caused by software scheduling and ensuring that the control signal can track the rapid current changes of the low-inductance motor in real time. In this step, the execution flow of the three-level closed-loop control operation of the current loop, speed loop, and position loop is as follows: CLA Start-up Loop Control: After receiving the hardware trigger signal, the CLA coprocessor executes three-level closed-loop control operations in the priority order of current loop, speed loop, and position loop. The current loop operation is performed. The dq axis current feedback value obtained by the three-phase phase current parameters of the motor collected by the AD sampling module after Clark transformation and Park transformation is compared with the current setpoint. The dq axis voltage control quantity is generated by the PI regulator. The operation period of the current loop is consistent with the period of the high-frequency PWM carrier signal, which is 10μs, to ensure the real-time performance of the current control. The speed loop operation compares the real-time motor speed feedback value collected by the encoder with the speed setpoint, and generates the current setpoint for the current loop through the PI regulator. The operation period of the speed loop is 10 times the high-frequency PWM carrier period, i.e., 100μs. The position loop operation compares the real-time position feedback value of the motor collected by the encoder with the position setpoint, and generates the speed setpoint value of the speed loop through the PI controller. The operation cycle of the position loop is 10 times that of the speed loop operation cycle, i.e., 1ms. After the calculation is completed, the CLA coprocessor will perform an inverse Park transformation on the dq axis voltage control quantity to generate a voltage control signal, which will be used to generate the subsequent PWM drive signal.

[0035] High-precision PWM output: After the CLA coprocessor completes the loop control calculation, it generates the corresponding control signal. This signal is then converted into a precise three-phase PWM drive signal by the space vector pulse width modulation (SVPWM) calculation and ePWM module and output to the motor drive module. The motor drive module drives the low-inductance motor to run smoothly and simultaneously feeds back the real-time operating parameters of the low-inductance motor to the main core. The specific process is as follows: After the CLA coprocessor completes the three-level closed-loop control operation to generate the control signal, it performs space vector pulse width modulation (SVPWM) calculation to convert the control signal into a three-phase PWM drive signal with the corresponding duty cycle. The CLA coprocessor transmits the three-phase PWM drive signal to the ePWM module through the internal bus of the dual-core DSP, and outputs the three-phase PWM drive signal to the motor drive module through the output pin of the ePWM module; The motor drive module controls the on / off state of the three-phase H-bridge power switching devices based on the received three-phase PWM drive signal, and outputs the corresponding three-phase AC power to the three-phase stator windings of the low-inductance motor to drive the low-inductance motor to run smoothly. At the same time, the real-time three-phase current and other operating parameters of the low-inductance motor are fed back to the dual-core DSP through the signal sampling and conditioning circuit, forming a complete closed-loop control link.

[0036] Motor operation and status monitoring: The signal sampling and conditioning circuit of the control module collects the three-phase phase current, bus voltage, power module temperature, motor winding temperature, speed, position and other operating parameter signals of the low inductance motor in real time. After the conditioned signal is converted by the AD sampling module, it is stored in the shared memory. The main core obtains the full-link operating parameters in real time through the shared memory and performs full-link monitoring of the low inductance motor and the entire system, continuously monitoring abnormal states such as overcurrent fault, overvoltage fault, overheating fault, motor stall fault and so on.

[0037] System operation status judgment and loop control: The main core checks whether it has received the operation end command from the host computer. If no operation end command is received, the main core continues to execute low-frequency general task, continuously completes bus communication, status monitoring and fault protection operations, and returns to step S200 to continue execution. The system enters the next "sampling-computation-control" closed-loop control cycle. When the operation end command is received, the main core sends a stop command to the CLA coprocessor through shared memory, controls the CLA coprocessor to stop outputting control signals, shuts off the PWM output of the ePWM module, and then shuts off all power switching devices of the motor drive module, controlling the system to stop in an orderly manner and completing the entire control process.

[0038] This embodiment, through the above steps, relies on the functionally isolated and specialized architecture of the dual-core DSP's main core and CLA coprocessor, combined with a 100kHz high-frequency PWM carrier, hardware original life and death zone compensation, and a cascaded hardware trigger full synchronization mechanism. It completely solves the core pain points of large current ripple, high control delay, computational resource contention, and prominent torque pulsation caused by the high current change rate of low-inductance motors. No additional hardware modules are required; all functions can be achieved solely by relying on the DSP's built-in hardware resources. While achieving high-precision control of low torque pulsation in low-inductance motors, it also takes into account the system's stability, economy, and engineering practicality.

[0039] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A low-torque ripple control method for a low-inductance motor based on a dual-core DSP, characterized in that, The steps of this method are as follows: S100: After the system is powered on and started, the main core of the dual-core DSP independently completes the initialization configuration of the hardware parameters and software programs of the entire system, establishing a unified hardware and software operating foundation for the system. After S200 initialization, a parallel operation mechanism for the main core of the dual-core DSP and the control law accelerator CLA coprocessor is constructed, the dedicated task boundaries of the main core and the CLA coprocessor are defined, and the computing resources are completely isolated and called in parallel. The S300 and CLA coprocessors control the ePWM module of the dual-core DSP to generate a high-frequency PWM carrier signal that matches the electrical characteristics of the low-inductance motor. At the same time, the original dead-time compensation function of the ePWM module is enabled, and the matching dead-time parameters are configured to suppress current spikes and current ripples caused by the high current change rate of the low-inductance motor. The S400's cascaded hardware triggering mechanism, through the hardware logic execution of the dual-core DSP, achieves full synchronization of sampling, carrier, and loop control. After the S500 and CLA coprocessors complete the loop control calculations, they generate corresponding control signals, which are then converted into three-phase PWM drive signals by the ePWM module and output to the motor drive module. The motor drive module drives the low-inductance motor to run. The S600 control module's signal sampling and conditioning circuit collects real-time parameter signals such as the position of the low-inductance motor, and also collects current, voltage, and temperature signals from the motor drive module. The conditioned signals are then fed back to the main core to perform full-link monitoring of the low-inductance motor. S700: The main core checks whether it has received a run-end instruction from the host computer. If no run-end instruction is received, the main core continues to execute low-frequency, general-purpose tasks and loops back to S200 to continue execution. If a run-end instruction is received, the main core sends a stop instruction to the CLA coprocessor, controlling the CLA coprocessor to stop outputting control signals and controlling the system to stop in an orderly manner.

2. The low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 1, characterized in that, In step S100, the initialization configuration includes: Initialize the AD sampling module and configure the sampling channel, sampling accuracy, sampling triggering method and sampling parameter range; ePWM module initialization, configuring the ePWM module's operating mode, counting period, output pin mapping, dead time, and triggering method, etc.; CLA coprocessor initialization: Configure the CLA coprocessor's control task mapping, running permissions, trigger sources, and memory space allocation, enabling the CLA coprocessor to have the hardware and software foundation for independent operation; Communication protocol initialization: Configure the communication parameters, data frame format, and interaction logic of the bus communication protocol integrated by the dual-core DSP, and complete the communication link configuration with the host computer.

3. The low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 1, characterized in that, In S200, the parallel task mechanism works as follows: After the S100 system initialization configuration is completed, the main core of the dual-core DSP and the CLA coprocessor enter a completely isolated parallel running state. Data interaction is performed through the shared memory of the dual-core DSP, without cross-occupancy of computing resources. The main core only undertakes low-frequency, overall planning tasks of the system. It communicates with the host computer through the communication interface module to receive instructions and upload status information via bus communication. It processes data from the signal sampling and conditioning circuit in real time and continuously performs full-link fault protection tasks. The CLA coprocessor independently undertakes high-frequency real-time dedicated tasks for low-inductance motor control, including motor operation state machine management, three-level closed-loop control calculation of current loop-speed loop-position loop, ePWM module control, and the entire process of control signal generation and output.

4. The low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 1, characterized in that, In S300, the method for determining the high-frequency PWM carrier frequency is as follows: based on the stator resistance and stator inductance parameters of the low-inductance motor, the electrical bandwidth of the low-inductance motor is calculated. For low-inductance motors with an inductance value range of 30uH-300uH, the electrical bandwidth range is 5kHz-15kHz. According to the matching criterion that the carrier frequency is 5-10 times the electrical bandwidth, the carrier frequency is set to ≥50kHz.

5. The low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 1, characterized in that, In the S300, the working principle of the original dead-live zone compensation function is as follows: while the CLA coprocessor starts the ePWM module to generate a high-frequency PWM carrier signal, it enables the original dead-live zone compensation function built into the ePWM module of the dual-core DSP, and configures the dead time to be 50ns.

6. The low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 1, characterized in that, The working principle of the cascaded hardware triggering mechanism in the S400 is as follows: The high-frequency PWM carrier signal generated by the ePWM module triggers the AD sampling module to start synchronous sampling through hardware pins. The sampling frequency is consistent with the high-frequency PWM carrier frequency. The sampling objects of the AD sampling module include the core operating parameters of the low-inductance motor, such as the three-phase current, bus voltage, power module temperature, and motor winding temperature. After the AD sampling module completes the sampling of all parameters, it sends a hardware trigger signal to the CLA coprocessor to start the CLA coprocessor to execute the three-level closed-loop control calculation of current loop-speed loop-position loop.

7. The low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 6, characterized in that, The execution flow of the three-level closed-loop control operation is as follows: After receiving the hardware trigger signal, the CLA coprocessor executes three-level closed-loop control operations in the order of current loop, speed loop, and position loop. The current loop operation is performed, and the three-phase current parameters of the motor collected by the AD sampling module are compared with the current setpoint. The voltage control quantity is generated by the PI regulator. The speed loop operation compares the real-time motor speed feedback value with the speed setpoint, and generates the current setpoint for the current loop through the PI controller. The position loop operation is performed, comparing the real-time position feedback value of the motor with the position setpoint, and generating the speed setpoint value of the speed loop through the PI controller; After the calculation is completed, the CLA coprocessor generates the final control signal, which is used to generate the PWM drive signal.

8. The low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 1, characterized in that, The working principle of the S500 is as follows: After the CLA coprocessor completes the three-level closed-loop control operation and generates the control signal, it performs space vector pulse width modulation calculation and converts the control signal into a three-phase PWM drive signal with the corresponding duty cycle. The CLA coprocessor transmits the three-phase PWM drive signal to the ePWM module through the control module, and outputs the three-phase PWM drive signal to the motor drive module through the output pin of the ePWM module; The motor drive module controls the on / off state of the three-phase H-bridge power switching devices based on the received three-phase PWM drive signal, and outputs the corresponding three-phase AC power to the low-inductance motor to drive the low-inductance motor to run.

9. A low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 3, characterized in that, The full-link fault protection task includes: the main core obtains the full-link operating parameters collected by the AD sampling module in real time through shared memory, and continuously monitors the abnormal states of the system such as overcurrent fault, overvoltage fault, overheating fault, and motor stall fault; when any fault state is detected, the main core sends a fault stop command to the CLA coprocessor. After receiving the fault stop command, the CLA coprocessor stops the output of the PWM drive signal, shuts down all power switching devices of the motor drive module, and executes the system's fast fault protection. At the same time, the main core uploads the fault code and fault parameters to the host computer through bus communication to complete the reporting and recording of the fault state.

10. A low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 1, characterized in that, The dual-core DSP includes, but is not limited to, DSP chips with a "main core + CLA" architecture.

11. A low-torque ripple control method for a low-inductance motor based on a dual-core DSP according to claim 2, characterized in that, The communication protocol includes, but is not limited to, one of CAN communication, EtherCAT bus communication, etc.

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