Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system including the semiconductor device are provided. The semiconductor device includes a gate stack structure, a channel structure, a cover insulating layer, and a common source layer. The gate stack structure has first and second surfaces opposite to each other, and includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on each other. The channel structure includes a channel through portion and a channel extension portion. The channel structure includes a channel layer and a gate dielectric layer. The gate dielectric layer includes a first dielectric portion in the channel through portion and a second dielectric portion extending from the first dielectric portion in a horizontal direction at a portion adjacent to the first surface of the gate stack structure.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0013156, filed with the Korean Intellectual Property Office on February 3, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices and electronic systems including semiconductor devices. Background Technology

[0003] In electronic systems that implement data storage devices, semiconductor devices capable of storing large amounts of data are required. Therefore, methods for increasing the data storage capacity of semiconductor devices are being researched. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0004] This disclosure attempts to provide semiconductor devices and electronic systems that include semiconductor devices, which can improve productivity and reliability.

[0005] A semiconductor device according to an embodiment includes a cell array region and a connection region. The semiconductor device includes a gate stack structure, a channel structure, a cover insulating layer, and a common source layer. The gate stack structure has a first surface and a second surface opposite to each other, and includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on top of each other. The channel structure includes a channel through-section and a channel extension. The channel through-section extends through the gate stack structure. The channel extension is on the first surface of the gate stack structure and has a width or area larger than the width or area of ​​the channel through-section. The cover insulating layer is on the first surface of the gate stack structure and covers the connection region and has an opening that exposes at least a portion of the cell array region. The common source layer includes a horizontally conductive portion. The horizontally conductive portion is on the first surface of the gate stack structure and the channel extension exposed by the opening. The channel structure includes a channel layer and a gate dielectric layer. The gate dielectric layer includes a first dielectric portion and a second dielectric portion, the first dielectric portion being in the channel through-section, and the second dielectric portion extending horizontally from the first dielectric portion at a portion adjacent to the first surface of the gate stack structure.

[0006] A semiconductor device according to an embodiment includes a gate stack structure, a channel structure, and a common source layer. The gate stack structure has a first surface and a second surface opposite to each other, and includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on top of each other. The channel structure includes a channel through-portion and a channel extension portion. The channel through-portion extends through the gate stack structure. The channel extension portion is on the first surface of the gate stack structure and has a width or area larger than the width or area of ​​the channel through-portion. The channel structure includes a channel layer and a gate dielectric layer. The gate dielectric layer includes a first dielectric portion and a second dielectric portion, the first dielectric portion being in the channel through-portion, and the second dielectric portion extending horizontally from the first dielectric portion at a portion adjacent to the first surface of the gate stack structure. A doped semiconductor layer includes a first extension portion and a second extension portion. The first extension portion is between the second dielectric portion and the channel extension portion. The second extension portion extends from the first extension portion and is located at a side surface of the channel through-portion.

[0007] An electronic system according to an embodiment includes a main substrate, a semiconductor device on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate. The semiconductor device includes a cell array region and a connection region. The semiconductor device includes a gate stack structure, a channel structure, a cover insulating layer, and a common source layer. The gate stack structure has a first surface and a second surface opposite to each other, and includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on top of each other. The channel structure includes a channel through-section and a channel extension. The channel through-section extends through the gate stack structure. The channel extension is on the first surface of the gate stack structure and has a width or area larger than the width or area of ​​the channel through-section. The cover insulating layer is on the first surface of the gate stack structure and covers the connection region and has an opening that exposes at least a portion of the cell array region. The common source layer includes a horizontally conductive portion. The horizontally conductive portion is on the first surface of the gate stack structure and the channel extension portion exposed by the opening. The channel structure includes a channel layer and a gate dielectric layer. The gate dielectric layer includes a first dielectric portion and a second dielectric portion, the first dielectric portion being in a through-channel portion, and the second dielectric portion extending horizontally from the first dielectric portion in a portion adjacent to a first surface of the gate stack structure.

[0008] A method of manufacturing a semiconductor device according to an embodiment includes a process for forming a pre-cell region. The pre-cell region includes a semiconductor substrate, a gate stack structure on the semiconductor substrate, and a channel structure. The channel structure includes a channel through-portion and a channel extension portion, the channel through-portion passing through the gate stack structure, and the channel extension portion being in the semiconductor substrate on a first surface of the gate stack structure and having a width or area larger than the width or area of ​​the channel through-portion. The method of manufacturing a semiconductor device according to an embodiment includes: a process for bonding the pre-cell region to a circuit region; a process for removing the semiconductor substrate; a process for forming a covering insulating layer with an opening configured to expose the first surface of the gate stack structure and the channel extension portion; a process for removing a portion of the gate dielectric layer in the channel extension portion on the first surface of the gate stack structure; and a process for forming a common source layer on the first surface of the gate stack structure and the channel extension portion.

[0009] The gate dielectric layer may include a first dielectric portion and a second dielectric portion, the first dielectric portion being in a through-channel portion, and the second dielectric portion extending horizontally from the first dielectric portion in a portion adjacent to a first surface of the gate stack structure.

[0010] Between the process of removing the portion of the gate dielectric layer and the process of forming the common source layer, a process of removing the portion of the channel layer adjacent to the channel extension portion may also be included. In the process of forming the common source layer, the common source layer may be formed to fill the empty space formed by removing the portion of the channel layer.

[0011] The process of forming a cover insulation layer with openings may include a process of forming a cover insulation layer and a process of forming openings in the cover insulation layer.

[0012] In the process of forming the opening, the opening can be formed by sequentially performing a first etching process and a second etching process that are different from each other.

[0013] The first etching process can be a dry etching process, and the second etching process can be a wet etching process.

[0014] In the first etching process, an opening may be formed in a portion of the covering insulating layer in the thickness direction of the covering insulating layer so as not to expose the channel extension portion, and in the second etching process, an opening may be formed so as to expose the channel extension portion but not the channel penetration portion.

[0015] According to an embodiment, a cover insulating layer with openings may be included, and a structure that selectively exposes at least a portion of the cell array region can be readily formed. The entire side surface of the channel penetration portion and / or channel extension portion may be surrounded by a gate dielectric layer, and the structural stability of the channel structure including the channel extension portion can be improved. A common source layer may be formed in the empty space created by removing the portion of the channel layer adjacent to the channel extension portion, and the cell current can be improved, while particles can be removed. Thus, the productivity and reliability of the semiconductor device can be improved. Attached Figure Description

[0016] Figure 1 This is a schematic plan view of a semiconductor device according to an embodiment.

[0017] Figure 2 It is shown schematically. Figure 1 A partial cross-sectional view of a semiconductor device is shown in the figure.

[0018] Figure 3 It is shown that it includes Figure 2 An enlarged cross-sectional view of the channel structure in a semiconductor device is shown in the figure.

[0019] Figure 4 It is shown that it includes Figure 2 The diagram shows a plan view of the second surface of the gate stack structure in a semiconductor device.

[0020] Figure 5 It is along Figure 4 The sectional view taken by line C-C' in the figure.

[0021] Figure 6 yes Figure 3 An enlarged sectional view of part D in the diagram.

[0022] Figure 7 It is shown Figure 6 The curve showing the doping concentration in direction E.

[0023] Figures 8 to 19 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0024] Figure 20 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment.

[0025] Figure 21 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment.

[0026] Figure 22 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment.

[0027] Figures 23 to 26 It is shown Figure 22 A cross-sectional view of a method for manufacturing a semiconductor device is shown in the figure.

[0028] Figure 27 This is a schematic partial cross-sectional view of a semiconductor device according to an embodiment.

[0029] Figure 28 An electronic system including a semiconductor device is schematically illustrated according to an embodiment.

[0030] Figure 29 This is a perspective view schematically illustrating an electronic system including semiconductor devices according to an embodiment.

[0031] Figure 30 This is a schematic cross-sectional view of a semiconductor package according to an embodiment. Detailed Implementation

[0032] In the following description, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings to enable those skilled in the art to readily practice the disclosure. The present disclosure may be implemented in various different forms and is not limited to the embodiments provided herein.

[0033] For the sake of clarity in describing this disclosure, parts not related to the description have been omitted, and throughout this specification, the same or similar components are indicated by the same reference numerals.

[0034] Furthermore, since the dimensions and / or thicknesses of the parts, regions, components, units, layers, membranes, substrates, etc. shown in the drawings may be arbitrarily shown for better understanding and ease of explanation, this disclosure is not limited to the dimensions and / or thicknesses shown. In the drawings, the thicknesses of parts, regions, components, units, layers, membranes, substrates, etc., may be enlarged or exaggerated for ease of explanation and / or simplicity.

[0035] It will be understood that when a component, such as a part, region, member, unit, layer, membrane, substrate, etc., is referred to as being "on" or "above" another component, the component may be directly on said other component, or an intervening component may be present. Conversely, when a component is referred to as being "directly on" another component, no intervening component is present. Furthermore, when a component is referred to as being "on" or "above" a reference component, the component may be positioned on or below the reference component, without necessarily being "on" or "above" the reference component in the opposite direction of gravity.

[0036] Furthermore, throughout the instruction manual, unless explicitly stated otherwise, the words “comprises,” “includes,” or “contains,” as well as variations such as “comprises,” “comprising,” “includes,” or “contains,” will be understood to imply the inclusion of other components rather than the exclusion of any other components.

[0037] Furthermore, throughout the specification, the phrases “on a plane,” “in a plane,” “on a plan view,” or “in a plan view” indicate a view of a portion taken from above or at the top, and the phrases “in a section” or “in a sectional view” indicate a view taken from the side (side view) along a vertical direction.

[0038] In the following text, refer to Figures 1 to 19 The following will describe in detail the semiconductor device and the method of manufacturing the semiconductor device according to the embodiments.

[0039] Figure 1 This is a schematic plan view of a semiconductor device 10 according to an embodiment. Figure 1 The main features shown are a memory region 10m including a cell array region 102 and a connection region 104, an outer region 12, and a covering insulating layer 168a.

[0040] Reference Figure 1 In an embodiment, the semiconductor device 10 may include a plurality of memory regions 10m divided, separated or defined by the outer region 12.

[0041] The memory region 10m can be a unit region of the semiconductor device 10, and can be referred to as a block (mat). Figure 1 As an example, a semiconductor device 10 is shown to include a plurality of memory regions 10m adjacent to each other in a first direction (the X-axis direction in the figure) and a plurality of memory regions 10m adjacent to each other in a second direction (the Y-axis direction in the figure). However, the embodiment is not limited to this, and the number, arrangement, etc. of the plurality of memory regions 10m can be modified in various ways.

[0042] 10m per memory region or 100 per cell region (refer to) Figure 2 The array may include a cell array region 102 and a connection region 104. In the cell array region 102, a gate stack structure 120 (see reference 104) is included. Figure 2 ) and channel structure CH (refer to Figure 2 ) can be configured. In the connection area 104, a plurality of gate contacts 192 (refer to Figure 2 ) can be connected to a plurality of gate electrodes 130 included in the gate stack structure 120 (see reference 120) Figure 2 ).exist Figure 1 As an example, each memory region 10m includes a plurality of cell array regions 102, and a connection region 104 is disposed at the edge region of each of the plurality of cell array regions 102 in a first direction (the X-axis direction in the figure). However, the embodiments are not limited thereto. In some embodiments, in the first direction, a connection region 104 may be disposed in each memory region 10m, or the connection region 104 may be disposed on one side of the cell array region 102. Various other modified embodiments are possible.

[0043] The outer region 12 may be disposed between multiple memory regions 10m to divide, partition, or define the multiple memory regions 10m. The outer region 12 may include at least one first outer region 12a extending longitudinally (or "length") in a first direction (X-axis direction in the figures) and at least one second outer region 12b extending longitudinally in a second direction (Y-axis direction in the figures). Thus, the structure of the outer region 12 can be simplified. However, the embodiments are not limited thereto. Depending on the arrangement of the multiple memory regions 10m, the first outer region 12a and / or the second outer region 12b may include bent portions, folded portions, curved portions, circular (rounded) portions, etc.

[0044] In an embodiment, the covering insulating layer 168a may be disposed in the connection region 104 and / or the outer region 12 and may have an opening 168p that exposes at least a portion of the cell array region 102, and the common source layer 170 (see reference) Figure 2 It can be electrically connected to the channel structure CH through the opening 168p covering the insulating layer 168a. This will be described in more detail later.

[0045] exist Figure 1 In the example shown, the opening 168p covering the insulating layer 168a may have a rectangular planar shape. However, the embodiment is not limited to this, and the opening 168p covering the insulating layer 168a may have any planar shape of various planar shapes. Figure 1 As an example, in each memory region 10m, the opening 168p covering the insulating layer 168a may include a plurality of openings 168p corresponding to the plurality of cell array regions 102 respectively. However, the embodiments are not limited thereto, and the number of openings 168p covering the insulating layer 168a may be modified in various ways in each memory region 10m.

[0046] Figure 2 It is shown schematically. Figure 1 A partial cross-sectional view of the semiconductor device 10 shown in the figure. Figure 2 It is along Figure 1The diagram shows cross-sectional views taken along lines A-A' and B-B'. For clarity, the gate contact 192 and the input / output connection wiring 194 are shown together. Figure 2 However, the positions of the gate contact 192 and the input / output connection wiring 194 can be modified in various ways. Figure 3 It is shown that it includes Figure 2 An enlarged cross-sectional view of the channel structure CH in the semiconductor device 10 shown in the figure. Figure 4 It is shown that it includes Figure 2 The diagram shows a plan view of the second surface 120b of the gate stack structure 120 in the semiconductor device 10.

[0047] Reference Figures 2 to 4 According to an embodiment, the semiconductor device 10 may include a cell region 100 and a circuit region 200. The cell region 100 includes a memory cell structure, and the circuit region 200 includes a peripheral circuit structure configured to control the operation of the memory cell structure. For example, the circuit region 200 and the cell region 100 may be respectively connected to... Figure 28 The electronic system 1000 shown corresponds to the first structure 1100F and the second structure 1100S of the semiconductor device 1100. For example, the circuit region 200 and the cell region 100 may respectively include Figure 30 The semiconductor chip 2200 shown in the figure has a first structure 4100 and a second structure 4200.

[0048] In an embodiment, the semiconductor device 10 may be a bonded (or “attached”) semiconductor device formed by separately forming cell region 100 and circuit region 200 and subsequently bonding cell region 100 to circuit region 200. For example, cell region 100 may be bonded to circuit region 200 via a hybrid bonding process, such as chip-to-chip (C2C) bonding, chip-to-wafer bonding, or wafer-to-wafer bonding. When cell region 100 and circuit region 200 are formed via separate processes, it prevents cell region 100 from affecting circuit region 200 during the process of cell region 100. For example, semiconductor device 10 may be a bonded vertical NAND flash memory (BV NAND flash memory).

[0049] In this embodiment, the cell region 100 may be disposed on the circuit region 200. Therefore, the region corresponding to the circuit region 200 does not need to be independent of the cell region 100. As a result, the area of ​​the semiconductor device 10 can be reduced.

[0050] Circuit region 200 is electrically connected to cell region 100 and may include substrate 210, circuit elements 220, and circuit wiring portions 280. Substrate 210 may be a semiconductor substrate comprising semiconductor material. For example, substrate 210 may be a semiconductor substrate comprising or formed of semiconductor material, or a semiconductor substrate in which semiconductor layers are on a substrate. For example, substrate 210 may include semiconductor materials having a single-crystal structure, epitaxial structure, or polycrystalline structure (e.g., silicon, germanium, silicon-germanium, etc.), silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc., or may be formed of semiconductor materials having a single-crystal structure, epitaxial structure, or polycrystalline structure (e.g., silicon, germanium, silicon-germanium, etc.), silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc.

[0051] The circuit element 220 on substrate 210 may include any of a variety of circuit elements to form a peripheral circuit structure that controls the operation of the memory cell structure in cell region 100. For example, circuit element 220 may form a decoder circuit 1110 (see reference 1110). Figure 28 Page buffer 1120 (refer to) Figure 28 ), Logic circuit 1130 (refer to) Figure 28 The peripheral circuit structure of , etc.

[0052] Circuit element 220 may include, for example, transistors, but the embodiments are not limited thereto. For example, circuit element 220 may include not only active elements (such as transistors, etc.) but also passive elements (such as capacitors, resistors, inductors, etc.).

[0053] A wiring portion 280 on substrate 210 is electrically connected to circuit element 220. In an embodiment, the wiring portion 280 may include a plurality of wiring layers 282 and a bonding structure 288, wherein the plurality of wiring layers 282 are spaced apart from each other while an insulating layer 286 is disposed between the plurality of wiring layers 282, and the plurality of wiring layers 282 are electrically connected through contact vias 284 to form a desired path, and the bonding structure 288 is electrically connected to the plurality of wiring layers 282. The wiring layers 282, contact vias 284, or bonding structure 288 of the wiring portion 280 may include any conductive material of various conductive materials, and the insulating layer 286 of the wiring portion 280 may include any insulating material of various insulating materials.

[0054] Cell region 100 may include gate stack structure 120, channel structure CH and wiring portions (e.g., first wiring portion 160, second wiring portion 180 and / or through wiring portion 190).

[0055] Cell region 100 may include cell array region 102 and connection region 104. In some embodiments, buffer region 106 may be further disposed between cell array region 102 and connection region 104. For clarity, buffer region 106 is described and shown as an example independent of cell array region 102 and connection region 104, but buffer region 106 may be a part of cell array region 102 or a part of connection region 104.

[0056] Within the cell array region 102, memory cell structures can be configured. For example, within the cell array region 102, gate stack structure 120 and channel structure CH can be configured.

[0057] The gate stack structure 120 may include a plurality of unit insulating layers 132 (e.g., a plurality of interlayer insulating layers 132m) and a plurality of gate electrodes 130 alternately stacked on top of each other. A channel structure CH may extend through the gate stack structure 120. For example, the extension direction of the channel structure CH may be the thickness direction of the semiconductor device 10, the vertical direction, or the Z-axis direction as shown in the figures.

[0058] The gate stack structure 120 may have a first surface 120a and a second surface 120b that are opposite to each other. The second surface 120b of the gate stack structure 120 may be a facing surface facing the circuit region 200, and the first surface 120a of the gate stack structure 120 may be a facing surface opposite to the circuit region 200.

[0059] The gate electrode 130 may comprise any conductive material from a variety of conductive materials. For example, the gate electrode 130 may comprise a metallic material (e.g., tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), etc.), polycrystalline silicon, metal nitrides (e.g., tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), etc.) or a combination thereof, or may be formed of a metallic material (e.g., tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), etc.), polycrystalline silicon, metal nitrides (e.g., tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), etc.) or a combination thereof. The unit insulating layer 132 may comprise any insulating material from a variety of insulating materials. For example, the interlayer insulating layer 132m may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than that of silicon oxide, or a combination thereof, or may be formed of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a dielectric constant lower than that of silicon oxide, or a combination thereof.

[0060] The channel structure CH may include a channel layer 140 and a gate dielectric layer 150 on the channel layer 140 between the gate electrode 130 and the channel layer 140. The gate dielectric layer 150 between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154 and a barrier layer 156 sequentially arranged on the channel layer 140.

[0061] The channel structure CH may also include a core insulation layer 142 in the channel layer 140. In some embodiments, the core insulation layer 142 may be omitted. The channel structure CH may also include a channel pad 144 on the channel layer 140 and / or the core insulation layer 142.

[0062] Each channel structure CH can form a memory cell string, and multiple channel structures CH can be spaced apart from each other to form rows and columns in a planar view. For example, multiple channel structures CH can be configured to form any shape of various shapes in a planar view (such as a grid shape, a zigzag shape, etc.). The channel structure CH can have a columnar shape. For example, in a cross-sectional view, due to the high aspect ratio (or "depth-to-width ratio"), the channel structure CH can have sloping side surfaces, such that the width of the channel structure CH decreases towards the first surface 120a of the gate stack structure 120. However, the implementation is not limited to this, and the arrangement, structure, shape, etc., of the channel structures CH can be modified in various ways.

[0063] The channel layer 140 may include a semiconductor material. For example, the channel layer 140 may include a semiconductor material having a polycrystalline or epitaxial structure (e.g., silicon). For example, the channel layer 140 may include an undoped semiconductor material (e.g., undoped silicon). The core insulating layer 142 may include any insulating material from a variety of insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, or may be formed of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0064] The tunneling layer 152 may include an insulating material (e.g., silicon oxide, silicon oxynitride, etc.) capable of tunneling charges. The charge storage layer 154 may serve as a data storage region and may include polysilicon, silicon nitride, etc. The barrier layer 156 may include an insulating material capable of preventing unwanted charge flow to the gate electrode 130. For example, the barrier layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In an embodiment, the barrier layer 156 may include a first barrier layer 156a and a second barrier layer 156b, the first barrier layer 156a including a portion extending horizontally on the gate electrode 130, and the second barrier layer 156b extending vertically between the first barrier layer 156a and the charge storage layer 154.

[0065] The channel pad 144 may cover the surface of the core insulating layer 142 (e.g., the surface facing the circuit region 200) and may be electrically connected to the channel layer 140. The channel pad 144 may include a conductive material. For example, the channel pad 144 may include a doped semiconductor material, such as a doped polycrystalline semiconductor material or an epitaxial semiconductor material (e.g., silicon).

[0066] However, the embodiments are not limited to the materials, structures, etc. of the channel layer 140, the core insulating layer 142, the gate dielectric layer 150, or the channel pad 144.

[0067] In an embodiment, the gate stack structure 120 may include a plurality of gate stack portions 121 and 122 stacked sequentially. This allows for an increase in the number of stacked gate electrodes 130, thereby enabling a stable increase in the number of memory cells. Figure 2 As an example, the gate stack structure 120 is shown to include a first gate stack portion 121 and a second gate stack portion 122. However, the embodiments are not limited thereto, and the gate stack structure 120 may include one gate stack portion or three or more gate stack portions.

[0068] When the plurality of gate stack portions 121 and 122 are configured as described above, the channel structure CH (e.g., the channel through portion CHa) may include a plurality of channel portions CH1 and CH2 passing through the plurality of gate stack portions 121 and 122, respectively. The plurality of channel portions CH1 and CH2 may be connected to each other. In a cross-sectional view, due to the high aspect ratio, each of the plurality of channel portions CH1 and CH2 may have a sloping side surface, such that the width of each of the plurality of channel portions CH1 and CH2 decreases toward the first surface 120a of the gate stack structure 120. Bending portions caused by the difference in width of the plurality of channel portions CH1 and CH2 may be provided at the boundary portions between the plurality of gate stack portions 121 and 122. In some embodiments, the plurality of channel portions CH1 and CH2 may have continuously extending sloping side surfaces without bending portions. Figure 3 In the illustration, each of the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of a plurality of channel portions CH1 and CH2 extends continuously to have an integral structure. In some embodiments, the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of the plurality of channel portions CH1 and CH2 may be formed individually and electrically connected to each other. In some embodiments, individual channel pads may be additionally disposed at the connection portions of the plurality of channel portions CH1 and CH2. Thus, the embodiments are not limited to the shape or type of the plurality of channel portions CH1 and CH2.

[0069] In an embodiment, the channel structure CH may include a channel through portion CHa and a channel extension portion CHb, and may also include a channel extension portion CHc extending to connect the channel through portion CHa and the channel extension portion CHb. This will be referred to later. Figure 5 and Figure 6 To describe in more detail.

[0070] The channel structure CH in cell array region 102 may include a connection channel structure CCH electrically connected to a first wiring portion 160 (e.g., common source layer 170) and / or a second wiring portion 180 (e.g., bit line BL). In an embodiment, in a region adjacent to buffer region 106, the channel structure CH may also include a dummy channel structure DCH that is not electrically connected to the first wiring portion 160 (e.g., common source layer 170) and / or the second wiring portion 180 (e.g., bit line BL). Figure 5 In the example shown, the dummy channel structure DCH has the same shape, form, and size as the connected channel structure CCH, and is electrically connected to the common source layer 170 but not electrically connected to the bit line BL. However, the embodiments are not limited thereto. In some embodiments where the gate dielectric layer and / or channel layer may be disposed in the channel extension portion of the dummy channel structure DCH, unlike the connected channel structure CCH, the dummy channel structure DCH may not be electrically connected to the common source layer 170.

[0071] The buffer region 106 may be configured to improve structural stability by minimizing the structural differences between the cell array region 102 and the connection region 104 in the manufacturing process of the semiconductor device 10. However, the embodiments are not limited thereto, and the buffer region 106 may be omitted.

[0072] Within buffer region 106, gate stack structure 120 and dummy structure DH may be included. Dummy structure DH may be configured to reduce stress applied to gate stack structure 120. Unlike channel structure CH (e.g., connecting channel structure CCH), dummy structure DH may not be electrically connected to wiring portions.

[0073] The dummy structure DH may include a dummy through portion DHa (see reference). Figure 5 ) and the virtual extension part DHb (refer to Figure 5A dummy through-portion DHa may extend through the gate stack structure 120. A dummy extension DHb may be disposed on the first surface 120a of the gate stack structure 120 and may have a width or area larger than the width or area of ​​the dummy through-portion DHa. The width of the dummy through-portion DHa or the dummy extension DHb may refer to the width (e.g., length or diameter) of the portion adjacent to the first surface 120a of the gate stack structure 120. The area of ​​the dummy through-portion DHa or the dummy extension DHb may refer to the area of ​​the portion adjacent to the first surface 120a of the gate stack structure 120.

[0074] In the cross-sectional view, due to the high aspect ratio, the dummy through-portion DHa may have sloping side surfaces, such that the width of the dummy through-portion DHa decreases toward the first surface 120a of the gate stack structure 120. Bends caused by the difference in width of portions of the dummy through-portion DHa may be provided at the boundary portions between the plurality of gate stack portions 121 and 122. In some embodiments, the dummy through-portion DHa may have continuously extending sloping side surfaces without bends. However, embodiments are not limited thereto, and the dummy structure DH may have any shape or form of various shapes or forms.

[0075] The dummy structure DH may include a material different from the material of the channel structure CH (e.g., an insulating material), or it may include the same material as the material of the channel structure CH. Figure 4 In the example shown, the width or area of ​​the dummy structure DH is larger than the width or area of ​​the channel structure CH, and the spacing between the dummy structures DH is larger than the spacing between the channel structures CH. However, the embodiments are not limited to this. In some embodiments, the dummy structure DH may have the same width or area as the channel structure CH or a smaller width or area than the channel structure CH, and / or the spacing between the dummy structures DH may be the same as or smaller than the spacing between the channel structures CH.

[0076] The gate stack structure 120 can be divided into multiple portions in a plan view by a separator structure 146 passing through the gate stack structure 120. A separator pattern 148 can be configured to be adjacent to a second surface 120b of the gate stack structure 120. In the plan view, the separator structure 146 and / or the separator pattern 148 can extend in a first direction (the X-axis direction in the figures). Multiple separator structures 146 and / or multiple separator patterns 148 can be spaced apart from each other at predetermined intervals in a second direction (the Y-axis direction in the figures) intersecting (e.g., perpendicular to) the first direction.

[0077] In the plan view, multiple gate stack structures 120 can extend in a first direction (the X-axis direction in the figures) via the partition structure 146, and can be spaced apart from each other at predetermined intervals in a second direction (the Y-axis direction in the figures) intersecting the first direction. The gate stack structures 120 divided by the partition structure 146 can form a memory cell block. However, the embodiments are not limited thereto, and the scope of the memory cell block is not limited thereto.

[0078] For example, a separator 146 may pass through the gate stack structure 120, and a separator pattern 148 may separate one or a portion of the plurality of gate electrodes 130. The separator pattern 148 may be disposed between the separator structures 146. In a cross-sectional view, the separator structure 146 or the separator pattern 148 may extend to pass through the gate stack structure 120 in the thickness direction or vertical direction (Z-axis direction in the figures) of the semiconductor device 10.

[0079] exist Figure 4 In the example shown, the side surface of the partition structure 146 has a continuously arranged curved surface with an outwardly convex curvature. Figure 2 In the diagram, a bent portion is shown as an example at the boundary of the plurality of gate stack portions 121, 122. A channel pre-through portion corresponding to the channel structure CH and a separator pre-through portion corresponding to the separator structure 146 can be formed together, and the through portion for the separator structure can be formed by an etching process that extends the separator pre-through portions to connect them to each other. Thereafter, material can be filled into the through portion for the separator structure to form the separator structure 146 having the above shape. Therefore, the additional etching process for forming the through portion for the separator structure with a high aspect ratio can be omitted, thus simplifying the manufacturing process.

[0080] The partition pre-through portion corresponding to the partition structure 146 may include a through portion passing through the gate stack structure 120 and an extension portion on the first surface 120a of the gate stack structure 120. The extension portion may have a width or area larger than the width or area of ​​the through portion. In the process of forming the through portion for the partition structure by extending the partition pre-through portion, the width or area of ​​the through portion may be increased, and the through portion in the through portion for the partition structure may have a width or area larger than the width or area of ​​the extension portion in the through portion for the partition structure. After forming the partition structure 146, at least a portion of the extension portion on the first surface 120a of the gate stack structure 120 may be removed in a process of removing a portion of the gate dielectric layer 150. Thus, in the final structure, the partition structure 146 may include the through portion passing through the gate stack structure 120 and may not include at least a portion of the extension portion.

[0081] However, the embodiments are not limited thereto. In some embodiments, in a cross-sectional view, due to the high aspect ratio, the partition structure 146 may have sloping side surfaces such that the width of the partition structure 146 decreases toward the first surface 120a of the gate stack structure 120. Bending portions caused by differences in the width of portions of the partition structure 146 may be provided at the boundary portions between the plurality of gate stack portions 121 and 122. In some embodiments, the partition structure 146 may have side surfaces parallel to the thickness direction or vertical direction (Z-axis direction in the figures) of the semiconductor device 10, or may have continuously extending sloping side surfaces without bending portions. In some embodiments, the partition structure 146 may include a through portion passing through the gate stack structure 120, and may also include at least a portion of an extension portion. The partition structure 146 may have any of the following shapes.

[0082] The partition structure 146 and / or partition pattern 148 may comprise any insulating material from a variety of insulating materials. For example, the partition structure 146 or partition pattern 148 may comprise, or be formed of, an insulating material (such as, silicon oxide, silicon nitride, or silicon oxynitride). However, embodiments are not limited thereto, and the structure, shape, etc., of the partition structure 146 or partition pattern 148 may be modified in various ways.

[0083] The connection region 104 and / or the outer region 12 and the wiring portion may be configured to connect the memory cell structure (e.g., gate stack structure 120 and channel structure CH) in the cell array region 102 to the circuit region 200 or external circuitry.

[0084] In an embodiment, the wiring portion may include any component configured to electrically connect the gate electrode 130 and / or the channel structure CH to the circuit region 200 or external circuitry. The wiring portion may include a first wiring portion 160 on a first surface 120a of the gate stack structure 120, a second wiring portion 180 on a second surface 120b of the gate stack structure 120 (e.g., between the second surface 120b of the gate stack structure 120 and the circuit region 200), and a through wiring portion 190 in the connection region 104 and / or the outer region 12.

[0085] In an embodiment, the first wiring portion 160 may include a common source layer 170, the second wiring portion 180 may include a bit line BL and a bonding structure 188, and the through wiring portion 190 may include a gate contact 192 and an input / output connection wiring 194.

[0086] In an embodiment, the first wiring portion 160 may include a first wiring layer 162 on a first surface 120a of the gate stack structure 120, a first contact 164 electrically connected to the first wiring layer 162, a pad 166 electrically connected to the first contact 164, and an insulating layer 168.

[0087] The first wiring layer 162 may include a common source layer 170 electrically connected to the channel structure CH on the first surface 120a of the gate stack structure 120. The first contact 164 may include a common source contact electrically connected to the common source layer 170 and an input / output connection contact electrically connected to the input / output connection wiring 194. For example, the common source contact may electrically connect the common source layer 170 and the pad 166, and the input / output connection contact may electrically connect the input / output connection wiring 194 and the pad 166.

[0088] The insulating layer 168 of the first wiring portion 160 may include a covering insulating layer 168a, and may also include a first insulating layer 168b, a second insulating layer 168c, a third insulating layer 168d, and a fourth insulating layer 168e on the covering insulating layer 168a. The covering insulating layer 168a may have an opening 168p that exposes at least a portion of the cell array region 102 (see reference). Figure 5 ).

[0089] The covering insulating layer 168a may have an opening 168p that exposes at least a portion of the cell array region 102, and may be disposed on at least the connection region 104, the buffer region 106, and / or the outer region 12. The covering insulating layer 168a may be disposed on the first surface 120a of the gate stack structure 120. For example, the surface of the covering insulating layer 168a adjacent to the first surface 120a of the gate stack structure 120 ( Figure 2 The lower surface of the common source layer 170 may be adjacent to the first surface 120a of the gate stack structure 120. Figure 2 (the lower surface of the middle) (for example, the first common source layer 172 (refer to) Figure 5 Part 172a (refer to) Figure 5 The surfaces of the common source layer 170 and the gate stack structure 120 are on the same plane. However, the embodiments are not limited thereto. In some embodiments, the surface of the insulating layer 168a adjacent to the first surface 120a of the gate stack structure 120 may be on a different plane from the surface of the common source layer 170 adjacent to the first surface 120a of the gate stack structure 120.

[0090] An opening 168p in the covering insulating layer 168a may be provided in at least a portion of the cell array region 102 in which the channel structure CH and the common source layer 170 are electrically connected to each other. Thus, at least a portion of the cell array region 102 in which the channel structure CH and the common source layer 170 are electrically connected to each other may be physically or structurally separated from another region. For example, the opening 168p in the covering insulating layer 168a may expose a portion of the cell array region 102, and the covering insulating layer 168a may be provided in the connection region 104, the buffer region 106, and / or the outer region 12. Thus, a portion of the cell array region 102 may be physically or structurally separated from the connection region 104, the buffer region 106, and / or the outer region 12.

[0091] In an embodiment, during the manufacturing process of the semiconductor device 10, the covering insulating layer 168a can protect the connection region 104, the buffer region 106, and / or the outer region 12. For example, in the process of electrically connecting the common source layer 170 and the channel structure CH, the covering insulating layer 168a can protect the structures (e.g., wiring portions) in the connection region 104, the buffer region 106, and / or the outer region 12. That is, in the process of removing the portion of the gate dielectric layer 150 in the channel extension portion CHb of the channel structure CH, the covering insulating layer 168a can be used as a mask layer. Therefore, with the covering insulating layer 168a protecting the connection region 104, the buffer region 106, and / or the outer region 12, the portion of the gate dielectric layer 150 in the channel extension portion CHb of the channel structure CH can be selectively removed. In the heat treatment process of the common source layer 170 (e.g., the first common source layer 172), the covering insulating layer 168a can absorb energy and heat and prevent metal from diffusing into the wiring portions in or at the lower part of the connection region 104 and / or the outer region 12.

[0092] The cover insulating layer 168a may include an insulating material. When the cover insulating layer 168a includes an insulating material, the manufacturing process can be simplified, and the cover insulating layer 168a can stably protect the connection region 104, the buffer region 106, and / or the outer region 12. In a comparative example where a cover layer comprising a semiconductor material or a metallic material other than an insulating material is included instead of the cover insulating layer 168a, considering wiring portions, the cover layer may be formed during the process of forming the pre-cell region, and / or a process for removing the cover layer may be additionally performed in a subsequent process. Therefore, this may be disadvantageous in the manufacturing process. Furthermore, the cover layer comprising a semiconductor material or a metallic material may be retained, which may be disadvantageous in performance.

[0093] In an embodiment, the covering insulating layer 168a may include silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, etc., or be formed of silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, etc., and may include a material different from the material of the unit insulating layer 132 (e.g., the interlayer insulating layer 132m). For example, the interlayer insulating layer 132m may include or be formed of silicon oxide, and the covering insulating layer 168a may include or be formed of silicon nitride. Thus, in the process of removing a portion of the gate dielectric layer 150 during the process of electrically connecting the common source layer 170 and the channel structure CH, the etching process can be stably stopped. However, the embodiments are not limited thereto.

[0094] In an embodiment, by using a covering insulating layer 168a comprising insulating material, the region where the channel structure CH and the common source layer 170 are electrically connected to each other can be separated from another region, and the manufacturing process of the semiconductor device 10 can be simplified, and the structural stability of the semiconductor device 10 can be improved.

[0095] The common source layer 170 may be electrically connected to the channel structure CH (e.g., channel layer 140) exposed by the opening 168p in the cell array region 102 covered by the insulating layer 168a.

[0096] The common source layer 170 may include a first common source layer 172 and a second common source layer 174. The first common source layer 172 may include a doped semiconductor layer (e.g., an n-type or p-type polysilicon layer), and the second common source layer 174 may include a metal. The first common source layer 172 may include a semiconductor material to improve the connection properties with the channel layer 140. The second common source layer 174 may include a metal having a lower resistance than the first common source layer 172 to reduce the resistance of the common source layer 170. However, embodiments are not limited thereto, and the first common source layer 172 or the second common source layer 174 may be omitted, or the common source layer 170 may include layers other than the first common source layer 172 and the second common source layer 174.

[0097] The first insulating layer 168b may be a planarization layer covering the covering insulating layer 168a and the common source layer 170. The second insulating layer 168c and the third insulating layer 168d may be insulating layers for hydrogen passivation, and the fourth insulating layer 168e may be a cover layer configured to protect the semiconductor device 10. The first insulating layer 168b, the second insulating layer 168c, the third insulating layer 168d, and the fourth insulating layer 168e may comprise any insulating material of various insulating materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, organic materials, etc.), or may be formed from any insulating material of various insulating materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, organic materials, etc.). For example, the second insulating layer 168c may comprise an insulating material layer containing hydrogen (e.g., a silicon oxide layer containing hydrogen), and the third insulating layer 168d may comprise a barrier layer (e.g., a silicon nitride layer). Hydrogen contained in the second insulating layer 168c can diffuse into the channel layer 140 of the channel structure CH through a heat treatment process, and the channel layer 140 can be hydrogen passivated.

[0098] However, the embodiments are not limited thereto. At least one of the first insulating layer 168b, the second insulating layer 168c, the third insulating layer 168d, and the fourth insulating layer 168e may be omitted, or insulating layers other than the first insulating layer 168b, the second insulating layer 168c, the third insulating layer 168d, and the fourth insulating layer 168e may be further included.

[0099] In one embodiment, the second wiring portion 180 may include a second wiring layer 182, a second contact 184, a bonding structure 188, and an insulating layer 186. The second wiring layer 182 may be disposed on a second surface 120b of the gate stack structure 120. The second contact 184 may be electrically connected to the second wiring layer 182. The bonding structure 188 may be electrically connected to the second wiring layer 182 at a portion facing the circuit region 200.

[0100] The second wiring layer 182 may include a bit line BL, and the second contact 184 may include a bit line contact electrically connecting the channel pad 144 of the channel structure CH to the bit line BL. The second wiring layer 182 may also include connection wiring electrically connected to the gate contact 192, input / output connection wiring 194, etc. The insulating layer 186 of the second wiring portion 180 may include an interlayer insulating layer and a bonding insulating layer. The interlayer insulating layer may be disposed at the periphery of the second wiring layer 182 and / or the second contact 184. The bonding insulating layer may be disposed at the periphery of the bonding structure 188 in the portion facing the circuit region 200.

[0101] The first wiring layer 162, the first contact 164, the pad 166, the second wiring layer 182, or the second contact 184 may comprise any conductive material of various conductive materials, and the insulating layer 168 of the first wiring portion 160 or the insulating layer 186 of the second wiring portion 180 may comprise any insulating material of various insulating materials. For example, the first wiring layer 162, the first contact 164, the pad 166, the second wiring layer 182, or the second contact 184 may comprise metallic materials (e.g., tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), etc.), semiconductor materials (e.g., polycrystalline silicon), metal nitrides (e.g., tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), etc.) or combinations thereof.

[0102] In an embodiment, in the connection region 104, a plurality of gate electrodes 130 may extend in a first direction (the X-axis direction in the figures), and a plurality of gate contacts 192 may pass through the gate stack structure 120 or the unit insulating layer 132 and may be electrically connected to the plurality of gate electrodes 130 extending into the connection region 104, respectively.

[0103] For example, in the connection region 104, multiple contact holes for which multiple gate contacts 192 are respectively provided can be individually provided in the gate stack structure 120, and the gate stack structure 120 can be integrally provided in the portion other than the separator structure 146 and / or separator pattern 148. For example, in the connection region 104, the extension lengths of the multiple gate electrodes 130 can be substantially the same. Substantially the same can mean having a difference within process tolerance (e.g., less than 10%). In embodiments, the gate stack structure 120 is removed so that a stepped-shaped portion (e.g., a pad region) for electrical connection between the gate electrode 130 and the gate contact 192 may not be provided, or an insulating layer (e.g., a pad insulating layer) in that portion (e.g., the pad region) may not be provided. Therefore, the process of electrically connecting the gate contact 192 and the gate electrode 130 can be simplified, and the area of ​​the connection region 104 can be reduced.

[0104] However, the embodiments are not limited thereto. In some embodiments, the extension length of the plurality of gate electrodes 130 may sequentially decrease in the connection region 104 away from the first surface 120a of the gate stack structure 120. For example, the plurality of gate electrodes 130 may have a stepped shape in one or more directions in the connection region 104, and portions of the gate stack structure 120 that are removed to have a stepped shape (e.g., pad regions) may be included. A plurality of gate contacts 192 may pass through the cell insulating layer 132 (e.g., pad insulating layer) in the pad regions and may be electrically connected to the plurality of gate electrodes 130 respectively. The electrical connection structure between the gate electrodes 130 and the gate contacts 192 may be modified in various ways.

[0105] In the connection region 104, a dummy structure DH may be disposed at the periphery of the gate contact 192. The dummy structure DH may be configured to reduce the stress applied to the gate stack structure 120.

[0106] exist Figure 2 As an example, the input / output connection wiring 194 is provided in the outer region 12 where the insulating stack structure 120s is provided, and passes through the insulating stack structure 120s.

[0107] The insulating stack structure 120s may include a plurality of unit insulating layers 132 (e.g., a plurality of interlayer insulating layers 132m) and a plurality of sacrificial insulating layers 130s alternately stacked on top of each other. The plurality of sacrificial insulating layers 130s of the insulating stack structure 120s may correspond to a plurality of gate electrodes 130 of the gate stack structure 120, and the plurality of interlayer insulating layers 132m of the insulating stack structure 120s may correspond to a plurality of interlayer insulating layers 132m of the gate stack structure 120, respectively. The sacrificial insulating layers 130s may include a material different from the material of the unit insulating layers 132 (e.g., interlayer insulating layers 132m). For example, the sacrificial insulating layers 130s may include silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, etc., or be formed of silicon, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, etc., and may include a material different from the material of the unit insulating layers 132 (e.g., interlayer insulating layers 132m).

[0108] The multiple interlayer insulating layers 132m of the insulating stack structure 120s may be insulating layers formed using the same process as the multiple interlayer insulating layers 132m of the gate stack structure 120. After forming the insulating stack structure 120s by alternately stacking multiple interlayer insulating layers 132m and multiple sacrificial insulating layers 130s in the cell array region 102, buffer region 106, connection region 104 and outer region 12, the multiple sacrificial insulating layers 130s may be selectively removed in at least a portion of the cell array region 102, buffer region 106 and connection region 104, and the gate electrode 130 may be formed in the portion where the sacrificial insulating layers 130s have been removed. Therefore, a gate stack structure 120 comprising a plurality of interlayer insulating layers 132m and a plurality of gate electrodes 130 alternately stacked on each other may be disposed in at least a portion of the cell array region 102, the buffer region 106 and the connection region 104, and an insulating stack structure 120s comprising a plurality of interlayer insulating layers 132m and a plurality of sacrificial insulating layers 130s alternately stacked on each other may be disposed in the outer region 12.

[0109] However, the embodiments are not limited thereto. In some embodiments, in the portion where the input / output connection wiring 194 is provided, the gate stack structure 120 and the insulating stack structure 120s may not be provided, and the cell insulating layer 132 may be provided, and the input / output connection wiring 194 may pass through the cell insulating layer 132.

[0110] exist Figure 2 As an example, the input / output connection wiring 194 includes a wiring through-port 194a and a wiring extension 194b. The wiring through-port 194a may extend through the gate stack structure 120. The wiring extension 194b may be disposed on the first surface 120a of the gate stack structure 120 and may have a width or area larger than that of the wiring through-port 194a. The width of the wiring through-port 194a or the wiring extension 194b may refer to the width (e.g., length or diameter) of the portion adjacent to the first surface 120a of the gate stack structure 120. The area of ​​the wiring through-port 194a or the wiring extension 194b may refer to the area of ​​the portion adjacent to the first surface 120a of the gate stack structure 120. However, the embodiment is not limited thereto, and the input / output connection wiring 194 may have any shape or form of various shapes or forms.

[0111] exist Figure 2 As an example, in a cross-sectional view, due to the high aspect ratio, the gate contact 192 and / or the input / output connection wiring 194 (e.g., wiring through-port 194a) have sloping side surfaces, such that the width of the gate contact 192 and / or the input / output connection wiring 194 decreases towards the first surface 120a of the gate stack structure 120. Bending portions caused by the difference in width of the portions of the gate contact 192 and / or the input / output connection wiring 194 may be provided at the boundary portions between the plurality of gate stack portions 121 and 122. However, the embodiment is not limited to this. The gate contact 192 and / or the input / output connection wiring 194 may not include bending portions at the boundary portions between the plurality of gate stack portions 121 and 122. Various other modified embodiments are possible.

[0112] Input / output connection wiring 194 can be electrically connected to pad 166 included in cell region 100. Figure 2As an example, input / output connection wiring 194 is shown electrically connected to pad 166 via input / output connection contacts passing through the insulating layer 168 of the first wiring portion 160. However, embodiments are not limited to this, and pad 166 and input / output connection wiring 194 can be electrically connected to each other in any of a variety of configurations. Input / output connection wiring 194 may be electrically connected to a portion of the engagement structure 188 of the second wiring portion 180. In some embodiments, additional input / output pads electrically connected to circuit region 200 may be provided.

[0113] In an embodiment, the cell region 100 and the circuit region 200 may be joined to each other by a hybrid bonding. For example, the cell region 100 and the circuit region 200 may be joined to each other by a hybrid bonding that includes a metal bonding between bonding structures 188 and 288 and an insulating layer bonding between bonding insulating layers at the periphery of bonding structures 188 and 288.

[0114] For example, the bonding structure 188 of the unit region 100 and / or the bonding structure 288 of the circuit region 200 may include at least one of copper, aluminum, tungsten, nickel, gold, tin, manganese, cobalt, titanium, tantalum, ruthenium, and beryllium, or may be formed from at least one of copper, aluminum, tungsten, nickel, gold, tin, manganese, cobalt, titanium, tantalum, ruthenium, and beryllium, or may include an alloy containing the above materials or be formed from an alloy containing the above materials. For example, the bonding structure 188 of the unit region 100 and the bonding structure 288 of the circuit region 200 may include copper, such that the unit region 100 and the circuit region 200 can be bonded to each other by copper-to-copper bonding (e.g., direct bonding).

[0115] For example, the bonding insulating layer of unit region 100 and the bonding insulating layer of circuit region 200 may comprise the same insulating material. For example, the bonding insulating layer of unit region 100 and the bonding insulating layer of circuit region 200 may comprise a layer containing silicon carbonitride or formed of silicon carbonitride at least at the bonding surface. However, the embodiments are not limited thereto. The bonding insulating layer of unit region 100 and / or the bonding insulating layer of circuit region 200 may comprise the same or different material as the unit insulating layer 132 of unit region 100 or the insulating layer 286 of circuit region 200.

[0116] In an embodiment, bit lines BL connected to the channel structure CH and / or gate electrode 130 can be electrically connected to the circuit element 220 of the circuit region 200 via the wiring portion and circuit wiring portion 280 of the cell region 100.

[0117] and Figure 2 and Figure 4 Refer to together Figures 5 to 7 The channel structure CH and the first wiring portion 160 according to the embodiment will be described in more detail.

[0118] Figure 5 It is along Figure 4 The sectional view taken by line C-C' in the figure. Figure 6 yes Figure 3 An enlarged sectional view of part D in the diagram. Figure 7 It is shown Figure 6 The graph shows the doping concentration along direction E. For simplicity, in... Figure 5 In the example shown, the channel structure CH and the dummy structure DH have the same width. However, the embodiments are not limited to this, and as... Figure 4 As shown, the channel structure CH and the dummy structure DH can have different widths or areas.

[0119] Reference Figure 2 , Figures 4 to 7 In an embodiment, the side surface of the covering insulating layer 168a with the opening 168p may include a circular (rounded) portion or a portion having a recessed shape. At least a portion of the opening 168p in the covering insulating layer 168a may be formed by a wet etching process of isotropic etching, and the side surface of the covering insulating layer 168a with the opening 168p may include a circular (rounded) portion or a recessed shape.

[0120] In this embodiment, a wet etching process can be used in the process of forming the opening 168p in the overlay insulating layer 168a, and the opening 168p can be stably formed at the desired location by an easy process. This will be described in more detail later in the method of manufacturing the semiconductor device 10.

[0121] In an embodiment, the channel structure CH may include a channel through portion CHa and a channel extension portion CHb, and may also include a channel extension portion CHc extending to connect the channel through portion CHa and the channel extension portion CHb.

[0122] A channel through-portion CHa may extend through the gate stack structure 120. A channel extension portion CHb may be disposed on the first surface 120a of the gate stack structure 120 and may have a width or area larger than that of the channel through-portion CHa. A channel extension portion CHc may extend to connect the channel through-portion CHa and the channel extension portion CHb on the first surface 120a of the gate stack structure 120 and may have a width or area smaller than that of the channel extension portion CHb. The width of the channel through-portion CHa, the channel extension portion CHb, or the channel extension portion CHc may refer to the width (e.g., length or diameter) of the portion adjacent to the first surface 120a of the gate stack structure 120. The area of ​​the channel through-portion CHa, the channel extension portion CHb, or the channel extension portion CHc may refer to the area of ​​the portion adjacent to the first surface 120a of the gate stack structure 120.

[0123] The channel through portion CHa may be disposed in the gate stack structure 120 and may include a gate dielectric layer 150, a channel layer 140 and a core insulating layer 142.

[0124] The channel extension portion CHb may be disposed on the first surface 120a of the gate stack structure 120, and may include a core insulating layer 142 without a gate dielectric layer 150 and a channel layer 140.

[0125] The channel extension portion CHc may be a portion of the channel layer 140 in which the portion between the channel through portion CHa and the channel extension portion CHb is removed. The channel extension portion CHc may have a shape extending from the channel through portion CHa and may be adjacent to the channel extension portion CHb. For example, the side surface of the channel extension portion CHc may include a surface (e.g., a sloped surface) that extends continuously from the side surface of the channel through portion CHa. The channel extension portion CHc may include a core insulating layer 142, without the gate dielectric layer 150 and the channel layer 140.

[0126] In the extension direction of the channel structure CH (Z-axis direction in the figures), the length (e.g., height) of the channel extension CHc can be substantially the same as the thickness T0 of the channel layer 140. For example, the length of the channel extension CHc can be in the range of 90% to 110% of the thickness T0 of the channel layer 140. However, the embodiments are not limited thereto. In some embodiments, if the channel extension CHc can be a portion in which a portion of the channel layer 140 is removed, the length of the channel extension CHc can be different from the thickness T0 of the channel layer 140. In the extension direction of the channel structure CH (Z-axis direction in the figures), the length of the channel extension CHc can be smaller than the thickness of the gate dielectric layer 150. However, the embodiments are not limited thereto.

[0127] A core insulating layer 142 may be disposed in the channel penetration portion CHa, the channel extension portion CHc, and the channel extension portion CHb. The core insulating layer 142 in the channel extension portion CHb may include a portion having a width or area larger than that of the core insulating layer 142 in each of the channel penetration portion CHa and the channel extension portion CHc. The core insulating layer 142 in the channel extension portion CHc may have a shape extending from the core insulating layer 142 in the channel penetration portion CHa.

[0128] The gate dielectric layer 150 may include a first dielectric portion 150a and a second dielectric portion 150b. The first dielectric portion 150a may extend in the channel penetration portion CHa in the extension direction of the channel structure CH (the Z-axis direction in the figures). The second dielectric portion 150b may extend from the first dielectric portion 150a in a horizontal direction (a direction parallel to the XY plane in the figures). The second dielectric portion 150b may be disposed on a side (side surface) of the first surface 120a of the gate stack structure 120, or may be adjacent to the first surface 120a of the gate stack structure 120. The gate dielectric layer 150 may also include a third dielectric portion 150c extending from the second dielectric portion 150b to be parallel to the side surface of the channel extension portion CHb. The second dielectric portion 150b may have a shape bent from the first dielectric portion 150a, and the third dielectric portion 150c may have a shape bent from the second dielectric portion 150b.

[0129] The portion of the gate dielectric layer 150 exposed on the first surface 120a of the gate stack structure 120 may be removed, and the portion of the gate dielectric layer 150 below the first surface 120a of the gate stack structure 120 on the side surface of the channel through portion CHa may not be removed, to form a gate dielectric layer 150 including a first dielectric portion 150a, a second dielectric portion 150b, and / or a third dielectric portion 150c.

[0130] In an embodiment, the gate dielectric layer 150 may include a first dielectric portion 150a and a second dielectric portion 150b, and the gate dielectric layer 150 may surround the entire side surface of the channel penetration portion CHa, such that the side surface of the channel penetration portion CHa is not exposed. Therefore, through the gate dielectric layer 150, the channel extension portion CHc or the channel penetration portion CHa may not include a portion in which the width of the portion is significantly reduced compared to the other portion. That is, the gate dielectric layer 150 may be disposed in the channel extension portion CHc and the channel penetration portion CHa adjacent to the channel extension portion CHb, and may stably support the channel extension portion CHb to improve the structural stability of the channel structure CH. For example, cutting or separating of the channel structure CH, or thereby minimizing particles from the channel structure CH, can be minimized in the portion adjacent to the channel extension portion CHb. Therefore, the structural stability of the channel structure CH can be improved, and defects can be minimized without new processes or equipment.

[0131] On the other hand, in a comparative example where a portion of the gate dielectric layer on the side surface of the channel penetration portion is removed during a removal process to remove a portion of the gate dielectric layer, the portion of the channel penetration portion where the gate dielectric layer has been removed can have a large length in the extension direction of the channel structure (e.g., a length equal to or greater than the sum of the thickness of the channel layer and the thickness of the gate dielectric layer). Consequently, the portion of the channel penetration portion adjacent to the channel extension portion and having a significantly reduced width or area can have a relatively large length, and the channel penetration portion may have difficulty stably supporting the channel extension portion. Therefore, the portion of the channel penetration portion adjacent to the channel extension portion can be cut or separated, and particles can be formed by cutting or separating this portion of the channel penetration portion. If particles are introduced by cutting or separating the channel structure, a defect can occur where the channel structure and the common source layer are not electrically connected to each other.

[0132] exist Figure 6 In the example shown, the first surface 120a of the gate stack structure 120 and the first surface 150h of the adjacent second dielectric portion 150b are shown. Figure 6 The upper surface of the middle) and the first surface of the third dielectric portion 150c ( Figure 6 The upper surface of the gate stack structure 120 is on the same plane. For example, the first surface 120a of the gate stack structure 120 may be spaced apart from the channel extension portion CHb. In the extension direction of the channel structure CH (the Z-axis direction in the figures), the distance between the first surface 120a of the gate stack structure 120 and the channel extension portion CHb may be the thickness of the channel layer 140. However, the embodiments are not limited thereto. Referring later... Figure 21 Detailed description of the embodiments.

[0133] In an embodiment, the channel layer 140 may be configured to correspond to a portion of the channel penetration portion CHa, and may not be disposed in the other portion of the channel penetration portion CHa, the channel extension portion CHc, and the channel extension portion CHb. For example, the channel layer 140 may be located in a portion of the channel penetration portion CHa between the core insulating layer 142 and the gate dielectric layer 150. The channel layer 140 may not be disposed in the other portion of the channel penetration portion CHa and the channel extension portion CHc between the core insulating layer 142 and the gate dielectric layer 150, and may not be disposed on the core insulating layer 142 in the channel extension portion CHb.

[0134] The channel layer 140 may be connected to a portion of the common source layer 170 in the channel penetration portion CHa (e.g., in contact with a portion of the common source layer 170 in the channel penetration portion CHa). This will be described after the description of the common source layer 170.

[0135] The common source layer 170 may be electrically connected to the channel extension portion CHb of the channel structure CH on the first surface 120a of the gate stack structure 120, which is exposed by the opening 168p. The common source layer 170 may include a first common source layer 172 and a second common source layer 174.

[0136] The first common source layer 172 may include a first portion 172a. The first portion 172a may be electrically connected to a channel extension portion CHb of the channel structure CH on the first surface 120a of the gate stack structure 120, which is exposed by the opening 168p. The first common source layer 172 may also include a second portion 172b and / or a third portion 172c. The second portion 172b may be disposed on the side surface of the covering insulating layer 168a where the opening 168p is provided. The third portion 172c may be disposed on the outer surface of the covering insulating layer 168a.

[0137] For example, a first portion 172a of the first common source layer 172 may contact the first surface 120a of the gate stack structure 120 and the channel extension portion CHb of the channel structure CH. A second portion 172b of the first common source layer 172 may contact the side surface (e.g., a circular (rounded) portion or a recessed shape) of the covering insulating layer 168a, and a third portion 172c of the first common source layer 172 may contact the outer surface of the covering insulating layer 168a.

[0138] When the first common source layer 172 contacts the first surface 120a of the gate stack structure 120, the channel extension portion CHb of the channel structure CH, and / or the covering insulating layer 168a, the channel structure CH and the common source layer 170 can be electrically connected to each other through an easy process. However, the embodiments are not limited thereto. In some embodiments, the first common source layer 172 may not contact the first surface 120a of the gate stack structure 120, the channel extension portion CHb of the channel structure CH, and / or the covering insulating layer 168a, and another layer may be further provided.

[0139] The first portion 172a of the first common source layer 172 may include horizontal conductive portions 1721a, 1722a, and 1723a. The horizontal conductive portions 1721a, 1722a, and 1723a may be disposed on the first surface 120a of the gate stack structure 120 exposed by the opening 168p and the channel extension portion CHb of the channel structure CH. The horizontal conductive portions 1721a, 1722a, and 1723a may include a first horizontal portion 1721a, a second horizontal portion 1722a, and a third horizontal portion 1723a. The first horizontal portion 1721a may be disposed on the first surface of the channel extension portion CHb opposite to or spaced apart from the gate stack structure 120. Figure 6The second horizontal portion 1722a may be disposed on the side surface of the channel extension portion CHb. The third horizontal portion 1723a may be disposed on the periphery of the channel extension portion CHb on the first surface 120a of the gate stack structure 120.

[0140] Horizontal conductive portions 1721a, 1722a, and 1723a (e.g., the first horizontal portion 1721a and the second horizontal portion 1722a) may contact the channel extension portion CHb. For example, horizontal conductive portions 1721a, 1722a, and 1723a may contact the core insulating layer 142 in the channel extension portion CHb. However, the embodiments are not limited thereto.

[0141] In the sectional view, the first horizontal portion 1721a and the second horizontal portion 1722a may be connected to have an obtuse angle (e.g., an angle greater than 90 degrees and less than 180 degrees). In the sectional view, the second horizontal portion 1722a and the third horizontal portion 1723a may be connected to have an obtuse angle (e.g., an angle greater than 90 degrees and less than 180 degrees).

[0142] exist Figure 6 In the example shown, the thickness T1 of the first horizontal portion 1721a, the thickness T2 of the second horizontal portion 1722a, and the thickness T3 of the third horizontal portion 1723a are substantially the same. "Substantially the same" can mean having differences within the range of process tolerances (e.g., less than 10%). However, the embodiment is not limited to this, and at least two of the thicknesses T1 of the first horizontal portion 1721a, T2 of the second horizontal portion 1722a, and T3 of the third horizontal portion 1723a may be different from each other.

[0143] The first portion 172a of the first common source layer 172 may further include extended conductive portions 1724a and 1725a. The extended conductive portions 1724a and 1725a may include portions between at least a portion of the gate stack structure 120 and the channel structure CH. For example, the first portion 172a of the first common source layer 172 or the extended conductive portions 1724a and 1725a may include a first extended portion 1724a and a second extended portion 1725a. The first extended portion 1724a may be disposed on a second surface of the channel extension portion CHb adjacent to the first surface 120a of the gate stack structure 120. Figure 6The second extension 1725a may extend from the first extension 1724a and may be disposed on the side surface of the channel through portion CHa on the first dielectric portion 150a. For example, the first extension 1724a may be disposed between the first surface 120a of the gate stack structure 120 and the second surface of the channel extension portion CHb. For example, the second extension 1725a may be disposed between the gate dielectric layer 150 and the core insulating layer 142 on the side surface of the channel through portion CHa.

[0144] For example, the first extension 1724a may be connected to the second surface of the channel extension CHb (e.g., the core insulation layer 142) (e.g., Figure 6 The second extension 1725a may contact the lower surface of the gate dielectric layer 150 and / or the first surface 120a of the gate stack structure 120. The second extension 1725a may contact the side surface of the gate dielectric layer 150 and / or the side surface of the core insulating layer 142 in the channel through portion CHa. However, the embodiments are not limited thereto.

[0145] For example, in the extension direction of the channel structure CH (Z-axis direction in the figures), the second extension portion 1725a may not be stacked with the gate electrode 130, or it may be stacked with one or two gate electrodes 130. Thus, the undesirable effects that the second extension portion 1725a may cause to the operation of the transistor including the gate electrode 130 can be reduced. For example, in the extension direction of the channel structure CH, the second extension portion 1725a may be configured to correspond to the interior of the outermost interlayer insulating layer 132n at the first surface 120a of the gate stack structure 120. Thus, the undesirable effects that the second extension portion 1725a may cause to the operation of the transistor including the gate electrode 130 can be minimized. However, the embodiments are not limited to this, and the second extension portion 1725a may be configured to be stacked with three or more gate electrodes 130 in the extension direction of the channel structure CH.

[0146] The first extension 1724a may extend parallel to the third horizontal portion 1723a. The thickness T4 of the first extension 1724a may be smaller than the thickness T1 of the first horizontal portion 1721a, the thickness T2 of the second horizontal portion 1722a, or the thickness T3 of the third horizontal portion 1723a. In a cross-sectional view, the first extension 1724a and the second extension 1725a may be connected at an obtuse angle (e.g., an angle greater than 90 degrees and less than 180 degrees) or a right angle. In a cross-sectional view, the angle between the first extension 1724a and the second extension 1725a may be smaller than the angle between the first horizontal portion 1721a and the second horizontal portion 1722a or the angle between the second horizontal portion 1722a and the third horizontal portion 1723a. The thickness T5 of the second extension 1725a may be smaller than the thickness T1 of the first horizontal portion 1721a, the thickness T2 of the second horizontal portion 1722a, or the thickness T3 of the third horizontal portion 1723a.

[0147] The second portion 172b of the first common source layer 172 can contact the side surface of the covering insulating layer 168a in which an opening 168p is provided. In an embodiment, by using the opening 168p of the covering insulating layer 168a, a portion of the cell array region 102 in which the first portion 172a of the first common source layer 172 is provided and another portion (e.g., the connection region 104, the buffer region 106, and the outer region 12) can be separated. Thus, additional region separation patterns configured to separate one portion of the cell array region 102 from another portion are not required, and the structure and manufacturing process are simplified.

[0148] On the other hand, in comparative examples that include additional region separation patterns configured to separate one part of the cell array region from another, photolithography, etching, deposition processes (e.g., atomic layer deposition (ALD)), chemical mechanical polishing, etc., may be additionally performed. Therefore, the manufacturing process can be complex. Specifically, the region separation patterns may be formed as fine patterns with small intervals between multiple channel structures or between channel structures and dummy structures, and the manufacturing process may be complex and / or new processes or equipment may be applied.

[0149] In an embodiment, the second common source layer 174 may include a first portion on a first portion 172a of the first common source layer 172. The second common source layer 174 may include a second portion on a second portion 172b of the first common source layer 172 and / or a third portion on a third portion 172c of the first common source layer 172.

[0150] For example, a first portion of the second common source layer 174 may contact a first portion 172a of the first common source layer 172, a second portion of the second common source layer 174 may contact a second portion 172b of the first common source layer 172, and / or a third portion of the second common source layer 174 may contact a third portion 172c of the first common source layer 172. However, the embodiments are not limited thereto. In some embodiments, the second common source layer 174 may not contact the first common source layer 172, and an additional layer may be disposed between the first common source layer 172 and the second common source layer 174. In some embodiments, the second common source layer 174 may be omitted.

[0151] The common source layer 170 may cover the entire opening 168p of the covering insulating layer 168a, and may also be disposed on a portion of the covering insulating layer 168a. In a plan view, the interior portion of the common source layer 170 may overlap with the opening 168p, and the edge portion of the common source layer 170 may overlap with the covering insulating layer 168a to have a rectangular shape, but the embodiments are not limited thereto.

[0152] The channel layer 140 (e.g., an end of the channel layer 140) may be connected in the channel through portion CHa to the ends of the extended conductive portions 1724a and 1725a (e.g., the second extension 1725a) (e.g., in contact with the ends of the extended conductive portions 1724a and 1725a (e.g., the second extension 1725a) in the channel through portion CHa). The extended conductive portions 1724a and 1725a may fill the portion of the channel layer 140 in which a portion is removed. For example, the portion of the channel layer 140 surrounding the channel extension portion CHb (e.g., the first surface of the channel layer 140 on the channel extension portion CHb). Figure 6 The upper surface, side surface and second surface (in) Figure 6 A portion of the lower surface of the channel layer 140 may be removed, and a first common source layer 172 may be formed in the portion of the channel layer 140 in which the portion is removed. Therefore, the first common source layer 172 may include extended conductive portions 1724a and 1725a.

[0153] The length of the channel extension CHc or the thickness T4 or T5 of the extended conductive portions 1724a or 1725a can be substantially the same as the thickness T0 of the channel layer 140. For example, the length of the channel extension CHc or the thickness T4 or T5 of the extended conductive portions 1724a or 1725a can be in the range of 90% to 110% of the thickness T0 of the channel layer 140. However, the embodiments are not limited thereto. In some embodiments, if the extended conductive portions 1724a and 1725a can be disposed in the portion in which a portion of the channel layer 140 is removed, the length of the channel extension CHc and the thickness of the channel layer 140 can be different from each other.

[0154] In the side surface of the channel penetration portion CHa, the channel layer 140 may include a diffusion-doped portion 140d in the portion adjacent to the first common source layer 172 (e.g., the second extension portion 1725a). The diffusion-doped portion 140d of the channel layer 140 may have the same conductivity type as the first common source layer 172, and may have a higher doping concentration than the undoped portion 140u of the channel layer 140.

[0155] like Figure 7 As shown, the first cascade layer 172 may have substantially the same or uniform doping concentration. For example, the first portion 172a (e.g., horizontal conductive portions 1721a, 1722a, and 1723a, and extended conductive portions 1724a and 1725a), the second portion 172b, and the third portion 172c of the first cascade layer 172 may have substantially the same or uniform doping concentration. "Substantially the same" may mean having a difference within process tolerances (e.g., less than 10%). The doping concentration of the diffused doped portion 140d may gradually decrease away from the first cascade layer 172. This may be because the diffused doped portion 140d is formed by the diffusion of dopant included in the first cascade layer 172 into a portion of the channel layer 140.

[0156] The location of the diffused doped portion 140d and the boundary between the diffused doped portion 140d and the first common source layer 172 can be confirmed or anticipated by the doping concentration.

[0157] In an embodiment, in the channel structure CH including the channel extension portion CHb, horizontal doped regions and sidewall doped regions may be included. The horizontal doped regions may be disposed between the second dielectric portion 150b (or the first surface 120a of the gate stack structure 120) and the second surface of the channel extension portion CHb (…). Figure 6 Between the lower surface of the channel through portion CH and the core insulating layer 142. A sidewall doped region may be disposed on the side surface of the channel through portion CHa on the first dielectric portion 150a. In the extension direction of the channel structure CH (Z-axis direction in the figures), the sidewall doped region may include a portion overlapping with the second dielectric portion 150b extending in the horizontal direction. For example, the sidewall doped region may be disposed on the side surface of the channel through portion CHa between the first dielectric portion 150a and the core insulating layer 142.

[0158] The horizontal doped region may be or include a portion of the common source layer 170. For example, the horizontal doped region may include at least a portion of the extended conductive portions 1724a and 1725a (e.g., the first extended portion 1724a). The sidewall doped region may include a portion of the common source layer 170 disposed between the first dielectric portion 150a and the core insulating layer 142 (e.g., at least a portion of the extended conductive portions 1724a and 1725a (e.g., the second extended portion 1725a)), and / or the diffused doped portion 140d of the channel layer 140.

[0159] As described above, the common source layer 170 (e.g., the first portion 172a of the first common source layer 172 or a doped semiconductor layer) may surround the entire surface (e.g., the first surface, side surface, and second surface) of the channel extension portion CHb. That is, horizontally doped regions with low resistance and sidewall doped regions may be provided at the corner portions (e.g., L-shaped portions) of the channel extension portion CHb. Therefore, the cell current at the corner portions (e.g., L-shaped portions) of the channel extension portion CHb can be improved.

[0160] In an embodiment, a first common source layer 172 (e.g., extended conductive portions 1724a and 1725a) may be formed in the portion of the channel layer 140 in which a portion of the channel extension portion CHb is removed. Therefore, a doped region with a high doping concentration can be formed at the corner portion of the channel extension portion CHb without performing additional doping processes and / or additional annealing processes to increase the doping concentration of the channel layer 140. This simplifies the manufacturing process by allowing it to be performed without new equipment or processes (e.g., ion implantation). In the process of removing a portion of the channel layer 140 from the channel extension portion CHb, particles at the periphery of the channel extension portion CHb can be removed, and defects can be reduced.

[0161] In an embodiment, the sidewall doped region may include the second extension 1725a and the diffusion doped region 140d together, and the sidewall doped region may have sufficient length or area. That is, by including the second extension 1725a extending along the channel penetration portion CHa, the diffusion doped region 140d may be formed by dopant diffusing from the second extension 1725a, and the sidewall doped region may have sufficient length or area. This effectively improves the cell current. However, the embodiment is not limited to this, and the sidewall doped region may include at least one of the second extension 1725a and the diffusion doped region 140d.

[0162] On the other hand, in a comparative example where a common source layer including a dopant is formed on the channel layer, the dopant can diffuse into a portion of the channel layer within the channel extension. Therefore, a portion of the channel layer at the outer surface of the channel extension may include a doped diffusion region where the doping concentration gradually decreases. In this case, the dopant may not diffuse sufficiently into the portion of the channel layer at the corner of the channel extension, and an undoped portion may be present at the corner of the channel extension. Consequently, the cell current at the corner of the channel extension may not be sufficient.

[0163] In an embodiment, the thickness of the covering insulating layer 168a may be greater than the thickness of the first common source layer 172 or the height of the channel extension portion CHb. The thickness of the covering insulating layer 168a may be the thickness (e.g., the maximum thickness) in the extension direction of the channel structure CH (Z-axis direction in the figures). The thickness of the first common source layer 172 may be the thickness (e.g., the maximum thickness) in a direction perpendicular to the extension direction of the first common source layer 172. For example, the thickness of the first common source layer 172 may be the maximum thickness among the thickness T1 of the first horizontal portion 1721a, the thickness T2 of the second horizontal portion 1722a, and the thickness T3 of the third horizontal portion 1723a. The height of the channel extension portion CHb may be the length or thickness (e.g., the maximum length or maximum thickness) in the extension direction of the channel structure CH. Thus, the covering insulating layer 168a can stably protect the connection region 104, the buffer region 106, and / or the outer region 12. However, the embodiment is not limited to this.

[0164] In an embodiment, the thickness of the first common source layer 172 may be smaller than the height of the channel extension portion CHb. For example, in the extension direction of the channel structure CH (the Z-axis direction in the figures), the first surface of the third horizontal portion 1723a ( Figure 6 The upper surface of the channel extension portion CHb is comparable to the first surface of the channel extension portion. Figure 6 The upper surface of the channel structure CH is lower than the lower surface of the channel extension portion CHb. For example, in the extension direction of the channel structure CH, the first surface of the third horizontal portion 1723a may be on the first surface of the channel extension portion CHb. Figure 6 The upper surface and the second surface Figure 6 Between the lower surface of the first common source layer 172 and the channel extension portion CHb. When the thickness of the first common source layer 172 is relatively small, the energy used in the heat treatment process of the first common source layer 172 can be reduced. However, the embodiments are not limited to this, and the thickness of the first common source layer 172 may be the same as or greater than the height of the channel extension portion CHb.

[0165] The thickness T6 (e.g., maximum thickness) of the second common source layer 174 may be smaller than the thickness (e.g., maximum thickness) of the first common source layer 172. However, the embodiments are not limited thereto, and the thickness T6 of the second common source layer 174 may be the same as or greater than the thickness of the first common source layer 172.

[0166] In an embodiment, in the extension direction of the channel structure CH (Z-axis direction in the figures), the length D1 of the second extension portion 1725a, the length D2 of the diffusion-doped portion 140d, or the length of the sidewall doped region may be greater than the thickness T4 of the first extension portion 1724a or the thickness of the horizontal doped region. The length D1 of the second extension portion 1725a may refer to the length (e.g., the maximum length) from the first surface 150h of the second dielectric portion 150b. The first surface 150h of the second dielectric portion 150b may refer to the surface adjacent to the first surface 120a of the gate stack structure 120. Thus, the length D1 of the second extension portion 1725a can be sufficient, and the cell current can be effectively improved.

[0167] In an embodiment, the length D1 of the second extension portion 1725a in the extension direction of the channel structure CH (Z-axis direction in the figures) may be smaller than the thickness (e.g., maximum thickness) of the first common source layer 172. For example, the length D1 of the second extension portion 1725a may be smaller than the thickness of the first common source layer 172 (e.g., the thickness T1 of the first horizontal portion 1721a, the thickness T2 of the second horizontal portion 1722a, or the thickness T3 of the third horizontal portion 1723a). Thus, the second extension portion 1725a can be stably formed. However, the embodiment is not limited to this. The length D1 of the second extension portion 1725a may be the same as or greater than the thickness of the first common source layer 172. Thus, the length D1 of the second extension portion 1725a may be sufficient to improve the cell current at the corner portion of the channel extension portion CHb.

[0168] In an embodiment, the length D2 of the diffused doped portion 140d in the extension direction of the channel structure CH (Z-axis direction in the figures) may be smaller than the thickness (e.g., maximum thickness) of the first common source layer 172. This minimizes any undesirable effects that the diffused doped portion 140d may cause on the operation of the transistor including the gate electrode 130. However, the embodiment is not limited thereto. In some embodiments, the length D2 of the diffused doped portion 140d may be the same as or greater than the thickness (e.g., maximum thickness) of the first common source layer 172.

[0169] In an embodiment, in the extension direction of the channel structure CH (Z-axis direction in the figures), the length D1 of the second extension portion 1725a may be greater than the length D2 of the diffusion-doped portion 140d. The length D2 of the diffusion-doped portion 140d may refer to the length (e.g., the maximum length) from the portion adjacent to the second extension portion 1725a. In some embodiments, the length D1 of the second extension portion 1725a may be the same as or smaller than the length D2 of the diffusion-doped portion 140d.

[0170] In an embodiment, the length D1 of the second extension portion 1725a or the length D2 of the diffusion-doped portion 140d in the extension direction of the channel structure CH (Z-axis direction in the figures) may be smaller than the height of the channel extension portion CHb. Therefore, the second extension portion 1725a can be stably formed, and the undesirable effects caused by the second extension portion 1725a or the diffusion-doped portion 140d on the operation of the transistor including the gate electrode 130 can be minimized. However, the embodiment is not limited to this, and the length D1 of the second extension portion 1725a or the length D2 of the diffusion-doped portion 140d may be the same as or greater than the height of the channel extension portion CHb.

[0171] According to an embodiment, a covering insulating layer 168a with an opening 168p may be included, and a structure that selectively exposes at least a portion of the cell array region 102 can be readily formed. The entire side surface of the channel through portion CHa and / or the channel extension portion CHc may be surrounded by a gate dielectric layer 150, and the structural stability of the channel structure CH including the channel extension portion CHb may be improved. A common source layer 170 may be formed in the empty space created by removing a portion of the channel layer 140 adjacent to the channel extension portion CHb, and the cell current at the corner portion of the channel extension portion CHb may be improved, and particles may be removed. This improves the productivity and reliability of the semiconductor device 10.

[0172] In the description, as an example, semiconductor device 10 is described as a bonded vertical NAND flash memory. However, the embodiments are not limited to this, and the embodiments can be applied to any semiconductor device or bonded semiconductor device of various types.

[0173] Figures 8 to 19 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment. Hereinafter, the method will be based on the gate stack structure 120, the channel structure CH, and the separator structure 146 (see reference 146) included in the cell region. Figure 2 The manufacturing method of a semiconductor device is described by covering an insulating layer 168a and a common source layer 170. Figures 8 to 14 as well as Figures 17 to 19 Showing with Figure 5 The corresponding part, and Figure 15 and Figure 16 Showing with Figure 6 The corresponding part.

[0174] like Figure 8 As shown, an etch stop pattern 114 can be formed in the semiconductor substrate 112, a first stack portion 121s can be formed on the semiconductor substrate 112, and a first pre-penetration portion P1 can be formed through the first stack portion 121s.

[0175] Semiconductor substrate 112 may include semiconductor materials. For example, semiconductor substrate 112 may be a semiconductor substrate comprising or formed of semiconductor materials, or a semiconductor substrate in which semiconductor layers are on a substrate. For example, semiconductor substrate 112 may include semiconductor materials having a single-crystal structure, epitaxial structure, or polycrystalline structure (e.g., silicon, germanium, silicon-germanium, etc.), silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc., or may be formed from semiconductor materials having a single-crystal structure, epitaxial structure, or polycrystalline structure (e.g., silicon, germanium, silicon-germanium, etc.), silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc.

[0176] An etch stop pattern 114 may be formed in the semiconductor substrate 112. The etch stop pattern 114 may be formed in the portion of the first pre-penetration portion P1 in the plan view. The etch stop pattern 114 may have a shape corresponding to the shape of the first pre-penetration portion P1, and may have a width or area larger than the width or area of ​​the first pre-penetration portion P1.

[0177] The etch stop pattern 114 may include at least one of a semiconductor material (e.g., polysilicon), a metal (e.g., tungsten), a metal nitride (e.g., tungsten nitride or titanium nitride), and carbon, or may be formed from at least one of a semiconductor material (e.g., polysilicon), a metal (e.g., tungsten), a metal nitride (e.g., tungsten nitride or titanium nitride), and carbon. The etch stop pattern 114 may include a single layer or multiple layers. In an embodiment, an interface layer comprising an insulating material may be further included between the semiconductor substrate 112 and the etch stop pattern 114.

[0178] The etch stop pattern 114 can be formed by using a mask layer to form a trench in a semiconductor substrate 112 in which an etch stop pattern 114 will be set, and then filling the trench with a filler material. The process of forming the trench can be performed by any of a variety of processes (e.g., an etching process, etc.), and the process of filling with the filler material can be performed by any of a variety of processes (e.g., a deposition process, etc.).

[0179] In an embodiment, an upper insulating layer may be further formed on the semiconductor substrate 112. For example, the upper insulating layer may be formed from the remainder of the mask layer used to form the etch stop pattern 114. When the upper insulating layer may comprise the same material as the interlayer insulating layer 132m of the first stack portion 121s, the boundary between the upper insulating layer and the interlayer insulating layer 132m may not be defined. In this case, as Figure 8 As shown, the upper surface of the etch stop pattern 114 may protrude from the upper surface of the semiconductor substrate 112. Various other modified embodiments are possible.

[0180] A first stacked portion 121s may be formed on a semiconductor substrate 112. For example, the first stacked portion 121s may be formed by alternately stacking an interlayer insulating layer 132m and a sacrificial insulating layer 130s on the semiconductor substrate 112. At least a portion of the sacrificial insulating layer 130s may be processed by a gate electrode 130 (see reference) in a subsequent process. Figure 10 Replacement. The sacrificial insulating layer 130s may be formed to correspond to the portion in which the gate electrode 130 will be disposed.

[0181] The sacrificial insulating layer 130s may include a material different from that of the interlayer insulating layer 132m. For example, the interlayer insulating layer 132m may include at least one of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, etc., or may be formed from at least one of silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, etc. The sacrificial insulating layer 130s may include at least one of silicon, silicon oxide, silicon carbide, and silicon nitride, or may be formed from at least one of silicon, silicon oxide, silicon carbide, and silicon nitride, and may include a material different from that of the interlayer insulating layer 132m.

[0182] The interlayer insulation layer 132m or the sacrificial insulation layer 130s can be formed by any of the various processes (e.g., deposition process, etc.).

[0183] A first preliminary through-portion P1 can be formed through the first stack portion 121s. The first preliminary through-portion P1 can be formed by any of various processes (e.g., etching process, etc.).

[0184] The end of the first pre-penetrating portion P1 adjacent to the semiconductor substrate 112 can be disposed in the etch stop pattern 114. Since the width or area of ​​the etch stop pattern 114 can be larger than the width or area of ​​the first pre-penetrating portion P1, the entire end of the first pre-penetrating portion P1 can be stably disposed in the etch stop pattern 114.

[0185] Subsequently, as Figure 9 As shown, an insulating stack structure 120s can be formed by forming a second stack portion 122s, and a pre-through portion P can be formed.

[0186] For example, a sacrificial portion can be formed by filling the first pre-penetrating portion P1 with sacrificial material, a second stacked portion 122s can be formed, a second pre-penetrating portion P2 can be formed through the second stacked portion 122s, and the sacrificial portion and etch stop pattern 114 can be removed (see reference). Figure 8 The portion originally provided with the etching stop pattern 114 can constitute an extended through portion P3. Thus, a pre-through portion P including a first pre-through portion P1, a second pre-through portion P2, and an extended through portion P3 can be formed.

[0187] The sacrificial portion in the first pre-penetrating portion P1 may include at least one of a semiconductor material (e.g., polysilicon), a metal (e.g., tungsten), a metal nitride (e.g., tungsten nitride or titanium nitride), and carbon, or may be formed of at least one of a semiconductor material (e.g., polysilicon), a metal (e.g., tungsten), a metal nitride (e.g., tungsten nitride or titanium nitride), and carbon. For example, the sacrificial portion may include the same or a different material than the material of the etch stop pattern 114.

[0188] The description of the sacrificial insulating layer 130s and / or interlayer insulating layer 132m of the first stack portion 121s can be applied to the sacrificial insulating layer 130s and / or interlayer insulating layer 132m of the second stack portion 122s. The second pre-existing through portion P2 can be formed by any of various processes (e.g., etching process, etc.). The process of removing the sacrificial portion and etching the stop pattern 114 can be performed by any of various processes (e.g., etching process, etc.).

[0189] In the embodiments, the insulating stack structure 120s is shown and described by way of example as including a first stack portion 121s and a second stack portion 122s sequentially stacked on the semiconductor substrate 112. However, the embodiments are not limited thereto, and the insulating stack structure 120s may include a single stack portion or three or more stack portions.

[0190] In an embodiment, the pre-penetrating portion P may include a channel structure CH (refer to...). Figure 10 The channel preparation penetration section P will be set in the CHP section. The preparation penetration section P may also include a dummy structure DH (refer to) therein. Figure 10 The virtual preparatory through-section DHP will be provided, in which a partition structure 146 will be installed (refer to...). Figure 2 At least a portion of the partition is prepared to pass through the section, and / or input / output connection wiring 194 will be provided therein (see reference). Figure 2 The wiring preparation for the through section.

[0191] As described above, the etch stop pattern 114 is configured to correspond to the portion where the pre-penetration portion P will be disposed, and the pre-penetration portion P may include an extended penetration portion P3 formed by removing the etch stop pattern 114. Therefore, in embodiments, each of the channel pre-penetration portion, the dummy pre-penetration portion, the partition pre-penetration portion, and / or the wiring pre-penetration portion may include an extended penetration portion P3.

[0192] The first pre-penetration portion P1 and the second pre-penetration portion P2 corresponding to the pre-penetration portion P of the channel structure CH, the dummy structure DH, or the input / output connection wiring may have shapes corresponding to the shapes of the channel penetration portion of the channel structure CH, the dummy penetration portion of the dummy structure DH, or the wiring penetration portion of the input / output connection wiring. The extended penetration portion P3 corresponding to the pre-penetration portion P of the channel structure CH, the dummy structure DH, or the input / output connection wiring may have shapes corresponding to the shapes of the channel extension portion of the channel structure CH, the dummy extension portion of the dummy structure DH, or the wiring extension portion of the input / output connection wiring. For example, the extended penetration portion P3 corresponding to the pre-penetration portion P of the channel structure CH, the dummy structure DH, or the input / output connection wiring may have any planar shape (e.g., circular shape, elliptical shape, polygonal shape, etc.) of various planar shapes corresponding to the channel extension portion of the channel structure CH, the dummy extension portion of the dummy structure DH, or the wiring extension portion of the input / output connection wiring. For example, the extended through portion P3 of the pre-pass portion P corresponding to the channel structure CH, dummy structure DH, or input / output connection wiring may have a width or area larger than the width or area of ​​each of the first pre-pass portion P1 and the second pre-pass portion P2 of the pre-pass portion P corresponding to the channel structure CH, dummy structure DH, or input / output connection wiring.

[0193] The first pre-penetrating portion P1 and the second pre-penetrating portion P2 corresponding to the partition structure may correspond to a portion of the partition structure. For example, the first pre-penetrating portion P1 and the second pre-penetrating portion P2 corresponding to the partition structure may have any planar shape of various planar shapes (e.g., circular shape, elliptical shape, polygonal shape, etc.). For example, the extended penetrating portion P3 corresponding to the partition structure may have a width or area larger than the width or area of ​​each of the first pre-penetrating portion P1 and the second pre-penetrating portion P2 corresponding to the partition structure.

[0194] In the embodiment, the pre-through portion P is described and shown as an example, excluding the gate contact 192 (see reference). Figure 10 The pre-penetration portion P may include the pre-penetration portion corresponding to the gate contact 192.

[0195] Subsequently, as Figure 10 As shown, the preparatory cell region 100a can be formed by forming a gate stack structure 120 and forming a channel structure CH, a dummy structure DH, a separator structure, a through wiring portion 190, and a second wiring portion 180.

[0196] CHP can be prepared for the penetration section of the trench (refer to) Figure 9 The channel structure CH is formed in the channel preparation through portion CHP. For example, the gate dielectric layer 150 (see reference) can be sequentially formed in the channel preparation through portion CHP. Figure 14 ), channel layer 140 (refer to) Figure 14 ) and core insulation layer 142 (refer to Figure 14 In this case, the first barrier layer 156a of the gate dielectric layer 150 may not be formed (see reference). Figure 3 ), and the first barrier layer 156a of the gate dielectric layer 150 can be formed in subsequent processes (see reference). Figure 3 The process of forming the gate dielectric layer 150, the channel layer 140, or the core insulating layer 142 can be performed by any of a variety of processes (e.g., deposition process, etc.).

[0197] A virtual pre-connection section DHP can be set up (refer to...) Figure 9 A dummy structure DH is formed within the dummy pre-penetration portion DHP. For example, the dummy structure DH can be formed by filling the dummy pre-penetration portion DHP with insulating material, or by filling the dummy pre-penetration portion DHP with a layer included in the channel structure CH. A portion of the dummy structure DH can be formed using sacrificial material, etc., in the dummy pre-penetration portion DHP. Various other modified embodiments are possible.

[0198] The through-hole portion for the partition structure can be formed by performing an etching process that extends the pre-existing through-hole portion P corresponding to the partition structure in the horizontal direction. Thus, the side surface of the through-hole portion for the partition structure can be as follows: Figure 4 The shape shown has a continuous arrangement of curved surfaces with outwardly convex curvature. However, the embodiments are not limited to this. In some embodiments, the pre-formed through-hole portion P corresponding to the partition structure may not be formed, and the through-hole portion for the partition structure may be formed after the insulating stack structure has been formed for 120 seconds. Various other modified embodiments are possible.

[0199] Gate contacts 192 may be formed in connection region 104, and input / output connection wiring may be formed in the outer region. Gate contacts 192 and / or input / output connection wiring may be formed by any of a variety of processes, but embodiments are not limited thereto.

[0200] The sacrificial insulating layer 130s can be replaced with the gate electrode 130 by using a through portion for separating the structure (see reference). Figure 9 The partition structure can be formed by filling the through-holes used for the partition structure with filler material. A partition pattern 148 (see reference) can be formed. Figure 2 ), and can form a second wiring section 180.

[0201] For example, the sacrificial insulating layer 130s can be selectively removed by using an etching process (e.g., a wet etching process) for the through portion used to separate the structure. A conductive material can be formed or filled in the portion where the sacrificial insulating layer 130s has been removed. The process of forming the gate electrode 130 can be performed by any of various processes (e.g., a deposition process, etc.). Thus, the horizontal region where the sacrificial insulating layer 130s was originally disposed can be replaced with the gate electrode 130. In this case, the formation of the first barrier layer 156a (see reference) can be further performed before the process of filling the conductive material constituting the gate electrode 130. Figure 3 The process of ).

[0202] Thus, a gate stack structure 120 including a gate electrode 130 and an interlayer insulating layer 132m can be formed. In an embodiment, the gate stack structure 120 may include a plurality of gate stack portions 121 and 122 sequentially stacked on a semiconductor substrate 112. However, the embodiments are not limited thereto.

[0203] The process of filling the through-section of a partition structure with filler material can be performed using any of a variety of processes (e.g., deposition processes, etc.). For example, an insulating layer can be formed to fill the through-section of the partition structure. The partition structure may include the through-section and an extension having a width or area smaller than that of the through-section.

[0204] It can be achieved in an insulating stacked structure in 120 seconds (refer to...) Figure 9 A partition pattern is formed in a portion of the gate stack structure 120. The partition pattern is formed by forming openings for the partition pattern via an etching process using a mask layer, and filling at least a portion of the openings with an insulating material. In semiconductor device manufacturing methods, the process for forming the partition pattern can be modified in various ways.

[0205] A second wiring portion 180 can be formed, comprising a second wiring layer 182, a second contact 184, an insulating layer 186, and a bonding structure 188, wherein the second wiring layer 182 includes bit lines BL. Thus, a pre-formed unit region 100a can be formed.

[0206] Subsequently, as Figure 11As shown, the pre-set cell region 100a can be bonded to the circuit region 200. For example, the pre-set cell region 100a can be bonded to the circuit region 200 to have an inverted structure. In the inverted structure, the portion of the pre-set cell region 100a remote from the semiconductor substrate 112 can be configured to face the circuit region 200. Hybrid bonding can be performed by an annealing process while the circuit region 200 and the pre-set cell region 100a are in contact with each other.

[0207] Subsequently, as Figure 12 As shown, the removable semiconductor substrate 112 (refer to) Figure 11 Furthermore, an insulating layer 168a can be formed on the first surface 120a of the gate stack structure 120.

[0208] The process of removing the semiconductor substrate 112 can be performed using any of various processes (etching, grinding, chemical mechanical polishing, etc.). When the semiconductor substrate 112 is removed, the first surface 120a of the gate stack structure 120 and the portion of the channel structure CH on the first surface 120a of the gate stack structure 120 are exposed.

[0209] In the process of forming the cover insulating layer 168a, the cover insulating layer 168a can be integrally formed on the first surface 120a of the gate stack structure 120 and the channel structure CH. The cover insulating layer 168a can be formed by any of a variety of processes. For example, the cover insulating layer 168a can be formed by a deposition process (as an example, plasma-enhanced chemical vapor deposition (PECVD)).

[0210] Subsequently, as Figure 13 and Figure 14 As shown, an opening 168p may be formed in the covering insulating layer 168a. The opening 168p of the covering insulating layer 168a may be configured to expose at least a portion of the cell array region 102. Thus, regions other than the cell array region 102 (e.g., connection region 104, buffer region 106, and / or external regions) may be protected by the covering insulating layer 168a, and at least a portion of the cell array region 102 may be exposed by the opening 168p.

[0211] For example, through such Figure 13 The opening 168p (e.g., opening portion 168s) is formed by using a first etching process, and as shown... Figure 14 The opening 168p can be formed by forming another portion of the opening 168p using a second etching process different from the first etching process.

[0212] exist Figure 13In the first etching process shown, the opening 168s can be formed by removing a portion of the covering insulating layer 168a in the thickness direction (Z-axis direction in the figure). The opening 168s can be formed as a protrusion CP that does not expose the channel structure CH protruding from the first surface 120a of the gate stack structure 120 (see figure). Figure 14 In other words, the insulating layer 168a can be disposed below the opening 168s to cover the protruding portion CP of the channel structure CH. The protruding portion CP of the channel structure CH can be the channel extension portion CHb that includes the channel structure CH (see reference). Figure 16 ) and / or the channel extension CHc (refer to Figure 16 ( ) part.

[0213] exist Figure 14 In the second etching process shown, the opening 168p can be formed by removing a portion of the covering insulating layer 168a corresponding to another portion of the opening 168p in the extension direction of the channel structure CH or the thickness direction of the covering insulating layer 168a (Z-axis direction in the figure). The opening 168p can be formed to expose the protruding portion CP of the channel structure CH. By a wet etching process, the side surface of the covering insulating layer 168a in which the opening 168p is disposed may include a portion having a circular (rounded) shape or a recessed shape. In this case, the protruding portion CP of the channel structure CH may include the gate dielectric layer 150 and the channel layer 140.

[0214] For example, the first etching process can be a dry etching process, and the second etching process can be a wet etching process. In areas where no protrusion CP is provided along the extension direction of the channel structure CH, the opening 168s can be formed using a dry etching process. Thus, the opening 168s can be formed at the desired location in the plan view, and the time of the second etching process (e.g., a wet etching process) can be reduced. In areas where the protrusion CP is provided along the extension direction of the channel structure CH, the portion of the insulating layer 168a covering the opening 168s in the cross-sectional view can be reliably removed using a wet etching process to expose the channel structure CH. This effectively prevents damage to the channel structure CH that could be caused by a dry etching process.

[0215] In an embodiment, by partially applying a first etching process and a second etching process that are different from each other, the opening 168p can be stably formed in the covering insulating layer 168a at the desired location in the plan view and in the cross-sectional view.

[0216] In one embodiment, the thickness of the portion of the insulating layer 168a removed by the first etching process may be greater than the thickness of the portion of the insulating layer 168a removed by the second etching process. This allows for precise formation of the opening 168p at a desired location in the plan view and reduces the process time of the second etching process (e.g., a wet etching process). However, the embodiment is not limited to this. In another embodiment, the thickness of the portion of the insulating layer 168a removed by the first etching process may be the same as or less than the thickness of the portion of the insulating layer 168a removed by the second etching process.

[0217] In an embodiment, the opening 168p can be formed in the covering insulating layer 168a by using a first etching process and a second etching process, and at least a portion of the cell array region 102 can be stably physically or structurally separated from another region without additional structure.

[0218] Subsequently, as Figure 15 As shown, a portion of the gate dielectric layer 150 within the protruding portion CP of the channel structure CH can be removed. This exposes the channel layer 140 of the channel structure CH to the outside.

[0219] In an embodiment, a portion of the gate dielectric layer 150 exposed in the channel structure CH through the opening 168p of the covering insulating layer 168a may be removed. For example, the first surface of the protruding portion CP of the gate dielectric layer 150 in the channel structure CH may be removed (…). Figure 15 The portion of the gate dielectric layer 150 at the top surface and side surface. Thus, another portion of the third dielectric portion 150c, the first dielectric portion 150a, and the second dielectric portion 150b of the gate dielectric layer 150 can be retained. For example, a portion of the gate dielectric layer 150 can be removed, such that the first surface of the gate dielectric layer 150 (the top surface) and the side surface are partially removed. Figure 15 The upper surface of the gate dielectric layer 150 is on the same plane as the first surface 120a of the gate stack structure 120. During the process of removing a portion of the gate dielectric layer 150, the portion of the outermost interlayer insulating layer 132n at the first surface 120a of the gate stack structure 120 can be removed together. Even in this case, the first surface of the gate dielectric layer 150 can still be on the same plane as the first surface 120a of the gate stack structure 120.

[0220] In an embodiment, during the process of removing a portion of the gate dielectric layer 150 to expose the channel layer 140 of the channel structure CH to the outside, a portion of the gate dielectric layer 150 at the protruding portion CP of the channel structure CH can be removed. That is, a portion of the gate dielectric layer 150 within the channel penetration portion CHa of the channel structure CH can be retained instead of being removed. Thus, the gate dielectric layer 150 can be disposed within the entirety of the channel penetration portion CHa, which has a relatively small width or area, and cutting, separation, damage, particles, etc., that may be caused or generated at the channel penetration portion CHa can be prevented. The gate dielectric layer 150 within the entirety of the side surface of the channel penetration portion CHa of the channel structure CH can physically or structurally support the channel structure CH, and cutting, separation, damage, particles, etc., that may be caused or generated at the channel penetration portion CHa can be prevented.

[0221] The process of removing a portion of the gate dielectric layer 150 can be performed using any of a variety of processes (e.g., etching process, etc.).

[0222] Subsequently, as Figure 16 As shown, at least the protruding portion CP of the channel layer 140 in the channel structure CH can be removed (refer to...). Figure 15 For example, the first surface of the protruding portion CP of the channel layer 140 at the channel structure CH can be removed. Figure 16 (upper surface), side surface, second surface) Figure 16 The portion at the lower surface of the channel layer 140 and the portion at the side surface of the channel penetration portion CHa of the channel structure CH.

[0223] The process of removing a portion of the trench layer 140 can be performed using any of a variety of processes (e.g., etching). For example, in the process of removing a portion of the trench layer 140, a wet etching process can be performed within five minutes (e.g., within one minute).

[0224] Subsequently, as Figure 17 As shown, a first common source layer 172 may be formed. The first common source layer 172 may be disposed on a first surface 120a of the gate stack structure 120 and may be electrically connected to the channel structure CH. For example, a heat treatment may be performed after the formation of the first common source layer 172.

[0225] In one embodiment, a first common source layer 172 is formed on the first surface 120a of the gate stack structure 120 exposed by the opening 168p and on the channel structure CH. The first common source layer 172 may include a first portion 172a electrically connected to the channel structure CH. The first portion 172a may include horizontal conductive portions 1721a, 1722a, and 1723a and extended conductive portions 1724a and 1725a. The horizontal conductive portions 1721a, 1722a, and 1723a may be disposed on the first surface 120a of the gate stack structure 120 and the channel structure CH. The extended conductive portions 1724a and 1725a may be disposed between the gate stack structure 120 and the channel structure CH. The first common source layer 172 may also include a second portion 172b and / or a third portion 172c. The second portion 172b may be disposed on a side surface of the covering insulating layer 168a, and the third portion 172c may be disposed on the outer surface of the covering insulating layer 168a.

[0226] Extended conductive portions 1724a and 1725a can fill the empty spaces formed during the process of removing a portion of the channel layer 140. Extended conductive portions 1724a and 1725a may include a first extended portion 1724a and a second extended portion 1725a. The first extended portion 1724a may be disposed on the second surface of the channel extension portion CHb. Figure 17 The second extension portion 1725a may be disposed on the side surface of the channel penetration portion CHa on the first dielectric portion 150a.

[0227] The first common source layer 172 may include a doped semiconductor layer (e.g., an n-type or p-type polysilicon layer), or be formed of a doped semiconductor layer (e.g., an n-type or p-type polysilicon layer). However, the embodiments are not limited thereto.

[0228] The dopant included in the first common source layer 172 can be diffused into a portion of the channel layer 140 by heat treatment, and a diffused doped portion 140d can be formed in the portion of the channel layer 140 adjacent to the first common source layer 172.

[0229] The process of forming the first common source layer 172 can be performed by any of various processes (e.g., deposition process, etc.). The heat treatment process can be performed by any of various processes (e.g., melt laser annealing (MLA process, etc.). However, the embodiments are not limited thereto.

[0230] The second extension 1725a and the diffusion-doped portion 140d at the side surface of the channel penetration portion CHa and / or the channel extension portion CHc of the channel structure CH can be sidewall doped regions.

[0231] In this embodiment, a portion of the channel layer 140 may be removed, and a common source layer 170 (e.g., a first common source layer 172) including a dopant may be formed directly in the portion where the channel layer 140 has been removed. Thus, instead of a process of doping the channel layer 140 with a dopant using an ion implantation process, a common source layer 170 (e.g., a first common source layer 172) including a dopant may be formed directly in portions that may have high resistance (e.g., corner portions). Therefore, in portions that may have high resistance, the cell current can be improved with a simpler process.

[0232] By diffusing doped portions 140d formed via the diffusion of dopants included in the first common source layer 172, the length or area of ​​the sidewall doped region with dopants at the side surface can be increased. This improves the cell current.

[0233] Subsequently, as Figure 18 As shown, the common source layer 170 can be formed by forming a second common source layer 174 on the first common source layer 172. In some embodiments, a patterning process for the common source layer 170 can be performed.

[0234] The second common source layer 174 can be formed by any of the various processes (e.g., deposition process, etc.), and the patterning process of the common source layer 170 can be performed by any of the various processes (e.g., etching process, etc.).

[0235] Subsequently, as Figure 19 As shown, a first wiring portion 160 may be formed in addition to the common source layer 170. For example, a first insulating layer 168b may be formed on the common source layer 170, a first contact 164 and a pad 166 may be formed, and a second insulating layer 168c, a third insulating layer 168d and a fourth insulating layer 168e may be formed to form the first wiring portion 160.

[0236] According to an embodiment, a covering insulating layer 168a with an opening 168p may be included, and a structure that selectively exposes at least a portion of the cell array region 102 can be formed by a simple manufacturing process. A portion of the gate dielectric layer 150 at the channel extension portion CHb of the channel structure CH can be selectively removed, improving the structural stability of the channel structure CH. A common source layer 170 can be formed in the empty space formed by removing a portion of the channel layer 140, improving the cell current at the corner portion of the channel extension portion CHb and removing particles. In other words, a semiconductor device with improved reliability can be easily formed by a simple process.

[0237] In the following text, refer to Figures 20 to 27The semiconductor device and manufacturing method according to the embodiments will be described in detail below. To the extent that an element is not described in detail below, it will be understood that the element is at least similar to a corresponding element already described elsewhere in this disclosure. Parts not described above will be described in detail.

[0238] Figure 20 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment. Figure 20 Showing with Figure 6 The corresponding part.

[0239] Reference Figure 20 In an embodiment, in the extension direction of the channel structure CH, the first common source layer 172 may include a portion that differs in length from the second extension portion 1725a, or the channel layer 140 may include a portion that differs in position from the diffusion-doped portion 140d. That is, in an embodiment, in the extension direction of the channel structure CH, the sidewall doped regions (e.g., the second extension portion 1725a and / or the diffusion-doped portion 140d) may include portions that differ in length or position.

[0240] For example, when the channel penetration portion CHa is not located at the center of the channel extension portion CHb and thus has an asymmetrical structure when viewed in cross-section, differences in the length of the channel layer 140 removed may exist during the process of removing the portion of the channel layer 140 adjacent to the channel extension portion CHb. For example, relatively more of the channel layer 140 may be removed in the portion closer to the edge of the channel extension portion CHb, and relatively less of the channel layer 140 may be removed in the portion farther from the edge of the channel extension portion CHb.

[0241] Therefore, in the extension direction of the channel structure CH, the first common source layer 172 may include a portion that differs in length along the second extension portion 1725a. When heat treatment is performed after the formation of the first common source layer 172, the first common source layer 172 may include a portion that differs at the position of the end where the diffusion of the dopant in the first common source layer 172 begins. Therefore, the channel layer 140 may include a portion that differs at the position of the diffusion-doped portion 140d.

[0242] Figure 21 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment. Figure 21 It shows the relationship with Figure 6 The corresponding part.

[0243] Reference Figure 21 In an embodiment, in the extension direction of the channel structure CH, the first surface 120a of the gate stack structure 120 may be connected to the first surface 150h of the second dielectric portion 150b of the gate dielectric layer 150. Figure 21The upper surface of the gate stack structure 120 is set higher than the upper surface of the channel structure CH. For example, in the extension direction of the channel structure CH, the first surface 120a of the gate stack structure 120 may be set on the first surface of the channel extension portion CHb. Figure 21 The upper surface and the second surface Figure 21 Between the lower surface of the middle.

[0244] In the extension direction of the channel structure CH, the third dielectric portion 150c may include a portion extending in a direction parallel to the side surface of the channel extension portion CHb, such that the third dielectric portion 150c includes a portion superimposed on the side surface of the channel extension portion CHb. For example, the first surface 120a of the gate stack structure 120 may be adjacent to the first surface of the third dielectric portion 150c of the gate dielectric layer 150. Figure 21 The upper surface of the third dielectric portion 150c is on the same plane as the channel extension portion CHb. The third dielectric portion 150c may include a portion that overlaps with the side surface of the channel extension portion CHb and is stably positioned around the entirety of the channel through portion CHa and the channel extension portion CHc.

[0245] The extended conductive portions 1724a, 1725a, and 1726a of the first common source layer 172 may include a first extension 1724a, a second extension 1725a, and a third extension 1726a. The third extension 1726a may be disposed between the channel extension portion CHb (e.g., the core insulating layer 142 in the channel extension portion CHb) and the third dielectric portion 150c. The third extension 1726a may extend in a direction parallel to the second horizontal portion 1722a and may connect the first extension 1724a to the second horizontal portion 1722a and / or the third horizontal portion 1723a. In a cross-sectional view, the third extension 1726a may have an obtuse angle (e.g., an angle greater than 90 degrees and less than 180 degrees) with each of the first extension portion 1724a and the third horizontal portion 1723a.

[0246] The thickness of the third extension 1726a may be substantially the same as the thickness of the first extension 1724a, the second extension 1725a, or the channel layer 140. For example, the thickness of the third extension 1726a may be in the range of 90% to 110% of the thickness of the first extension 1724a, the second extension 1725a, or the channel layer 140. (Refer to...) Figure 6 The description of the thickness T4 of the first extension 1724a and / or the thickness T5 of the second extension 1725a can be applied to the thickness of the third extension 1726a.

[0247] Figure 22 This is a cross-sectional view showing a portion of a semiconductor device according to an embodiment. Figures 23 to 26 It is shown Figure 22A cross-sectional view of a method for manufacturing a semiconductor device is shown in the figure. Figures 22 to 26 Showing with Figure 6 The corresponding part.

[0248] Reference Figure 22 In an embodiment, the channel structure CH may include a channel through portion CHa and a channel extension portion CHb.

[0249] The channel through-portion CHa may extend through the gate stack structure 120. The channel extension portion CHb may be on the first surface 120a of the gate stack structure 120 and may have a width or area larger than that of the channel through-portion CHa. The channel through-portion CHa may be disposed in the gate stack structure 120 and may include a gate dielectric layer 150, a channel layer 140, and a core insulating layer 142. The channel extension portion CHb may be disposed on the first surface 120a of the gate stack structure 120 and may include the channel layer 140 and the core insulating layer 142 without the gate dielectric layer 150.

[0250] In an embodiment, the channel layer 140 may be disposed in the channel extension portion CHb. For example, in the channel extension portion CHb, the channel layer 140 may be disposed on the first surface of the core insulating layer 142. Figure 22 The upper surface, side surface and second surface (in) Figure 22 On the lower surface of the channel. (Refer to the channel extension CHc). Figure 6 The corresponding part may not be included.

[0251] In an embodiment, the channel layer 140 may include a highly doped portion 140i, a diffusely doped portion 140d, and an undoped portion 140u. The highly doped portion 140i may be disposed on a first surface, a side surface, and a second surface of the core insulating layer 142 within the channel extension portion CHb. The diffusely doped portion 140d may be disposed on a side surface of a portion of the channel penetration portion CHa adjacent to the highly doped portion 140i. The undoped portion 140u may be disposed on a side surface of another portion of the channel penetration portion CHa, in a portion other than the diffusely doped portion 140d.

[0252] The high-concentration doped portion 140i can be a region formed by doping a portion of the channel extension portion CHb of the channel layer 140 with a dopant, and the diffusion doped portion 140d can be formed by the diffusion of the dopant included in the high-concentration doped portion 140i into a portion of the channel layer 140.

[0253] The high-concentration doped portion 140i may have a higher doping concentration than the diffused doped portion 140d and the undoped portion 140u. The high-concentration doped portion 140i may have a substantially the same or uniform doping concentration. For example, the first portion 172a (e.g., horizontally conductive portions 1721a, 1722a, and 1723a), the second portion, and the third portion of the first common source layer 172 may have substantially the same or uniform doping concentration. The diffused doped portion 140d may have a higher doping concentration than the undoped portion 140u, and the doping concentration of the diffused doped portion 140d may gradually decrease away from the high-concentration doped portion 140i.

[0254] The locations of the high-concentration doped portion 140i and the diffused doped portion 140d, as well as the boundaries between them, can be identified or anticipated based on the doping concentration.

[0255] In an embodiment, in a channel structure CH including a channel extension portion CHb, on the second surface of the channel extension portion CHb ( Figure 22 The horizontal doped region at the lower surface of the channel layer 140 and the sidewall doped region adjacent to the side surface of the channel penetration portion CHa may be included. For example, the horizontal doped region may include at least a portion of the high-concentration doped portion 140i, and the sidewall doped region may include the diffused doped portion 140d of the channel layer 140.

[0256] In an embodiment, the first portion 172a of the first common source layer 172 may include horizontal conductive portions 1721a, 1722a, and 1723a. The horizontal conductive portions 1721a, 1722a, and 1723a may include a first horizontal portion 1721a, a second horizontal portion 1722a, and a third horizontal portion 1723a. The first horizontal portion 1721a may be disposed on the first surface of the channel extension portion CHb. Figure 22 The second horizontal portion 1722a may be disposed on the side surface of the channel extension portion CHb. The third horizontal portion 1723a may be disposed on the periphery of the channel extension portion CHb on the first surface 120a of the gate stack structure 120. Figure 6 The portions corresponding to the extended conductive portions 1724a and 1725a in the diagram may be excluded.

[0257] The first horizontal portion 1721a and the second horizontal portion 1722a may be disposed on the channel layer 140 (e.g., the highly doped portion 140i). For example, the first horizontal portion 1721a and the second horizontal portion 1722a may be in contact with the channel layer 140 (e.g., the highly doped portion 140i). However, the embodiments are not limited thereto.

[0258] The doping concentration of the high-concentration doped portion 140i can be lower than the doping concentration of the first common source layer 172. However, the embodiments are not limited to this.

[0259] Reference Figures 23 to 26 A method for manufacturing a semiconductor device is described. To the extent that an element is not described in detail below, it will be understood that the element is at least similar to a corresponding element already described elsewhere in this disclosure. The parts not described above will be described in detail.

[0260] like Figure 23 As shown, the pre-cell region can be bonded to the circuit region, the semiconductor substrate can be removed, a cover insulating layer with openings can be formed, and a portion of the gate dielectric layer 150 in the protruding portion of the channel structure CH can be removed. (Refer to...) Figures 8 to 15 The description can be applied here.

[0261] Subsequently, as Figure 24 As shown, a highly doped portion 140i can be formed in the channel layer 140, and a first common source layer 172 can be formed. The first common source layer 172 can be formed on the first surface 120a of the gate stack structure 120 and can be electrically connected to the channel structure CH.

[0262] The process of forming a highly doped portion 140i in the channel layer 140 can be performed using any of a variety of doping processes (e.g., ion implantation, etc.) involving dopant (e.g., n-type or p-type dopant). The process of forming the first cascade layer 172 can be performed using any of a variety of processes (e.g., deposition, etc.). The first cascade layer 172 may include a doped semiconductor layer (e.g., an n-type or p-type polysilicon layer). However, the embodiments are not limited thereto.

[0263] Subsequently, as Figure 25 As shown, a diffusion-doped portion 140d can be formed in the portion of the channel layer 140 adjacent to the highly doped portion 140i by performing a heat treatment process. The heat treatment process can be performed by any of various processes (e.g., melt laser annealing process, etc.). However, the embodiments are not limited thereto.

[0264] Subsequently, as Figure 26 As shown, the common source layer 170 can be formed by forming a second common source layer 174 on the first common source layer 172. (Refer to...) Figure 18 The description can be applied to the process of forming the common source layer 170. A first wiring portion, excluding the common source layer 170, can be formed. (Refer to...) Figure 19 The description can be applied to the process of forming the first wiring section.

[0265] According to an embodiment, by forming a highly doped portion 140i by doping this portion of the channel layer 140 without removing a portion of the channel layer 140, horizontal doped regions and sidewall doped regions can be formed in the channel structure CH, including the channel extension portion CHb. Therefore, the cell current at the corner portion of the channel extension portion CHb can be improved.

[0266] Figure 27 This is a schematic partial cross-sectional view of a semiconductor device according to an embodiment. Figure 27 Showing with Figure 5 The corresponding part.

[0267] Reference Figure 27 In an embodiment, in the first common source layer 172, the first surface of the first horizontal portion ( Figure 27 The upper surface of the middle), the first surface of the second horizontal part ( Figure 27 The upper surface of the middle section and the first surface of the third horizontal section ( Figure 27 The upper surface of the first common source layer 172 (e.g., the third horizontal portion) can be disposed on the same plane. In the extension direction of the channel structure CH (Z-axis direction in the figures), the thickness of the first common source layer 172 (e.g., the third horizontal portion) can be greater than the height of the channel extension portion CHb, and the first surface of the first common source layer 172 ( Figure 27 The upper surface of the first common source layer 172 can be disposed outside the channel extension portion CHb. For example, the first surface of the first portion 172a of the first common source layer 172 ( Figure 27 The upper surface of the first common source layer 172 can be a substantially flat surface, and the second surface of the first portion 172a of the first common source layer 172 ( Figure 27 The lower surface of the structure may have a bent portion or a stepped portion.

[0268] The first portion of the second common source layer 174 on the first portion 172a of the first common source layer 172 may have a planar shape extending in the horizontal direction. The first surface of the first portion of the second common source layer 174 on the first portion 172a of the first common source layer 172 ( Figure 27 The upper surface and the second surface Figure 27 Each of the lower surfaces (in the model) can be a flat surface.

[0269] For example, the first common source layer 172 may have the above shape when it includes a material that is modified or melted in a heat treatment process performed after the formation of the first common source layer 172, or when it is formed from a material that is modified or melted in a heat treatment process performed after the formation of the first common source layer 172. In some embodiments, the first common source layer 172 may have a relatively large thickness, and a first common source layer 172 having the above shape may be formed.

[0270] The following will describe in detail an example of an electronic system that includes semiconductor devices.

[0271] Figure 28 An electronic system including a semiconductor device is schematically illustrated according to an embodiment.

[0272] Reference Figure 28 The electronic system 1000 according to an embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0273] Semiconductor device 1100 may be a non-volatile memory device. For example, semiconductor device 1100 may be a reference. Figures 1 to 27 The NAND flash memory device described. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S disposed on the first structure 1100F. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common-source line CSL, a word line WL, a first gate upper line UL1, a second gate upper line UL2, a first gate lower line LL1, a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common-source line CSL.

[0274] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be modified in various ways according to embodiments.

[0275] In this embodiment, the lower transistor LT1 or LT2 may include a ground select transistor, and the upper transistor UT1 or UT2 may include a string select transistor. The first lower gate line LL1 and the second lower gate line LL2 may be the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the first upper gate line UL1 and the second upper gate line UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0276] The common-source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, the first upper gate line UL1, and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection wiring 1115 extending within the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection wiring 1125 extending within the first structure 1100F to the second structure 1100S.

[0277] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one memory cell transistor selected from a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0278] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0279] Processor 1210 controls the overall operation of electronic system 1000, including controller 1200. Processor 1210 operates according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface (I / F) 1221 for processing communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted via NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When control commands are received from external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0280] Figure 29 This is a perspective view schematically illustrating an electronic system including semiconductor devices according to an embodiment.

[0281] Reference Figure 29The electronic system 2000 according to an embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 disposed on the main substrate 2001.

[0282] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In embodiments, the electronic system 2000 may communicate with the external host according to any of the architectures such as Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Memory (UFS). In embodiments, the electronic system 2000 may operate via power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0283] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0284] DRAM 2004 can be a buffer memory used to mitigate or buffer the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. DRAM 2004 included in the electronic system 2000 can also be a cache memory and can also provide space for temporarily storing data during control operations for the semiconductor package 2003. When the electronic system 2000 includes DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003, controller 2002 may also include a DRAM controller for controlling DRAM 2004.

[0285] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 disposed on the package substrate 2100, an adhesive layer 2300 at the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0286] The package substrate 2100 may be a printed circuit board including a package top pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may be coupled with... Figure 28 The input / output pad 1101 corresponds to this. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. The semiconductor chip 2200 may include reference... Figures 1 to 27 The semiconductor device described.

[0287] In an embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 and the package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire type, and the semiconductor chips 2200 may be electrically connected to the package pad 2130 of the package substrate 2100 using a bonding wire type. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including a through-silicon via (or "through-silicon via"; TSV) instead of a bonding wire type connection structure 2400.

[0288] In an embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate intermediate substrate, different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be interconnected with each other via wiring on the intermediate substrate.

[0289] Figure 30 This is a schematic cross-sectional view of a semiconductor package according to an embodiment. Figure 30 Show Figure 29An embodiment of the semiconductor package 2003 is shown, and conceptually illustrated by cutting along line I-I'. Figure 29 The area obtained by semiconductor packaging in 2003.

[0290] Reference Figure 30 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120, a top package pad 2130 on the upper surface of the package substrate body portion 2120, a bottom package pad 2125 disposed on or exposed through the lower surface of the package substrate body portion 2120, and internal wiring 2135 electrically connecting the top package pad 2130 and the bottom package pad 2125 within the package substrate body portion 2120. The top package pad 2130 may be electrically connected to a connection structure 2400. The bottom package pad 2125 may be connected to a conductive connection portion 2800. Figure 29 The wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 is shown in the figure.

[0291] In the semiconductor package 2003, each semiconductor chip 2200 may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded to the first structure 4100 by a wafer bonding type.

[0292] The first structure 4100 may include a peripheral circuit region, which includes peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 penetrating the gate stack structure 4210, a separator structure 4230, and a word line WL electrically connected to the channel structure 4220 and the gate stack structure 4210 (see reference). Figure 28 The second bonding structure 4250 is a second bonding structure. For example, the second bonding structure 4250 can be electrically connected to the channel structure 4220 and the word line WL via a bit line 4240 electrically connected to the channel structure 4220 and a gate connection wiring electrically connected to the word line WL. The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 can contact and bond to each other. For example, the portion where the first bonding structure 4150 and the second bonding structure 4250 are bonded may include copper (Cu).

[0293] In one embodiment, a covering insulating layer with an opening may be included, the entire side surface of the channel penetration portion may be surrounded by a gate dielectric layer, and a common source layer may be formed in the empty space created by removing a portion of the channel layer, thereby improving the cell current. Consequently, the productivity and reliability of the semiconductor device can be improved.

[0294] Each of the semiconductor chips 2200 may further include an input / output pad 2210 and an input / output connection wiring 4265 at the lower portion of the input / output pad 2210. The input / output connection wiring 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0295] In one embodiment, within the semiconductor package 2003, a plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure 2400 having a bonding wire type. In another embodiment, the plurality of semiconductor chips 2200 or a plurality of portions constituting the plurality of semiconductor chips 2200 may be electrically connected via a connection structure including a through-silicon via (TSV).

[0296] While some examples have been described in conjunction with what are now considered to be some practical embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, and the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising a cell array region and a connection region, the semiconductor device comprising: A gate stack structure having a first surface and a second surface opposite to each other, wherein the gate stack structure includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on each other; A channel structure includes a channel through portion and a channel extension portion, wherein the channel through portion extends through a gate stack structure, and the channel extension portion is on a first surface of the gate stack structure and has a width greater than the width of the channel through portion or an area greater than the area of ​​the channel through portion. An insulating layer is provided on the first surface of the gate stack structure, covering the connection region and having an opening that exposes at least a portion of the cell array region; and The common source layer includes horizontal conductive portions on the first surface of the gate stack structure exposed by the opening and on the channel extension portion. The channel structure includes a channel layer and a gate dielectric layer, and The gate dielectric layer includes a first dielectric portion and a second dielectric portion. The first dielectric portion is in the channel through portion, and the second dielectric portion extends horizontally from the first dielectric portion in a portion adjacent to the first surface of the gate stack structure.

2. The semiconductor device according to claim 1, wherein, The gate dielectric layer also includes a third dielectric portion that extends from the second dielectric portion to be parallel to the side surface of the channel extension portion.

3. The semiconductor device according to claim 1, wherein, The common source layer also includes an extended conductive portion, which is included in the portion between at least a portion of the gate stack structure and the channel structure.

4. The semiconductor device according to claim 3, wherein, The thickness of the extended conductive portion is the same as the thickness of the channel layer.

5. The semiconductor device according to claim 3, wherein, The thickness of the extended conductive portion is smaller than the thickness of the horizontal conductive portion.

6. The semiconductor device according to claim 1, wherein, The common source electrode layer also includes a first extension and a second extension. The first extension portion lies between the surface of the channel extension portion and the second dielectric portion, and the surface of the channel extension portion is adjacent to the first surface of the gate stack structure. The second extension extends from the first extension and lies on the first dielectric portion on the side surface of the channel through portion.

7. The semiconductor device according to claim 6, wherein, In the extension direction of the channel structure, the second extension portion is not superimposed with the plurality of gate electrodes, or is superimposed with one or two of the plurality of gate electrodes.

8. The semiconductor device according to claim 6, wherein, In the extension direction of the channel structure, the second extension portion is inside the outermost interlayer insulating layer at the first surface of the gate stack structure among the plurality of interlayer insulating layers.

9. The semiconductor device of claim 1, wherein the semiconductor device comprises: The horizontally doped region is located between the second dielectric portion and the channel extension portion; as well as The sidewall doped region is located on the first dielectric portion on the side surface of the channel structure or gate stack structure.

10. The semiconductor device according to claim 9, wherein, The horizontally doped region is or includes part of the common source layer.

11. The semiconductor device according to claim 9, wherein, The channel structure also includes a core insulating layer in the channel layer, and The sidewall doped region includes the extended conductive portion of the common source layer between the first dielectric portion and the core insulating layer, and the diffused doped portion of the channel layer adjacent to the common source layer.

12. The semiconductor device according to claim 9, wherein, In the extension direction of the channel structure, the length of the sidewall doped region is greater than the thickness of the horizontal doped region.

13. The semiconductor device of claim 9, wherein the semiconductor device comprises: Multiple portions that differ in length or location of the sidewall doped region in the extension direction of the channel structure.

14. The semiconductor device according to claim 1, wherein, The common source electrode layer surrounds the surface of the extended portion of the channel.

15. The semiconductor device according to claim 1, wherein, The side surface covered by the insulating layer with the opening includes a portion having a recessed shape.

16. A semiconductor device, comprising: A gate stack structure having a first surface and a second surface opposite to each other, wherein the gate stack structure includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on each other; A channel structure includes a channel through portion and a channel extension portion, wherein the channel through portion extends through a gate stack structure, and wherein the channel extension portion is on a first surface of the gate stack structure and has a width greater than the width of the channel through portion or an area greater than the area of ​​the channel through portion. A doped semiconductor layer is connected to the channel structure on the first surface of the gate stack structure. in: The channel structure includes a channel layer and a gate dielectric layer. The gate dielectric layer includes a first dielectric portion and a second dielectric portion. The first dielectric portion is located in a through-channel portion, and the second dielectric portion extends horizontally from the first dielectric portion in a portion adjacent to a first surface of the gate stack structure. The doped semiconductor layer includes a first extension portion and a second extension portion. The first extension portion is between the second dielectric portion and the channel extension portion, and The second extension extends from the first extension and is located on the side surface of the channel penetration portion.

17. The semiconductor device according to claim 16, wherein, The end of the second extension is connected to the end of the channel layer in the channel penetration portion.

18. The semiconductor device according to claim 17, wherein, The channel layer includes a diffused doped portion adjacent to the second extension portion, and In this process, the doping concentration in the diffused doping portion gradually decreases as it moves away from the second extended portion.

19. The semiconductor device according to claim 16, wherein, The surface of the doped semiconductor layer surrounding the extended portion of the channel.

20. An electronic system comprising: Primary base; A semiconductor device, on a main substrate, including a cell array region and a connection region; as well as The controller is connected to the semiconductor device on the main substrate. The semiconductor device includes: A gate stack structure having a first surface and a second surface opposite to each other, wherein the gate stack structure includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on each other; A channel structure includes a channel through portion and a channel extension portion, wherein the channel through portion extends through a gate stack structure, and the channel extension portion is on a first surface of the gate stack structure and has a width greater than the width of the channel through portion or an area greater than the area of ​​the channel through portion. An insulating layer is provided on the first surface of the gate stack structure, covering the connection region and having an opening that exposes at least a portion of the cell array region; and The common source layer includes horizontal conductive portions on the first surface of the gate stack structure exposed by the opening and on the channel extension portion. The channel structure includes a channel layer and a gate dielectric layer, and The gate dielectric layer includes a first dielectric portion and a second dielectric portion. The first dielectric portion is in the channel through portion, and the second dielectric portion extends horizontally from the first dielectric portion in a portion adjacent to the first surface of the gate stack structure.

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