A clock circuit, a clock signal control method, and a chip

Abstract

This invention discloses a clock circuit, a clock signal control method, and a chip, relating to the field of chip design technology. The clock circuit includes: a first clock generator configured to generate a first clock signal; a second clock generator configured to generate a second clock signal; and a clock switching module connected to the first clock generator and the second clock generator, respectively; configured to switch the output first clock signal to the second clock signal according to the clock switching signal after the controlled unit's cycle operation ends and it enters an idle mode, thereby adjusting the operating bias of the controlled unit. This invention is applicable to scenarios involving improving aging effects such as NBTI in products.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a clock circuit, a clock signal control method, and a chip. Background Technology

[0002] In modern chip design, as process nodes become increasingly advanced, aging is an issue that cannot be ignored. Chip aging refers to the aging phenomenon that occurs in the metal interconnects and components within a chip as it operates for longer periods. This can lead to a significant decline in the performance of some components, causing the operating state of local circuits to deviate from the design expectations. Ultimately, this results in a noticeable degradation in the chip's frequency, power consumption, and other performance characteristics, and may even lead to the chip failing to function properly after several years of operation.

[0003] In the current integrated circuit design process, there are some modules in the chip that may be idle for a long time. If the module does not work for a long time, some internal devices will be in a fixed bias state for a long time. This will cause the devices to be affected by aging effects such as negative bias temperature instability (NBTI), the device performance will begin to degrade, and the product life will be shortened quickly. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a clock circuit, a clock signal control method, and a chip, which can improve the aging degree of products and thus increase the product's service life.

[0005] In a first aspect, the present invention provides a clock circuit, comprising: a first clock generator configured to generate a first clock signal; a second clock generator configured to generate a second clock signal; and a clock switching module connected to the first clock generator and the second clock generator respectively; configured to, after the controlled unit finishes its periodic operation and enters an idle mode, switch the output first clock signal to the second clock signal according to the clock switching signal, so as to adjust the operating bias of the controlled unit.

[0006] According to one embodiment of the present invention, the frequency of the second clock signal is lower than that of the first clock signal, and the second clock signal is configured to flip at preset intervals to adjust the operating bias of the controlled unit.

[0007] According to one embodiment of the present invention, the clock switching module includes a first input terminal, a second input terminal, and a selection control terminal. The first input terminal is connected to the first clock generator and receives the first clock signal; the second input terminal is connected to the second clock generator and receives the second clock signal; and the selection control terminal receives the clock switching signal.

[0008] According to one embodiment of the present invention, the clock switching signal is an enable control signal of the controlled unit, configured to output a corresponding clock signal based on the state of the enable control signal to control the state of the controlled unit; the state includes a working mode and an idle mode.

[0009] According to one embodiment of the present invention, the state of the enable control signal includes: when the enable signal is at a first level, indicating the operating mode; when the enable signal is at a second level complementary to the first level, indicating the idle mode; wherein the operating mode corresponds to the first clock signal, and the idle mode corresponds to the second clock signal.

[0010] According to one embodiment of the present invention, the controlled unit includes a device in a biased state in the idle mode and a circuit containing the device, the device including a charging device, a clamping device and a biasing device, and at least one of the charging device, the clamping device and the biasing device includes a P-channel metal-oxide-semiconductor field-effect transistor.

[0011] According to one embodiment of the present invention, the controlled unit includes a sensitive amplifier circuit, and the clock switching module includes a first clock switching module and a second clock switching module. The sensitive amplifier circuit is connected to the output terminals of the first clock switching module and the second clock switching circuit. The sensitive amplifier circuit includes a sensitive amplifier, a first charging tube, a second charging tube, a first balanced switch tube, and a second balanced switch tube. The first terminals of the first charging tube and the second charging tube are respectively connected to a power supply voltage, and their second terminals are respectively connected to the two input terminals of the sensitive amplifier. The first balanced switch tube and the second balanced switch tube are respectively connected between the two input terminals of the sensitive amplifier. The control terminals of the first charging tube and the first balanced switch tube are connected together and connected to the output terminal of the first clock switching module. The control terminals of the second charging tube and the second balanced switch tube are connected together and connected to the output terminal of the second clock switching module.

[0012] Secondly, the present invention also provides a clock signal control method, the method comprising: after a controlled unit enters an idle mode during periodic operation; switching a first clock signal indicating the operating mode to a second clock signal according to a clock switching signal; and adjusting the operating bias of the controlled unit based on the second clock control signal.

[0013] According to one embodiment of the present invention, the clock switching signal includes an enable control signal; the step of switching the first clock signal to the second clock signal according to the clock switching signal includes: based on the state of the enable control signal, when the enable control signal indicates an idle mode, outputting a second clock signal; wherein, the state of the enable control signal includes: when the enable signal is at a first level, indicating an operating mode; when the enable signal is at a second level complementary to the first level, indicating an idle mode.

[0014] According to one embodiment of the present invention, adjusting the operating bias of the controlled unit based on the second clock control signal includes: generating a control signal that flips at a preset interval based on the second clock signal to adjust the operating bias of the controlled unit.

[0015] Thirdly, the present invention also provides a chip, comprising: a clock circuit and a functional module, wherein the clock circuit is connected to a controlled unit in the functional module; wherein the clock circuit is the clock circuit of the aforementioned embodiments.

[0016] This invention provides a clock circuit, clock signal control method, and chip. The two input terminals of the clock switching module are respectively connected to the output terminals of a first clock generator and a second clock generator to receive a first clock signal and a second clock signal. According to the received clock switching signal, after the controlled unit finishes its cycle operation and enters the idle mode, the output first clock signal is switched to the second clock signal to adjust the working bias of the controlled unit, which can improve the aging degree of the product and thus increase the product's service life. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a circuit diagram of a memory-sensitive amplifier in the prior art; Figure 2 The waveform diagram is shown below when the memory sensitive amplifier circuit in the prior art is working. Figure 3 This is a schematic diagram of a clock circuit structure provided in an embodiment of the present invention; Figure 4 This is a circuit diagram of a memory sensitive amplifier using the clock circuit provided in an embodiment of the present invention; Figure 5The waveform diagram shows the operation of the memory sensitive amplifier using the clock circuit provided in the embodiment of the present invention. Figure 6 This is a schematic flowchart of a clock signal control method according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a chip structure provided in an embodiment of the present invention. Detailed Implementation

[0019] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0021] NBTI: Negative Bias Temperature Instability, refers to the degradation of a series of electrical parameters caused by applying a negative gate voltage to a PMOSFET (P-type metal-oxide-semiconductor field-effect transistor) at high temperatures.

[0022] HCI: Hot Carrier Injection. In advanced processes, due to the reduction in device size, the effective electric field strength within the device is enhanced. Under a strong electric field, the energy of the carriers is greatly enhanced, becoming hot carriers. Collisions of hot carriers within the device can lead to device performance degradation, such as a shift in the MOS threshold.

[0023] In modern integrated circuit design, most circuits use PLLs (Phase Locked Logic) or ring oscillators (ROs) to generate clock signals for internal chip timing control. When a functional module is working normally, the clock participates in the control of the internal module, ensuring that the module operates according to its design. When the module is not working, it can be turned off using a clock gate and an enable signal. In this way, the clock signal actually received by the module is always in an idle state, and the internal logic does not operate. However, if a module remains in an idle state for an extended period, the internal clock will be in an invalid state (0 or 1 level) for a prolonged period. This can cause the internal MOS devices to remain at a certain bias level for an extended period, making them prone to aging effects such as NBTI (Not-In-Time) biasing.

[0024] Specifically, the explanation will be based on an example of an SA (Sense Amplifier) ​​circuit in a memory. Figure 1This is a circuit diagram of a memory-sensitive amplifier in the prior art. In the diagram, RdEn is the read operation enable signal of the memory. When RdEn=1, a read operation is performed. SAPCH is the charging clock signal of the sensitive amplifier, active high. That is, when SAPCH=1, the two complementary input signals SAT / SAC of SA are charged. SAPCHX is the inverted (complementary) signal of SAPCH, active low. When SAPCHX=0, the two complementary input signals SAT / SAC of SA are charged. SAT / SAC are the two complementary input signals of the sensitive amplifier. When the potential difference between the two signals reaches a certain threshold, the sensitive amplifier is activated. The sensitive amplifier amplifies the potential difference between SAT / SAC, generating a large signal output. SAEN is the enable signal of the sensitive amplifier. When SAEN=1, the sensitive amplifier starts working and amplifies the potential difference between SAT / SAC. The amplifier is a sensitive amplifier that amplifies a small potential difference between two complementary input signals SAT / SAC into a large signal. Before the read operation begins, both input signals SAT / SAC of SA are at a high level. After the read operation begins, one input is gradually pulled low while the other input remains high, creating a small potential difference between the two signals. When SAEN is active (SAEN=1), the sensitive amplifier quickly amplifies the potential difference between SAT / SAC into a large output signal.

[0025] See Figure 2 As shown, Figure 2The figure shows the waveforms corresponding to the operation of a memory sensitive amplifier circuit in the prior art. When the read enable signal EdEn is 1, the memory begins the read operation. First, the rising edge of the clock signal CLK pulls SAPCH low (segment 202 in the figure), and SAPCH pulls SAPCHX high (segment 203 in the figure), stopping the charging of the sensitive amplifier SA. After a certain potential difference develops between SAT / SAC, SAEN turns on (segment 201 in the figure), and the sensitive amplifier starts working, amplifying the potential difference of the input signal and reading out this data. Then, when the clock falls, the falling edge of the clock signal CLK triggers SAEN to turn off (segment 204 in the figure) and SAPCH to rise (segment 205 in the figure). The rising SAPCH turns on SAPCHX (segment 206 in the figure), thereby turning on the charging transistors P0 / P1 and the balancing transistor P2, starting to charge SAT / SAC and maintaining their potentials at the same level. When there is no read operation, SAPCHX remains at a low level, and devices P0 / P1 / P2 are always in a conducting (pre-charged) state (as shown in segment 207 in the figure). In the current clocking scheme, if the memory is inactive for a long time, devices P0 / P1 / P2 will be in a negative bias state for an extended period. This causes the PMOS device to exhibit the NBTI effect (negative gate temperature instability), leading to a gradual degradation in device performance.

[0026] Therefore, this embodiment provides a clock circuit that introduces an additional clock generator. When the functional module is in an idle state, it switches to this additional clock generator. Based on the low-frequency clock signal generated by this off-task clock generator, devices with aging effects can switch states in a timely manner to avoid being in a biased state for a long time.

[0027] See Figure 3 As shown, the clock circuit 1 provided in this embodiment of the invention includes: The first clock generator 10 is configured to generate a first clock signal; The second clock generator 20 is configured to generate a second clock signal; The clock switching module 30 is connected to the first clock generator and the second clock generator respectively; it is configured to switch the output first clock signal to the second clock signal according to the clock switching signal after the controlled unit finishes its periodic operation and enters the idle mode, so as to adjust the working bias of the controlled unit.

[0028] In this embodiment, the controlled unit refers to a functional module or circuit that is controlled by a clock circuit to perform functions. These modules or circuits are typically in an idle state and are normally kept at a fixed bias, such as charging devices, clamping devices, and biasing devices. Additionally, other circuits with a fixed bias state are also included.

[0029] In some embodiments, the clock switching module 30 includes a first input terminal, a second input terminal, and a selection control terminal. The first input terminal is connected to the first clock generator 10 and receives the first clock signal; the second input terminal is connected to the second clock generator 20 and receives the second clock signal; the selection control terminal receives the clock switching signal.

[0030] For details, please refer to Figure 3 As shown, the two input terminals of the clock switching module 30 are respectively connected to the output terminals of the first clock generator 10 and the second clock generator 20, receiving the first clock signal and the second clock signal, and the selection control terminal receives the clock switching signal; wherein, the first clock signal is the clock signal required for the controlled unit to work normally, and the second clock signal is a low-frequency clock pulse signal generated by the second clock generator that can be adjusted as needed, used to control the switching state of the device (controlled unit) that has been in a fixed bias state for a long time during the long-term idle state.

[0031] In some embodiments, the controlled unit includes a device in a biased state in the idle mode and circuitry including the device, the device including a charging device, a clamping device and a biasing device, and at least one of the charging device, the clamping device and the biasing device includes a P-channel metal-oxide-semiconductor field-effect transistor.

[0032] In some embodiments, the frequency of the second clock signal is lower than that of the first clock signal, and the second clock signal is configured to flip at preset intervals to adjust the operating bias of the controlled unit.

[0033] In this embodiment, the second clock signal is a low-frequency, low-flip-rate clock pulse signal generated by an additional second clock generator. It is used to control the switching state of devices that have been in a fixed bias state for an extended period during an idle state. It should be noted that the second clock signal in this embodiment is not the clock signal used to control the entire functional module controlled by the clock circuit, but rather to control devices that would otherwise be in a fixed bias state for an extended period during idle. Taking the SA circuit as an example, the second clock signal in this embodiment is used to generate a flip at preset intervals, improving the situation where the charging transistor and the balancing transistor are in a fixed bias state for a long time.

[0034] In some embodiments, the clock switching signal is an enable control signal for the controlled unit, configured to output a corresponding clock signal based on the state of the enable control signal to control the state of the controlled unit; the state includes a working mode and an idle mode.

[0035] In this embodiment, the clock switching signal can be the enable control signal of the controlled unit. When the controlled unit of the clock circuit needs to switch from the normal working state / mode to the idle state / mode, the clock of the controlled unit is switched from the first clock signal to the second clock signal.

[0036] In some embodiments, the state of the enable control signal includes: when the enable signal is at a first level, it indicates the operating mode; When the enable signal is a second level complementary to the first level, it indicates the idle mode; The operating mode corresponds to the first clock signal, and the idle mode corresponds to the second clock signal.

[0037] In this embodiment, taking the sensitive amplifier circuit in the memory as an example, the clock switching signal is the read operation enable signal RdEn. In normal working state / mode, RdEn is 1, i.e., high level, and in idle state / mode, it is 0, i.e., low level.

[0038] In some embodiments, the controlled unit includes a sensitive amplifier circuit, and the clock switching module includes a first clock switching module and a second clock switching module, wherein the sensitive amplifier circuit is connected to the output terminals of the first clock switching module and the second clock switching circuit. The sensitive amplifier circuit includes a sensitive amplifier, a first charging transistor, a second charging transistor, a first balanced switch transistor, and a second balanced switch transistor. The first terminals of the first charging transistor and the second charging transistor are respectively connected to the power supply voltage, and the second terminals are respectively connected to the two input terminals of the sensitive amplifier. The first balanced switch transistor and the second balanced switch transistor are respectively connected between the two input terminals of the sensitive amplifier. The control terminals of the first charging transistor and the first balanced switch transistor are connected to each other and are also connected to the output terminal of the first clock switching module. The control terminals of the second charging transistor and the second balanced switch transistor are also connected to each other and are also connected to the output terminal of the second clock switching module.

[0039] In this embodiment, taking the memory's sensitive amplifier circuit as an example, the clock circuit provided in this embodiment is used to improve its aging process and prevent aging effects such as NBTI. For details, please refer to... Figure 4As shown, a first clock generator is connected to the first input terminal of the first clock switching module MUX0 and the second clock switching module MUX1 via a NOT gate. A second clock generator is connected to the second input terminal of both the first and second clock switching modules MUX0 and MUX1. A NOT gate is placed between the second clock generator and the first clock switching module, such that the clock signal output by the first clock switching module is inverted and in phase with the second clock signal, and the clock signal output by the second clock switching module is in phase with the second clock signal. The control terminals of the first charging transistor P0 and the first balancing switch transistor P21 are connected to the first clock switching module. The output of MUX0 is controlled by the clock signal SAPCHX0 output by the first clock switching module MUX0; the control terminals of the second charging tube P1 and the second balanced switch P22 are connected to the output of the second clock switching module MUX1 and are controlled by the clock signal SAPCHX1 output by the second clock switching module MUX1; the first terminals of the first charging tube P0 and the second charging tube P1 are respectively connected to the power supply voltage VDD, and the second terminals are respectively connected to the two input terminals of the sensitive amplifier SA; the first balanced switch P21 and the second balanced switch P22 are respectively connected between the two input terminals of the sensitive amplifier SA. In this circuit, SAPCH is the first clock signal, which is the clock signal required for the sensitive amplifier to operate normally, i.e., the charging clock of the sensitive amplifier, and is active high; Idle_clock is the second clock signal; SAPCHX0 is the clock signal output by the first clock switching module, which is the charging signal of the sensitive amplifier, and is active low; SAPCHX1 is the clock signal output by the second clock switching module, which is the charging signal of the sensitive amplifier, and is active low; SAT and SAC are two complementary input signals of the sensitive amplifier: when not reading, both SAT and SAC are charged to a high level; during a read operation, one of SAT and SAC is gradually pulled down, while the other remains high, and the potential difference between them reaches a certain threshold, which can be amplified and read by the sensitive amplifier; RdEn is the read enable signal, i.e., the clock switching signal, active high; SAEN is the enable signal of the sensitive amplifier. It should be noted that the clock circuit provided in this embodiment of the invention is not limited to the memory sensitive amplifier circuit; other circuits, including clamping devices and biasing devices, etc., that require eliminating bias to prevent aging effects are all within the scope of protection of this invention.

[0040] See Figure 5 As shown, Figure 5 The operating waveform diagram of the memory sensitive amplifier using the clock circuit provided in the embodiment of the present invention is as follows: During normal operation (within the working cycle), RdEn is 1. The first clock switching module MUX0 and the second clock switching module MUX1 select the first clock signal SAPCH generated by the first clock generator as the input signal and output SAPCHX0 and SAPCHX1. The rising edge of CLK will successively trigger the falling edge of SAPCH (see segment 502 in the figure) and the rising edge of SAEN (see segment 501 in the figure). The falling edge of SAPCH will trigger the rising edge of SAPCHX0 and SAPCHX1 output by the first clock switching module MUX0 and the second clock switching module MUX1 (see segment 503 in the figure). At this time, the first charging tube P0, the second charging tube P1, the first balanced tube P21, and the second balanced tube P22 are all turned off, and the sensitive amplifier starts to work, amplifying and reading out the data. The falling edge of CLK will successively trigger the falling edge of SAEN (see segment 504 in the figure) and the rising edge of SAPCH (see segment 505 in the figure). The falling edge of SAEN will turn off the sensitive amplifier. Then the rising edge of SAPCH will trigger the falling edges of SAPCHX0 and SAPCHX1 (see segment 506 in the figure). The first charging transistor P0, the second charging transistor P1, the first balanced transistor P21, and the second balanced transistor P22 will all start working, pre-charging SAT / SAC to a high level.

[0041] When the cycle ends and the device is in idle state / mode, RdEn is 0. The first clock switching module MUX0 and the second clock switching module MUX1 select the second clock signal Idle_clock generated by the second clock generator as the input signal, and output SAPCHX0 and SAPCHX1. SAPCHX0 is out of phase with Idle_clock, and SAPCHX1 is in phase with Idle_clock. Idle_clock is generated by a separate clock generator and is a low-frequency, low-flip-rate clock that can flip once at intervals. Its purpose is to improve the situation where the device is in a fixed bias for a long time. Specifically, after entering the Idle state, both SAPCHX0 and SAPCHX1 are triggered by the second clock signal Idle_clock. The rising edge of Idle_clock triggers the falling edge of SAPCHX0 (see segment 507 in the figure) and the rising edge of SAPCHX1 (see segment 508 in the figure). At this time, the first charging transistor P0 and the first balancing transistor P21 are turned on, charging SAT and SAC, while the second charging transistor P1 and the second balancing transistor P22 are turned off. The falling edge of Idle_clock triggers the rising edge of SAPCHX0 (see segment 509 in the figure) and the falling edge of SAPCHX1 (see segment 510 in the figure). At this time, the second charging transistor P1 and the second balancing transistor P22 are turned on, charging SAT and SAC; while the first charging transistor P0 and the first balancing transistor P21 are turned off.

[0042] Therefore, when the second clock signal Idle_clock is high and low, one set of balance transistors and charging transistors will work, while the other set will be off. As the level of the second clock signal Idle_clock switches, the two sets of devices will work and turn off alternately. This can effectively prevent one set of devices from being in a fixed bias state for a long time and effectively prevent aging effects such as NBTI.

[0043] This embodiment also provides a clock signal control method, see below. Figure 6 As shown, the method includes: S110. After the controlled unit finishes its cycle work and enters the idle mode, the first clock signal indicating the working mode is switched to the second clock signal according to the clock switching signal. S120. Adjust the operating bias of the controlled unit based on the second clock control signal.

[0044] The clock signal control method provided in this embodiment can switch to a second clock signal after the controlled unit finishes its cycle and enters an idle mode / state, thereby adjusting the operating bias state of the controlled unit in a timely manner and avoiding a situation where it remains at a fixed bias for a long time. Specifically, according to Figure 4 and Figure 5 As shown, in idle mode / state, the second clock signal Idle_clock controls the first charging transistor P0, the first balancing transistor P21, the second charging transistor P1, and the second balancing transistor P22. When the second clock signal Idle_clock is high and low, one set of balancing transistors and charging transistors are working, while the other set is off. As the level of the second clock signal Idle_clock switches, the two sets of devices will work and turn off alternately. This can effectively prevent one set of devices from being in a fixed bias state for a long time and effectively prevent aging effects such as NBTI.

[0045] In some embodiments, the clock switching signal includes an enable control signal; The step of switching the first clock signal to the second clock signal according to the clock switching signal includes: Based on the state of the enable control signal, when the enable control signal indicates an idle mode, a second clock signal is output; wherein, the state of the enable control signal includes: when the enable signal is at a first level, it indicates an operating mode; when the enable signal is at a second level complementary to the first level, it indicates an idle mode.

[0046] In this embodiment, the clock switching signal can be an enable control signal. During normal operation, the enable control signal is at a first level; in idle mode, the enable control signal is at a second level complementary to the first level. For example, see... Figure 5As shown, RdEn is the clock switching signal, which is the read enable signal of the memory sensitive amplifier circuit. It is active high. In normal operation (working mode), RdEn is 1, selecting the first clock signal as the input and outputting the clock signal; in idle state (idle mode), RdEn is 0, selecting the second clock signal as the input and outputting the clock signal.

[0047] In some embodiments, adjusting the operating bias of the controlled unit based on the second clock control signal includes: Based on the second clock signal, a control signal is generated that flips at a preset interval to adjust the operating bias of the controlled unit.

[0048] In this embodiment, the second clock signal can be a low-frequency, low-flip-rate clock that flips once at preset intervals. (See attached image.) Figure 5 As shown, when Idle_clock is high and low, one set of balance transistors and charging transistors are working, while the other set is off. As the Idle_clock level switches, the two sets of devices will work and rest alternately. This can effectively prevent one set of devices from being in a fixed bias state for a long time and effectively prevent aging effects such as NBTI.

[0049] This invention also provides a chip, see below. Figure 7 As shown, it includes: a clock circuit 1 and a functional module 2, wherein the clock circuit 1 is connected to the controlled unit in the functional module 2; wherein the clock circuit is the aforementioned clock circuit.

[0050] In summary, the embodiments of the present invention provide a clock circuit, a clock signal control method, and a chip. The two input terminals of the clock switching module are respectively connected to the output terminals of the first clock generator and the second clock generator, receiving the first clock signal and the second clock signal. According to the received clock switching signal, after the controlled unit finishes its periodic operation and enters the idle mode, the output first clock signal is switched to the second clock signal to adjust the working bias of the controlled unit, which can improve the aging degree of the product and thus increase the product's service life.

[0051] It should be noted that in this article, relational terms such as first and second are only used to refer to... Distinguishing one entity or operation from another does not necessarily require or imply these distinctions. There is no such actual relationship or order between entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0053] For ease of description, if systems, servers, etc. are involved, they may be described separately as various units / modules based on their functions. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0054] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0055] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A clock circuit, characterized in that, include: A first clock generator is configured to generate a first clock signal; A second clock generator is configured to generate a second clock signal; A clock switching module is connected to the first clock generator and the second clock generator respectively; It is configured to switch the output first clock signal to the second clock signal according to the clock switching signal after the controlled unit finishes its cycle operation and enters the idle mode, so as to adjust the operating bias of the controlled unit.

2. The clock circuit according to claim 1, characterized in that, The frequency of the second clock signal is lower than that of the first clock signal, and the second clock signal is configured to flip at preset intervals to adjust the operating bias of the controlled unit.

3. The clock circuit according to claim 1, characterized in that, The clock switching module includes a first input terminal, a second input terminal, and a selection control terminal. The first input terminal is connected to the first clock generator and receives the first clock signal. The second input terminal is connected to the second clock generator to receive the second clock signal; The selection control terminal receives the clock switching signal.

4. The clock circuit according to claim 1, characterized in that, The clock switching signal is the enable control signal of the controlled unit, and is configured to output a corresponding clock signal based on the state of the enable control signal in order to control the state of the controlled unit. The states include working mode and idle mode.

5. The clock circuit according to claim 4, characterized in that, The state of the enable control signal includes: when the enable signal is at a first level, it indicates the operating mode; When the enable signal is a second level complementary to the first level, it indicates the idle mode; The operating mode corresponds to the first clock signal, and the idle mode corresponds to the second clock signal.

6. The clock circuit according to claim 1, characterized in that, The controlled unit includes at least a device in a biased state in the idle mode and a circuit containing the device. The device includes a charging device, a clamping device, and a biasing device, and at least one of the charging device, the clamping device, and the biasing device includes a P-channel metal-oxide-semiconductor field-effect transistor.

7. The clock circuit according to claim 1, characterized in that, The controlled unit includes a sensitive amplifier circuit, and the clock switching module includes a first clock switching module and a second clock switching module. The sensitive amplifier circuit is connected to the output terminals of the first clock switching module and the second clock switching circuit. The sensitive amplifier circuit includes a sensitive amplifier, a first charging tube, a second charging tube, a first balanced switch tube, and a second balanced switch tube. The first terminals of the first charging tube and the second charging tube are respectively connected to the power supply voltage. The control terminals of the first charging tube and the first balanced switch tube are connected to each other and are connected to the output terminal of the first clock switching module. The control terminals of the second charging tube and the second balanced switch tube are connected to each other and are connected to the output terminal of the second clock switching module.

8. A clock signal control method, characterized in that, The method includes: After the controlled unit finishes its cycle and enters the idle mode, the first clock signal indicating the working mode is switched to the second clock signal according to the clock switching signal. The operating bias of the controlled unit is adjusted based on the second clock control signal.

9. The clock signal control method according to claim 8, characterized in that, The clock switching signal includes an enable control signal; The step of switching the first clock signal to the second clock signal according to the clock switching signal includes: Based on the state of the enable control signal, when the enable control signal indicates an idle mode, a second clock signal is output; wherein, the state of the enable control signal includes: when the enable signal is at a first level, it indicates an operating mode; when the enable signal is at a second level complementary to the first level, it indicates an idle mode.

10. The clock signal control method according to claim 8, characterized in that, The adjustment of the operating bias of the controlled unit based on the second clock control signal includes: Based on the second clock signal, a control signal is generated that flips at a preset interval to adjust the operating bias of the controlled unit.

11. A chip, characterized in that, include: A clock circuit and a functional module, wherein the clock circuit is connected to a controlled unit in the functional module; wherein the clock circuit is the clock circuit described in any one of claims 1-7.

Images