A method and system for automatic conversion of test program across test platform chips

Abstract

The application discloses a kind of cross test platform chip test procedure automatic conversion method and system, receive and parse the engineering file set from source test platform;Respectively parse the scattered configuration file and test procedure file therein, generate platform independent uniform resource mapping information, and linear test sequence obtained after state propagation rule flattening processing;Extract test item parameter expression and solve and unit normalization in conjunction with resource mapping, then integrated to generate structured uniform intermediate representation;According to the code template of target platform rule configuration, data in intermediate representation is injected into template and rendered to generate target test code;While providing manual check and modification interface to intermediate representation, support iterative generation based on revision result.The application realizes high-fidelity conversion of test logic and accurate mapping of test resources, improves the degree of automation and efficiency of cross-platform migration, while ensuring controllability of the conversion process and accuracy of the results.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit testing automation technology, and in particular relates to a method and system for automatic conversion of chip testing programs. Background Technology

[0002] Chip testing refers to the use of automated test equipment (ATE) to inspect the device under test (DUT) to ensure that the chip's functionality and performance meet design requirements, control product costs, and guarantee chip yield. With the continuous development of the integrated circuit industry, migrating existing chip test programs from one ATE platform to another has become a frequent and critical engineering task during the R&D verification, mass production, and continuous iteration of integrated circuit chips, catering to different testing needs or production line configurations. Currently, cross-platform migration mainly relies on manual refactoring by test engineers. Engineers typically need to manually locate entry points and upstream / downstream related files, analyze process call relationships segment by segment, manually organize parameter mappings, convert execution units, and then rewrite the code according to the target platform's syntax. However, due to significant differences between different test platforms in project directory structure, process script syntax, pin and power definition methods, and timing level parameter expressions, manual code rewriting is time-consuming, heavily reliant on personal experience, and suffers from inconsistent output quality across teams, easily introducing human error and resulting in low chip test migration efficiency.

[0003] It is evident that the traditional method of manually analyzing and rewriting test programs is labor-intensive and time-consuming, and can no longer meet the demands of rapidly iterating and increasingly large-scale chip testing projects. Therefore, it is necessary to design a more efficient, accurate, and less manual-dependent method for automatic cross-platform conversion of test programs.

[0004] At the same time, most existing script-based conversion tools are limited to simple text replacement. While they can reduce the workload of writing code manually to some extent, they are difficult to handle the deep logic conversion problems in real test projects. Specifically: First, test project files are highly scattered, with complex cross-file hierarchy references. Simple script processing can easily miss upstream and downstream related files, thus requiring the design of an automated project pathfinding and related resource extraction mechanism. Second, real test programs contain a large number of conditional branch executions and nested test suites. Simple replacement tools cannot handle the propagation of "skip" states in nested levels, which can easily lead to the complete destruction of the target platform's test logic. Therefore, it is urgent to introduce a process state propagation and hierarchical synchronization mechanism to achieve complete restoration of the test logic. Third, the level and timing parameters in the source program often rely on complex variable equation derivations, and the physical quantity units required by each platform are different. Simple text mapping can lead to test threshold and boundary errors. Therefore, it is necessary to establish a variable-dependency-based equation iterative solution and parameter unit normalization mechanism. Finally, enterprise-level mass production engineering emphasizes auditable results. Existing tools lack a structured intermediate data layer. Once a logical deviation occurs, it is extremely difficult to trace and review the source in a large amount of code, increasing rework costs. Therefore, it is necessary to build a unified intermediate data table to completely decouple information parsing from code generation, supporting engineers to perform mid-process verification and secondary modifications to ensure the absolute accuracy of code generation. Summary of the Invention

[0005] The purpose of this invention is to address the problems of low efficiency, inaccurate logic restoration, and lack of auditable intermediate layers in the existing technology by proposing an automatic conversion method and system for chip test programs across test platforms. By constructing a platform-independent unified intermediate representation, the invention achieves efficient, accurate, and automated migration of test programs that supports manual verification.

[0006] To achieve the above objectives, the present invention employs the following technical solution: This invention proposes an automatic conversion method for chip test programs across test platforms, comprising the following steps: S1. Receive a set of project files from the source test platform, wherein the set of project files includes at least a distributed configuration file that defines the distribution of test resources and a test process file that defines the test execution logic; S2. Parse the distributed configuration file, extract the pin definitions, power parameters and sorter settings, and generate platform-independent unified resource mapping information; S3. Parse the test process file, identify the process control markers and test item hierarchy, and flatten the nested test process into a linear test sequence composed of valid test items according to the state propagation rules. S4. Extract the parameter expressions of the test items in the linear test sequence, combine them with the unified resource mapping information to solve the constraints, convert the solution of the parameter expressions into physical quantity values ​​that conform to the target test platform standard, and integrate the linear test sequence, the normalized parameters and the unified resource mapping information to generate a structured unified intermediate representation. S5. Configure code templates according to the syntax rules of the target testing platform, inject the data in the unified intermediate representation into the corresponding code templates, and render and generate test code that can be executed on the target testing platform. S6. Provide an editing interface for the unified intermediate representation, update the unified intermediate representation in response to a modification instruction, and trigger step S5 to regenerate the test code based on the updated unified intermediate representation.

[0007] Furthermore, in step S3, the flattening of the nested test process according to the state propagation rules specifically includes: Identify the flow control markers in the test flow file used to mark test items as skipped; When an outer test item is identified as being marked as skipped, the skipped status is synchronously passed to all nested lower test items within it. The test items that were not marked as skipped after state propagation are arranged in the order of execution to form the linear test sequence.

[0008] Furthermore, in step S4, the constraint solving based on the unified resource mapping information includes: Identify references to resources already defined within the Uniform Resource Mapping information in the parameter expressions; The parameter expression is solved by using the referenced resource value as a known quantity.

[0009] Furthermore, in step S4, the unified intermediate representation adopts a tabular form and includes at least: a test plan table for storing the linear test sequence and a parameter and resource table for storing the normalized parameters and resource mapping relationships.

[0010] Furthermore, in step S5, the rendering to generate test code executable on the target test platform includes: For the pin group-oriented test operations defined in the unified intermediate representation, the group operations are expanded into independent control instruction sequences for specific channels according to the channel rules of the target test platform.

[0011] 11. Further, in step S4, after generating the structured unified intermediate representation, the following is also included: Step S4.1: Perform syntax and logic consistency verification on the unified intermediate representation.

[0012] Secondly, this invention also proposes an automatic conversion system for chip test programs across test platforms, comprising: The source project file parsing module is used to receive a set of project files from the source test platform. The set of project files includes at least a distributed configuration file that defines the distribution of test resources and a test process file that defines the test execution logic. The engineering resource integration and semantic mapping module is used to parse the scattered configuration files, extract the pin definitions, power parameters and sorter settings, and generate platform-independent unified resource mapping information. The test process parsing and logic flattening module is used to parse the test process file, identify the process control markers and test item hierarchy, and flatten the test process with nested hierarchy into a linear test sequence composed of valid test items according to the state propagation rules. The parameter normalization and intermediate representation construction module is used to extract the parameter expressions of the test items in the linear test sequence, combine them with the unified resource mapping information to solve the constraints, convert the solution of the parameter expressions into physical quantity values ​​that conform to the target test platform standard, and integrate the linear test sequence, the normalized parameters and the unified resource mapping information to generate a structured unified intermediate representation. A template-driven code generation engine is used to configure code templates according to the syntax rules of the target testing platform, inject data from the unified intermediate representation into the corresponding code templates, and render and generate test code that can be executed on the target testing platform. The human-machine collaborative verification and iterative generation module is used to provide an editing interface for the unified intermediate representation, update the unified intermediate representation in response to modification instructions, and trigger the template-driven code generation engine to regenerate test code based on the updated unified intermediate representation.

[0013] Furthermore, the test process parsing and logic planeification module is specifically used to: identify the process control flags in the test process file used to mark test items as skipped; when an outer test item is identified as being marked as skipped, synchronously pass the skipped status to all nested lower-level test items; and arrange the test items that are not marked as skipped after the status propagation in the order of execution to form the linear test sequence.

[0014] Furthermore, the parameter normalization and intermediate representation construction module is specifically used in constraint solving to: identify references to defined resources in the unified resource mapping information in the parameter expression, and use the referenced resource values ​​as known quantities to solve the parameter expression.

[0015] Furthermore, the template-driven code generation engine is specifically used to: for the pin-group-oriented test operations defined in the unified intermediate representation, expand the group operations into independent control instruction sequences oriented to specific channels according to the channel rules of the target test platform.

[0016] This invention addresses the problems of low efficiency, inaccurate logic reconstruction, and lack of auditable intermediate layers in existing technologies. By constructing a platform-independent unified intermediate representation and a corresponding automated conversion process, it achieves efficient, accurate, and auditable cross-platform migration. Compared with existing technologies, it has the following beneficial technical effects: 1. Significantly improve conversion efficiency and accuracy: By automating the integration of engineering resources, parsing test processes, normalizing parameters, and generating templated code, it completely replaces traditional manual rewriting, greatly improving the efficiency and consistency of program conversion while ensuring logical fidelity and parameter accuracy.

[0017] 2. Enhanced project controllability and security, reduced maintenance costs: The platform-independent unified intermediate representation provides a clearly structured, auditable, and modifiable data core for the entire conversion process. This not only makes the conversion process transparent and controllable, facilitating problem traceability and debugging, but also supports direct revision and secondary generation of the intermediate representation, significantly reducing rework costs and potential risks caused by platform differences.

[0018] 3. Excellent scalability and platform adaptability: The template-driven generation mechanism and support for iterative generation of a unified intermediate representation enable this solution to flexibly adapt to the syntax rules of different target testing platforms. By updating resource mapping rules and code templates, it can be quickly extended to new target platforms, improving the applicability and lifecycle of the solution. Attached Figure Description

[0019] Figure 1 This is an overall flowchart of an automatic conversion method for chip test programs across test platforms according to the present invention.

[0020] Figure 2 This is a roadmap for the specific implementation of an automatic conversion method for chip test programs across test platforms according to the present invention.

[0021] Figure 3 This is an architecture diagram of a cross-test platform chip test program automatic conversion system according to the present invention.

[0022] Figure 4 This is a diagram of the unified intermediate data table structure of the present invention.

[0023] Figure 5 This is a flowchart of the template code generation process of the present invention. Detailed Implementation

[0024] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and should not be construed as limiting the scope of protection of the present invention.

[0025] like Figure 1 As shown, an automatic conversion method for chip test programs across test platforms according to the present invention is illustrated, which specifically includes the following steps: S1. Receive a set of project files from the source test platform, wherein the set of project files includes at least a distributed configuration file that defines the distribution of test resources and a test process file that defines the test execution logic; S2. Parse the distributed configuration file, extract the pin definitions, power parameters and sorter settings, and generate platform-independent unified resource mapping information; S3. Parse the test process file, identify the process control markers and test item hierarchy, and flatten the nested test process into a linear test sequence composed of valid test items according to the state propagation rules. S4. Extract the parameter expressions of the test items in the linear test sequence, combine them with the unified resource mapping information to solve the constraints, convert the solution of the parameter expressions into physical quantity values ​​that conform to the target test platform standard, and integrate the linear test sequence, the normalized parameters and the unified resource mapping information to generate a structured unified intermediate representation. S5. Configure code templates according to the syntax rules of the target testing platform, inject the data in the unified intermediate representation into the corresponding code templates, and render and generate test code that can be executed on the target testing platform. S6. Provide an editing interface for the unified intermediate representation, update the unified intermediate representation in response to a modification instruction, and trigger step S5 to regenerate the test code based on the updated unified intermediate representation.

[0026] In phase S1, the project files are received from the source test platform, and the entry file path is parsed. The path resolution algorithm locates the project root directory, completes context initialization, and automatically discovers and associates all scattered resource configuration files. If a necessary file is detected as missing, the process is terminated and a clear error location message is output.

[0027] In phase S3, the test flow file is parsed to construct a hierarchical call diagram of the test items. Addressing the common requirement for shielding test modules in test programs, this phase employs a state propagation and synchronization mechanism to ensure the logical consistency of nested structures: when the parser detects that an outer test suite contains a "skip" or "Bypass" flag, it automatically propagates this state to all nested inner test items below it and marks them as skipped. After this mechanism, the system outputs a logically correct linear test sequence consisting of the actual test items to be executed.

[0028] In phase S4, resource configuration and test parameters are extracted, and constraint solving and normalization are performed. First, pin definitions, channel mappings, power supply and selector settings are extracted from the resource file, and conflict detection and early warning are implemented. Then, dependency analysis is performed on the parameter expressions, and the solution is completed through iterative calculation. The results (current, voltage, time, etc.) are uniformly converted into physical units and range standards that meet the requirements of the target test platform. Finally, the system integrates the linear test sequence, normalized parameters, and resource mapping relationships to generate a structured, platform-independent unified intermediate representation and records a complete audit log.

[0029] In stages S5 and S6, code templates are configured according to the target platform rules, and data from the unified intermediate representation is injected into the templates to generate target test code. This stage supports manual intervention, allowing for verification and modification of the unified intermediate representation. Upon receiving a revision instruction, the system can regenerate code based on the updated unified intermediate representation, thus achieving a fully automated—manual verification—iterative generation secure and controllable closed-loop process.

[0030] Furthermore, the specific descriptions of the test process logic and platform-independent unified resource mapping information are as follows.

[0031] 1. Test process documents: Test process files refer to structured information parsed from the test process files of the source test platform, used to control the execution order and conditions of test items. Their core meaning is not limited to static sequence definitions, but also encompasses dynamic runtime flow control, specifically including: Test plan call relationships: The hierarchical organization and call relationships between different test items (such as TestSuite and specific tests) in the test project, i.e., the execution skeleton of the entire test program. The system reconstructs the execution logic of the original test program by reading the original test project, and supports global call chain tracing across file levels.

[0032] Conditional branching structure: Conditional logic (such as if / else statements) that controls whether a test item is executed in the test process. By extracting these conditional branches, the system ensures that the transformed target code can accurately execute the corresponding branch flow based on different test results or pre-set flags.

[0033] The "Skip" flag and its propagation status: Test nodes marked as Bypass or with a condition of false. The documentation specifically emphasizes that the system uses a state propagation mechanism to synchronously pass the "Skip" status of outer test nodes (such as test suites) to all their nested test items, ultimately determining a valid set of test plans to be executed. This is crucial for reconstructing complex test logic.

[0034] 2. Resource mapping information: Resource mapping information refers to the definitions extracted from various resource configuration files of the source test platform, describing the test hardware resources and their usage. After deduplication, conflict checking, and normalization, it forms a standardized structural representation that is completely detached from the specific machine syntax. Its specific content includes: Pin Definitions and Grouping: The physical channel mapping relationship of each pin of the Device Under Test (DUT) on the test machine, as well as the functional grouping information of the pins. It also covers the electrical attribute definitions of the pins (such as digital I / O, analog pins, high-voltage pins, etc.) to ensure accurate allocation of hardware resources during multi-channel parallel testing.

[0035] Power supply configuration: The voltage and current specifications of various power supplies (such as VDD and VSS) applied to the DUT during the test, as well as their connection status. In addition, it covers the power-on and power-off timing control of these power supplies and the delay time to ensure signal stability.

[0036] Sorting Mapping: The rules for mapping test results (such as Pass / Fail) to chip sorting (BinMap) are used to classify chips in mass production. Specifically, it includes software sorting (Soft Bin) and hardware sorting (Hard Bin), as well as sorting priority decision mechanisms (such as forcing Fail status to override Pass status).

[0037] Relay switch status: The relay switch configuration that controls the signal path of the hardware in the test system. Since different test items require connection to different test instruments, the system must accurately analyze the on / off status of the relays and their specific operating sequence. Accurate extraction of these state mappings ensures correct connection of test signals and effectively prevents hardware damage caused by incorrect switch switching.

[0038] Example 2: As Figure 2As shown, an automatic conversion system for chip test programs across test platforms according to the present invention is illustrated, comprising: a source project file parsing module 100, a project resource integration and semantic mapping module 200, a test process parsing and logic planeification module 300, a parameter normalization and intermediate representation construction module 400, a template-driven code generation engine 500, and a human-machine collaborative verification and iterative generation module 600.

[0039] The source project file parsing module 100 is used to receive a set of project files from the source test platform. The set of project files includes at least a distributed configuration file that defines the distribution of test resources and a test process file that defines the test execution logic. The engineering resource integration and semantic mapping module 200 is used to parse the scattered configuration files, extract the pin definitions, power parameters and sorter settings, and generate platform-independent unified resource mapping information. The test process parsing and logic flattening module 300 is used to parse the test process file, identify the process control markers and test item hierarchy, and flatten the test process with nested hierarchy into a linear test sequence composed of valid test items according to the state propagation rules. The parameter normalization and intermediate representation construction module 400 is used to extract the parameter expressions of the test items in the linear test sequence, combine them with the unified resource mapping information to solve the constraints, convert the solution results of the parameter expressions into physical quantity values ​​that conform to the target test platform standard, and integrate the linear test sequence, the normalized parameters and the unified resource mapping information to generate a structured unified intermediate representation. Template-driven code generation engine 500 is used to configure code templates according to the syntax rules of the target testing platform, inject data from the unified intermediate representation into the corresponding code template, and render and generate test code that can be executed on the target testing platform. The human-machine collaborative verification and iterative generation module 600 is used to provide an editing interface for the unified intermediate representation, update the unified intermediate representation in response to modification instructions, and trigger the template-driven code generation engine to regenerate test code based on the updated unified intermediate representation.

[0040] like Figure 3The diagram illustrates the overall architecture of an automatic conversion system for chip test programs across test platforms according to the present invention. The system consists of multiple logical layers from top to bottom, including: an input layer, an automatic pathfinding layer, a logic parsing layer, an intermediate data table layer, a rule generation layer, and an output layer. The input layer receives the entry file, project directory, and rule configuration; the automatic pathfinding layer performs chained indexing based on path identification and associated resources; the logic parsing layer performs in-depth analysis and extraction of the source test platform's process logic, resource configuration, and parameters; the intermediate data table layer structures the extracted content into a unified standard format; the rule generation layer performs conversion based on query mapping and a template rendering engine; and the final output layer produces the target platform's project definition code, level timing code, and test method code. This layered architecture effectively decouples source platform parsing from target code generation.

[0041] like Figure 4 The diagram illustrates the unified intermediate data table structure of this invention. This intermediate data table serves as the system's data hub, existing in a standardized and structured form, independent of the syntax of any specific machine platform. Its structure includes core table A (Test Plan Master Table), core table B (Test Parameter Table), core table C (Resource Mapping Information), core table D (Sorting Rule Table), and core table E (Level / Timing Sub-Table). These core tables achieve cross-table indexing through stable links and are uniformly supplemented with extended fields, including anomaly flags, version numbers, and audit timestamps. This structure not only ensures standardized data transmission but also provides clear and intuitive data support for subsequent difference comparisons, problem backtracking, and manual intervention.

[0042] like Figure 5 The diagram illustrates the processing flow of the template code generation engine (corresponding to the code rendering parts of processes S6 and S7) in this invention. This flow details the target code generation mechanism: First, a predefined target platform rule file is loaded, including field mapping rules, condition rules, and template rules. Next, intermediate data tables are queried according to test plan items, and corresponding variable contexts are established for data binding. Subsequently, condition mapping and unit formatting are performed. When processing hardware pin operations, the engine executes a loop expansion strategy according to pin groups, automatically traversing and expanding a single group operation into a code sequence for multiple specific channels. Then, according to the condition rendering process control flags, the engine renders the processed context, concatenates code fragments, and forms the final target project configuration file and test code. Finally, the system outputs the generated code, along with information including exception markers and audit logs, for regression verification and review to ensure the generated code meets the target production line requirements.

[0043] In summary, the present invention provides an automatic conversion method for chip test programs across test platforms. This method constructs a standardized, high-fidelity unified intermediate data table through automatic engineering pathfinding, state propagation filtering, and iterative parameter solving, and then uses a rule-driven generation engine to complete code mapping and rendering. Data communication and transmission between modules are achieved through this unified intermediate data table, ensuring both extremely high efficiency and accuracy of the automated conversion process, while also empowering test engineers to verify and intervene in intermediate stages. This significantly improves the efficiency and engineering reliability of cross-platform migration of chip test programs.

[0044] The above description is merely an embodiment of the present invention and is not intended to limit the methods proposed in this invention. The scope of protection of this invention is defined by the claims. Any obvious modifications or variations in form and detail made by those skilled in the art without departing from the spirit and scope of this invention should fall within the scope of protection of this invention.

Claims

1. A method for automatic conversion of chip test programs across test platforms, characterized in that, Includes the following steps: S1. Receive a set of project files from the source test platform, wherein the set of project files includes at least a distributed configuration file that defines the distribution of test resources and a test process file that defines the test execution logic; S2. Parse the distributed configuration file, extract the pin definitions, power parameters and sorter settings, and generate platform-independent unified resource mapping information; S3. Parse the test process file, identify the process control markers and test item hierarchy, and flatten the nested test process into a linear test sequence composed of valid test items according to the state propagation rules. S4. Extract the parameter expressions of the test items in the linear test sequence, combine them with the unified resource mapping information to solve the constraints, convert the solution of the parameter expressions into physical quantity values ​​that conform to the target test platform standard, and integrate the linear test sequence, the normalized parameters and the unified resource mapping information to generate a structured unified intermediate representation. S5. Configure code templates according to the syntax rules of the target testing platform, inject the data in the unified intermediate representation into the corresponding code templates, and render and generate test code that can be executed on the target testing platform. S6. Provide an editing interface for the unified intermediate representation, update the unified intermediate representation in response to a modification instruction, and trigger step S5 to regenerate the test code based on the updated unified intermediate representation.

2. The method for automatic conversion of chip test programs across test platforms according to claim 1, characterized in that, In step S3, the flattening of the nested test process according to the state propagation rules specifically includes: Identify the flow control markers in the test flow file used to mark test items as skipped; When an outer test item is identified as being marked as skipped, the skipped status is synchronously passed to all nested lower test items within it. The test items that were not marked as skipped after state propagation are arranged in the order of execution to form the linear test sequence.

3. The method for automatic conversion of chip test programs across test platforms according to claim 1, characterized in that, In step S4, the constraint solving based on the unified resource mapping information includes: Identify references to resources already defined within the Uniform Resource Mapping information in the parameter expressions; The parameter expression is solved by using the referenced resource value as a known quantity.

4. The method for automatic conversion of chip test programs across test platforms according to claim 1, characterized in that, In step S4, the unified intermediate representation is in tabular form and includes at least: a test plan table for storing the linear test sequence and a parameter and resource table for storing the normalized parameters and resource mapping relationships.

5. The method for automatic conversion of chip test programs across test platforms according to claim 1, characterized in that, In step S5, the rendering process generates test code that can be executed on the target test platform, including: For the pin group-oriented test operations defined in the unified intermediate representation, the group operations are expanded into independent control instruction sequences for specific channels according to the channel rules of the target test platform.

6. The method for automatic conversion of chip test programs across test platforms according to claim 1, characterized in that, Step S4, after generating the structured unified intermediate representation, also includes: Step S4.1: Perform syntax and logic consistency verification on the unified intermediate representation.

7. An automatic conversion system for chip test programs across test platforms, characterized in that, include: The source project file parsing module is used to receive a set of project files from the source test platform. The set of project files includes at least a distributed configuration file that defines the distribution of test resources and a test process file that defines the test execution logic. The engineering resource integration and semantic mapping module is used to parse the scattered configuration files, extract the pin definitions, power parameters and sorter settings, and generate platform-independent unified resource mapping information. The test process parsing and logic flattening module is used to parse the test process file, identify the process control markers and test item hierarchy, and flatten the test process with nested hierarchy into a linear test sequence composed of valid test items according to the state propagation rules. The parameter normalization and intermediate representation construction module is used to extract the parameter expressions of the test items in the linear test sequence, combine them with the unified resource mapping information to solve the constraints, convert the solution of the parameter expressions into physical quantity values ​​that conform to the target test platform standard, and integrate the linear test sequence, the normalized parameters and the unified resource mapping information to generate a structured unified intermediate representation. A template-driven code generation engine is used to configure code templates according to the syntax rules of the target testing platform, inject data from the unified intermediate representation into the corresponding code templates, and render and generate test code that can be executed on the target testing platform. The human-machine collaborative verification and iterative generation module is used to provide an editing interface for the unified intermediate representation, update the unified intermediate representation in response to modification instructions, and trigger the template-driven code generation engine to regenerate test code based on the updated unified intermediate representation.

8. The automatic conversion system for chip test programs across test platforms according to claim 7, characterized in that, The test process parsing and logic planeification module is specifically used to: identify the process control flags in the test process file used to mark test items as skipped; when an outer test item is identified as being marked as skipped, synchronously pass the skipped status to all nested lower-level test items; and arrange the test items that are not marked as skipped after the status propagation in the order of execution to form the linear test sequence.

9. The automatic conversion system for chip test programs across test platforms according to claim 7, characterized in that, The parameter normalization and intermediate representation construction module is specifically used in constraint solving to: identify references to defined resources in the unified resource mapping information in the parameter expression, and use the referenced resource values ​​as known quantities to solve the parameter expression.

10. The automatic conversion system for chip test programs across test platforms according to claim 7, characterized in that, The template-driven code generation engine is specifically used to: expand the test operations defined in the unified intermediate representation for pin groups into independent control instruction sequences for specific channels according to the channel rules of the target test platform.

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