Chip power map making method and making system
By dividing the chip into power grid units according to modules, and using tabular data processing and computer-aided drawing software, a high-precision power map is automatically generated, which solves the problem of inaccurate power density distribution in traditional methods and achieves efficient and accurate thermal simulation support.
Patent Information
- Application Number
- CN202611131725.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-29
- Publication Date
- 2026-08-25
AI Technical Summary
Traditional methods for creating chip power maps cannot accurately reflect the non-uniform power density distribution inside the chip, resulting in large deviations in thermal simulation results, which affects the accuracy of heat dissipation design and chip reliability.
The chip is divided into power grid cells according to the actual module distribution. High-precision power maps are automatically generated using tabular data processing tools and computer-aided plotting software. This includes code verification, data parsing, grid optimization, and format standardization to ensure data consistency and compatibility with simulation software.
It achieves high-fidelity, accurate and efficient power map production, shortens the production cycle, reduces human error, improves the quality of simulation mesh generation and the stability of thermal simulation numerical calculation, and supports dynamic power consumption data iterative updates.
Smart Images
Figure CN122635262A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip thermal simulation design technology, and to a method and system for creating a chip power map, particularly a high-fidelity, accurate and efficient method and system for creating a power map. Background Technology
[0002] A power map is a precise description of the power density distribution inside a chip. It serves as a dedicated input file for thermal simulation software, providing the chip's heat source distribution and determining the accuracy of the entire simulation chain, from thermal analysis to power integrity and reliability. Traditional chip power map creation methods have several inherent flaws: First, the single heat source method directly applies a total power consumption to the center of the chip, treating it as a uniform heat source, which fails to reflect the true non-uniform power distribution inside the chip, leading to a significant underestimation of hotspot temperatures. Second, the non-uniform heat source method simplifies the chip's power consumption according to its main functional modules, which is suitable for small, low-power chips. However, for large chips, especially high-performance AI chips with significant power gradients, this method lacks fine-grained gridded power mapping and cannot accurately characterize the non-uniform power density distribution inside the chip, resulting in significant discrepancies between subsequent thermal simulation and experimental results.
[0003] Modern AI chips consume over 1000W of power, with local power densities exceeding 1.5W / mm², and hotspot temperatures can be more than 25°C higher than the average. If the power map is inaccurate, thermal simulations cannot pinpoint the actual hotspot locations, leading to insufficient redundancy or overly conservative heat dissipation designs. This results in thermal simulations severely underestimating peak temperatures. In actual chip operation, this can trigger overheating and frequency throttling, or even thermal failure, causing a reduction in chip computing power and reliability. Summary of the Invention
[0004] This invention provides a method and system for creating power maps for chips, specifically a high-fidelity, accurate, and efficient method and system for creating power maps. The entire chip is divided into power grid cells according to the actual module distribution, aiming to solve the problems of traditional methods such as single heat sources, poor accuracy, and inability to reflect dynamic over-temperature risks, achieving seamless and high-precision conversion from floorplan code to simulation software.
[0005] The first aspect of this invention provides a method for creating a power map of a chip, comprising the following steps: S1. Provide chip layout source code, wherein the chip layout source code includes several partition sets and rectangular units within the partition sets, wherein the partition sets are defined as functional partition groups and the rectangular units are defined as functional sub-blocks; S2. Use a table data processing tool to parse the original code of chip layout by line and column, generate a standardized data table, and automatically splice the coordinate parameters in the standardized data table to obtain the rectangle drawing control statement adapted to computer-aided drawing software. S3. Extract the names of functional sub-blocks and rectangle drawing control statements from the standardized data table, and export the first automated drawing control file. The first automated drawing control file is classified and stored by functional partition group. All rectangle drawing control statements corresponding to the same functional partition group are arranged and stored in a centralized manner. That is, in the first automated drawing control file, each functional partition group is used as a dividing unit. The rectangle drawing control statements corresponding to all functional sub-blocks in each functional partition group are written in a centralized manner below the partition identifier of each group. The drawing statements of different functional partition groups are separated from each other and stored in partitions. S4. Create a second automated drawing control file based on the functional partition group, and import the second automated drawing control file and the first automated drawing control file into the computer-aided drawing software to generate the initial power map. S5. Perform mesh geometry optimization on the initial power map; S6. In the optimized power map, batch measure and extract the coordinate parameters of each functional zone group grid cell, and generate a standardized coordinate parameter table to unify the data format of the power map; and S7. Based on the standardized coordinate parameter table, the optimized power map is formatted and then imported into the thermal simulation software to complete the chip power heat source modeling.
[0006] Furthermore, it also includes compliance verification of the original code for chip layout, including: the names of functional partition groups are not duplicated, the coordinates of all functional sub-blocks within the same functional partition group are arranged in the same row, and each functional sub-block is defined by a rectangular area by the first diagonal x-coordinate, the first diagonal y-coordinate, the second diagonal x-coordinate, and the second diagonal y-coordinate.
[0007] Furthermore, in step S2, the header of the standardized data table includes the name of the functional sub-block, the first diagonal x-coordinate, the first diagonal y-coordinate, the second diagonal x-coordinate, and the second diagonal y-coordinate.
[0008] Furthermore, the tabular data processing tool is a data processing program capable of parsing row and column data, splitting fields, and generating structured data tables. For example, it could be an Excel file or a script program capable of parsing structured text data, used to split the original text-formatted map code into rows and columns, extract group names and diagonal coordinates, and generate standardized data tables in Excel or CSV format.
[0009] Furthermore, the computer-aided drawing software is a two-dimensional CAD drawing software such as AutoCAD, which can read external automated control files, create new layers, set layer colors, batch draw rectangular graphics, and generate layered and visualized power map drawings according to file instructions.
[0010] Furthermore, the first automated drawing control file contains partition identifiers to distinguish different functional partition groups, and each rectangular drawing control statement in the file corresponds to a functional sub-block. Setting partition identifiers and having each statement correspond to a single functional sub-block allows the drawing software to identify the functional partition group to which each drawing statement belongs, and accurately match the layers and color schemes in the second automated drawing control file.
[0011] Further, in step S4, generating the power map includes the following steps: S401. Create a second automated drawing control file, which creates a dedicated layer for each functional area group, and different functional area groups are matched with different display colors; and S402. Open the computer-aided drawing software, and import the second automated drawing control file and the first automated drawing control file in sequence through the software's built-in file import function. The software will automatically render the initial power map in layers.
[0012] Furthermore, the second automated drawing control file is an automated execution file adapted to computer-aided drawing software, which configures an independent layer and exclusive display color for each functional partition group; the first automated drawing control file stores the rectangle drawing control statements corresponding to each functional sub-block.
[0013] Furthermore, the second automated drawing control file includes layer creation control instructions and layer color assignment control instructions.
[0014] Furthermore, in step S5, the mesh geometry optimization of the initial power map includes at least one of stretching and aligning misaligned boundaries, trimming overlapping blocks, or filling tiny gaps between cells, in order to eliminate at least one of cell gaps, block intersections, or boundary misalignment defects, and ensure the continuity and integrity of the chip heat source space.
[0015] Furthermore, the standardized coordinate parameter table includes the diagonal coordinates of functional partition groups, graphic area, boundary feature points, and layer attribute information. After formatting using the standardized coordinate parameter table, it is imported into the thermal simulation software, enabling the power map to be recognized and read by the simulation software, successfully building the chip heat source model, and completing the entire process of creating a power map from code parsing to simulation application.
[0016] A second aspect of the present invention provides a power map generation system for a chip, which is used to execute the power map generation method for the chip described in the first aspect. The power map generation system includes: The code verification module is configured to perform compliance verification of the functional partition group names and functional sub-block coordinates in the original code of the chip layout. The table parsing and conversion module is configured to split the original code of the chip layout, generate a standardized data table, and automatically stitch together the control statements for drawing rectangles. The control file generation module is configured to output a first automated drawing control file that stores rectangle drawing control statements and a second automated drawing control file that stores layer color matching rules. The computer-aided drawing module is configured to import the first and second automated drawing control files and automatically generate a layered and visualized initial power map. A grid optimization module is configured to identify and repair geometric defects in the initial power map; The coordinate extraction module is configured to batch collect the coordinates and geometric parameters of optimized mesh cells and output a standardized coordinate parameter table; and The simulation docking module is configured to import the standardized power map into the thermal simulation software to complete the heat source modeling.
[0017] Furthermore, the geometric defects include at least one of grid gaps, block intersections, or boundary misalignments.
[0018] The present invention has at least the following beneficial effects: 1) The present invention directly parses the original code of chip layout to achieve full-process automation, eliminating the need for manual mesh drawing, greatly shortening the power map production cycle, eliminating human error caused by manual coordinate input and drawing, ensuring that the data from the original layout data to the visualized power map is consistent throughout the entire process, and improving the efficiency of layout generation and data reliability; 2) The present invention automatically creates an exclusive layer for each functional partition group based on the original grouping information, with the layer name corresponding one-to-one with the group identifier and each group assigned a distinguishing color number, realizing modular control of the layout, and reducing the operational difficulty of later layout iteration modification and defect investigation; 3) The present invention uniformly performs boundary alignment, gap filling and overlap clipping optimization on the initial power map, so that the geometric region of the heat source is continuously closed, avoiding simulation adaptation problems caused by layout topology defects from the source, improving the quality of simulation mesh division, ensuring that thermal simulation numerical calculation can converge stably, and broadening the compatibility and adaptation capability of the power map file with mainstream thermal simulation tools; 4) The power map generated by the present invention supports dynamic power consumption data iterative updates, and can be extended to dynamic power consumption modeling, electrothermal multi-physics field collaborative simulation optimization work. Attached Figure Description
[0019] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.
[0020] Figure 1 A schematic flowchart of a chip power map creation method in some embodiments of the present invention is shown; Figure 2 The diagram illustrates example data formats of the original code for chip layout in some embodiments of the present invention. Figure 3 The following diagrams illustrate the standardized data table structure and the generation of drawing control statements in some embodiments of the present invention. Figure 4 An example diagram of the contents of a first automated drawing control file is shown in some embodiments of the present invention; Figure 5 This invention illustrates a comparison diagram of a second automated drawing control file and automatically generated layers in some embodiments. Figure 6 This invention illustrates a comparison diagram of two types of automated drawing control files imported to generate initial power maps in some embodiments of the present invention. Figure 7 This invention illustrates a power map after geometric defect optimization in some embodiments. Figure 8 This invention illustrates a schematic diagram of optimized power map coordinate parameter extraction in some embodiments. Figure 9 The diagram illustrates a power map being imported into thermal simulation software to complete heat source modeling in some embodiments of the present invention. Detailed Implementation
[0021] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.
[0022] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.
[0023] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.
[0024] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.
[0025] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".
[0026] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0027] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.
[0028] The following embodiment provides a method for creating a power map for a chip. Figure 1 A schematic diagram of the power map creation method is shown, including the following steps: S1. Receive the original chip floorplan code. After confirming that the code information is complete and the format is correct, perform compliance verification: The original chip floorplan code contains several partition sets and rectangular units within the partition sets. The partition sets are defined as functional partition groups, and the rectangular units are defined as functional sub-blocks. The compliance verification includes: the names of the functional partition groups are not repeated; the coordinates of all functional sub-blocks within the same functional partition group are arranged in the same row; and each functional sub-block is defined by a rectangular area defined by the first diagonal x-coordinate, the first diagonal y-coordinate, the second diagonal x-coordinate, and the second diagonal y-coordinate. S2. Using a table data processing tool (such as Microsoft Excel), the verified chip layout original code is parsed row by row and column by column to generate a standardized data table. The data is converted into a standardized format of functional sub-block names and two sets of vertex coordinates. Based on the coordinate parameters in the standardized data table, the rectangle drawing control statements adapted to computer-aided drawing software (such as AutoCAD) are automatically concatenated. The header of the standardized data table includes the functional sub-block name, the first diagonal x-coordinate, the first diagonal y-coordinate, the second diagonal x-coordinate, and the second diagonal y-coordinate. S3. Extract the names of functional sub-blocks and rectangle drawing control statements from the standardized data table. Organize the preprocessed data into the scr command line format and export the first automated drawing control file (clayer_rectang.scr). The first automated drawing control file is categorized and stored by functional partition group. All rectangle drawing control statements corresponding to the same functional partition group are arranged and stored together. That is, in the first automated drawing control file, each functional partition group is used as a dividing unit. The rectangle drawing control statements corresponding to all functional sub-blocks in each functional partition group are written below the partition identifier of each group. The drawing statements of different functional partition groups are separated and stored in partitions. The first automated drawing control file sets partition identifiers to distinguish different functional partition groups. Each rectangle drawing control statement in the file corresponds to a functional sub-block. S4. Create a second automated drawing control file based on the functional partition group. Import the second automated drawing control file and the first automated drawing control file into the computer-aided drawing software sequentially to automatically generate the initial power map. Generating the power map includes the following steps: S401. Create a second automated drawing control file (group_layer_color.scr). This second automated drawing control file creates a separate layer for each functional group, and different functional groups are matched with different display colors. The second automated drawing control file contains layer creation control instructions and layer color assignment control instructions; and S402. Open the computer-aided drawing software and import the second automated drawing control file and the first automated drawing control file in sequence through the software's built-in file import function. The software will automatically render the initial power map in layers. S5. Optimize the mesh geometry of the initial power map to optimize the overall shape of the initial power map and the gap between each functional sub-block. This includes stretching and aligning misaligned boundaries, trimming overlapping blocks, or filling small gaps between units to eliminate at least one of the defects in unit gaps, block crossovers, or boundary misalignments, ensuring the continuity and integrity of the chip's heat source space. S6. Extract the coordinate data of each functional sub-block in batches using computer-aided plotting software and export it to a table. In the optimized power map, measure and extract the coordinate parameters of each functional zone group's grid cell in batches, generating a standardized coordinate parameter table to unify the power map's data format. The standardized coordinate parameter table includes the diagonal coordinates of the functional zone group, the graphic area, boundary feature points, and layer attribute information. S7. Based on the standardized coordinate parameter table, the optimized power map is formatted and then imported into the thermal simulation software to complete the chip power heat source modeling. The power map is formatted using the standardized coordinate parameter table and then imported into the thermal simulation software so that it can be recognized and read by the simulation software, successfully building the chip heat source model and completing the entire process of creating the power map from code parsing to simulation application.
[0029] The following embodiments also provide a power map creation system for a chip, which is used to execute the power map creation method for the chip in the first aspect. The power map creation system includes: The code verification module is configured to perform compliance verification of the functional partition group names and functional sub-block coordinates in the original code of the chip layout. The table parsing and conversion module is configured to split the original code of the chip layout, generate a standardized data table, and automatically stitch together the control statements for drawing rectangles. The control file generation module is configured to output a first automated drawing control file that stores rectangle drawing control statements and a second automated drawing control file that stores layer color matching rules. The computer-aided plotting module is configured to import a first automated plotting control file and a second automated plotting control file, and automatically generate a layered and visualized initial power map. The grid optimization module is configured to identify and repair geometric defects in the initial power map; geometric defects include at least one of grid gaps, block intersections, or boundary misalignments. The coordinate extraction module is configured to batch collect the coordinates and geometric parameters of optimized mesh cells and output a standardized coordinate parameter table; and The simulation docking module is configured to import the standardized power map into the thermal simulation software to complete the heat source modeling.
[0030] Specifically, the implementation steps for creating a chip power map are as follows: Figure 2 The diagram shows an example of the raw code data format for chip floorplan. After receiving the raw code for chip floorplan, compliance verification is performed. The code text adopts a hierarchical nested format, with the example format as follows: group01{{20.52 19904.4 2236.68 20171.16} {20.52 12250.44 3016.44 19904.4}}.
[0031] The specific verification rules are as follows: 1) No two groups have the same name; 2) Under the same group entry, all block coordinate parameters contained therein are written in the same line of text; 3) A single set of curly braces {} contains four coordinate parameters used to define the diagonal coordinates of a block, uniquely identifying the rectangular functional sub-block. That is, after receiving the chip's floorplan code, it is necessary to confirm that its group name is unique, the coordinates of each block within the group are on the same line, and the position of each block is defined by the four coordinates within the curly braces.
[0032] Figure 3 This document demonstrates a standardized data table structure and an example diagram of the generated drawing control statements. A table data processing tool is used to break down the verified chip layout source code into rows and columns, generating a standardized data table. The table header is set sequentially as block name, X1, Y1, X2, and Y2. The block name indicates the group and number to which the functional sub-block belongs, and X1, Y1, X2, and Y2 are the four coordinate parameters of the two sets of diagonal vertices required to determine a single rectangular block. Taking the functional partition group with the group identifier group00 as an example, this partition group contains four independent rectangular functional sub-blocks. Each row of coordinate data corresponds to a rectangular unit, and the spatial position of the rectangle is uniquely defined by the four coordinate parameters X1, Y1, X2, and Y2 of that row. Subsequently, using the table text concatenation function, the coordinate fields under each row header are integrated and converted according to the syntax recognizable by CAD software, batch generating script-format drawing instructions adapted to the computer-aided drawing software. This ultimately forms a rectangle drawing control statement with a unified format: RECTANGX1,Y1X2,Y2. In other words, using a table data processing tool, after splitting columns and rows, a new table is output. The table header consists of "Block name, X1, Y1, X2, Y2". For example, a block named "group00" consists of 4 rectangles. Each rectangle is defined by 4 coordinate parameters of 2 vertices. Then, the 4 coordinate parameters are converted into a script format suitable for CAD operation, namely "RECTANG X1,Y1,X2,Y2".
[0033] Figure 4 The diagram shows an example of the content of the first automated drawing control file. It extracts the group identifiers and corresponding rectangle drawing control statements from the standardized data table, arranges the text content according to the functional partition group order, and saves the entire content as a first automated drawing control file with the .scr extension and the filename "clayer_rectang.scr". Specifically, it extracts the named rows from the table and saves them as "clayer_rectang.scr".
[0034] To facilitate subsequent visual inspection and drawing modifications, this solution assigns a dedicated layer to each functional area group. The layer name matches the corresponding group name, and different layers are configured with different display color codes for differentiation. For example... Figure 5 As shown, a script was written to automatically create layers and assign colors in batches. This script was saved as group_layer_color.scr, which is the second automated drawing control file. The script import function of the computer-aided drawing software was used to import the second automated drawing control file and the first automated drawing control file sequentially. The software then executed the layer creation and color matching instructions and the batch rectangle drawing instructions in sequence, generating a layered layout structure, ultimately resulting in the image shown. Figure 6 The initial power map shown is as follows: To facilitate inspection and modification, each group is placed on a separate layer, named with its group name, and each layer has a different color. For example... Figure 5 As shown, create a script to automatically generate layers and name it "group_layer_color.scr". In the drawing software's command bar, type "scr". After importing and creating the layers, import the previously created script files "group_layer_color.scr" and "clayer_rectang.scr" into the drawing software sequentially to obtain the desired result. Figure 5 and Figure 6 The effect Figure 6 This refers to the power map generated initially.
[0035] However, current power maps suffer from minor gaps, cell intersections, and misaligned boundaries, which may prevent simulation software from correctly meshing the data. To ensure the continuity of the chip's heat sources, guarantee mesh quality, and achieve computational convergence, it is necessary to perform mesh geometry optimization on the initial power map, such as... Figure 7 The image shows the optimized power map after defect correction, boundary alignment, gap filling, and overlap trimming.
[0036] like Figure 8 As shown, the coordinates of each group cell are measured in the optimized power map.
[0037] like Figure 9 As shown, import the formatted power map into the simulation software to complete the entire process.
[0038] This invention generates a high-resolution, dynamically updatable power map by analyzing real power grid data at the chip floorplan code level. This solves the problems of low accuracy, inaccurate hotspot location, and inability to reflect transient risks in traditional single-heat-source or module-level partitioning methods. Future development can extend this to dynamic power modeling and multi-physics collaborative optimization (deep integration of thermal, electrical, and mechanical chip design flows).
[0039] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.
Claims
1. A method for creating a power map of a chip, characterized in that, Includes the following steps: S1. Provide chip layout source code, wherein the chip layout source code includes several partition sets and rectangular units within the partition sets, wherein the partition sets are defined as functional partition groups and the rectangular units are defined as functional sub-blocks; S2. Use a table data processing tool to parse the original code of chip layout by line and column, generate a standardized data table, and automatically splice the coordinate parameters in the standardized data table to obtain the rectangle drawing control statement adapted to computer-aided drawing software. S3. Extract the names of functional sub-blocks and rectangle drawing control statements from the standardized data table, and export the first automated drawing control file. The first automated drawing control file is classified and stored by functional partition group, and all rectangle drawing control statements corresponding to the same functional partition group are centrally arranged and stored. S4. Create a second automated drawing control file based on the functional partition group, and import the second automated drawing control file and the first automated drawing control file into the computer-aided drawing software to generate the initial power map. S5. Perform mesh geometry optimization on the initial power map; S6. In the optimized power map, batch measure and extract the coordinate parameters of each functional zone group grid cell, and generate a standardized coordinate parameter table; and S7. Based on the standardized coordinate parameter table, the optimized power map is formatted and then imported into the thermal simulation software to complete the chip power heat source modeling.
2. The method for creating a power map for a chip according to claim 1, characterized in that, It also includes compliance verification of the original code for chip layout, including: the names of functional partition groups are not duplicated, the coordinates of all functional sub-blocks in the same functional partition group are arranged in the same row, and each functional sub-block is defined by a rectangular area by the first diagonal x-coordinate, the first diagonal y-coordinate, the second diagonal x-coordinate, and the second diagonal y-coordinate.
3. The method for creating a power map for a chip according to claim 1, characterized in that, In step S2, the header of the standardized data table includes the name of the functional sub-block, the first diagonal x-coordinate, the first diagonal y-coordinate, the second diagonal x-coordinate, and the second diagonal y-coordinate.
4. The method for creating a power map for a chip according to claim 1, characterized in that, The first automated drawing control file has internal partition identifiers to distinguish different functional partition groups, and a single rectangle drawing control statement in the file corresponds to a functional sub-block.
5. The method for generating a power map for a chip according to claim 1, characterized in that, In step S4, generating the power map includes the following steps: S401. Create a second automated drawing control file, which creates a dedicated layer for each functional area group, and different functional area groups are matched with different display colors; and S402. Open the computer-aided drawing software, and import the second automated drawing control file and the first automated drawing control file in sequence through the software's built-in file import function. The software will automatically render the initial power map in layers.
6. The method for generating a power map for a chip according to claim 1, characterized in that, The second automated drawing control file contains layer creation control instructions and layer color assignment control instructions.
7. The method for generating a power map for a chip according to claim 1, characterized in that, In step S5, the mesh geometry optimization of the initial power map includes at least one of stretching and aligning misaligned boundaries, trimming overlapping blocks, or filling tiny gaps between cells.
8. The method for generating a power map for a chip according to claim 1, characterized in that, The standardized coordinate parameter table includes the diagonal coordinates of the functional partition group, the area of the graphic, the boundary feature points, and the layer attribute information.
9. A power map generation system for a chip, characterized in that, A power map generation method for executing the chip according to any one of claims 1 to 8, the power map generation system comprising: The code verification module is configured to perform compliance verification of the functional partition group names and functional sub-block coordinates in the original code of the chip layout. The table parsing and conversion module is configured to split the original code of the chip layout, generate a standardized data table, and automatically stitch together the control statements for drawing rectangles. The control file generation module is configured to output a first automated drawing control file that stores rectangle drawing control statements and a second automated drawing control file that stores layer color matching rules. The computer-aided drawing module is configured to import the first and second automated drawing control files and automatically generate a layered and visualized initial power map. A grid optimization module is configured to identify and repair geometric defects in the initial power map; The coordinate extraction module is configured to batch collect the coordinates and geometric parameters of optimized mesh cells and output a standardized coordinate parameter table; and The simulation docking module is configured to import the standardized power map into the thermal simulation software to complete the heat source modeling.
10. The chip power map generation system according to claim 9, characterized in that, The geometric defects include at least one of grid gaps, block intersections, or boundary misalignments.