FPGA-based PXI vector network analyzer multi-module synchronization system
By using an FPGA-based multi-module synchronization system, the clock of the PXI vector network analyzer module and the ADC clock were synchronized, solving the problems of amplitude instability and phase jump in the measurement process of cascaded modules, and improving measurement accuracy and flexibility.
Patent Information
- Application Number
- CN202610711334.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-22
- Publication Date
- 2026-08-25
AI Technical Summary
In existing technologies, when cascading PXI vector network analyzer modules, the data acquisition modules are located in different modules, which leads to amplitude instability and phase fluctuations during the measurement process, affecting the measurement accuracy.
A multi-module synchronization system based on FPGA is adopted. The system clock is transmitted to the slave module through the FPGA control unit of the master module to achieve system clock synchronization. The ADC clocks of the master and slave modules are synchronized through phase-locked loop synchronization to ensure the synchronization of measurement and data acquisition.
It solves the problems of amplitude instability and phase jump, improves measurement accuracy, reduces costs, and enhances measurement flexibility, eliminating the need for customized dedicated multi-port equipment.
Smart Images
Figure CN122640097A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication testing technology, and in particular to a multi-module synchronization system for a PXI vector network analyzer based on FPGA. Background Technology
[0002] A vector network analyzer is an electromagnetic wave energy testing device primarily used to measure the scattering parameters of electronic components such as radio frequency microwave devices, antennas, and cables across a wide frequency range, from kilohertz to terahertz. Its core applications include wireless communication, radar systems, aerospace, and materials science research, enabling precise quantitative evaluation of the transmission and reflection characteristics of passive / active devices.
[0003] When using vector network analyzers for automated test system (ATE) testing, multi-port measurements are required. A single vector network analyzer can support 2-port or 4-port measurements, but achieving 8-port, 16-port, or other multi-port measurements with a single analyzer requires custom design, resulting in high cost and poor flexibility. High-performance vector network analyzers based on the PXIe architecture are specifically designed for ATE and compact laboratory applications. They combine the flexibility of PXI modular instruments with the measurement accuracy of VNAs, making them suitable for testing radio frequency (RF), microwave, and millimeter-wave devices. Employing multi-module ADC data synchronization technology and cascading multiple PXI vector network analyzer modules, up to 64 ports of multi-port or multi-site measurements can be performed within a single chassis.
[0004] When using cascaded PXI vector network analyzer modules, amplitude and phase stability is a fundamental characteristic. However, because the data acquisition modules of cascaded PXI vector network analyzer modules are located in different modules, amplitude instability and phase fluctuations may occur during the measurement process, affecting the measurement accuracy. Summary of the Invention
[0005] In view of this, this application provides a multi-module synchronization system for a PXI vector network analyzer based on FPGA to address the shortcomings of the existing technology.
[0006] The first aspect of this application provides a multi-module synchronization system for a PXI vector network analyzer based on an FPGA, comprising: It includes a master module and at least one slave module, and each is equipped with an FPGA control unit; the FPGA control unit transmits the system clock of the master module to all slave modules through a cascading line, serving as the system clock for all slave modules; Before starting the measurement, the main module sends a synchronization request instruction through the FPGA control unit. When the slave module receives the synchronization request instruction, it returns a received instruction. After receiving the received instructions from all slave modules, the main module ends the synchronization request and starts the measurement. After measurement is started, the main module sends a data acquisition request instruction through the FPGA control unit when the preset conditions are met. The instruction is transmitted to the slave module through the cascade line. When the slave module receives the data acquisition request instruction, it returns a request to end instruction. After receiving the request to end instructions from all slave modules, the main module ends the data acquisition request and simultaneously starts the data acquisition operation of the main module and the slave module. The ADC clock of the master module is phase-locked synchronized with its own system clock as the reference clock, and the ADC clocks of all slave modules are phase-locked synchronized with the system clock transmitted by the master module as the reference clock.
[0007] In one possible implementation of the first aspect, both the master module and the slave module are MVN2053A PXI vector network analyzer modules with a measurement frequency range of 100kHz to 53GHz.
[0008] In one possible implementation of the first aspect, both the master module and the slave module are 2-port devices.
[0009] In one possible implementation of the first aspect, the number of master modules is m, the number of all slave modules is n, and the master modules and all slave modules are cascaded to form a vector network analysis system with 2m+2n ports, realizing multi-port parallel measurement, where m≥1 and n≥1.
[0010] In one possible implementation of the first aspect, the vector network analysis system formed by cascading the main module and all slave modules supports parallel measurements of up to 64 ports.
[0011] In one possible implementation of the first aspect, when there are multiple slave modules, the master module sends synchronization request instructions to all slave modules in sequence; after the last slave module receives the synchronization request instruction, all slave modules, starting from the last slave module, relay the received instruction to the master module level by level until all slave modules have completed the feedback.
[0012] In one possible implementation of the first aspect, when there are multiple slave modules, the master module sends data retrieval request instructions to all slave modules in sequence; after the last slave module receives the data retrieval request instruction, all slave modules send request termination instructions to the master module level by level, starting from the last slave module, until all slave modules have completed the feedback.
[0013] In one possible implementation of the first aspect, after measurement is initiated, the main module sends a data retrieval request instruction when preset conditions are met, including: After the main module starts measurement, it transmits a continuous wave at the command frequency as the source signal, and at the same time generates a fixed-frequency local oscillator signal that differs from the source signal by one intermediate frequency, and transmits it to all slave modules. After the source signal is transmitted through the external device under test, it is mixed with the local oscillator signal in the main module or the corresponding slave module to form an intermediate frequency signal. The intermediate frequency signal is acquired by the ADC and processed by the DDC before being uploaded to the host computer. The ADC sampling ready information sent by the host computer is sent to the main module as the preset condition.
[0014] In one possible implementation of the first aspect, the path through which the source signal is transmitted via the external device under test includes a reflection path and a direct path. The signal from the reflection path returns to the receiving end of the main module, and the signal from the direct path is transmitted to the receiving end of the corresponding main module or slave module.
[0015] In one possible implementation of the first aspect, the phase-locked synchronization of the ADC clock by the master module and all slave modules includes ADC data acquisition clock synchronization and ADC initial acquisition setup time synchronization.
[0016] The beneficial effects are as follows: This invention provides a multi-module synchronization system for a PXI vector network analyzer based on FPGA, comprising a master module, each equipped with an FPGA control unit, and at least one slave module. The master module's FPGA transmits its own system clock to the slave modules via cascading lines, serving as the slave module's system clock. Before starting measurement, the master module sends a synchronization request command. After all slave modules respond that they have received the command, measurement is started synchronously. After measurement starts, the master module sends a data acquisition request command when ADC sampling is satisfied. After all slave modules respond with a request to end, data acquisition operations of the master module and all slave modules are started synchronously. The master module's ADC clock uses its own system clock as a reference clock for phase-locked synchronization, and the slave module's ADC clock uses the system clock transmitted by the master module as a reference clock for phase-locked synchronization. This invention effectively solves the problems of amplitude instability and phase jump caused by clock frequency discrepancies and asynchronous measurement data acquisition in traditional multi-module cascading, and eliminates the need for customized dedicated multi-port equipment, significantly reducing costs and improving measurement flexibility. Simultaneously, it ensures phase and amplitude stability in multi-port measurements, guaranteeing the accuracy of scattering parameter measurements. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a multi-module synchronization system for a PXI vector network analyzer based on FPGA, provided in an embodiment of this application. Figure 2 This is a schematic diagram of the principle of a vector network analyzer in the existing technology; Figure 3 This is a schematic diagram of the synchronization timing of the measurement process provided in the embodiments of this application; Figure 4 This is a schematic diagram of the ADC clock synchronization timing provided in the embodiments of this application. Detailed Implementation
[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.
[0021] Example In existing technologies, vector network analyzers are electromagnetic wave energy testing devices primarily used to measure the scattering parameters of electronic components such as radio frequency microwave devices, antennas, and cables over a wide frequency range, from kilohertz to terahertz. Their core application areas include wireless communication, radar systems, aerospace, and materials science research, enabling precise quantitative evaluation of the transmission and reflection characteristics of passive / active devices. Figure 2As shown, the vector network analyzer transmits a fixed-frequency signal through a transmitter source, which is then transmitted or directly transmitted through a coupler. The signal is mixed with the corresponding fixed-frequency local oscillator signal to generate an intermediate frequency signal. The signal is then acquired by an ADC, processed, and uploaded to a host computer for use.
[0022] When PXI vector network analyzer modules are cascaded, amplitude and phase stability is a fundamental characteristic. However, because the data acquisition modules of the cascaded PXI vector network analyzer modules are located in different modules, amplitude instability and phase fluctuations may occur during the measurement process, affecting the measurement accuracy.
[0023] Therefore, this application provides a multi-module synchronization system for a PXI vector network analyzer based on FPGA, such as... Figure 1 As shown, it includes a master module and at least one slave module, all of which are equipped with an FPGA control unit; the FPGA control unit transmits the system clock of the master module to all slave modules through a cascading line, serving as the system clock for all slave modules; Before starting the measurement, the main module sends a synchronization request instruction through the FPGA control unit. When the slave module receives the synchronization request instruction, it returns a received instruction. After receiving the received instructions from all slave modules, the main module ends the synchronization request and starts the measurement. After measurement is started, the main module sends a data acquisition request instruction through the FPGA control unit when the preset conditions are met. The instruction is transmitted to the slave module through the cascade line. When the slave module receives the data acquisition request instruction, it returns a request to end instruction. After receiving the request to end instructions from all slave modules, the main module ends the data acquisition request and simultaneously starts the data acquisition operation of the main module and the slave module. The ADC clock of the master module is phase-locked synchronized with its own system clock as the reference clock, and the ADC clocks of all slave modules are phase-locked synchronized with the system clock transmitted by the master module as the reference clock.
[0024] This embodiment provides a multi-module synchronization system for a PXI vector network analyzer based on FPGA. The core of this system is to achieve precise timing alignment between the master and slave modules through a triple synchronization mechanism, thereby solving the problems of amplitude instability and phase jump during cascaded measurements. Ultimately, it enables high-precision measurement of multi-port scattering parameters. The system composition, triple synchronization mechanism, and complete workflow are explained in detail.
[0025] 1. Basic System Components The hardware foundation of this system is an architecture consisting of a master module, slave modules, an FPGA control unit, and cascaded lines. Each part has a clearly defined function and works in concert. The main module, configured with an FPGA control unit, a signal transmission unit, and an ADC sampling unit, serves as the clock source and instruction initiator for the entire system, and is responsible for transmitting a fixed-frequency source signal and a fixed-frequency local oscillator signal that differs from the source signal by one intermediate frequency. The module, with a minimum quantity of one, is also configured with an FPGA control unit, a signal transmission unit, and an ADC sampling unit. It receives the clock and instructions from the main module and completes signal reception, mixing, and data acquisition. Cascading lines are used for bidirectional transmission of clock signals, command signals, and feedback signals between master and slave modules, and serve as the physical channel for implementing synchronization mechanisms. The host computer, as the system control center, issues measurement start and stop commands, determines the ADC sampling ready status, and receives and processes the collected data to calculate scattering parameters.
[0026] 2. Triple synchronization mechanism The triple synchronization mechanism is the core technology of the system, which progresses layer by layer from three levels: hardware benchmark, action coordination, and data accuracy, to ensure measurement accuracy.
[0027] First step: System clock synchronization (unifying hardware timing benchmarks) The purpose is to eliminate frequency deviations between the master module and slave module caused by independent clock sources, and to avoid misalignment of measurement triggering and data acquisition timing.
[0028] The principle is that the FPGA control unit of the main module transmits its own system clock to all slave modules in real time through the cascading line. The slave modules abandon their own independent clocks and directly use the clock transmitted by the main module as their own clocks.
[0029] Its function is to ensure that the hardware operating timing of the master module and slave module is completely consistent, laying the foundation for subsequent measurement and data acquisition synchronization.
[0030] The second layer: Measurement process synchronization (achieving coordinated actions between master and slave modules), such as... Figure 3 As shown The mechanism is divided into two stages: measurement-triggered synchronization and data retrieval-triggered synchronization. It adopts the logic of the master module sending requests, the slave modules providing feedback step by step, and the actions being executed synchronously. It supports the expansion of multiple slave modules.
[0031] Measurement triggers synchronization: After the host computer issues the measurement command, the main module FPGA sends a synchronization request command to all slave modules; After receiving instructions from a module, the system feeds back the received instructions to the modules level by level, starting from the last module, to ensure that no module is missed. After receiving feedback from all slave modules, the master module ends the synchronization request. The master and slave modules start measurement at the same time, generating and transmitting fixed-frequency source signals and local oscillator signals.
[0032] Data retrieval triggers synchronization: After the source signal is transmitted through the device under test, it is mixed with the local oscillator signal to generate a stable intermediate frequency signal; after the host computer detects that the signal is stable, it sends ADC sampling ready information to the main module. The master FPGA module sends data retrieval request commands to all slave modules; After receiving the instruction from the module, the same step-by-step feedback method is used to send a request to end the process to the main module; After the master module receives all feedback, it triggers both the master and slave modules to perform ADC data retrieval operations at the same time to avoid amplitude fluctuations caused by data retrieval time differences.
[0033] The third layer: ADC data acquisition synchronization (ensuring the phase stability of the intermediate frequency signal), such as Figure 4 As shown The aim is to solve the phase jump problem caused by inconsistent sampling timing of multi-module ADCs, which is the key to determining measurement accuracy.
[0034] The principle is that synchronization includes two dimensions: ADC data acquisition clock synchronization and ADC initial acquisition setup time synchronization. The master module ADC uses its own system clock as a reference for phase-locked synchronization, and all slave module ADCs use the system clock transmitted by the master module for phase-locked synchronization.
[0035] Its function is to ensure that the ADC sampling frequency and initial acquisition time of the master and slave modules are completely aligned, so as to ensure that the phase of the intermediate frequency signal is consistent during sampling and completely eliminate phase jump.
[0036] 3. Complete Workflow Step 1: Cascade multiple MVN2053 modules.
[0037] The principle is to establish a physical connection between the master module and the slave module through a dedicated cascading line, and to open up a bidirectional transmission channel for clock signals, command signals and data signals. This provides the hardware foundation for subsequent system clock synchronization, command interaction and data transmission, and is a prerequisite for multi-module collaborative measurement.
[0038] Step 2: The FPGA control unit synchronizes the ADC clocks of multiple MVN2053 modules.
[0039] The principle is that this is the core execution step of ADC data acquisition synchronization. The master module FPGA uses its own system clock as a reference to perform phase-locked synchronization of the master module ADC clock; the slave module FPGA uses the system clock transmitted by the master module as a reference to perform phase-locked synchronization of the slave module ADC clock. This operation unifies the ADC data acquisition clock frequency and initial acquisition setup time of all modules, ensuring phase synchronization during intermediate frequency signal sampling and solving the phase jump problem.
[0040] Step 3: The host computer activates the measurement signal.
[0041] The principle is that the host computer acts as the control center of the system, sending a measurement start command to trigger the main module to enter the measurement preparation process. It is the total trigger signal for the entire multi-module synchronous measurement process, which clarifies the system's working start sequence.
[0042] Step 4: After the measurement signal is turned on, the MVN2053 master module sends a synchronization request to each MVN2053 slave module.
[0043] The principle is that this is the starting point of the measurement process synchronization. The master module actively initiates a synchronization request through the FPGA to notify all slave modules to enter the measurement preparation state, ensuring that the start-up sequence of the measurement actions of the master and slave modules is aligned, and avoiding amplitude fluctuations caused by independent module startup.
[0044] Step 5: After receiving the synchronization request from the slave module, the MVN2053 sends synchronization ready signals sequentially from the last slave module forward. All modules simultaneously start measurement triggering and generate fixed frequency signals when the synchronization request ends.
[0045] The principle is to adopt a step-by-step feedback mechanism, feeding back the ready signal from the last slave module to the front, which can ensure that no module is missed and the master module can accurately confirm that all slave modules have completed preparation; all modules synchronously start measurement triggering at the end of the synchronization request, generate fixed frequency signal, realize that the timing of fixed frequency signal transmission of master and slave modules is completely consistent, and ensure the synchronous output of source signal.
[0046] Step 6: When the MVN2053 master module determines that data can be retrieved, it sends a data retrieval request to each MVN2053 slave module.
[0047] The principle is that after the main module detects that the intermediate frequency signal is stable and meets the ADC sampling conditions, it initiates a data acquisition request and notifies the slave module to enter the data acquisition preparation state. This is the trigger signal of the data acquisition link in the measurement process synchronization, which ensures the coordinated start of the data acquisition action.
[0048] Step 7: After receiving the data retrieval request from the slave module, the MVN2053 sends the data retrieval ready signal sequentially from the last slave module forward. All modules retrieve the data simultaneously when the data retrieval request ends and transmit it to the host computer for use.
[0049] The principle is to continue the step-by-step feedback mechanism to confirm that all slave modules have completed data acquisition preparation; all modules synchronously execute ADC data acquisition operation at the end of the data acquisition request to ensure that the timing of data acquisition by master and slave modules is consistent, avoid amplitude deviation caused by data acquisition time difference, and upload the acquired and processed digital signal to the host computer for scattering parameter calculation and analysis.
[0050] Step 8: Stop the measurement according to user requirements. The principle is that the user sends a stop command through the host computer, the main module triggers all slave modules to synchronously stop signal transmission and data acquisition, and ends the measurement process, ensuring the consistency of system start-up and shutdown, while also allowing the user to flexibly control the measurement duration according to test requirements.
[0051] The core contribution of the technical solution involved in this embodiment compared with the prior art is that it proposes a multi-module triple synchronization mechanism for a PXI vector network analyzer based on FPGA units. By transmitting the system clock from the master module to the slave module, synchronously initiating measurement and data acquisition requests and performing feedback interaction, the ADC clock phase-locked synchronization reference of the master and slave modules is unified. This effectively solves the problems of amplitude instability and phase jump caused by different clock frequencies and asynchronous measurement and data acquisition when traditional multi-module cascaded modules are used. Moreover, it eliminates the need for customized dedicated multi-port equipment, greatly reducing costs and improving measurement flexibility. At the same time, it ensures the stability of phase and amplitude of multi-port measurements and ensures the accuracy of scattering parameter measurement.
[0052] In some embodiments, both the master module and the slave module are MVN2053A PXI vector network analyzer modules, with a measurement frequency range of 100kHz to 53GHz.
[0053] In some embodiments, both the master module and the slave module are 2-port devices.
[0054] In some embodiments, the number of master modules is m, the number of slave modules is n, and the master modules and all slave modules are cascaded to form a vector network analysis system with 2m+2n ports, realizing multi-port parallel measurement, where m≥1 and n≥1.
[0055] In some embodiments, the vector network analysis system formed by cascading the main module and all slave modules can support parallel measurements of up to 64 ports.
[0056] In some embodiments, when there are multiple slave modules, the master module sends synchronization request instructions to all slave modules in sequence; after the last slave module receives the synchronization request instruction, all slave modules, starting from the last slave module, send feedback to the master module level by level to indicate receipt of the instruction, until all slave modules have completed the feedback.
[0057] In some embodiments, when there are multiple slave modules, the master module sends data retrieval request instructions to all slave modules in sequence; after the last slave module receives the data retrieval request instruction, all slave modules send request termination instructions to the master module level by level, starting from the last slave module, until all slave modules have completed the feedback.
[0058] In some embodiments, after measurement is initiated, the main module sends a data retrieval request instruction when preset conditions are met, including: After the main module starts measurement, it transmits a continuous wave at the command frequency as the source signal, and at the same time generates a fixed-frequency local oscillator signal that differs from the source signal by one intermediate frequency, and transmits it to all slave modules. After the source signal is transmitted through the external device under test, it is mixed with the local oscillator signal in the main module or the corresponding slave module to form an intermediate frequency signal. The intermediate frequency signal is acquired by the ADC and processed by the DDC before being uploaded to the host computer. The ADC sampling ready information sent by the host computer is sent to the main module as the preset condition.
[0059] In some embodiments, the path through which the source signal is transmitted via the external device under test includes a reflection path and a direct path. The signal from the reflection path returns to the receiving end of the main module, while the signal from the direct path is transmitted to the receiving end of the corresponding main module or slave module.
[0060] In some embodiments, the phase-locked synchronization of the ADC clock by the master module and all slave modules includes ADC data acquisition clock synchronization and ADC initial acquisition setup time synchronization.
[0061] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computing software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0062] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0063] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A multi-module synchronization system for a PXI vector network analyzer based on FPGA, characterized in that, It includes a master module and at least one slave module, and each is equipped with an FPGA control unit; the FPGA control unit transmits the system clock of the master module to all slave modules through a cascading line, serving as the system clock for all slave modules; Before starting the measurement, the main module sends a synchronization request instruction through the FPGA control unit. When the slave module receives the synchronization request instruction, it returns a received instruction. After receiving the received instructions from all slave modules, the main module ends the synchronization request and starts the measurement. After measurement is started, the main module sends a data acquisition request instruction through the FPGA control unit when the preset conditions are met. The instruction is transmitted to the slave module through the cascade line. When the slave module receives the data acquisition request instruction, it returns a request to end instruction. After receiving the request to end instructions from all slave modules, the main module ends the data acquisition request and simultaneously starts the data acquisition operation of the main module and the slave module. The ADC clock of the master module is phase-locked synchronized with its own system clock as the reference clock, and the ADC clocks of all slave modules are phase-locked synchronized with the system clock transmitted by the master module as the reference clock.
2. The multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 1, characterized in that, Both the master module and the slave module are MVN2053A PXI vector network analyzer modules, with a measurement frequency range of 100kHz to 53GHz.
3. The multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 2, characterized in that, Both the master module and the slave module are 2-port devices.
4. The multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 3, characterized in that, The number of master modules is m, and the number of slave modules is n. The master modules and all slave modules are cascaded to form a vector network analysis system with 2m+2n ports, realizing multi-port parallel measurement, where m≥1 and n≥1.
5. A multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 4, characterized in that, The vector network analysis system formed by cascading the main module and all slave modules supports parallel measurements of up to 64 ports.
6. The multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 1, characterized in that, When there are multiple slave modules, the master module sends synchronization request instructions to all slave modules in sequence; after the last slave module receives the synchronization request instruction, all slave modules, starting from the last slave module, send feedback to the master module in turn until all slave modules have completed the feedback.
7. A multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 1, characterized in that, When there are multiple slave modules, the master module sends data retrieval request instructions to all slave modules in sequence; after the last slave module receives the data retrieval request instruction, all slave modules send request termination instructions to the master module level by level, starting from the last slave module, until all slave modules have completed the feedback.
8. A multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 1, characterized in that, After measurement is initiated, the main module sends a data retrieval request instruction when preset conditions are met, including: After the main module starts the measurement, it transmits a continuous wave of a specified frequency as the source signal, and at the same time generates a fixed-frequency local oscillator signal that differs from the source signal by one intermediate frequency, and transmits it to all slave modules. After the source signal is transmitted through the external device under test, it is mixed with the local oscillator signal in the main module or the corresponding slave module to form an intermediate frequency signal. The intermediate frequency signal is acquired by the ADC and processed by the DDC before being uploaded to the host computer. The ADC sampling ready information sent by the host computer is sent to the main module as the preset condition.
9. A multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 8, characterized in that, The source signal is transmitted through an external device under test via a path that includes a reflection path and a direct path. The signal from the reflection path returns to the receiving end of the main module, while the signal from the direct path is transmitted to the receiving end of the corresponding main module or slave module.
10. A multi-module synchronization system for a PXI vector network analyzer based on FPGA according to claim 1, characterized in that, The phase-locked synchronization of the ADC clock for the main module and all slave modules includes ADC data acquisition clock synchronization and ADC initial acquisition setup time synchronization.