Method, apparatus, device, medium and product for flow control based on storage array

Abstract

The application provides a storage array-based traffic control method, device, equipment, medium and product. The method comprises: obtaining target characteristic data of a target path, the target path comprising a path between a host and a storage array and / or a path between a takeover storage array and a heterogeneous storage array; predicting, by using a preset delay prediction model, a transmission delay of the target path in a future target time period according to the target characteristic data of the target path, and outputting a target delay time, so as to predict the transmission delay time of the target path in the future target time period, and determine a target input / output parameter of the target path in the future target time period based on the target delay time, so that the system can pre-configure the target input / output parameter to adapt to an upcoming load change according to the target delay time, effectively avoiding performance fluctuations and service interruptions caused by remediation after input / output congestion occurs, and reducing the average input / output delay of the system.

Description

Technical Field

[0001] This application relates to the field of data processing, and more particularly to a flow control method, apparatus, device, medium, and product based on a storage array. Background Technology

[0002] With the deepening of enterprise digital transformation, the amount of data in enterprise-level data centers is growing exponentially. Heterogeneous storage integration technology has become one of the core technologies for data infrastructure construction and is widely used in key industries such as finance, telecommunications, and government to achieve unified management and resource sharing of storage devices from different manufacturers and of different models.

[0003] In existing technologies, input and output flow control typically employs a static threshold triggering mechanism, which pre-configures fixed input and output parameters and performance alarm thresholds. When the system detects that the actual performance indicators exceed the thresholds, it passively triggers input and output flow limiting operations.

[0004] However, the above methods cannot adapt to dynamic changes in load, resulting in a low success rate of data transmission. Summary of the Invention

[0005] This application provides a flow control method, apparatus, device, medium, and product based on a storage array to solve the technical problem of low data transmission success rate due to the inability to adapt to dynamic load changes.

[0006] In a first aspect, this application provides a flow control method based on a storage array, comprising:

[0007] Obtain target feature data of the target path; the target path includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array;

[0008] A preset delay prediction model is used to predict the delay of the target path based on the target path's feature data, and the target delay time is output; the target delay time is the transmission delay time of the target path within a future target time period;

[0009] Based on the target delay time, the target input and output parameters of the target path within the future target time period are determined.

[0010] In this application, by acquiring target feature data of the target path, which includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array, a preset latency prediction model is used to predict the transmission latency of the target path within a future target time period based on the target feature data of the target path, and outputs the target latency time. This enables the prediction of the transmission latency time of the target path within the future target time period, and determines the target input and output parameters of the target path within the future target time period based on the target latency time. This allows the system to pre-configure the target input and output parameters according to the target latency time to adapt to upcoming load changes, effectively avoiding performance fluctuations and service interruptions caused by remediation after input and output congestion occurs, significantly reducing the average input and output latency of the system, improving the overall throughput and stability of the storage system, and enhancing the initiative and foresight of traffic control. It can simultaneously adapt to multiple storage architectures such as local direct connection paths and heterogeneous relay paths.

[0011] Optionally, in the method described above, the target path includes a first preset path and a second preset path; the first preset path is the path between the host and the takeover storage array; the second preset path is the path between the takeover storage array and the heterogeneous storage array.

[0012] The acquisition of target feature data for the target path includes:

[0013] Acquire first original feature data of the first preset path within a first preset time period and second original feature data of the second preset path within the first preset time period; the original feature data includes target load data.

[0014] The first original feature data and the second original feature data are scaled using a preset scaling algorithm to obtain scaled first original feature data and scaled second original feature data.

[0015] Feature extraction is performed on the scaled first original feature data and the scaled second original feature data respectively to obtain the target feature data of the target path; the target feature data includes the first target feature data and the second target feature data.

[0016] In this application, by scaling and extracting features from the original feature data of the first and second preset paths respectively, the unified standardization of data with different dimensions is achieved, eliminating the interference of data distribution differences between heterogeneous devices on the preset delay prediction model.

[0017] Optionally, in the method described above, the step of employing a preset delay prediction model and predicting the delay of the target path based on the target feature data of the target path, and outputting the target delay time, includes:

[0018] The first target feature data of the first preset path is input into the preset delay prediction model, and the preset delay prediction model is used to predict the delay of the first preset path and output the first delay time.

[0019] The second target feature data of the second preset path is input into the preset delay prediction model, and the preset delay prediction model is used to predict the delay of the second preset path and output the second delay time.

[0020] In this application, by subdividing the target path into a first preset path and a second preset path, and inputting them into a preset delay prediction model for independent delay prediction, the performance status of each preset path can be obtained, and precise control of each preset path can be achieved.

[0021] Optionally, in the method described above, the target path is the first preset path; the target input / output parameters include data block size, concurrent queue depth, and transmission time interval;

[0022] The step of determining the target input / output parameters of the target path within the future target time period based on the target delay time includes:

[0023] In response to the first delay time being less than the first preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to the first preset value, the concurrent queue depth is set to the first preset depth, and the sending time interval is set to the first preset interval.

[0024] In response to the first delay time being greater than or equal to a first preset threshold and less than a second preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to a second preset value, the concurrent queue depth is set to a second preset depth, and the sending time interval is set to a second preset interval.

[0025] In response to the first delay time being greater than or equal to the second preset threshold and less than the third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to the third preset value, the concurrent queue depth is set to the third preset depth, and the sending time interval is set to the third preset interval.

[0026] In response to the first delay time being greater than or equal to a third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to a fourth preset value, the concurrent queue depth is set to a fourth preset depth, and the sending time interval is set to a fourth preset interval; the first preset value is greater than a second preset value, the second preset value is greater than the third preset value; the third preset value is greater than the fourth preset value; the first preset depth is greater than the second preset depth, the second preset depth is greater than the third preset depth, and the third preset depth is greater than the fourth preset depth; the first preset interval is less than the second preset interval; the second preset interval is less than the third preset interval; and the third preset interval is less than the fourth preset interval.

[0027] In this application, a multi-level threshold determination mechanism is established based on the predicted first delay time to dynamically adjust the data block size, concurrent queue depth and sending interval of the front-end path (the path between the host and the takeover storage array), which can effectively prevent host service lag caused by front-end congestion and significantly improve the user experience.

[0028] Optionally, in the method described above, the target path is the first preset path and the second preset path;

[0029] The step of determining the target input / output parameters of the target path within the future target time period based on the target delay time includes:

[0030] In response to the first delay time being greater than or equal to the third preset threshold, the data block size in the target input / output parameters corresponding to the second preset path is set to the fourth preset value, the concurrent queue depth is set to the fourth preset depth, and the sending time interval is set to the fourth preset interval.

[0031] In response to the first delay time being less than the third preset threshold and the second delay time being less than or equal to the first delay time, the target input / output parameters corresponding to the second preset path are set to be the same as the target input / output parameters corresponding to the first preset path.

[0032] In response to the first delay time being less than the third preset threshold and the second delay time being greater than the first delay time, the target input and output parameters of the second preset path within the future target time period are determined based on the second delay time.

[0033] In this application, the target input / output parameters of the second preset path are adjusted by combining a first delay time and a second delay time. When the host-side link is congested, if the backend (the takeover storage array and the heterogeneous storage array) continues to write data to the heterogeneous array at a high speed, the buffer of the takeover array will quickly fill up, thus preventing new data from being written. When the first delay time is detected to be greater than or equal to a third preset threshold, the target input / output parameters of the second preset path are adjusted to prevent buffer overflow within the takeover storage array and reduce the probability of data transmission failure.

[0034] Optionally, the method described above further includes:

[0035] Obtain the current delay time; the current delay time is the real-time delay time obtained at any moment within the future target time period;

[0036] The difference between the current delay time and the target delay time is calculated to obtain the target delay difference;

[0037] If the target delay difference is greater than a preset difference threshold, the step of using a preset delay prediction model to predict the delay of the target path based on the target feature data of the target path and outputting the target delay time is re-executed.

[0038] In this application, a closed-loop feedback calibration mechanism is constructed by acquiring the current delay time in real time and calculating the difference between the current delay time and the predicted target delay time. Once the target delay difference exceeds the preset difference threshold, the current preset delay prediction model or the current environmental assumption is determined to be invalid, and the system immediately triggers re-prediction. This ensures that the flow control strategy is always based on the latest and most accurate environmental prediction results, avoiding incorrect parameter tuning caused by model aging or sudden environmental changes, thereby ensuring the high reliability and robustness of the system under long-term operation.

[0039] Secondly, this application provides a flow control device based on a storage array, comprising:

[0040] The acquisition module is used to acquire target feature data of the target path; the target path includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array.

[0041] The prediction module is used to predict the delay of the target path using a preset delay prediction model and based on the target feature data of the target path, and output the target delay time; the target delay time is the transmission delay time of the target path that will be delayed in a future target time period;

[0042] The determination module is used to determine the target input and output parameters of the target path within the future target time period based on the target delay time.

[0043] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0044] The memory stores computer-executed instructions;

[0045] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0046] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0047] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0048] The flow control method, apparatus, device, medium, and product based on storage arrays provided in this application acquire target characteristic data of the target path, which includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array. By using a preset latency prediction model to predict the transmission latency of the target path within a future target time period based on the target characteristic data, the system outputs the target latency time. This achieves the prediction of the transmission latency time of the target path within the future target time period and determines the target input / output parameters of the target path within the future target time period based on the target latency time. This allows the system to pre-configure the target input / output parameters according to the target latency time to adapt to upcoming load changes, effectively avoiding performance fluctuations and service interruptions caused by remediation after input / output congestion occurs. It significantly reduces the average input / output latency of the system, improves the overall throughput and stability of the storage system, and enhances the initiative and foresight of flow control. It can simultaneously adapt to various storage architectures such as local direct-connect paths and heterogeneous relay paths. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0050] Figure 1 A schematic diagram illustrating an application scenario for the flow control method based on a storage array provided in this application;

[0051] Figure 2 A flowchart illustrating a flow control method based on a storage array provided in one embodiment of this application;

[0052] Figure 3 A flowchart illustrating a flow control method based on a storage array, provided in another embodiment of this application;

[0053] Figure 4 A schematic diagram of the structure of a flow control device based on a storage array provided in one embodiment of this application;

[0054] Figure 5 A schematic diagram of the structure of the electronic device provided in this application.

[0055] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0056] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0057] The technical solution of this application involves the collection, storage, use, processing, transmission, provision and disclosure of user personal information and data, which comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0058] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0059] In related technologies, with the deepening of enterprise digital transformation, the data volume of enterprise-level data centers is growing exponentially. Heterogeneous storage integration technology has become one of the core technologies for data infrastructure construction, widely used in key industries such as finance, telecommunications, and government to achieve unified management and resource sharing of storage devices from different manufacturers and of different models. In existing technologies, input / output flow control typically adopts a static threshold triggering mechanism, which pre-configures fixed input / output parameters and performance alarm thresholds. When the system detects that the actual performance indicators exceed the threshold, it passively triggers input / output flow limiting operations, resulting in low transmission success rates and low system resource utilization.

[0060] To address the aforementioned technical issues, this application proposes the following technical concept: By acquiring target feature data of the target path, which includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array, a preset latency prediction model is used to predict the transmission latency of the target path within a future target time period based on the target feature data of the target path, and the target latency time is output. This enables the prediction of the transmission latency time of the target path within a future target time period, and the determination of the target input and output parameters of the target path within the future target time period based on the target latency time. This allows the system to pre-configure the target input and output parameters according to the target latency time to adapt to upcoming load changes, effectively avoiding performance fluctuations and service interruptions caused by remediation after input and output congestion occurs. It significantly reduces the average input and output latency of the system, improves the overall throughput and stability of the storage system, and enhances the initiative and foresight of traffic control. It can simultaneously adapt to various storage architectures such as local direct connection paths and heterogeneous relay paths.

[0061] Figure 1 A schematic diagram illustrating the application scenario of the flow control method based on storage array provided in this application, such as... Figure 1As shown, the application scenario provided in this embodiment includes: host 10, takeover storage array 11, and heterogeneous storage array 12. The takeover storage array 11 includes a processor 110. A flow control method based on the storage array is applied to the takeover storage array 11. The host is a computing device that runs business applications and generates input / output (IO) requests, including but not limited to physical servers, virtual machines, containers, and cloud hosts. The takeover storage array refers to an intermediate storage device with storage virtualization capabilities deployed between host 10 and heterogeneous storage array 12. Heterogeneous storage array 12 refers to a third-party storage device that differs from the takeover storage array 11. The takeover storage array 11 uses storage virtualization technology to abstract all heterogeneous storage array resources into a unified logical storage pool. Host 10 only needs to establish a connection with the takeover storage array 11 to access all storage resources in the pool. The target path includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array. Host 10 can send input / output requests to the takeover storage array 11, and the takeover storage array 11 returns corresponding data based on the input / output requests. The takeover storage array 11 has a communication link with the host 10, and a communication link with the heterogeneous storage array 12. Therefore, the takeover storage array 11 acquires target feature data of the target path, uses a preset delay prediction model, and predicts the delay of the target path based on the target feature data, outputting the target delay time. The target delay time is the transmission delay time of the target path within a future target time period. Based on the target delay time, the target input and output parameters of the target path within the future target time period are determined, thereby adjusting the input and output parameters of the communication links between the takeover storage array 11 and the host 10, and between the takeover storage array 11 and the heterogeneous storage array 12.

[0062] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0063] Figure 2 A flowchart of a flow control method based on a storage array provided in one embodiment of this application is shown below. Figure 2 As shown, the execution subject of the storage array-based flow control method provided in this embodiment can be any form of electronic device. For example, this embodiment uses a computer device as the execution subject for illustration. The storage array-based flow control method provided in this embodiment includes the following steps:

[0064] S201, Obtain target feature data for the target path.

[0065] In this embodiment, the execution entity is the processor that takes over the storage array, or simply the processor.

[0066] The target path includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array.

[0067] In this context, a host refers to a computing device that initiates input / output read / write requests. A storage array refers to a hardware device consisting of multiple disk drives that provides centralized data storage services.

[0068] The target path can be either the data transfer path between the host and the takeover storage array, or the data transfer path between the host and the heterogeneous storage array. The data transfer path between the host and the heterogeneous storage array consists of the data transfer path between the host and the takeover storage array, and the data transfer path between the takeover storage array and the heterogeneous storage array.

[0069] Among them, target feature data refers to quantitative indicators that reflect the current operating status of the storage and transmission path and are related to the path transmission delay.

[0070] Optionally, the target feature data may include bandwidth utilization, congestion level, storage array controller load, cache hit rate, and packet size.

[0071] Bandwidth utilization rate refers to the ratio of the actual amount of data transmitted on a transmission path per unit time to the theoretical maximum transmission capacity of that path, expressed as a percentage, reflecting the degree of utilization of path bandwidth resources.

[0072] Congestion level refers to the degree of backlog of unprocessed I / O requests on the transmission path. It is quantified by the ratio of the average waiting time of the path queue to the baseline waiting time. The larger the value, the more severe the path congestion.

[0073] Among them, the storage array controller load refers to the weighted average of the CPU utilization and memory utilization of the storage array controller, which reflects the controller's capacity margin for handling I / O requests.

[0074] The cache hit rate refers to the proportion of IO requests that can directly read data from the storage array cache within a unit of time to the total number of IO requests, expressed as a percentage. The higher the cache hit rate, the faster the IO processing speed.

[0075] Here, refers to the size of the data block transmitted by a single IO request, in bytes. In this embodiment, the average size of all IO request data packets within a preset time period is used as the feature value.

[0076] Optionally, the preset time period can be pre-set, such as within the past 1 second, or it can be set manually.

[0077] Furthermore, in another possible implementation, the specific implementation steps of S201 include:

[0078] Acquire first original feature data of a first preset path within a first preset time period and second original feature data of a second preset path within the first preset time period; the original feature data includes target load data.

[0079] The first and second original feature data are scaled using a preset scaling algorithm to obtain scaled first and scaled second original feature data.

[0080] Feature extraction is performed on the scaled first original feature data and the scaled second original feature data respectively to obtain the target feature data of the target path; the target feature data includes the first target feature data and the second target feature data.

[0081] The target path includes a first preset path and a second preset path. The first preset path is the path between the host and the managed storage array. The second preset path is the path between the managed storage array and the heterogeneous storage array.

[0082] The first preset time period refers to the time range of the original data used to aggregate and generate a single target feature data sample.

[0083] For example, in this embodiment, the processor reads the number of bytes actually transmitted in the past 100ms corresponding to the target path, divides it by the maximum bandwidth of the interface, and obtains the bandwidth utilization rate within a preset time period. It reads the queue waiting time of all IO requests in the past 100ms from the IO queue management module and calculates the average value. This average value is divided by the baseline queue waiting time measured when the system is idle to obtain the congestion level within the preset time period. It reads the average CPU utilization and average memory utilization of the controller in the past 100ms from the system monitoring module, calculates a weighted average with weights of 0.6 and 0.4, and obtains the storage array controller load within the preset time period. It reads the number of cache-hit IOs and the total number of IOs in the past 100ms from the cache management module, calculates the ratio between the two, and obtains the cache hit rate within the preset time period. It reads the data block size of all IO requests in the past 100ms from the IO request parsing module, calculates the average value, and obtains the data packet size within the preset time period.

[0084] For example, in this embodiment, the processor continuously collects raw feature data of the first and second preset paths at a sampling frequency of 100ms. The raw feature data includes bandwidth utilization, congestion level, storage array controller load, cache hit rate, and packet size. Every minute, all raw feature data within a first preset time period before the current moment is extracted to obtain the first raw feature data and the second raw feature data. The Min-Max normalization algorithm is used to scale the first and second raw feature data, mapping all feature values ​​to the [0,1] interval to obtain the scaled first and second raw feature data. The arithmetic mean of each feature parameter in the scaled first and second raw feature data is calculated to obtain the first target feature data and the second target feature data.

[0085] Specifically, by scaling and extracting features from the original feature data of the first and second preset paths respectively, the unified standardization of data with different dimensions is achieved, eliminating the interference of data distribution differences between heterogeneous devices on the preset delay prediction model.

[0086] S202 uses a preset delay prediction model and predicts the delay of the target path based on the target feature data of the target path, and outputs the target delay time.

[0087] The preset delay prediction model is pre-trained.

[0088] The target delay time is the time during which the target path may be delayed within the target time period in the future.

[0089] Understandably, assuming the target time period can be 1 hour, the target delay time refers to the time that the target path may be delayed within the next 1 hour, starting from the time when the latest target feature data is obtained from the target path.

[0090] The target time period corresponds to the time period that the preset delay prediction model can predict.

[0091] The preset delay prediction model is a pre-trained long short-term memory network, and the first preset path and the second preset path share the same preset delay prediction model.

[0092] For example, the training process of the preset delay prediction model is as follows: A sample set, a preset model structure constraint policy, and an initial delay prediction model are obtained. The initial delay prediction model is an untrained LSTM network model. The sample set is divided into a training sample set, a validation sample set, and a test sample set. Data preprocessing operations, identical to those in the online inference process, are performed on all sample sets. The preprocessed training sample set and the preset model structure constraint policy are input into the initial delay prediction model for structure learning, enabling the initial delay prediction model to generate the target network structure, thus obtaining the structure-learned initial delay prediction model. Then, the target network structure and the preprocessed training sample set are input into the structure-learned initial delay prediction model for parameter learning, enabling the initial delay prediction model to generate target weight parameters, thus obtaining the parameter-learned initial delay prediction model. The initial latency prediction model after parameter learning is validated using a validation sample set. The preprocessed validation sample set is input into the initial latency prediction model for latency prediction. The predicted latency time and corresponding actual latency time for each validation sample are calculated. A latency prediction accuracy index is calculated based on the output results. Training ends when the latency prediction accuracy index meets a preset accuracy threshold, and the initial latency prediction model after parameter learning is determined as the preset latency prediction model. After model deployment, incremental training is performed daily during off-peak periods using newly added running data to update the model weight parameters.

[0093] Optionally, the preset model structure constraint strategy consists of predefined network structure rules or restrictions to guide the construction of the LSTM network topology, including but not limited to: a fixed input dimension of 5 (corresponding to five feature parameters: bandwidth utilization, congestion level, storage array controller load, cache hit rate, and packet size); a fixed output dimension of 1 (corresponding to average path latency); 1-2 LSTM layers; 32-128 hidden layer dimensions; and 1 fully connected layer. The preset model structure constraint strategy can be customized according to the computational resources and performance requirements of different storage systems.

[0094] Optionally, the preset accuracy threshold can be set independently.

[0095] In this embodiment, the preset accuracy threshold is the coefficient of determination R² ≥ 0.9.

[0096] The goal of structure learning is to determine the optimal network structure that can effectively extract I / O time-series features while meeting the computational resource constraints of the storage array, thus balancing prediction accuracy and inference speed.

[0097] The sample set includes normal operation samples and abnormal load samples. The sample collection frequency can be 100ms, and the collection period is no less than 14 days. Each sample is generated through a sliding time window with a length of 10 minutes and a step size of 1 minute. The input feature of the sample is the average of 5 IO parameters within the window, and the label of the sample is the average actual latency of the corresponding path in the next hour after the window ends.

[0098] Furthermore, in another possible implementation, the specific implementation steps of S202 include:

[0099] The first target feature data of the first preset path is input into the preset delay prediction model, and the delay prediction model is used to predict the delay of the first preset path and output the first delay time.

[0100] The second target feature data of the second preset path is input into the preset delay prediction model, and the delay prediction model is used to predict the delay of the second preset path and output the second delay time.

[0101] Optionally, the preset delay prediction model can be a Long Short-Term Memory Network.

[0102] Specifically, in this embodiment, the processor inputs the first target feature data of the first preset path into the preset delay prediction model, so that the preset delay prediction model predicts the future delay time of the first preset path, thereby obtaining the first delay time output by the preset delay prediction model.

[0103] Specifically, in this embodiment, the processor inputs the second target feature data of the second preset path into the preset delay prediction model, so that the preset delay prediction model predicts the future delay time of the second preset path, thereby obtaining the second delay time output by the preset delay prediction model.

[0104] It is understandable that the preset delay prediction model predicts the first preset path and the second preset path respectively.

[0105] In this embodiment, by subdividing the target path into a first preset path and a second preset path, and inputting them into a preset delay prediction model for independent delay prediction, the performance status of each preset path can be obtained, and precise control of each preset path can be achieved.

[0106] S203, determine the target input and output parameters of the target path within the future target time period based on the target delay time.

[0107] Among them, target input / output parameters refer to dynamically configurable parameters that can affect the performance of storage and transmission paths.

[0108] The target input / output parameters include at least one of the following: data block size, concurrent queue depth, and transmission time interval.

[0109] Here, block size refers to the size of the largest data unit processed by the storage system in a single I / O transfer. Concurrency queue depth refers to the maximum number of I / O requests that the storage system allows to queue for processing simultaneously. Send interval refers to the minimum time interval between two consecutive I / O requests.

[0110] It is understandable that when the target latency of the target path is high, the path load can be reduced and congestion avoided by decreasing the data block size, decreasing the concurrent queue depth, and / or increasing the sending interval. When the target latency of the target path is low, the path resource utilization can be improved and system performance can be enhanced by increasing the data block size, increasing the concurrent queue depth, and / or decreasing the sending interval.

[0111] Specifically, in this embodiment, the processor determines the target input and output parameters of the target path within a future target time period from a preset mapping table based on the range of the target delay time corresponding to the target path.

[0112] In this embodiment, by acquiring target feature data of the target path, which includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array, a preset latency prediction model is used to predict the transmission latency of the target path within a future target time period based on the target feature data of the target path, and outputs the target latency time. This enables the prediction of the transmission latency time of the target path within a future target time period, and the determination of the target input and output parameters of the target path within the future target time period based on the target latency time. This allows the system to pre-configure the target input and output parameters according to the target latency time to adapt to upcoming load changes, effectively avoiding performance fluctuations and service interruptions caused by remediation after input and output congestion occurs. It significantly reduces the average input and output latency of the system, improves the overall throughput and stability of the storage system, and enhances the initiative and foresight of traffic control. It can simultaneously adapt to various storage architectures such as local direct connection paths and heterogeneous relay paths.

[0113] Furthermore, in one possible implementation, the method provided in this application, which determines the target input and output parameters of the target path within a future target time period based on the target delay time, includes:

[0114] In response to the first delay time being less than the first preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to the first preset value, the concurrent queue depth is set to the first preset depth, and the sending time interval is set to the first preset interval.

[0115] In response to a first delay time being greater than or equal to a first preset threshold and less than a second preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to the second preset value, the concurrent queue depth is set to the second preset depth, and the sending time interval is set to the second preset interval.

[0116] In response to the first delay time being greater than or equal to the second preset threshold and less than the third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to the third preset value, the concurrent queue depth is set to the third preset depth, and the sending time interval is set to the third preset interval.

[0117] If the first delay time is greater than or equal to the third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to the fourth preset value, the concurrent queue depth is set to the fourth preset depth, and the sending time interval is set to the fourth preset interval.

[0118] In this embodiment, the target path is the first preset path.

[0119] The target input / output parameters include data block size, concurrent queue depth, and transmission time interval.

[0120] Among them, the first preset value is greater than the second preset value, the second preset value is greater than the third preset value, the third preset value is greater than the fourth preset value, the first preset depth is greater than the second preset depth, the second preset depth is greater than the third preset depth, the third preset depth is greater than the fourth preset depth, the first preset interval is less than the second preset interval, the second preset interval is less than the third preset interval, and the third preset interval is less than the fourth preset interval.

[0121] Optionally, the first preset threshold, the second preset threshold, and the third preset threshold are preset.

[0122] The first delay time is the predicted delay time corresponding to the first preset path.

[0123] For example, the first preset threshold can be 10ms. The second preset threshold can be 50ms. The third preset threshold is 100ms.

[0124] For example, in this embodiment, the processor compares the first delay time of the first preset path with the corresponding preset threshold. If the first delay time is less than the first preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to 1MB, the concurrent queue depth to 256, and the transmission time interval to 0ms. If the first delay time is greater than or equal to the first preset threshold and less than the second preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to 512KB, the concurrent queue depth to 128, and the transmission time interval to 5ms. If the first delay time is greater than or equal to the second preset threshold and less than the third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to 256KB, the concurrent queue depth to 64, and the transmission time interval to 10ms. If the first delay time is greater than or equal to the third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to 64KB, the concurrent queue depth to 14, and the transmission time interval to 20ms.

[0125] In this embodiment, a multi-level threshold determination mechanism is established based on the predicted first delay time. The data block size, concurrent queue depth and sending time interval of the front-end path (the path between the host and the takeover storage array) are dynamically adjusted, which can effectively prevent host service lag caused by front-end congestion and significantly improve the user experience.

[0126] Furthermore, in one possible implementation, the method provided in this application, which determines the target input and output parameters of the target path within a future target time period based on the target delay time, includes:

[0127] In response to the first delay time being greater than or equal to the third preset threshold, the data block size in the target input / output parameters corresponding to the second preset path is set to the fourth preset value, the concurrent queue depth is set to the fourth preset depth, and the sending time interval is set to the fourth preset interval.

[0128] In response to the first delay time being less than the third preset threshold and the second delay time being less than or equal to the first delay time, the target input and output parameters corresponding to the second preset path are set to be the same as the target input and output parameters corresponding to the first preset path.

[0129] In response to the first delay time being less than the third preset threshold and the second delay time being greater than the first delay time, the target input and output parameters of the second preset path in the future target time period are determined based on the second delay time.

[0130] In this embodiment, the target path is the first preset path and the second preset path.

[0131] It is understandable that the target path, which is the first preset path and the second preset path, refers to the path between the host and the heterogeneous storage array.

[0132] For example, in this embodiment, if the processor responds to the first delay time being greater than or equal to the third preset threshold, it sets the data block size in the target input / output parameters corresponding to the second preset path to 64KB, the concurrent queue depth to 14, and the sending time interval to 20ms.

[0133] It is understandable that the host does not communicate directly with the heterogeneous storage array, but rather through the takeover of the storage array. Therefore, the first preset path is the common entry point for all services. Whether it is the takeover of the storage array or the heterogeneous storage array, it is necessary to go through the first preset path.

[0134] Understandably, when the first latency is greater than or equal to the third preset threshold, it indicates that the link between the front end, i.e., the host, and the takeover storage array, has become severely congested. If the second preset path continues to use higher target input / output parameters, it will further compete for bandwidth and controller resources on the shared link, causing the latency of the first path to continue to spike. Therefore, the data block size in the target input / output parameters corresponding to the second preset path is set to the fourth preset value, the concurrent queue depth is set to the fourth preset depth, and the transmission interval is set to the fourth preset interval. This reduces the traffic from heterogeneous relays and prioritizes the allocation of limited shared resources to local direct-connect services.

[0135] Understandably, when the first delay time is less than the third preset threshold and the second delay time of the second preset path is less than or equal to the first delay time of the first preset path, it indicates that the performance of the second preset path is better than that of the first preset path, and the overall bottleneck of the system is the first preset path. In this case, even if the second preset path is configured with higher target input / output parameters, its performance will still be limited by the bottleneck of the first preset path and cannot be fully utilized; instead, it will increase scheduling complexity. Using the same parameters as the first preset path simplifies the IO scheduling logic, reduces system overhead, and ensures the performance consistency of the two business paths, avoiding problems such as excessively large differences in business experience.

[0136] Understandably, when the first latency is less than the third preset threshold and the latency of the second preset path is higher than that of the first preset path, it indicates that the second preset path is an independent bottleneck in the system, and its performance is not limited by the first preset path. In this case, continuing to use the same target input / output parameters as the first preset path would further degrade the performance of the second preset path. Configuring parameters specifically tailored to the latency of the second preset path allows for targeted optimization of its transmission efficiency, maximizing the throughput of heterogeneous relay services without affecting the performance of the first preset path.

[0137] Specifically, in this embodiment, determining the target input and output parameters of the second preset path within a future target time period based on the second delay time can be specifically achieved by comparing the second delay time with the judgment logic of the first delay time. If the second delay time meets the threshold range of the first delay time, the target input and output parameters of the corresponding range are adjusted.

[0138] Optionally, a corresponding threshold can be set according to the second delay time, and the corresponding target input and output parameters can be set according to the threshold that is met.

[0139] In this embodiment, the target input / output parameters of the second preset path are adjusted by combining the first delay time and the second delay time. When the host-side link is congested, if the backend (the takeover storage array and the heterogeneous storage array) continues to write data to the heterogeneous array at a high speed, the buffer of the takeover array will quickly fill up, thus preventing new data from being written. When the first delay time is detected to be greater than or equal to the third preset threshold, the target input / output parameters of the second preset path are adjusted to prevent the internal buffer of the takeover storage array from overflowing, thereby reducing the probability of data transmission failure.

[0140] Figure 3 A flowchart of a flow control method based on a storage array provided in another embodiment of this application is shown below. Figure 3 As shown. In one possible implementation, prior to S201, the flow control method based on a storage array provided in this embodiment further includes the following steps:

[0141] S301, Get the current delay time.

[0142] The current delay time is the real-time delay time obtained at any point within the future target time period.

[0143] The current delay time collection and calculation can be triggered according to the verification cycle. For example, after predicting the target delay time of the target path within the future target time period, the current delay time can be calculated according to the verification cycle within the future target time period.

[0144] Optionally, the verification period is preset and can be set independently according to requirements.

[0145] For example, in this embodiment, it is assumed that the target latency time for the first preset path is 10ms and the target latency time for the second preset path is 15ms within the next hour. The verification period is 20 minutes. After running for 20 minutes according to the target input / output parameters determined by the target latency time, the processor calculates the current latency time of the target path. The current latency time is the total latency of all IO requests in the past 20 minutes divided by the total number of IO requests.

[0146] S302, calculate the difference between the current delay time and the target delay time to obtain the target delay difference.

[0147] Specifically, in this embodiment, the processor calculates the difference between the current delay time and the target delay time to obtain the target delay difference.

[0148] S303, in response to the target delay difference being greater than the preset difference threshold, the step of using the preset delay prediction model and predicting the delay of the target path based on the target feature data of the target path, and outputting the target delay time is re-executed.

[0149] Optionally, the preset difference threshold is pre-set.

[0150] For example, in this embodiment, the preset difference threshold is 10ms. Assume that the target delay time for the first preset path is predicted to be 10ms and the target delay time for the second preset path is predicted to be 15ms within the next hour. The verification period is 20 minutes. After running for 20 minutes according to the target input / output parameters determined by the target delay time, the processor calculates the current delay time of the target path and determines that the current delay time of the first preset path is 30ms and the current delay time of the second preset path is 15ms. Therefore, the target delay difference for the first preset path is 20ms, and the target delay difference for the second preset path is 0ms. Since the target delay difference for the first preset path is greater than 10ms, the target delay time corresponding to the current target path is invalid. Therefore, the target feature data of the target path is re-acquired, and the target delay time of the target path is re-calculated using the preset delay prediction model.

[0151] Optionally, during online model operation, the system automatically records complete information for each prediction, including: prediction time, input target feature data, output target delay time, and corresponding prediction period. After the prediction period ends, the system automatically obtains the actual average delay time of the path within that period, uses it as a label value, and pairs it with the corresponding input target feature data to form an incremental training sample. All incremental samples are stored in a local incremental sample library, retaining data from the most recent 30 days. Incremental training can be timed. For all newly added samples in the incremental sample library, preprocessing operations identical to the initial training process are performed, including outlier handling, missing value handling, and Min-Max normalization, ensuring the distribution of incremental data is consistent with the initial training data. The currently used preset delay prediction model weights are loaded, and the model is fine-tuned using the preprocessed incremental samples as training data. The number of training epochs is set to 5-10, with parameter updates performed only on the last layer of the fully connected layers and the LSTM layer. Mini-batch training is used, with a batch size of 16. After fine-tuning, the new model is validated using the incremental samples from the most recent 7 days as a validation set. If the determination coefficient R² of the new model is not lower than that of the original model, the new model will be replaced by the currently running preset delayed prediction model; if the performance of the new model degrades, the new model will be discarded and the original model will continue to be used.

[0152] Optionally, the preset number of days is pre-set.

[0153] Optionally, the timer trigger can be set independently.

[0154] Optionally, parameters such as the learning rate, number of training rounds, and batch size for incremental training can be adjusted according to the computing resources of the storage array.

[0155] In this embodiment, a closed-loop feedback calibration mechanism is constructed by acquiring the current delay time in real time and calculating the difference between the current delay time and the predicted target delay time. Once the target delay difference exceeds the preset difference threshold, the current preset delay prediction model or the current environmental assumption is determined to be invalid, and the system immediately triggers re-prediction. This ensures that the flow control strategy is always based on the latest and most accurate environmental prediction results, avoiding incorrect parameter tuning caused by model aging or sudden environmental changes, thereby ensuring the high reliability and robustness of the system under long-term operation.

[0156] Figure 4 This is a schematic diagram of the structure of a flow control device based on a storage array provided in one embodiment of this application, as shown below. Figure 4 As shown, the storage array-based flow control device 40 provided in this embodiment includes an acquisition module 41, a prediction module 42, and a determination module 43.

[0157] Specifically, the acquisition module 41 is used to acquire target feature data of the target path; the target path includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array; the prediction module 42 is used to perform delay prediction on the target path using a preset delay prediction model and based on the target feature data of the target path, and output the target delay time; the target delay time is the transmission delay time of the target path in the future target time period; the determination module 43 is used to determine the target input and output parameters of the target path in the future target time period based on the target delay time.

[0158] Optionally, the target path includes a first preset path and a second preset path; the first preset path is the path between the host and the takeover storage array; the second preset path is the path between the takeover storage array and the heterogeneous storage array.

[0159] Accordingly, the acquisition module 41, when acquiring target feature data of the target path, is specifically used to acquire first original feature data of the first preset path within a first preset time period and second original feature data of the second preset path within the first preset time period; the original feature data includes target load data; the first original feature data and the second original feature data are scaled using a preset scaling algorithm to obtain scaled first original feature data and scaled second original feature data; feature extraction is performed on the scaled first original feature data and scaled second original feature data to obtain target feature data of the target path; the target feature data includes first target feature data and second target feature data.

[0160] Optionally, when the prediction module 42 uses a preset delay prediction model to predict the delay of the target path based on the target feature data of the target path and outputs the target delay time, it is specifically used to input the first target feature data of the first preset path into the preset delay prediction model, use the preset delay prediction model to predict the delay of the first preset path and output the first delay time; input the second target feature data of the second preset path into the preset delay prediction model, use the preset delay prediction model to predict the delay of the second preset path and output the second delay time.

[0161] Optionally, the target path is a first preset path. The target input / output parameters include the data block size, concurrent queue depth, and transmission time interval.

[0162] Accordingly, when determining the target input / output parameters of the target path within a future target time period based on the target delay time, the determining module 43 specifically sets the data block size, concurrent queue depth, and transmission time interval of the target input / output parameters corresponding to the first preset path to a first preset value, the concurrent queue depth to a first preset depth, and the transmission time interval to a first preset interval, in response to the first delay time being less than a first preset threshold; in response to the first delay time being greater than or equal to the first preset threshold and less than a second preset threshold, the data block size, concurrent queue depth, and transmission time interval of the target input / output parameters corresponding to the first preset path to a second preset value, the concurrent queue depth to a second preset depth, and the transmission time interval to a second preset interval; and in response to the first delay time being greater than or equal to the second preset threshold and less than a third preset threshold, the target input / output parameters of the first preset path are set to a first preset value, the concurrent queue depth to a second preset depth, and the transmission time interval to a second preset interval. The data block size in the input / output parameters is set to a third preset value, the concurrent queue depth is set to a third preset depth, and the sending time interval is set to a third preset interval. In response to a first delay time greater than or equal to a third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to a fourth preset value, the concurrent queue depth is set to a fourth preset depth, and the sending time interval is set to a fourth preset interval. The first preset value is greater than the second preset value, the second preset value is greater than the third preset value, the third preset value is greater than the fourth preset value, the first preset depth is greater than the second preset depth, the second preset depth is greater than the third preset depth, and the third preset depth is greater than the fourth preset interval. The first preset interval is less than the second preset interval, the second preset interval is less than the third preset interval, and the third preset interval is less than the fourth preset interval.

[0163] Optionally, the target path can be a first preset path or a second preset path.

[0164] Accordingly, when determining the target input / output parameters of the target path within a future target time period based on the target delay time, the determining module 43, in response to the first delay time being greater than or equal to the third preset threshold, sets the data block size in the target input / output parameters corresponding to the second preset path to the fourth preset value, the concurrent queue depth to the fourth preset depth, and the sending time interval to the fourth preset interval; in response to the first delay time being less than the third preset threshold and the second delay time being less than or equal to the first delay time, sets the target input / output parameters corresponding to the second preset path to the same as those corresponding to the first preset path; in response to the first delay time being less than the third preset threshold and the second delay time being greater than the first delay time, determines the target input / output parameters of the second preset path within a future target time period based on the second delay time.

[0165] Optionally, the storage array-based flow control device may also include a computing module and an execution module.

[0166] Accordingly, the acquisition module 41 is used to acquire the current delay time; the current delay time is the real-time delay time acquired at any moment within the future target time period. The calculation module is used to calculate the difference between the current delay time and the target delay time to obtain the target delay difference. The execution module is used to re-execute the step of using a preset delay prediction model and predicting the delay of the target path based on the target feature data of the target path, and outputting the target delay time, in response to the target delay difference being greater than a preset difference threshold.

[0167] The flow control device based on storage array provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0168] Figure 5 A schematic diagram of the structure of the electronic device provided in this application. Figure 5 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus.

[0169] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0170] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0171] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0172] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0173] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0174] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0175] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0176] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0177] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0178] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0179] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0180] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0181] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0182] When integrated units / modules are implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0183] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0184] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0185] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0186] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A flow control method based on a storage array, characterized in that, The method includes: Obtain target feature data of the target path; the target path includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array; A preset delay prediction model is used to predict the delay of the target path based on the target path's feature data, and the target delay time is output; the target delay time is the transmission delay time of the target path within a future target time period; Based on the target delay time, the target input and output parameters of the target path within the future target time period are determined.

2. The method according to claim 1, characterized in that, The target path includes a first preset path and a second preset path; the first preset path is the path between the host and the managed storage array. The second preset path is the path between the takeover storage array and the heterogeneous storage array; The acquisition of target feature data for the target path includes: Acquire first original feature data of the first preset path within a first preset time period and second original feature data of the second preset path within the first preset time period; the original feature data includes target load data. The first original feature data and the second original feature data are scaled using a preset scaling algorithm to obtain scaled first original feature data and scaled second original feature data. Feature extraction is performed on the scaled first original feature data and the scaled second original feature data respectively to obtain the target feature data of the target path; the target feature data includes the first target feature data and the second target feature data.

3. The method according to claim 2, characterized in that, The step of using a preset delay prediction model and predicting the delay of the target path based on the target feature data of the target path, and outputting the target delay time, includes: The first target feature data of the first preset path is input into the preset delay prediction model, and the preset delay prediction model is used to predict the delay of the first preset path and output the first delay time. The second target feature data of the second preset path is input into the preset delay prediction model, and the preset delay prediction model is used to predict the delay of the second preset path and output the second delay time.

4. The method according to claim 3, characterized in that, The target path is the first preset path; the target input / output parameters include data block size, concurrent queue depth, and sending time interval; The step of determining the target input / output parameters of the target path within the future target time period based on the target delay time includes: In response to the first delay time being less than the first preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to the first preset value, the concurrent queue depth is set to the first preset depth, and the sending time interval is set to the first preset interval. In response to the first delay time being greater than or equal to a first preset threshold and less than a second preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to a second preset value, the concurrent queue depth is set to a second preset depth, and the sending time interval is set to a second preset interval. In response to the first delay time being greater than or equal to the second preset threshold and less than the third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to the third preset value, the concurrent queue depth is set to the third preset depth, and the sending time interval is set to the third preset interval. In response to the first delay time being greater than or equal to a third preset threshold, the data block size in the target input / output parameters corresponding to the first preset path is set to a fourth preset value, the concurrent queue depth is set to a fourth preset depth, and the sending time interval is set to a fourth preset interval; the first preset value is greater than a second preset value, the second preset value is greater than the third preset value; the third preset value is greater than the fourth preset value; the first preset depth is greater than the second preset depth, the second preset depth is greater than the third preset depth, and the third preset depth is greater than the fourth preset depth; the first preset interval is less than the second preset interval; the second preset interval is less than the third preset interval; and the third preset interval is less than the fourth preset interval.

5. The method according to claim 3, characterized in that, The target path is the first preset path and the second preset path; The step of determining the target input / output parameters of the target path within the future target time period based on the target delay time includes: In response to the first delay time being greater than or equal to the third preset threshold, the data block size in the target input / output parameters corresponding to the second preset path is set to the fourth preset value, the concurrent queue depth is set to the fourth preset depth, and the sending time interval is set to the fourth preset interval. In response to the first delay time being less than the third preset threshold and the second delay time being less than or equal to the first delay time, the target input / output parameters corresponding to the second preset path are set to be the same as the target input / output parameters corresponding to the first preset path. In response to the first delay time being less than the third preset threshold and the second delay time being greater than the first delay time, the target input and output parameters of the second preset path within the future target time period are determined based on the second delay time.

6. The method according to claim 1, characterized in that, The method further includes: Obtain the current delay time; the current delay time is the real-time delay time obtained at any moment within the future target time period; The difference between the current delay time and the target delay time is calculated to obtain the target delay difference; If the target delay difference is greater than a preset difference threshold, the step of using a preset delay prediction model to predict the delay of the target path based on the target feature data of the target path and outputting the target delay time is re-executed.

7. A flow control device based on a storage array, characterized in that, include: The acquisition module is used to acquire target feature data of the target path; The target path includes the path between the host and the storage array and / or the path between the takeover storage array and the heterogeneous storage array; The prediction module is used to predict the delay of the target path using a preset delay prediction model and based on the target feature data of the target path, and output the target delay time; the target delay time is the transmission delay time of the target path that will be delayed in a future target time period; The determination module is used to determine the target input and output parameters of the target path within the future target time period based on the target delay time.

8. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-6.

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