An LDMOS device and a manufacturing method thereof

Abstract

The application provides an LDMOS device and a manufacturing method thereof. The LDMOS device comprises a substrate, a drift region of a first conductive type and a body region of a second conductive type in the substrate, a drain region of the first conductive type in the drift region, a source region of the first conductive type in the body region, the source region being spaced apart from the drift region, a gate structure on the substrate and covering part of surfaces of the drift region and the body region, the source region and the drain region being respectively on two sides of the gate structure, and the drain region being spaced apart from the gate structure, a self-aligned silicide blocking layer covering part of surfaces of the gate structure and part of surfaces of the drift region between the gate structure and the drain region, and a field plate at least partially arranged on the self-aligned silicide blocking layer between the gate structure and the drain region, wherein the field plate comprises an alloy compound layer. The application can reduce the difficulty of contact hole etching process and improve the switching speed of the LDMOS device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to an LDMOS device and a method for manufacturing the same. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are one of the core components of the BCD (Bipolar-CMOS-DMOS) process platform. They are compatible with both bipolar junction transistors (BJTs) and complementary metal-oxide-semiconductor (CMOS) processes, possessing high-voltage, high-current drive capabilities and extremely low power consumption in switching mode. LDMOS devices are widely used as high-voltage power devices in motor drives, automotive electronics, industrial control, switching power supplies, and other power integrated circuits. An LDMOS device consists of hundreds or thousands of single-structure LDMOS cells, and its area is determined by the required drive capability of the chip. For example, in a power management chip, LDMOS devices may occupy more than half of the chip area. Therefore, the performance of the LDMOS device directly determines the overall drive capability and area of ​​the chip.

[0003] The structural performance of LDMOS devices directly affects the performance of power integrated circuits. The main technical indicators of LDMOS devices include breakdown voltage (BV) and on-resistance. In related technologies, field plate technology is generally used to balance the good voltage withstand characteristics and low on-resistance of LDMOS devices. However, in the field plate manufacturing process of related technologies, large-size trench-shaped contact hole field plates are generally formed together with the contact holes. This brings great process challenges to the etching of contact holes. Furthermore, the metal filling capacity after contact hole etching limits the growth of the contact hole field plate size. Therefore, the ability to improve breakdown voltage is limited.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides an LDMOS device, comprising: Substrate; A drift region of the first conductivity type is located in the substrate; A body region of the second conductivity type is located in the substrate; The drain region of the first conductivity type is located in the drift region; A source region of a first conductivity type is located in the body region and is spaced apart from the drift region; A gate structure is located on the substrate and covers a portion of the surface of the drift region and the body region. The source region and the drain region are located on opposite sides of the gate structure, and the drain region and the gate structure are spaced apart. A self-aligned silicide barrier layer covers a portion of the surface of the gate structure and a portion of the surface of the drift region between the gate structure and the drain region; A field plate is disposed at least partially on the self-aligned silicide barrier layer between the gate structure and the drain region, wherein the field plate includes an alloy compound layer.

[0007] For example, the field plate also includes a contact hole plug located on a portion of the alloy compound layer.

[0008] For example, the number of contact hole plugs is one or more. When the number of contact hole plugs is more than one, the multiple contact hole plugs are arranged at intervals along the length direction of the gate structure. In the width direction of the gate structure, the size of the contact hole plug is smaller than the size of the alloy compound layer.

[0009] For example, the semiconductor device further includes: A metal silicide layer is located on the surface of the source region, the surface of the drain region, and the surface of the exposed gate structure, wherein the material of the metal silicide layer is different from that of the alloy compound layer.

[0010] For example, The alloy compound layer is made of Ni-B alloy compound, Co-B alloy compound, Ni-P alloy compound, or Co-P alloy compound.

[0011] For example, the semiconductor device further includes: A field oxide layer is located on a portion of the surface of the drift region and between the source region and the drain region. The gate structure extends from the side where the source region is located to cover a portion of the field oxide layer. The self-aligned silicide barrier layer extends from the side where the drain region is located to cover a portion of the field oxide layer and a portion of the gate structure. The first conductive plug is electrically connected to the gate structure; The second conductive plug is electrically connected to the source region; The third conductive plug is electrically connected to the drain area.

[0012] This application also provides a method for manufacturing an LDMOS device, the method comprising: A substrate is provided in which a drift region of a first conductivity type and a body region of a second conductivity type are formed; A gate structure, a source region of a first conductivity type, and a drain region of a first conductivity type are formed, wherein the gate structure is located on the substrate and covers a portion of the surface of the drift region and the body region, the source region is located in the body region and is spaced apart from the drift region, the drain region is located in the drift region and is spaced apart from the gate structure, and the source region and the drain region are respectively located on both sides of the gate structure; A self-aligned silicide barrier layer is formed, the self-aligned silicide barrier layer covering a portion of the surface of the gate structure and a portion of the surface of the drift region between the gate structure and the drain region; A field plate is formed on the self-aligned silicide barrier layer at least between the gate structure and the drain region, wherein the field plate is made of an alloy compound layer.

[0013] Exemplarily, the formation of the self-aligned silicide barrier layer includes: A self-aligned silicide barrier material layer is formed to cover the gate structure and the exposed substrate; The self-aligned silicide barrier layer is removed from the surface of the source region, the surface of the drain region, and a portion of the gate structure surface to form a self-aligned silicide barrier layer covering a portion of the surface of the gate structure and a portion of the surface of the drift region between the gate structure and the drain region.

[0014] Exemplarily, forming a field plate on the self-aligned silicide barrier layer at least between the gate structure and the drain region includes: Before or after removing the self-aligned silicide barrier layer from the source region surface, the drain region surface, and a portion of the gate structure surface, at least a portion of the self-aligned silicide barrier layer between the gate structure and the drain region is ion implanted to form a doped layer. A metal material layer is formed, which covers the self-aligned silicide barrier layer, the doped layer, the exposed surface of the gate structure, and the exposed substrate; Heat treatment is performed to diffuse the dopant elements in the doped layer into the metal material layer in contact with it, so as to form the alloy compound layer on the self-aligned silicide barrier layer at least between the gate structure and the drain region, while metal silicide layers are formed on the source region, the drain region and the exposed gate structure, wherein the material of the metal silicide layer is different from that of the alloy compound. Contact hole plugs are formed on a portion of the alloy compound layer, the alloy compound layer and the contact hole plugs constitute a field plate, wherein the number of contact hole plugs is one or more, when the number of contact hole plugs is more than one, the multiple contact hole plugs are arranged at intervals along the length direction of the gate structure, and in the width direction of the gate structure, the contact area between the contact hole plugs and the alloy compound layer, the size of the contact hole plugs is smaller than the size of the alloy compound layer.

[0015] Exemplarily, before forming the gate structure, the method further includes: forming a field oxide layer on the drift region, the field oxide layer covering a portion of the surface of the drift region and the field oxide layer being located between the source region and the drain region, the gate structure extending from the side where the source region is located to cover a portion of the field oxide layer, and the self-aligned silicide barrier layer extending from the side where the drain region is located to cover a portion of the field oxide layer and a portion of the gate structure; After forming the field plate, the process also includes: A first conductive plug, a second conductive plug, and a third conductive plug are formed, wherein the first conductive plug is electrically connected to the gate structure, the second conductive plug is electrically connected to the source region, and the third conductive plug is electrically connected to the drain region.

[0016] The LDMOS device and its manufacturing method according to the embodiments of this application form a field plate including an alloy compound layer on the self-aligned silicide barrier layer between the gate structure and the drain region. This can shorten the field plate size, eliminate the need for a large-sized contact hole field plate, reduce the difficulty of contact hole etching and metal filling, effectively improve the breakdown voltage, and at the same time, by eliminating the large-sized contact hole field plate, the parasitic gate-source capacitance of the LDMOS device can be reduced, thereby improving the switching speed of the LDMOS device. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0018] In the attached image: Figure 1A A cross-sectional schematic diagram of an LDMOS device related to this technology is shown; Figure 1B A planar schematic diagram of an LDMOS device related to the technology is shown. Figures 2A-2G This illustration shows a cross-sectional schematic diagram of an LDMOS device obtained by sequentially implementing a manufacturing method of an LDMOS device according to a specific embodiment of this application. Figure 2HA planar schematic diagram of an LDMOS device obtained by implementing a manufacturing method of an LDMOS device according to a specific embodiment of this application is shown. Figure 3 A flowchart illustrating a method for manufacturing an LDMOS device according to a specific embodiment of this application is shown. Detailed Implementation

[0019] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0021] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0025] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0026] In related technologies, field plate technology is generally used to balance the good voltage withstand characteristics and low on-resistance of LDMOS devices. For example, such as... Figure 1A and Figure 1BAs shown, an LDMOS device is formed by forming a field plate 103 on a self-aligned silicide block (SAB) layer 102 to form an SAB field plate and a conductive plug 104. The LDMOS device uses the SAB field plate to reduce the surface electric field intensity of the drift region 101 and optimize the electric field distribution, thereby increasing the breakdown voltage of the LDMOS device and reducing the on-resistance of the LDMOS device.

[0027] In the existing LDMOS field plate manufacturing process, the field plate trenches are generally formed together with the contact holes, which brings great process challenges to the etching of the contact holes. In addition, in order to achieve a good increase in the device breakdown voltage, the size of the field plate needs to be relatively large. However, the metal filling capacity after the contact hole etching limits the increase in the size of the field plate. Therefore, the method of improving the device breakdown voltage solely through the field plate is greatly limited by the existing process.

[0028] In addition, in order to ensure better withstand voltage performance, the field plate is generally shorted to the source terminal of the LDMOS device, which causes the gate-source parasitic capacitance of the LDMOS device to be too large, resulting in a decrease in the switching speed of the device. Furthermore, the field plate technology will increase the device pitch, which in turn leads to an increase in planar area and a decrease in integration density.

[0029] In view of the aforementioned technical problems, embodiments of this application provide an LDMOS device, comprising: Substrate; A drift region of the first conductivity type is located in the substrate; A body region of the second conductivity type is located in the substrate; The drain region of the first conductivity type is located in the drift region; A source region of a first conductivity type is located in the body region and is spaced apart from the drift region; A gate structure is located on the substrate and covers a portion of the surface of the drift region and the body region. The source region and the drain region are located on opposite sides of the gate structure, and the drain region and the gate structure are spaced apart. A self-aligned silicide barrier layer covers a portion of the surface of the gate structure and a portion of the surface of the drift region between the gate structure and the drain region; A field plate is disposed at least partially on the self-aligned silicide barrier layer between the gate structure and the drain region, wherein the field plate includes an alloy compound layer.

[0030] The LDMOS device and its manufacturing method according to the embodiments of this application form a field plate including an alloy compound layer on the self-aligned silicide barrier layer between the gate structure and the drain region. This can shorten the field plate size, eliminate the need for a large-sized contact hole field plate, reduce the difficulty of contact hole etching and metal filling, effectively improve the breakdown voltage, and at the same time, by eliminating the large-sized contact hole field plate, the parasitic gate-source capacitance of the LDMOS device can be reduced, thereby improving the switching speed of the LDMOS device.

[0031] Example 1 Below, for reference Figure 2G and 2H The LDMOS device of this application is described in detail. This LDMOS device can be manufactured using the manufacturing method described in Example 2 below.

[0032] like Figure 2G As shown, the LDMOS device of this application includes a substrate 200, a drift region 203 of a first conductivity type, a body region 204 of a second conductivity type, a source region (not shown) of a first conductivity type, a drain region (not shown) of a first conductivity type, a gate structure, an alignment silicide barrier layer 211, and a field plate 212, wherein: the drift region 203 and the body region are both located in the substrate 200, the source region is located in the body region and is spaced apart from the drift region, the drain region is located in the drift region 203, the gate structure is located on the substrate 200 and covers part of the surface of the drift region 203 and the body region 204, the source region and the drain region are respectively located on both sides of the gate structure, and the drain region... A self-aligned silicide barrier layer 211, spaced apart from the gate structure, covers a portion of the surface of the gate structure (including a portion of the gate electrode layer 209) and a portion of the surface of the drift region 203 between the gate structure and the drain region, covering areas where metal silicide formation is not required. A field plate 212 is at least partially disposed on the self-aligned silicide barrier layer 211 between the gate structure and the drain region, forming an SAB field plate structure with the self-aligned silicide barrier layer 211. This optimizes the electric field distribution of the drift region 203, improves the device's breakdown voltage, and reduces the device's on-resistance. The field plate includes an alloy compound layer 205. By forming a small and thin field plate including the alloy compound layer 205 on the self-aligned silicide barrier layer 211, the difficulty of subsequent contact hole etching and metal filling processes can be reduced. Furthermore, the parasitic gate-source capacitance of the LDMOS device can be reduced, improving the device's switching speed. Simultaneously, the absence of physical size limitations associated with contact hole field plates provides space for further miniaturization of the device.

[0033] In one example, such as Figure 2G and Figure 2HAs shown, the field plate also includes contact hole plugs 207 located on the alloy compound layer. The number of contact hole plugs can be one or more. When there are multiple contact hole plugs, the multiple contact hole plugs 207 are arranged at intervals along the length direction of the gate structure. The line connecting the source region and the drain region is also the width direction of the gate structure, while the length direction is perpendicular to this width direction. Exemplarily, the material of the alloy compound layer includes Ni-B alloy compound or other suitable alloy compounds; this application does not limit this.

[0034] In one example, the thickness of the alloy compound layer 205 is less than the thickness of the self-aligned silicide barrier layer 211. The function of the self-aligned silicide barrier layer 211 is to prevent the metal from contacting the underlying silicon. Therefore, the thickness of the self-aligned silicide barrier layer needs to be greater than the thickness of the metal silicide. Otherwise, the metal may penetrate the self-aligned silicide barrier layer 211 and react in areas where the metal silicide layer should not be formed, leading to device short circuits or performance failure.

[0035] In one example, a metal silicide layer 206 is formed on the source region, drain region, and the surface of the exposed gate structure. The metal silicide layer 206 is used to form an ohmic contact, i.e., a non-rectified, low-resistance conductive connection. The metal silicide layer 206 and the alloy compound layer 205 can be formed simultaneously, and the materials of the metal silicide layer 206 and the alloy compound layer 205 are different, but they can have the same elements. For example, both the metal silicide layer and the alloy compound layer contain Ni metal. Specifically, the material of the metal silicide layer includes, but is not limited to, Ni-Si compounds, and the material of the alloy compound layer includes, but is not limited to, Ni-B alloy compounds.

[0036] In one example, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type. The following explanation will use N-type for the first conductivity type and P-type for the second conductivity type.

[0037] In one example, substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors; or substrate 200 may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form substrate 200 have been described herein, any material that can serve as substrate 200 falls within the spirit and scope of this application.

[0038] In one example, such as Figure 2G As shown, the gate structure includes a gate electrode layer 209 and sidewall layers 210 located on both sides of the gate electrode layer 209. The gate electrode layer 209 can be made of semiconductor materials commonly used in the art. Specifically, the gate electrode layer 209 can be made of polycrystalline silicon or amorphous silicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds can also be used as the material of the gate electrode layer 209. Exemplarily, the sidewall layer 210 can be a single-layer film or a composite film structure composed of an oxide layer and / or a nitride layer. For example, the sidewall layer 210 can be a single-layer silicon oxide film, or a double-layer film structure composed of a single-layer silicon oxide film and a single-layer silicon nitride film, or a triple-layer film structure composed of a double-layer silicon oxide film and a single-layer silicon nitride film. Exemplarily, the gate structure may also include a gate dielectric layer (not shown) located between the gate electrode layer 209 and the surface of the substrate 200. The gate dielectric layer serves as an isolation layer, and the material of the gate dielectric layer includes, but is not limited to, silicon oxide.

[0039] In one example, the source and drain regions are located on opposite sides of the gate structure along a first direction, and the sidewall layer 210 is also located on opposite sides of the gate electrode layer 209 along the first direction. Figures 2A-2G This is a cross-sectional view along a first direction, which is perpendicular to the thickness direction of the substrate 200.

[0040] In one example, the drift region 203, source region, and drain region are N-type conductivity types, and the body region 204 is P-type conductivity type. The majority carriers in the drift region 203, source region, and drain region are free electrons, and the majority carriers in the body region 204 are holes. The body region 204 isolates the source region from the drift region. Taking LDMOS as an enhancement-mode MOS as an example, when the voltage applied to the gate electrode layer 209 is less than the threshold voltage, the LDMOS device is in the off state; when the voltage applied to the gate electrode layer 209 is higher than the threshold voltage, a redistribution of charge carriers occurs in the body region 204 near the gate electrode layer 209. Free electrons in the body region 204 are attracted to the area below the gate electrode layer 209 to form an N-type inversion layer (N-type channel). This N-type inversion layer is called the conductive channel between the source and drain regions. At this time, when a positive voltage is applied between the drain and source regions (the drain region is electrically connected to the positive terminal of the power supply, and the source region is electrically connected to the negative terminal of the power supply), electrons can move from the source region to the drift region 203 through the N-type inversion layer, and then move to the drain region, turning on the LDMOS device.

[0041] In one example, such as Figure 2G As shown, the substrate 200 includes a base layer 2001 and an epitaxial layer 2002 located on the base layer 2001. The drift region 203 and the body region 204 are both located in the epitaxial layer 2002, and the gate structure is located on the epitaxial layer 2002.

[0042] In one example, the LDMOS device of this application further includes a body lead-out region (not shown) of a second conductivity type located in the body region 204, wherein the doping concentration of the body lead-out region is greater than the doping concentration of the body region 204 to reduce contact resistance. Exemplarily, the body lead-out region is in contact with the source region.

[0043] In one example, such as Figure 2G As shown, the LDMOS device of this application further includes a first conductive plug 213, a second conductive plug 214, and a third conductive plug 215. The first conductive plug 213 is electrically connected to the gate structure. More specifically, the first conductive plug 213 is electrically connected to the gate electrode layer 209 and is used to lead out the gate structure. The second conductive plug 214 is electrically connected to the source region and the body lead-out region and is used to lead out the source region and prevent the potential of the body region 204 from floating. The third conductive plug 215 is electrically connected to the drain region and is used to lead out the drain region.

[0044] In one example, such as Figure 2G As shown, the LDMOS device of this application further includes a field oxide layer 208, which is located on a portion of the surface of the drift region 203 and between the source and drain regions. A gate structure extends from the side where the source region is located to cover a portion of the field oxide layer 208. A self-aligned silicide barrier layer 211 extends from the side where the drain region is located to cover a portion of the field oxide layer 208 and a portion of the gate structure. More specifically, a gate electrode layer 209 covers a portion of the surface of the field oxide layer 208 near the source region. Taking polysilicon as an example, the portion of the gate electrode layer 209 on the field oxide layer 208 can together with the field oxide layer 208 to form a polysilicon field plate structure. This polysilicon field plate structure can further optimize the electric field distribution of the drift region 203, thereby further improving the breakdown voltage of the LDMOS device. Exemplarily, a gate dielectric layer is formed between the portion of the gate electrode layer 209 not on the field oxide layer 208 and the substrate 200.

[0045] This concludes the introduction to the structure of the LDMOS device according to the embodiments of this application. A complete LDMOS device may also include other constituent structures, which will not be described in detail here.

[0046] In summary, the LDMOS device of this application embodiment forms a field plate including an alloy compound layer on the self-aligned silicide barrier layer between the gate structure and the drain region. This can shorten the field plate size, eliminate the need for a large-sized contact hole field plate, reduce the difficulty of contact hole etching and metal filling, effectively improve the breakdown voltage, and at the same time, eliminate the large-sized contact hole field plate, which can reduce the parasitic gate-source capacitance of the LDMOS device, thereby improving the switching speed of the LDMOS device.

[0047] Example 2 This application also provides a method for manufacturing an LDMOS device, which is used to manufacture the LDMOS device in the aforementioned embodiment one. Below, refer to... Figures 2A-2H as well as Figure 3 The manufacturing method of the LDMOS device of this application is described in detail.

[0048] For example, the method for manufacturing an LDMOS device according to an embodiment of this application includes the following steps: First, execute step S1, as follows: Figure 2A As shown, a substrate 200 is provided, in which a drift region 203 of a first conductivity type and a body region 204 of a second conductivity type are formed. Exemplarily, the drift region 203 and the body region 204 can be formed in the substrate 200 using an ion implantation process.

[0049] In one example, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type. The following explanation will use N-type for the first conductivity type and P-type for the second conductivity type.

[0050] In one example, substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors; or substrate 200 may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form substrate 200 have been described herein, any material that can serve as substrate 200 falls within the spirit and scope of this application.

[0051] In one example, such as Figure 2A As shown, the substrate 200 includes a base layer 2001 and an epitaxial layer 2002 located on the base layer 2001. The drift region 203 and the body region 204 are both located in the epitaxial layer 2002.

[0052] Next, proceed to step S2, as follows: Figure 2A As shown, a gate structure, a source region of a first conductivity type, and a drain region of a first conductivity type are formed. The gate structure is located on the substrate 200 and covers a portion of the surface of the drift region 203 and the body region 204. The source region is located in the body region 204 and spaced apart from the drift region 203. The drain region is located in the drift region 203 and spaced apart from the gate structure. The source region and drain region are located on opposite sides of the gate structure. Exemplarily, the gate structure is located on the epitaxial layer 2002. Exemplarily, an ion implantation process can be used to form the source region and drain region.

[0053] In one example, such as Figure 2A As shown, the gate structure includes a gate electrode layer 209 and sidewall layers 210 located on both sides of the gate electrode layer 209. The gate electrode layer 209 can be made of semiconductor materials commonly used in the art. Specifically, the gate electrode layer 209 can be made of polycrystalline silicon or amorphous silicon. In other embodiments, metals, metal nitrides, metal silicides, or similar compounds can also be used as the material of the gate electrode layer 209. Exemplarily, the sidewall layer 210 can be a single-layer film or a composite film structure composed of an oxide layer and / or a nitride layer. For example, the sidewall layer 210 can be a single-layer silicon oxide film, or a double-layer film structure composed of a single-layer silicon oxide film and a single-layer silicon nitride film, or a triple-layer film structure composed of a double-layer silicon oxide film and a single-layer silicon nitride film. Exemplarily, the gate structure may also include a gate dielectric layer (not shown) located between the gate electrode layer 209 and the surface of the substrate 200. The gate dielectric layer serves as an isolation layer, and the material of the gate dielectric layer includes, but is not limited to, silicon oxide. For example, the gate electrode layer 209, the sidewall layer 210 and the gate dielectric layer can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0054] In one example, the source and drain regions are located on opposite sides of the gate structure along a first direction, and the sidewall layer 210 is also located on opposite sides of the gate electrode layer 209 along the first direction. Figures 2A-2G This is a cross-sectional view along a first direction, which is perpendicular to the thickness direction of the substrate 200.

[0055] In one example, the drift region 203, source region, and drain region are of N-type conductivity, and the body region 204 is of P-type conductivity. The majority carriers in the drift region 203, source region, and drain region are free electrons, while the majority carriers in the body region 204 are holes. The body region 204 isolates the source region from the drift region 203. Taking LDMOS as an enhancement-mode MOS as an example, when the voltage applied to the gate electrode layer 209 is less than the threshold voltage, the LDMOS device is in the off state; when the voltage applied to the gate electrode layer 209 is higher than the threshold voltage, a redistribution of charge carriers occurs in the body region 204 near the gate electrode layer 209. Free electrons in the body region 204 are attracted to the area below the gate electrode layer 209 to form an N-type inversion layer (N-type channel). This N-type inversion layer is called the conductive channel between the source and drain regions. At this time, when a positive voltage is applied between the drain and source regions (the drain region is electrically connected to the positive terminal of the power supply, and the source region is electrically connected to the negative terminal of the power supply), electrons can move from the source region to the drift region 203 through the N-type inversion layer, and then move to the drain region, turning on the LDMOS device.

[0056] In one example, such as Figure 2AAs shown, before forming the gate structure, the process further includes forming a field oxide layer 208 on the drift region 203. The field oxide layer 208 covers a portion of the surface of the drift region 203 and is located between the source and drain regions. The gate structure extends from the side where the source region is located to cover a portion of the field oxide layer 208. A subsequently formed self-aligned silicide barrier layer 211 extends from the side where the drain region is located to cover a portion of the field oxide layer 208 and a portion of the gate structure. Exemplarily, a local oxidation of silicon (ROS) process can be used to form the field oxide layer 208.

[0057] Specifically, the gate electrode layer 209 covers a portion of the surface of the field oxide layer 208 near the source region. Taking polysilicon as an example, the portion of the gate electrode layer 209 on the field oxide layer 208 can together with the field oxide layer 208 to form a polysilicon field plate structure. The electric field distribution of the drift region 203 can be further optimized through the polysilicon field plate structure. Exemplarily, a gate dielectric layer is formed between the portion of the gate electrode layer 209 not on the field oxide layer 208 and the substrate 200.

[0058] In one example, after forming the gate structure, the method further includes forming a body lead-out region of a second conductivity type, the body lead-out region being located in body region 204.

[0059] In one example, an ion implantation process can be used to form a body lead-out region in body region 204. The doping concentration of the body lead-out region is greater than that of body region 204 to reduce contact resistance. Exemplarily, the body lead-out region is in contact with the source region.

[0060] Next, step S3 is performed to form a self-aligned silicide barrier layer, which covers a portion of the surface of the gate structure and a portion of the surface of the drift region between the gate structure and the drain region.

[0061] For example, such as Figure 2B As shown, a self-aligned silicide barrier material layer 2111 is formed to cover the gate structure and the exposed substrate 200. For example, the self-aligned silicide barrier material layer 2111 is deposited on the gate structure and the exposed substrate using a plasma-enhanced chemical vapor deposition (PECVD) process. The material of the self-aligned silicide barrier material layer may include, but is not limited to, silicon oxide.

[0062] Next, as Figure 2CAs shown, at least the self-aligned silicide barrier layer 2111 between the gate structure and the drain region is ion implanted to form a doped layer 217. Specifically, a patterned mask layer 216 is formed on the self-aligned silicide barrier layer 2111, defining the area for ion implantation. Then, ion implantation is performed on the exposed self-aligned silicide layer 2111, for example, implanting B or P elements into the exposed self-aligned silicide layer 2111 to form the doped layer 217. This ion implantation can be low-energy ion implantation; therefore, the patterned mask layer can be a thinner photoresist layer, which is beneficial for further reducing the critical dimensions of the subsequently formed field plate. Next, the patterned mask layer is removed.

[0063] In another embodiment, after the self-aligned silicide barrier material layer on the source region surface, drain region surface and part of the gate structure surface is subsequently removed, at least part of the self-aligned silicide barrier material layer between the gate structure and the drain region is ion implanted to form a doped layer 217. The specific formation process is similar to that described above and will not be repeated here.

[0064] Next, as Figure 2D As shown, the self-aligned silicide barrier layer 2111 is etched to remove the self-aligned silicide barrier layer 2011 on the source region surface, drain region surface, and part of the gate structure, thereby forming a self-aligned silicide barrier layer 211 covering part of the gate structure surface and part of the drift region 203 between the gate structure and the drain region. The doped layer 217 is located on the self-aligned silicide barrier layer 211.

[0065] Next, step S4 is performed to form a field plate on the self-aligned silicide barrier layer at least between the gate structure and the drain region, wherein the field plate includes an alloy compound layer.

[0066] For example, such as Figure 2E As shown, a metal material layer 218 is formed on the self-aligned silicide barrier layer, the surface of the exposed gate structure, and the exposed substrate. The material of the metal material layer may include Ni, Co, or other suitable metals.

[0067] Next, as Figure 2F As shown, heat treatment is performed to diffuse the dopant elements in the doped layer 217 into the metal material layer in contact with it, so as to form an alloy compound layer 205 at least on the self-aligned silicide barrier layer between the gate structure and the drain region. At the same time, the metal elements in the metal material layer react with the Si elements in the source region, drain region and exposed gate structure to form a metal silicide layer 206 on the source region, drain region and exposed gate structure. The alloy compound layer 205 is used to form a field plate.

[0068] Specifically, taking a metal layer made of Ni and doped with boron as an example, a first rapid annealing process is performed. Ni reacts with silicon in the uncovered areas of the self-aligned silicide barrier layer 211 and on the silicide layer to form a metal silicide layer. Simultaneously, boron on the surface of the self-aligned silicide barrier layer 211 begins to precipitate and diffuse into the Ni metal, forming a Ni-B alloy. Next, selective wet etching removes the unreacted Ni metal, leaving only an alloy compound layer composed of Ni-B compounds and a metal silicide layer composed of Ni-Si compounds. A second rapid annealing process is then performed, resulting in a stable, low-resistance phase in the metal silicide layer. The metal silicide layer formed in the uncovered areas of the self-aligned silicide barrier layer 211 is used to form an ohmic contact, while the alloy compound layer on the self-aligned silicide barrier layer 211 is used to form a field plate, i.e., a metal field plate. If the metal layer is made of Co, the resulting alloy compound layer is a Co-B compound.

[0069] In some examples, the dopant element is P, and the alloy compound layer can be a Ni-P compound or a Co-P compound.

[0070] Next, as Figure 2G As shown, a contact hole plug 207 is formed on a portion of the alloy compound layer 205. The contact hole plug 207 is electrically connected to the alloy compound layer 205, and the alloy compound layer 205 and the contact hole plug 207 constitute a field plate. A first conductive plug 213, a second conductive plug 214, and a third conductive plug 215 are formed. The first conductive plug 213 is electrically connected to the gate structure, the second conductive plug 214 is electrically connected to the source region and the body lead-out region, and the third conductive plug 215 is electrically connected to the drain region. It is worth mentioning that the contact hole plug and the first conductive plug, the second conductive plug, and the third conductive plug can be formed simultaneously or separately, and this application does not impose any restrictions on this.

[0071] like Figure 2H As shown, the number of contact hole plugs 207 is one or more. When the number of contact hole plugs 207 is more than one, the multiple contact hole plugs 207 are arranged at intervals along the length direction of the gate structure. In the width direction of the gate structure, the contact hole plugs 207 are in contact with the alloy compound layer 205. The size of the contact hole plugs 207 is smaller than the size of the alloy compound layer 205.

[0072] In one example, taking the gate electrode layer 209 as a polycrystalline silicon material, the portion of the gate electrode layer 209 located on the field oxide layer 208 can form a polycrystalline silicon field plate structure together with the field oxide layer 208. The electric field distribution of the drift region 203 can be further optimized through the polycrystalline silicon field plate structure.

[0073] In one example, the first conductive plug 213 is electrically connected to the gate electrode layer 209 for leading out the gate structure, the second conductive plug 214 is used to lead out the source region and prevent the body region 204 from floating, and the third conductive plug 215 is used to lead out the drain region.

[0074] This concludes the description of the key steps in the manufacturing method of the LDMOS device of this application. The manufacturing of a complete LDMOS device may include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0075] In summary, the method for manufacturing an LDMOS device according to the embodiments of this application forms a field plate including a metal silicide layer on a self-aligned silicide barrier layer between the gate structure and the drain region, thereby eliminating the need for a large-size contact hole field plate, removing the large parasitic capacitance caused by the contact hole field plate, and thus improving the switching speed and high-frequency application of the LDMOS device.

[0076] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. An LDMOS device, characterized in that, include: Substrate; A drift region of the first conductivity type is located in the substrate; A body region of the second conductivity type is located in the substrate; The drain region of the first conductivity type is located in the drift region; A source region of a first conductivity type is located in the body region and is spaced apart from the drift region; A gate structure is located on the substrate and covers a portion of the surface of the drift region and the body region. The source region and the drain region are located on opposite sides of the gate structure, and the drain region and the gate structure are spaced apart. A self-aligned silicide barrier layer covers a portion of the surface of the gate structure and a portion of the surface of the drift region between the gate structure and the drain region; A field plate is disposed at least partially on the self-aligned silicide barrier layer between the gate structure and the drain region, wherein the field plate includes an alloy compound layer.

2. The LDMOS device as described in claim 1, characterized in that, The field plate also includes contact hole plugs located on a portion of the alloy compound layer.

3. The LDMOS device as described in claim 1, characterized in that, The number of contact hole plugs is one or more. When the number of contact hole plugs is more than one, the multiple contact hole plugs are arranged at intervals along the length direction of the gate structure. In the width direction of the gate structure, the size of the contact hole plug is smaller than the size of the alloy compound layer.

4. The LDMOS device as described in claim 1, characterized in that, Also includes: A metal silicide layer is located on the surface of the source region, the surface of the drain region, and the surface of the exposed gate structure, wherein the material of the metal silicide layer is different from the material of the alloy compound layer.

5. The LDMOS device as described in claim 1, characterized in that, The alloy compound layer is made of Ni-B alloy compound, Co-B alloy compound, Ni-P alloy compound, or Co-P alloy compound.

6. The LDMOS device as described in claim 1, characterized in that, Also includes: A field oxide layer is located on a portion of the surface of the drift region and between the source region and the drain region. The gate structure extends from the side where the source region is located to cover a portion of the field oxide layer. The self-aligned silicide barrier layer extends from the side where the drain region is located to cover a portion of the field oxide layer and a portion of the gate structure. The first conductive plug is electrically connected to the gate structure; The second conductive plug is electrically connected to the source region; The third conductive plug is electrically connected to the drain area.

7. A method for manufacturing an LDMOS device, characterized in that, The manufacturing method includes: A substrate is provided in which a drift region of a first conductivity type and a body region of a second conductivity type are formed; A gate structure, a source region of a first conductivity type, and a drain region of a first conductivity type are formed, wherein the gate structure is located on the substrate and covers a portion of the surface of the drift region and the body region, the source region is located in the body region and is spaced apart from the drift region, the drain region is located in the drift region and is spaced apart from the gate structure, and the source region and the drain region are respectively located on both sides of the gate structure; A self-aligned silicide barrier layer is formed, the self-aligned silicide barrier layer covering a portion of the surface of the gate structure and a portion of the surface of the drift region between the gate structure and the drain region; A field plate is formed on the self-aligned silicide barrier layer at least between the gate structure and the drain region, wherein the field plate is made of an alloy compound layer.

8. The manufacturing method as described in claim 7, characterized in that, The formation of the self-aligned silicide barrier layer includes: A self-aligned silicide barrier material layer is formed to cover the gate structure and the exposed substrate; The self-aligned silicide barrier layer is removed from the surface of the source region, the surface of the drain region, and a portion of the gate structure surface to form a self-aligned silicide barrier layer covering a portion of the surface of the gate structure and a portion of the surface of the drift region between the gate structure and the drain region.

9. The manufacturing method as described in claim 8, characterized in that, The formation of a field plate on the self-aligned silicide barrier layer at least between the gate structure and the drain region includes: Before or after removing the self-aligned silicide barrier layer from the source region surface, the drain region surface, and a portion of the gate structure surface, at least a portion of the self-aligned silicide barrier layer between the gate structure and the drain region is ion implanted to form a doped layer. A metal material layer is formed, which covers the self-aligned silicide barrier layer, the doped layer, the exposed surface of the gate structure, and the exposed substrate; Heat treatment is performed to diffuse the dopant elements in the doped layer into the metal material layer in contact with it, so as to form the alloy compound layer on the self-aligned silicide barrier layer at least between the gate structure and the drain region, while metal silicide layers are formed on the source region, the drain region and the exposed gate structure, wherein the material of the metal silicide layer is different from that of the alloy compound. Contact hole plugs are formed on a portion of the alloy compound layer, the alloy compound layer and the contact hole plugs constitute a field plate, wherein the number of contact hole plugs is one or more, when the number of contact hole plugs is more than one, the multiple contact hole plugs are arranged at intervals along the length direction of the gate structure, and in the width direction of the gate structure, the contact area between the contact hole plugs and the alloy compound layer, the size of the contact hole plugs is smaller than the size of the alloy compound layer.

10. The manufacturing method as described in claim 7, characterized in that, Before forming the gate structure, the method further includes: forming a field oxide layer on the drift region, the field oxide layer covering a portion of the surface of the drift region and the field oxide layer being located between the source region and the drain region, the gate structure extending from the side where the source region is located to cover a portion of the field oxide layer, and the self-aligned silicide barrier layer extending from the side where the drain region is located to cover a portion of the field oxide layer and a portion of the gate structure; After forming the field plate, the process also includes: A first conductive plug, a second conductive plug, and a third conductive plug are formed, wherein the first conductive plug is electrically connected to the gate structure, the second conductive plug is electrically connected to the source region, and the third conductive plug is electrically connected to the drain region.

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