Perovskite and crystalline silicon cell laminated structure

Abstract

The utility model discloses a perovskite and crystalline silicon cell laminated structure, which comprises a bottom cell and a top cell which are laminated, the bottom cell is a crystalline silicon cell, the top cell is a perovskite cell, the crystalline silicon cell comprises a crystalline silicon substrate, a tunneling oxide layer and a doping layer, and the tunneling oxide layer and the doping layer are sequentially arranged upwards from the crystalline silicon substrate. The front surface of the tunneling oxide layer is divided into a first region and a second region, and the doping layer correspondingly covers the first region; the laminated structure further comprises a transparent conductive film layer. According to the utility model, on one hand, through regional distribution of the doping layer, a field passivation effect can be achieved, recombination is reduced, unnecessary parasitic absorption is reduced, and optical loss is effectively reduced; and on the other hand, the transparent conductive film layer is arranged, so that the crystalline silicon cell is compatible with the perovskite cell, the thickness of the doping layer can be remarkably reduced, the preparation cost of the cell is effectively reduced, in addition, efficient combined utilization of solar spectrum and superposition of open-circuit voltage are realized, and the photoelectric conversion efficiency is greatly improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of solar cells, and particularly relates to a perovskite and crystalline silicon cell stacked structure. Background Art

[0002] At present, high-efficiency and low-cost solar cells are the key devices for photovoltaic power generation. This field has become the focus of attention in the academic and industrial circles. TOPCon cells are the single-crystalline cells with the most promising development prospects and relatively high market share at present. However, their compatibility is poor and the improvement of the photoelectric conversion efficiency has reached a bottleneck. The perovskite / single-crystalline stacked solar cell is one of the technical directions most promising to further improve the photoelectric conversion efficiency of single-crystalline silicon cells. Among them, crystalline silicon cells mainly absorb visible light, while perovskite cells have better absorption characteristics for visible light and near-infrared light. The stacked design of single-crystalline cells and perovskite cells can effectively utilize solar energy in a wider spectral range to improve the photoelectric conversion efficiency.

[0003] The efficiency of TOPCon cells has gradually approached the limit of 28.7% at present, and it is difficult to improve the photoelectric conversion efficiency. In conventional TOPCon cells on the market, the doping layer covers the front and back of the silicon wafer and forms an antireflection layer composed of a passivation layer. Therefore, it has the following technical defects:

[0004] 1. Generally, the thickness formed by the doping layer of TOPCon cells is about 120 - 130 nm, which not only increases the thickness of the cell wafer, causes unnecessary parasitic absorption, but also results in waste of resources in the redundant doping layer, and further increases the preparation cost of the cell wafer.

[0005] 2. The antireflection layer composed of the passivation layer only plays an antireflection role and does not consider its compatibility, that is, it cannot be compatible with perovskite cells and cannot realize the stacking of the two types of cells. Summary of the Utility Model

[0006] The technical problem to be solved by the utility model is to overcome the deficiencies of the prior art and provide an improved perovskite and crystalline silicon cell stacked structure.

[0007] To solve the above technical problem, the technical solution adopted by the utility model is as follows:

[0008] A perovskite and crystalline silicon cell stacked structure, which includes a bottom cell and a top cell stacked on top of each other. The bottom cell is a crystalline silicon cell, and the top cell is a perovskite cell. The crystalline silicon cell includes a crystalline silicon substrate, a tunneling oxide layer and a doping layer sequentially arranged upward from the crystalline silicon substrate. The front surface of the tunneling oxide layer is divided into a first region and a second region, and the doping layer correspondingly covers the first region. The stacked structure further includes a transparent conductive thin film layer disposed between the crystalline silicon cell and the perovskite cell. The transparent conductive thin film layer is stacked and covers the doping layer and the second region, and the perovskite cell is stacked on the front surface of the transparent conductive thin film layer. It should be particularly noted that the transparent conductive thin film layer has good carrier mobility and transmittance. Its lateral conductivity can not only reduce the thickness of the doping layer of the crystalline silicon cell to a certain extent to reduce costs, but also be compatible with the perovskite cell.

[0009] According to a specific implementation and preferred aspect of the present invention, there are multiple doping layers, and the multiple doping layers are arranged in a cross or spaced manner on the front surface of the tunneling oxide layer.

[0010] Preferably, the doping layer is strip-shaped, and multiple doping layers are parallel and arranged side by side at intervals on the front surface of the tunneling oxide layer; and / or, the cross-section of each doping layer is rectangular. Here, the multiple doping layers are evenly distributed, which is convenient for preparation.

[0011] Preferably, the thickness of the doping layer is 15 - 30 nm; and / or, the doping layer is a poly-si layer. Here, through the layout of the thickness of the doping layer, the passivation effect and reduction of optical loss formed by the doping layer can reach the best.

[0012] According to another specific implementation and preferred aspect of the present invention, the thickness of the part of the transparent conductive thin film layer covering the doping layer is equal to the thickness of the part of the transparent conductive thin film layer covering the second region. Here, a deposition method is used to prepare the transparent conductive thin film layer to accurately control the uniform distribution of the transparent conductive thin film layer.

[0013] Preferably, the thickness of the transparent conductive thin film layer is 65 - 85 nm. Under this layout, the best conductivity is achieved.

[0014] Preferably, the material of the transparent conductive thin film layer is indium tin oxide, fluorine-doped tin oxide, aluminum-doped tin oxide or antimony-doped tin oxide. Here,

[0015] According to another specific implementation and preferred aspect of the present invention, the crystalline silicon cell further includes a p-type emitter, a passivation layer, a passivation layer antireflection layer and a back electrode sequentially arranged downward from the crystalline silicon substrate.

[0016] According to another specific implementation and preferred aspect of the present invention, the tunneling oxide layer is a SiO 2 layer; and / or, the passivation layer is an Al 2 O3 layer; and / or, the passivation layer antireflection layer is SiN X / SiO 2 layer.

[0017] According to another specific implementation and preferred aspect of the present utility model, the perovskite battery includes a hole transport layer, a perovskite layer, an electron transport layer, and a front electrode sequentially arranged upward from the front side of the transparent conductive thin film layer, wherein the back side of the hole transport layer is embedded and arranged with the front side of the transparent conductive thin film layer, and the front side of the hole transport layer is flat.

[0018] Due to the implementation of the above technical solutions, the present utility model has the following advantages compared with the prior art:

[0019] The thickness formed by the doping layer of the existing TOPCon battery is generally about 120 - 130 nm, which not only increases the thickness of the battery chip, causing unnecessary parasitic absorption, but also causes waste of resources in the redundant doping layer, thereby increasing the manufacturing cost of the battery chip. At the same time, the passivation layer constitutes the antireflection layer, which only plays an antireflection role and does not consider its compatibility, that is, it cannot be compatible with the perovskite battery and cannot achieve lamination; while the present application conducts an overall design on the lamination structure of the perovskite and crystalline silicon battery, skillfully solving the deficiencies and defects of the prior art. After adopting this lamination structure, first, a doping layer is selectively and regionally prepared in a part of the area on the front side of the tunneling oxide layer in the crystalline silicon battery, then a transparent conductive thin film layer is added in another part of the area on the front side of the doping layer and the tunneling oxide layer, and finally the perovskite battery layer is laminated on the front side of the transparent conductive thin film layer to form the lamination structure of the perovskite and crystalline silicon battery. Therefore, compared with the prior art, on the one hand, through the regional distribution of the doping layer, the present utility model can play a field passivation role, achieve reduced recombination, reduce unnecessary parasitic absorption, and effectively reduce optical loss; on the other hand, by setting the transparent conductive thin film layer, while realizing the compatibility between the crystalline silicon battery and the perovskite battery, it can also significantly reduce the thickness of the doping layer, effectively reduce the preparation cost of the battery. In addition, it realizes the efficient combined utilization of the solar spectrum and the superposition of the open circuit voltage, greatly improving the photoelectric conversion efficiency. Description of the Drawings

[0020] Figure 1 It is a schematic structural diagram of the lamination structure of the perovskite and crystalline silicon battery in this embodiment;

[0021] Figure 2 It is a schematic structural diagram of the lamination structure of the perovskite and crystalline silicon battery in this comparative example;

[0022] Wherein: 01, crystalline silicon substrate; 02, p-type emitter; 03, passivation layer; 04, passivation layer antireflection layer; 05, tunneling oxide layer; 06, transparent conductive thin film layer; 07, hole transport layer; 08, perovskite layer; 09, electron transport layer; 10, electrode; 11, doping layer. Detailed implementation manners

[0023] To make the above objects, features and advantages of the present utility model more obvious and understandable, the present utility model will be described in detail below in conjunction with the accompanying drawings and specific implementation manners. Many specific details are set forth in the following description in order to fully understand the present utility model. However, the present utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed below.

[0024] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present utility model.

[0025] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present utility model, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0026] In the present utility model, unless otherwise clearly specified and defined, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0027] In a utility model, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply indicates that the horizontal height of the first feature is less than that of the second feature.

[0028] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are only for the purpose of illustration and do not represent the only implementation.

[0029] Embodiment

[0030] Please refer to Figure 1 , a perovskite and crystalline silicon cell stacked structure provided by this embodiment includes a bottom cell and a top cell stacked, the bottom cell is a crystalline silicon cell, and the top cell is a perovskite cell.

[0031] Specifically, the crystalline silicon cell includes an n-type crystalline silicon substrate 01; a p-type emitter 02, a passivation layer 03, a passivation layer antireflection layer 04 and an electrode 10 sequentially arranged downward from the crystalline silicon substrate 01; a tunneling oxide layer 05 and a doping layer 11 sequentially arranged upward from the crystalline silicon substrate 01.

[0032] In some specific embodiments, the passivation layer 03 is an Al 2 O 3 layer and is prepared by an ALD device; the passivation layer antireflection layer 04 is a SiN X / SiO 2 layer and is prepared by PECVD; the tunneling oxide layer 05 is a SiO 2 layer and is prepared by a thermal oxidation furnace; the doping layer 11 is a poly-si layer and is prepared by PECVD or LPCVD, and the preparation thickness of the doping layer 11 is 15 - 30 nm.

[0033] For the convenience of implementation, the front of the tunnel oxide layer 05 is divided into a first area and a second area, and the doping layer 11 covers the first area accordingly. Therefore, when preparing the doping layer 11, quartz needs to be used to cover the second area; there are multiple doping layers 11, and the doping layers 11 are in strip shape, and the cross section of each doping layer 11 is rectangular. In some specific embodiments, multiple doping layers 11 are parallel and laid side by side on the front of the tunnel oxide layer 05; in other specific embodiments, multiple doping layers 11 can also be laid on the front of the tunnel oxide layer 05 in a cross shape, for example, multiple doping layers 11 form a grid.

[0034] In this example, the stacked structure further includes a transparent conductive film layer 06 disposed between the crystalline silicon cell and the perovskite cell, wherein the transparent conductive film layer 06 is stacked and covers the doped layer 11 and the second region. It should be particularly noted that the transparent conductive film layer has good carrier mobility and transmittance, and its lateral conductive performance can not only reduce the thickness of the doped layer of the crystalline silicon cell to a certain extent to reduce the cost, but also be compatible with the perovskite cell.

[0035] Specifically, the transparent conductive film layer 06 is prepared by a PVD magnetron sputtering device, and the thickness of the portion of the transparent conductive film layer 06 covering the doped layer 11 is equal to the thickness of the portion of the transparent conductive film layer 06 covering the second region; the thickness of the transparent conductive film layer 06 is 65-85nm; the material of the transparent conductive film layer 06 is indium tin oxide, fluorine-doped tin oxide, aluminum-doped tin oxide or antimony-doped tin oxide.

[0036] In addition, the perovskite battery of this embodiment includes a hole transport layer 07, a perovskite layer 08, an electron transport layer 09 and an electrode 10 which are stacked in sequence from the transparent conductive film layer 06 upward, wherein the back side of the hole transport layer 07 is embedded in the transparent conductive film layer 06, and the front side of the hole transport layer 07 is a plane; in some specific embodiments, the hole transport layer 07 is prepared by solution spin coating, the perovskite layer 08 is prepared by vapor deposition or coating, the electron transport layer 09 is prepared by solution spin coating, and the electrode 10 is prepared by vacuum evaporation.

[0037] Comparative Example

[0038] See also Figure 2 The structure and preparation process of the top cell perovskite and bottom cell crystalline silicon cell stacked structure provided in this comparative example are basically the same as those in the embodiment, except that the doping layer 11 of this comparative example completely covers the top of the tunneling oxide layer 05 and has a thickness of 120-130nm.

[0039] Performance Test: Two groups of the batteries prepared in the above-mentioned examples and comparative examples were taken respectively, and the following electrical performance verification tests were carried out. The test method was as follows: Use an IV tester to test the photoelectric conversion efficiency and related electrical performance parameters of the batteries under standard illumination power under a simulated solar light source. The specific test results are shown in Table 1 (Eta: photoelectric conversion efficiency; Voc: open-circuit voltage; Jsc: short-circuit current; FF: fill factor).

[0040] Table 1

[0041] Group Eta Voc Jsc FF Example 1 29.25 1.77 20.20 81.03 Example 2 29.44 1.76 20.38 81.08 Comparative Example 1 28.93 1.75 20.12 81.01 Comparative Example 2 28.81 1.75 20.08 80.99

[0042] As can be seen from Table 1, compared with the conventional perovskite and crystalline silicon tandem cell structure, the short-circuit current, fill factor and open-circuit voltage of the perovskite and crystalline silicon tandem cell structure of this embodiment are all slightly increased, and the photoelectric conversion efficiency is significantly improved. Therefore, it can be shown that the defects of the prior art are solved, and the perovskite and crystalline silicon tandem cell structure of this application greatly improves the photoelectric conversion efficiency of solar cells.

[0043] In summary, after adopting this tandem cell structure, first, a doped layer is selectively and regionally prepared in a part of the area on the front of the tunneling oxide layer in the bottom crystalline silicon cell, then a transparent conductive thin film layer is added in another part of the area on the front of the doped layer and the tunneling oxide layer, and finally the perovskite cell layer is stacked on the front of the transparent conductive thin film layer to form a perovskite and crystalline silicon tandem cell structure. Therefore, compared with the prior art, on the one hand, through the regional distribution of the doped layer, the field passivation effect can be achieved, reducing recombination and unnecessary parasitic absorption, and effectively reducing optical losses; on the other hand, by setting the transparent conductive thin film layer, while realizing the compatibility between the crystalline silicon cell and the perovskite cell, the thickness of the doped layer can be significantly reduced, effectively reducing the preparation cost of the battery. In addition, the efficient combined utilization of the solar spectrum and the superposition of the open-circuit voltage are realized, greatly improving the photoelectric conversion efficiency.

[0044] The above has made a detailed description of the present invention, aiming to enable those skilled in this field to understand the content of the present invention and implement it. However, the protection scope of the present invention cannot be limited thereby. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A perovskite and crystalline silicon cell stacked structure, comprising a bottom cell and a top cell stacked in phase, wherein the bottom cell is a crystalline silicon cell, and the top cell is a perovskite cell, wherein the crystalline silicon cell comprises a crystalline silicon substrate, a tunneling oxide layer and a doping layer sequentially arranged from the crystalline silicon substrate upward, characterized in that: The front side of the tunneling oxide layer is divided into a first area and a second area, and the doping layer covers the first area accordingly; the stacked structure also includes a transparent conductive film layer arranged between the crystalline silicon cell and the perovskite cell, wherein the transparent conductive film layer is stacked and covers the doping layer and the second area, and the perovskite cell is stacked on the front side of the transparent conductive film layer.

2. The perovskite and crystalline silicon cell stacking structure according to claim 1, characterized in that: There are a plurality of doping layers, and the plurality of doping layers are laid crosswise or at intervals on the front side of the tunnel oxide layer.

3. The perovskite and crystalline silicon cell stacking structure according to claim 2, characterized in that: The doped layers are in strip shape, and a plurality of the doped layers are arranged in parallel and spaced side by side on the front side of the tunneling oxide layer; and / or the cross section of each of the doped layers is rectangular.

4. The perovskite and crystalline silicon cell stacking structure according to claim 1, 2 or 3, characterized in that: The thickness of the doping layer is 15-30 nm; and / or the doping layer is a poly-si layer.

5. The perovskite and crystalline silicon cell stacking structure according to claim 1, characterized in that: The thickness of a portion of the transparent conductive film layer covering the doping layer is equal to the thickness of a portion of the transparent conductive film layer covering the second region.

6. The perovskite and crystalline silicon cell stacking structure according to claim 5, characterized in that: The thickness of the transparent conductive film layer is 65-85 nm.

7. The perovskite and crystalline silicon cell stacking structure according to claim 1, 5 or 6, characterized in that: The material of the transparent conductive film layer is indium tin oxide, fluorine-doped tin oxide, aluminum-doped tin oxide or antimony-doped tin oxide.

8. The perovskite and crystalline silicon cell stacking structure according to claim 1, characterized in that: The crystalline silicon cell further comprises a p-type emitter, a passivation layer, a passivation layer anti-reflection layer and a back electrode which are sequentially arranged from the crystalline silicon substrate downward.

9. The perovskite and crystalline silicon cell stacking structure according to claim 8, characterized in that: The tunneling oxide layer is a SiO2 layer; and / or the passivation layer is an Al2O3 layer; and / or the passivation layer anti-reflection layer is a SiN X / SiO2 layer.

10. The perovskite and crystalline silicon cell stacking structure according to claim 1, characterized in that: The perovskite cell includes a hole transport layer, a perovskite layer, an electron transport layer and a front electrode which are arranged in sequence from the front side of the transparent conductive film layer to the top side, wherein the back side of the hole transport layer is embedded in the front side of the transparent conductive film layer, and the front side of the hole transport layer is a plane.

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