Device structure including four-transistor ternary content addressable memory cell

Abstract

The utility model provides a device structure comprising a four-transistor ternary content addressable memory cell, which comprises a first series connection part of a first non-hysteresis transistor (e.g., a thin film transistor) and a first memory transistor (e.g., a thin film transistor), and a second series connection part of a second non-hysteresis transistor (e.g., a thin film transistor). The first memory transistor includes a first memory component configured to store a first binary bit; and a second series connection of a second non-hysteresis transistor and a second memory transistor, the second memory transistor including a second memory component configured to store a second binary bit. The first series connection portion and the second series connection portion are connected in parallel between the match line and the word line.

Description

Technical Field

[0001] The utility model relates to a device structure including a four-transistor ternary content-addressable memory cell. Background Art

[0002] A ternary content-addressable memory (TCAM) cell is a high-speed memory cell that can be used in networking devices (such as routers and switches) to perform fast table lookup and matching operations. The TCAM cell can accelerate the packet forwarding and routing process by enabling simultaneous parallel searches among multiple table entries. The TCAM cell is different from traditional memory technologies (such as random-access memory (RAM)) because the TCAM cell provides comparisons based on ternary logic. Ternary logic allows for three possible states: "0", "1", and "don't care" (alternatively represented as "X" or "*"). This ability makes TCAM devices very suitable for performing complex matching operations using wildcards and range-based patterns.

[0003] In typical networking applications, TCAM devices can be used to store forwarding tables, access control lists (ACLs), and other types of data used in packet processing. In the case of a packet arrival, the header information is compared with the table entries in the TCAM device to determine the appropriate action to take, such as forwarding the packet to a specific port or applying a specific policy. The TCAM cells in the TCAM device can operate in parallel, enabling the TCAM device to perform a high-speed search on a large data set within a single clock cycle. This characteristic makes the TCAM device very efficient in tasks that require fast matching and decision-making, but this efficiency comes at the cost of the device complexity of the TCAM cell. For example, a typical TCAM cell known in this technology includes 10 or more transistors in each cell. In addition, as a result of each TCAM cell containing many transistors, the TCAM device consumes more power compared to alternative memory cells. Summary of the Utility Model

[0004] An embodiment of the present utility model provides a device structure including a four-transistor ternary content addressable memory cell. The four-transistor ternary content addressable memory cell includes: a first series connection portion of a first non-hysteretic transistor and a first memory transistor, the first memory transistor including a first memory component configured to store a first binary digit; and a second series connection portion of a second non-hysteretic transistor and a second memory transistor, the second memory transistor including a second memory component configured to store a second binary digit, wherein the first series connection portion and the second series connection portion are connected in parallel between a match line and a word line.

[0005] An embodiment of the present utility model provides a device structure, the device structure including: a first dielectric layer, covering a substrate; a first series connection portion of a first non-hysteretic transistor and a first memory transistor, the first memory transistor including a first memory component configured to store a first binary digit, the first series connection portion covering the dielectric layer; a second series connection portion of a second non-hysteretic transistor and a second memory transistor, the second memory transistor including a second memory component configured to store a second binary digit, wherein the first non-hysteretic transistor, the first memory transistor, the second non-hysteretic transistor, and the second memory transistor are formed in a second dielectric layer; and a match line and a word line, which can be formed in a third dielectric layer, wherein the first series connection portion and the second series connection portion are connected in parallel between the match line and the word line. Brief Description of the Drawings

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a circuit diagram of a four-transistor ternary content addressable memory cell according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of a first exemplary structure after forming complementary metal oxide semiconductor (CMOS) transistors and a first metal interconnect structure embedded in a lower-level dielectric layer according to a first embodiment of the present disclosure.

[0009] FIG. 3A to FIG. 3D is various views of a region of a first exemplary structure after forming a via structure embedded in a via-level dielectric layer according to a first embodiment of the present disclosure. Figure 3A is a vertical cross-sectional view of a first region for forming a memory transistor. Figure 3B is Figure 3A a top view of the first region shown in Figure 3C is a vertical cross-sectional view of a second region for forming a non-hysteretic transistor. Figure 3D is Figure 3C a top view of the second region shown in

[0010] 4A to 4D various views of regions of a first exemplary structure after forming a patterned layer stack according to a first embodiment of the present disclosure. Figure 4A is a vertical cross-sectional view of a first region. Figure 4B is a top view of a first region. Figure 4C is a vertical cross-sectional view of a second region. Figure 4D is a top view of a second region.

[0011] FIG. 5A to FIG. 5D various views of regions of a first exemplary structure after forming a contact-level dielectric layer and a contact via structure according to a first embodiment of the present disclosure. Figure 5A is a vertical cross-sectional view of a first memory transistor. Figure 5B is a vertical cross-sectional view of a second memory transistor. Figure 5C is a vertical cross-sectional view of a first non-hysteretic transistor. Figure 5D is a vertical cross-sectional view of a second non-hysteretic transistor.

[0012] FIG. 6A to FIG. 6D various views of regions of a first exemplary structure after forming a via-level dielectric layer, a connection via structure, a line-level dielectric layer, and a metal line according to a first embodiment of the present disclosure. Fig. 6A is a vertical cross-sectional view of a first memory transistor. Figure 6B is a vertical cross-sectional view of a second memory transistor. Figure 6C is a vertical cross-sectional view of a first non-hysteretic transistor. Fig.6D is a vertical cross-sectional view of a second non-hysteretic transistor.

[0013] FIG. 7A to FIG. 7D various views of regions of an alternative configuration of a first exemplary structure after forming a via-level dielectric layer, a connection via structure, a line-level dielectric layer, and a metal line according to a first embodiment of the present disclosure. Fig. 7A is a vertical cross-sectional view of a first memory transistor. Figure 7B is a vertical cross-sectional view of a second memory transistor. Figure 7C is a vertical cross-sectional view of a first non-hysteretic transistor. Fig.7D is a vertical cross-sectional view of a second non-hysteretic transistor.

[0014] Figure 8 is a schematic diagram of a device structure including a four-transistor ternary content-addressable memory cell that uses the example of a transistor described with reference to FIG. 6A to FIG. 6D or uses the example of a transistor described with reference to FIG. 7A to FIG. 7D

[0015] ​ Fig. 9A and Fig. 9B is a view of a region of a second exemplary structure after forming search lines and bit lines according to a second embodiment of the present disclosure. Fig. 9A It is a vertical cross-sectional view. Fig. 9B It is a top view. Fig. 9B The vertical plane A-A’ in Fig. 9A is the cutting plane of the vertical cross-sectional view shown.

[0016] Fig. 10A and Fig. 10B is a view of a region of a second exemplary structure after forming a back gate dielectric layer according to a second embodiment of the present disclosure. Fig. 10A It is a vertical cross-sectional view. Fig. 10B It is a top view. Fig. 10B The vertical plane A-A’ in Fig. 10A is the cutting plane of the vertical cross-sectional view shown.

[0017] Fig.11A and Fig. 11B is a view of a region of a second exemplary structure after forming a patterned layer stack according to a second embodiment of the present disclosure. Fig.11A It is a vertical cross-sectional view. Fig. 11B It is a top view. Fig. 11B The vertical plane A-A’ in Fig.11A is the cutting plane of the vertical cross-sectional view shown.

[0018] Fig. 12A and Fig. 12B is a view of a region of a second exemplary structure after forming a contact-level dielectric layer according to a second embodiment of the present disclosure. Fig. 12A It is a vertical cross-sectional view. Fig. 12B It is a top view. Fig. 12B The vertical plane A-A’ in Fig. 12A is the cutting plane of the vertical cross-sectional view shown.

[0019] Fig.13A and Fig. 13B is a view of a region of a second exemplary structure after forming a contact via structure according to a second embodiment of the present disclosure. Fig.13A It is a vertical cross-sectional view. Fig. 13B It is a top view. Fig. 13B The vertical plane A-A’ in Fig.13A is the cutting plane of the vertical cross-sectional view shown.

[0020] FIG. 14A to FIG. 14C is a view of a region of a second exemplary structure after forming a via-level dielectric layer and a connecting via structure according to a second embodiment of the present disclosure. Fig.14A It is a first vertical cross-sectional view. Fig. 14B It is a top view. Fig. 14CIt is a second vertical cross-sectional view. Fig. 14B The vertical plane A-A' in Fig.14A is the cutting plane of the vertical cross-sectional view shown. Fig. 14B The vertical plane C-C' in Fig. 14C is the cutting plane of the vertical cross-sectional view shown.

[0021] FIG. 15A to FIG. 15C It is a view of a region of a second exemplary structure after forming a line-level dielectric layer, matching lines, and character lines according to a second embodiment of the present disclosure. Fig.15A It is a first vertical cross-sectional view. Fig. 15B It is a top view. Fig. 15C It is a second vertical cross-sectional view. Fig. 15B The vertical plane A-A' in Fig.15A is the cutting plane of the vertical cross-sectional view shown. Fig. 15B The vertical plane C-C' in Fig. 15C is the cutting plane of the vertical cross-sectional view shown.

[0022] FIG. 16A to FIG. 16C It is a view of a region of an alternative configuration of a second exemplary structure after forming a line-level dielectric layer, matching lines, and character lines according to a second embodiment of the present disclosure. Fig.16A It is a first vertical cross-sectional view. Fig. 16B It is a top view. Fig. 16C It is a second vertical cross-sectional view. Fig. 16B The vertical plane A-A' in Fig.16A is the cutting plane of the vertical cross-sectional view shown. Fig. 16B The vertical plane C-C' in Fig. 16C is the cutting plane of the vertical cross-sectional view shown.

[0023] 17A to 17C It is a view of a region of a third exemplary structure after forming search lines and bit lines according to a third embodiment of the present disclosure. Fig.17A It is a first vertical cross-sectional view. Fig. 17B It is a top view. Fig. 17C It is a second vertical cross-sectional view. Fig. 17B The vertical plane A-A' in Fig.17A is the cutting plane of the vertical cross-sectional view shown. Fig. 17B The vertical plane C-C' in Fig. 17C is the cutting plane of the vertical cross-sectional view shown.

[0024] 18A to 18C It is a view of a region of a third exemplary structure after forming a lower via-level dielectric layer and via structures according to a third embodiment of the present disclosure. Fig.18A It is a first vertical cross-sectional view. Fig.18B It is a top view. Fig. 18C It is a second vertical cross-sectional view. Fig.18B The vertical plane A-A' in Fig.18A is the cutting plane of the vertical cross-sectional view shown. Fig.18B The vertical plane C-C' in Fig. 18C is the cutting plane of the vertical cross-sectional view shown.

[0025] FIG. 19A to FIG. 19C is a view of a region of a third exemplary structure after forming a back gate dielectric layer according to a third embodiment of the present disclosure. Fig.19A is a first vertical cross-sectional view. Fig.19B is a top view. Fig.19C is a second vertical cross-sectional view. Fig.19B The vertical plane A-A' in Fig.19A is the cutting plane of the vertical cross-sectional view shown. Fig.19B The vertical plane C-C' in Fig.19C is the cutting plane of the vertical cross-sectional view shown.

[0026] FIG. 20A to FIG. 20C is a view of a region of a third exemplary structure after forming a patterned layer stack according to a third embodiment of the present disclosure. Fig. 20A is a first vertical cross-sectional view. Fig. 20B is a top view. Fig. 20C is a second vertical cross-sectional view. Fig. 20B The vertical plane A-A' in Fig. 20A is the cutting plane of the vertical cross-sectional view shown. Fig. 20B The vertical plane C-C' in Fig. 20C is the cutting plane of the vertical cross-sectional view shown.

[0027] FIG. 21A to FIG. 21C is a view of a region of a third exemplary structure after forming a contact level dielectric layer and a contact via structure according to a third embodiment of the present disclosure. Fig.21A is a first vertical cross-sectional view. Fig.21B is a top view. Fig. 21C is a second vertical cross-sectional view. Fig.21B The vertical plane A-A' in Fig.21A is the cutting plane of the vertical cross-sectional view shown. Fig.21B The vertical plane C-C' in Fig. 21C is the cutting plane of the vertical cross-sectional view shown.

[0028] FIG. 22A to FIG. 22C is a view of a region of a third exemplary structure after forming a via level dielectric layer and a connecting via structure according to a third embodiment of the present disclosure. Fig.22A is a first vertical cross-sectional view. Fig. 22B is a top view. Fig. 22C is a second vertical cross-sectional view. Fig. 22B The vertical plane A-A' in Fig.22A The cutting plane of the vertical cross-sectional view shown. Fig. 22B The vertical plane C-C' in Fig. 22C The cutting plane of the vertical cross-sectional view shown.

[0029] FIG. 23A to FIG. 23C Is a view of a region of a third exemplary structure after forming the line-level dielectric layer, the character lines, and the matching lines according to the third embodiment of the present disclosure. Fig.23A Is a first vertical cross-sectional view. Fig. 23B Is a top view. Fig.23C Is a second vertical cross-sectional view. Fig. 23B The vertical plane A-A' in Fig.23A The cutting plane of the vertical cross-sectional view shown. Fig. 23B The vertical plane C-C' in Fig.23C The cutting plane of the vertical cross-sectional view shown.

[0030] FIG. 24A to FIG. 24E Is a view of a region of an alternative configuration of a third exemplary structure after forming the via-level dielectric layer and the via connection structure according to the third embodiment of the present disclosure. Fig.24A Is a first vertical cross-sectional view. Fig. 24B Is a top view. Fig.24C Is a second vertical cross-sectional view. Fig.24D Is a third vertical cross-sectional view. Fig.24E Is a fourth vertical cross-sectional view. Fig. 24B The vertical plane A-A' in Fig.24A The cutting plane of the vertical cross-sectional view shown. Fig. 24B The vertical plane C-C' in Fig.24C The cutting plane of the vertical cross-sectional view shown. Fig. 24B The vertical plane D-D' in Fig.24D The cutting plane of the vertical cross-sectional view shown. Fig. 24B The vertical plane E-E' in Fig.24E The cutting plane of the vertical cross-sectional view shown.

[0031] FIG. 25A to FIG. 25E Is a view of a region of an alternative configuration of a third exemplary structure after forming the line-level dielectric layer, the character lines, and the matching lines according to the third embodiment of the present disclosure. Fig.25A Is a first vertical cross-sectional view. Fig.25B Is a top view. Fig.25C Is a second vertical cross-sectional view. Fig.25D Is a third vertical cross-sectional view. Fig.25E Is a fourth vertical cross-sectional view. Fig.25B The vertical plane A-A' in Fig.25A The cutting plane of the vertical cross-sectional view shown. Fig.25B The vertical plane C-C' in Fig.25CThe cutting plane of the vertical cross-sectional view shown. Fig.25B The vertical plane D-D' in Fig.25D is the cutting plane of the vertical cross-sectional view shown. Fig.25B The vertical plane E-E' in Fig.25E is the cutting plane of the vertical cross-sectional view shown.

[0032] FIG. 26A to FIG. 26C is a view of a region of a fourth exemplary structure after forming a patterned layer stack according to a fourth embodiment of the present disclosure. Fig.26A is a first vertical cross-sectional view. Fig.26B is a top view. Fig.26C is a second vertical cross-sectional view. Fig.26B The vertical plane A-A' in Fig.26A is the cutting plane of the vertical cross-sectional view shown. Fig.26B The vertical plane C-C' in Fig.26C is the cutting plane of the vertical cross-sectional view shown.

[0033] FIG. 27A to FIG. 27F is a view of a region of a fourth exemplary structure after forming a contact-level dielectric layer and a contact via structure according to a fourth embodiment of the present disclosure. Fig.27A is a first vertical cross-sectional view. Fig.27B is a top view. Fig.27C is a second vertical cross-sectional view. Fig.27D is a third vertical cross-sectional view. Fig.27E is a fourth vertical cross-sectional view. Fig.27F is a fifth vertical cross-sectional view. Fig.27B The vertical plane A-A' in Fig.27A is the cutting plane of the vertical cross-sectional view shown. Fig.27B The vertical plane C-C' in Fig.27C is the cutting plane of the vertical cross-sectional view shown. Fig.27B The vertical plane D-D' in Fig.27D is the cutting plane of the vertical cross-sectional view shown. Fig.27B The vertical plane E-E' in Fig.27E is the cutting plane of the vertical cross-sectional view shown. Fig.27B The vertical plane F-F' in Fig.27F is the cutting plane of the vertical cross-sectional view shown.

[0034] FIG. 28A to FIG. 28F is a view of a region of a fourth exemplary structure after forming a via-level dielectric layer, a connecting via structure, a line-level dielectric layer, a character line, and a matching line according to a fourth embodiment of the present disclosure. Fig.28A is a first vertical cross-sectional view. Fig.28B is a top view. Fig.28C is a second vertical cross-sectional view. Fig.28D is a third vertical cross-sectional view. Fig.28E It is the fourth vertical sectional view. Fig.28F It is the fifth vertical sectional view. Fig.28B The vertical plane A-A’ in Fig.28A is the sectional plane of the vertical sectional view shown. Fig.28B The vertical plane C-C’ in Fig.28C is the sectional plane of the vertical sectional view shown. Fig.28B The vertical plane D-D’ in Fig.28D is the sectional plane of the vertical sectional view shown. Fig.28B The vertical plane E-E’ in Fig.28E is the sectional plane of the vertical sectional view shown. Fig.28B The vertical plane F-F’ in Fig.28F is the sectional plane of the vertical sectional view shown.

[0035] FIG. 29A to FIG. 29F It is a view of an area of an alternative embodiment of a fourth exemplary structure after forming a via-level dielectric layer, a via connection structure, a line-level dielectric layer, a character line, and a matching line according to a fourth embodiment of the present disclosure. Fig.29A It is the first vertical sectional view. Fig.29B It is a top view. Fig.29C It is the second vertical sectional view. Fig.29D It is the third vertical sectional view. Fig.29E It is the fourth vertical sectional view. Fig.29F It is the fifth vertical sectional view. Fig.29B The vertical plane A-A’ in Fig.29A is the sectional plane of the vertical sectional view shown. Fig.29B The vertical plane C-C’ in Fig.29C is the sectional plane of the vertical sectional view shown. Fig.29B The vertical plane D-D’ in Fig.29D is the sectional plane of the vertical sectional view shown. Fig.29B The vertical plane E-E’ in Fig.29E is the sectional plane of the vertical sectional view shown. Fig.29B The vertical plane F-F’ in Fig.29F is the sectional plane of the vertical sectional view shown.

[0036] Fig.30 It is a vertical sectional view of an exemplary structure after forming at least one upper-level dielectric layer and an upper-level metal internal connection structure according to an embodiment of the present disclosure.

[0037] Fig.31 It is a table showing programming conditions and search conditions that can be used during the operation of a four-transistor ternary content-addressable memory cell of the present disclosure.

[0038] Fig.32is a flowchart showing a set of processing steps that can be used to form a device structure according to an embodiment of the present disclosure. Detailed Description

[0039] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Like reference numerals refer to like components or similar components, and unless otherwise expressly stated, components with the same reference numeral are assumed to have the same material composition and the same function.

[0040] In addition, for ease of illustration, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and similar terms may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless otherwise expressly indicated, components with the same reference numeral refer to the same component and are assumed to have the same material composition and the same thickness range.

[0041] Embodiments of the present disclosure are generally related to four-transistor ternary content addressable memory (4TFT-TCAM) cells and methods of forming the same. As used herein, a ternary content addressable memory (TCAM) cell refers to a memory cell configured to store ternary value data, the ternary value data including three possible states: "0", "1", and "X" (where "X" may also be represented as "*"). Ternary logic enables flexible pattern matching and wildcard-based searches. A TCAM cell may store a combination of the three states in its storage component. A match line and a provide line are provided for each TCAM cell. The match line is used to compare the stored data with an input pattern. The match line receives the input pattern and compares the input pattern with the value stored within the cell. The match line operates in parallel with other TCAM cells in a TCAM array, thereby enabling simultaneous searches across multiple table entries. During a search operation, the provide line controls the enabling of the TCAM cell. The provide line determines whether the data stored within the TCAM cell will participate in the comparison process. By selectively enabling or disabling specific TCAM cells, the TCAM can perform complex matching operations and adapt to changing search requirements. The four transistors may be thin-film transistors (TFTs).

[0042] According to aspects of the present disclosure, a TCAM cell includes two memory transistors and two non-hysteretic transistors formed using a set of shared processing steps. As used herein, a "non-hysteretic" device refers to a device that exhibits device characteristics that are independent of the device history and thus do not store data. The memory transistors include a hysteretic component that can store data, and the value of the data can be detected by measuring the characteristics of the memory transistors. The TCAM cells of the present disclosure can be formed only within the back-end-of-line (BEOL) level within an interlayer dielectric (ILD) layer. Thus, the TCAM devices of the present disclosure do not occupy any front-end-of-line (FEOL) real estate in a semiconductor die, but are provided as BEOL structures formed within the metal interconnect levels. Additionally, the total number of transistors per TCAM cell is limited (e.g., four transistors). Further, the TCAM cells of the present disclosure are non-volatile. Thus, the TCAM cells do not consume power in a standby state, in which the data is stored but not actively used. The various aspects of the TCAM cells of the present disclosure are now described with reference to the accompanying drawings.

[0043] Referring to Figure 1 , Figure 1A circuit diagram showing a four-transistor ternary content addressable memory (TCAM) cell C_mn according to an embodiment of the present disclosure. The ternary content addressable memory cell C_mn includes a finite number of transistors (e.g., no more than four field effect transistors) and provides the function of a ternary content addressable memory cell (i.e., provides storage for ternary bit data). In some embodiments, the ternary content addressable memory cell C_mn may be referred to as a four-transistor ternary content addressable memory cell C_mn. The ternary content addressable memory cell C_mn is a memory cell located at the position of the m-th column and the n-th row in the M×N array of ternary content addressable memory cells. The column index m can be a positive integer between 1 and M, and the row index n can be a positive integer between 1 and N. The value of M can range from 2 to 2 20 within a certain range, and the value of N can range from 2 to 2 20 within a certain range, but smaller and larger values can also be used.

[0044] The four-transistor ternary content addressable memory cell C_mn includes a first series connection of a first non-hysteretic transistor 321 (e.g., a thin film transistor) and a first memory transistor 221 (e.g., a thin film transistor), and the first memory transistor 221 includes a first memory component (e.g., a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a first binary bit. The four-transistor ternary content addressable memory cell C_mn may further include a second series connection of a second non-hysteretic transistor 322 and a second memory transistor 222, and the second memory transistor 222 includes a second memory component (e.g., a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a second binary bit. The combination of the first binary bit and the second binary bit can have a set of values (0, 0), (1, 0), and (0, 1). These three sets of values can be used to store ternary bit data. Generally, the set of values (1, 1) is not needed.

[0045] The main search line SLn, complementary search line SLn*, main bit line BLn, and complementary bit line BLn* can be used to apply an electrical bias to the gate electrodes of the four transistors (221, 222, 321, 322). For the four-transistor ternary content addressable memory cell C_mn, the main search line SLn can be the n-th main search line selected from N main search lines, the complementary search line SLn* can be the n-th complementary search line selected from N complementary search lines, the main bit line BLn can be the n-th main bit line selected from N main bit lines, and the complementary bit line BLn* can be the n-th complementary bit line selected from N complementary bit lines. An electrical bias can be applied to the gate electrode of the first memory transistor 221 through the main bit line BLn; an electrical bias can be applied to the gate electrode of the second memory transistor 222 through the complementary bit line BLn*; an electrical bias can be applied to the gate electrode of the first non-hysteretic transistor 321 through the complementary search line SLn*; and an electrical bias can be applied to the gate electrode of the second non-hysteretic transistor 322 through the main search line SLn.

[0046] The first series connection portion includes a first conductive path (741, 941) between the source / drain structure of the first non-hysteretic transistor 321 and the source / drain structure of the first memory transistor 221. The first conductive path (741, 941) can include a first contact via structure 741 that makes direct contact with the source / drain structure of the first non-hysteretic transistor 321 and the source / drain structure of the first memory transistor 221, or can include a metal connection line 941 that is connected to the source / drain structure of the first non-hysteretic transistor 321 and the source / drain structure of the first memory transistor 221 via an intermediate via structure. The second series connection portion includes a second conductive path (742, 942) between the source / drain structure of the second non-hysteretic transistor 322 and the source / drain structure of the second memory transistor 222. The second conductive path (742, 942) can include a second contact via structure 742 that makes direct contact with the source / drain structure of the second non-hysteretic transistor 322 and the source / drain structure of the second memory transistor 222, or can include a metal connection line 942 that is connected to the source / drain structure of the second non-hysteretic transistor 322 and the source / drain structure of the second memory transistor 222 via an intermediate via structure.

[0047] Generally, the main search line SLn, complementary search line SLn*, main bit line BLn, and complementary bit line BLn* may include a first metal line formed within a first dielectric material layer. The first metal line level may be any metal line level in the metal interconnect structure. In an illustrative non-limiting example, the first metal line level may include an i-th metal line structure formed within the dielectric material layer of the i-th interconnect level. For example, if the index is 2, the main search line SLn, complementary search line SLn*, main bit line BLn, and complementary bit line BLn* may include a second metal line structure 628.

[0048] Field effect transistors (221, 222, 321, 322) may be formed within a second dielectric material layer, which is referred to herein as a memory level dielectric layer or a contact level dielectric layer. The match line 98 (MLm) and the word line 92 (WLm) may include a second metal line formed within a third dielectric material layer that overlies the second dielectric material layer. For example, the match line 98 (MLm) may include a second metal line structure, and the word line 92 (WLm) may include an additional second metal line structure.

[0049] Referring Figure 2 , Figure 2 , there is shown a first exemplary structure in accordance with a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at least at an upper portion of the substrate 8. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate or may be the top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 comprises a single crystal semiconductor material (e.g., single crystal silicon). In one embodiment, the substrate 8 may include a single crystal silicon substrate comprising a single crystal silicon material.

[0050] In an upper portion of the semiconductor material layer 9, a shallow trench isolation structure 720 including a dielectric material (e.g., silicon oxide) may be formed. In each region laterally surrounded by a portion of the shallow trench isolation structure 720, a suitable doped semiconductor well (e.g., a p-type well and an n-type well) may be formed. Above the top surface of the semiconductor material layer 9, a field effect transistor 701 may be formed. For example, each field effect transistor 701 may include a source region 732, a drain region 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source region 732 and the drain region 738, and a gate structure 750. The semiconductor channel 735 may include a single crystal semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate capping dielectric 758, and dielectric gate spacers 756. On each source region 732, a source side metal region or a metal-semiconductor alloy region serving as a source electrode 722 may be formed, and on each drain region 738, a drain side metal region or a metal-semiconductor alloy region serving as a drain electrode 728 may be formed.

[0051] A first exemplary structure may include a memory array region 100, and a four-transistor ternary content addressable memory cell array may be formed in the memory array region 100 subsequently. The first exemplary structure may further include a peripheral region 200 where peripheral metal wirings for the four-transistor ternary content addressable memory cell array are provided. Generally, the field effect transistors 701 in a complementary metal-oxide-semiconductor (CMOS) circuit system 700 may be electrically connected to electrodes of corresponding four-transistor ternary content addressable memory cells through a corresponding set of metal interconnection structures.

[0052] Devices (e.g., field effect transistors 701) located on the semiconductor material layer 9 may provide functions for operating a four-transistor ternary content addressable memory cell array to be formed subsequently. Specifically, the devices located on the semiconductor material layer 9 may be configured to control the programming operation, the erasing operation, and the sensing (reading) operation of the four-transistor ternary content addressable memory cell array. For example, the devices located on the semiconductor material layer 9 may include sensing circuitry and / or programming circuitry. Devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.) and are collectively referred to as a CMOS circuit system 700.

[0053] One or more of the field effect transistors 701 in the CMOS circuit system 700 may include a semiconductor channel 735 that includes a portion of a semiconductor material layer 9 located in a substrate 8. In embodiments where the semiconductor material layer 9 comprises a single crystal semiconductor material (e.g., single crystal silicon), the semiconductor channel 735 of each field effect transistor 701 in the CMOS circuit system 700 may include a single crystal semiconductor channel (e.g., a single crystal silicon channel). In one embodiment, the plurality of field effect transistors 701 in the CMOS circuit system 700 may include corresponding nodes that are subsequently electrically connected to the nodes of the corresponding memory cells to be formed subsequently. For example, the plurality of field effect transistors 701 in the CMOS circuit system 700 may include corresponding source regions 732 or corresponding drain regions 738, or corresponding source electrodes 722 or select drain electrodes 728, which are subsequently electrically connected to the nodes of the corresponding memory cells to be formed subsequently.

[0054] In one embodiment, the substrate 8 may comprise a single crystal semiconductor material (e.g., single crystal silicon) and the field effect transistor 701 may include a corresponding semiconductor channel 735 that includes a portion of a single crystal semiconductor material or comprises the same material as the single crystal semiconductor material. In one embodiment, the semiconductor channel may be semiconductive.

[0055] In accordance with aspects of the present disclosure, the field effect transistor 701 may subsequently be electrically connected to the drain electrode and the gate electrode of a memory transistor to be formed above the field effect transistor 701. In one embodiment, a subset of the field effect transistors 701 may subsequently be electrically connected to at least one of the drain electrode and the gate electrode. For example, the field effect transistor 701 may include a first word line driver and a second word line driver, the first word line driver being configured to apply a first gate voltage to a first word line via a first subset of lower level metal interconnect structures to be formed subsequently, and the second word line driver being configured to apply a second gate voltage to a second word line via a second subset of lower level metal interconnect structures. Additionally, the field effect transistor 701 may include a bit line driver configured to apply a bit line bias voltage to a bit line to be formed subsequently and a sense amplifier configured to detect a current flowing through a match line during a read operation.

[0056] Subsequently, various metal interconnect structures formed within a dielectric material layer may be formed over the substrate 8 and a semiconductor device (such as a field effect transistor 701) located on the substrate 8. In an illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 601 (sometimes referred to as a contact level dielectric material layer 601) that may be a layer surrounding contact structures connected to the source and drain, a first interconnect level dielectric material layer 610, and a second interconnect level dielectric material layer 620. The metal interconnect structures may include device contact via structures 612 formed in the first dielectric material layer 601 and in contact with corresponding components of the CMOS circuit system 700, a first metal line structure 618 formed in the first interconnect level dielectric material layer 610, a first metal via structure 622 formed in a lower portion of the second interconnect level dielectric material layer 620, and a second metal line structure 628 formed in an upper portion of the second interconnect level dielectric material layer 620.

[0057] Each of the dielectric material layers (601, 610, 620) may comprise a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorocarbon, a porous variant thereof, or a combination thereof. Each of the metal interconnect structures (612, 618, 622, 628) may comprise at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or a metal carbide) and a metal fill material. Each metal liner may comprise TiN, TaN, WN, TiC, TaC, and WC, and each metal fill material portion may comprise W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal fill materials within the scope contemplated by this disclosure may also be used. In one embodiment, the first metal via structure 622 and the second metal line structure 628 may be formed as an integrated line and via structure by a dual damascene process. The dielectric material layers (601, 610, 620) are referred to herein as lower level dielectric material layers or first dielectric material layers. The metal interconnect structures (612, 618, 622, 628) formed in the lower level dielectric material layers are referred to herein as lower level metal interconnect structures or first metal interconnect structures.

[0058] Generally, a dielectric material layer (such as the second interconnection level dielectric material layer 620) may be formed over the field effect transistor 701. A four-transistor ternary content addressable memory cell C_mn may be formed above the dielectric material layer. In one embodiment, the main search line SLn, complementary search line SLn*, main bit line BLn, and complementary bit line BLn* may be formed in an upper portion of such a dielectric material layer (such as the second interconnection level dielectric layer 620). In this embodiment, the main search line SLn, complementary search line SLn*, main bit line BLn, and complementary bit line BLn* may include the second metal line structure 628.

[0059] FIG. 3A to FIG. 3D Are various views of a region of a first exemplary structure after formation of a via structure formed in a via level dielectric layer according to a first embodiment of the present disclosure. Figure 3A Is a vertical cross-sectional view of a first region for forming a memory transistor (such as Figure 1 the first memory transistor 221 or the second memory transistor 222 shown in Figure 3B Is Figure 3A a top view of the first region shown in Figure 3C Is a vertical cross-sectional view of a second region for forming a non-hysteretic transistor (such as, Figure 1 the first non-hysteretic transistor 321 or the second non-hysteretic transistor 322 shown in Figure 3D Is Figure 3C a top view of the second region shown in Figure 3B And Figure 3D show a first horizontal direction hd1 and a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0060] With reference to Figure 1 And FIG. 3A to FIG. 3D collectively, a via level dielectric layer may be formed over the second metal line structure 628 as needed. The via level dielectric layer (if formed) is referred to herein as the lower via level dielectric layer 12. The lower via level dielectric layer 12 may be used as a first dielectric material layer in which a first via structure 215 and a second via structure 315 are formed. The first via structure 215 may be used as a gate electrode (also referred to as a first gate electrode) of the first memory transistor 221 and the second memory transistor 222. The second via structure 315 may be used as some portions of gate electrodes (also referred to as second gate electrodes) of the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322.

[0061] Generally, the first vias structure 215 and the second vias structure 315 are optional structures. In embodiments where the first vias structure 215 and the second vias structure 315 are not formed, portions of the main search lines SLn, complementary search lines SLn*, main bit lines BLn, and complementary bit lines BLn* including the second metal line structure 628 located within the unit cell region UC can be used as some portions of the gate electrodes or gate electrodes of the transistors (221, 222, 321, 322) of each four-transistor ternary content addressable memory cell C_mn.

[0062] FIG. 4A to FIG. 4D Are various views of a region of a first exemplary structure after forming a patterned layer stack according to a first embodiment of the present disclosure. Figure 4A Is a vertical cross-sectional view of a first region. Figure 4B Is a top view of a first region. Figure 4C Is a vertical cross-sectional view of a second region. Figure 4D Is a top view of a second region.

[0063] With reference to Figure 1 And FIG. 4A to FIG. 4D , a back gate dielectric 218 can be formed in the regions of the first memory transistor 221 and the second memory transistor 222 without covering the regions of the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322. The back gate dielectric 218 includes a gate dielectric material such as silicon oxide, silicon oxynitride, dielectric metal oxide, or a combination thereof. The back gate dielectric 218 can be deposited as a blanket material layer and patterned to cover a first region of the first dielectric material layer (e.g., the lower via level dielectric layer 12 and / or the second interconnection level dielectric material layer 620) for forming the first memory transistor 221 and the second memory transistor 222, without covering a second region of the first dielectric material layer for forming the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322. The thickness of the back gate dielectric layer can range from 1 nanometer to 30 nanometers, but smaller and larger thicknesses can also be used.

[0064] Subsequently, a layer stack of a gate electrode material layer 220 / 230, a front gate dielectric layer 240 / 340, and a semiconductor material layer 250 / 350 can be formed in the first region and the second region. The gate electrode material layer 220 / 320 includes a conductive material, such as a metal material or a heavily doped semiconductor material. For example, the gate electrode material layer 220 / 320 can include at least one conductive material (such as a conductive metal nitride material (such as, TiN, TaN, MoN, WN, etc.)), at least one elemental metal and / or an intermetallic alloy and / or can be substantially composed of at least one conductive material (such as a conductive metal nitride material (such as, TiN, TaN, MoN, WN, etc.)), at least one elemental metal and / or an intermetallic alloy. The thickness of the gate electrode material layer can range from 20 nanometers to 200 nanometers, but smaller and larger thicknesses can also be used.

[0065] The front gate dielectric layer 240 / 340 includes a gate dielectric material, such as silicon oxide, silicon oxynitride, a dielectric metal oxide, or a combination thereof. The thickness of the front gate dielectric layer can range from 1 nanometer to 30 nanometers, but smaller and larger thicknesses can also be used.

[0066] The semiconductor material layer 250 / 350 includes a semiconducting material. Exemplary compound semiconductor materials that can be used for the semiconductor material layer include, but are not limited to, indium gallium zinc oxide (IGZO), indium oxide, indium tin oxide, indium zinc oxide, indium tungsten oxide, gallium oxide, gallium zinc oxide, doped zinc oxide, doped indium oxide (such as tungsten-doped indium oxide), doped cadmium oxide, gallium nitride, indium phosphide, gallium phosphide, gallium antimonide, indium antimonide, gallium arsenide, aluminum arsenide, indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium arsenide, indium gallium phosphide, aluminum indium arsenide, silicon carbide, aluminum indium gallium phosphide, cadmium sulfide, cadmium selenide, cadmium telluride, zinc sulfide, zinc selenide, zinc telluride, lead sulfide, lead telluride, mercury telluride, silicon, germanium, silicon-germanium alloy, a semiconducting carbon material, and various other doped variants derived therefrom. Other suitable semiconducting materials are also within the scope of this disclosure. In one embodiment, the semiconductor material layer can include indium gallium zinc oxide.

[0067] The semiconductor material layer 250 / 350 can include a polycrystalline semiconducting material or an amorphous semiconducting material. The semiconductor material layer can be deposited by physical vapor deposition, atomic layer deposition, chemical vapor deposition, pulsed laser deposition, etc. The thickness of the semiconductor material layer can range from 1 nanometer to 100 nanometers (such as from 2 nanometers to 50 nanometers and / or from 3 nanometers to 20 nanometers), but smaller and larger thicknesses can also be used.

[0068] For example, the layer stack and the back gate dielectric 218 can be patterned by applying a photoresist layer over the semiconductor material layer 250 / 350, patterning the photoresist layer, and performing an anisotropic etching process that transfers the pattern in the photoresist layer through the layer stack and the back gate dielectric 218. The first patterned portion of the layer stack and the patterned portion of the back gate dielectric 218 are formed in the regions for the first memory transistor 221 and the second memory transistor 222. The second patterned portion of the layer stack is formed in the regions for the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322.

[0069] A first vertical stack of the back gate dielectric 218, the first gate electrode plate 220, the front gate dielectric 240, and the first semiconductor channel 250 can be formed in each region for the first memory transistor 221 (e.g., the first thin film memory transistor) and the second memory transistor 222 (e.g., the second thin film memory transistor). The sidewalls of the back gate dielectric 218, the sidewalls of the first gate electrode plate 220, the sidewalls of the front gate dielectric 240, and the sidewalls of the first semiconductor channel 250 can coincide with each other in the vertical direction within each first vertical stack. As used herein, the first surface and the second surface "coincide in the vertical direction" in an example where the second surface overlies or is located under the first surface and where there is a vertical plane including the first surface and the second surface. A second vertical stack of the second gate electrode plate 320, the non-hysteretic gate dielectric 340, and the second semiconductor channel 350 can be formed in each region for the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322. The sidewalls of the second gate electrode plate 320, the sidewalls of the non-hysteretic gate dielectric 340, and the sidewalls of the second semiconductor channel 350 can coincide with each other in the vertical direction within each second vertical stack.

[0070] Each back gate dielectric 218 can be a patterned portion of a back gate dielectric layer and can always have a uniform thickness. Each first gate electrode plate 220 and each second gate electrode plate 320 are patterned portions of a gate electrode material layer and can have the same conductive material composition and the same thickness. Each front gate dielectric 240 and each non-hysteretic gate dielectric 340 are patterned portions of a front gate dielectric layer and can have the same dielectric material composition and the same thickness. Each first semiconductor channel 250 and each second semiconductor channel 350 are patterned portions of a semiconductor material layer and can have the same semiconductor material composition and the same thickness.

[0071] In one embodiment, each memory transistor (221, 222) can be a flash memory device configured to store charge in a floating gate electrode. Each memory transistor (221, 222) can be a thin film transistor. In one embodiment, each first gate electrode plate 220 serves as the floating gate electrode of the corresponding memory transistor (221, 222). In this embodiment, the first via structure 215 (or alternatively, the portion of the second metal line structure 628 that contacts the bottom surface of the back gate dielectric 218) serves as the control gate electrode of the memory transistor (221, 222). In one embodiment, each non-hysteretic transistor (321, 322) includes a non-floating gate electrode (including the second gate electrode plate 320). The floating gate electrodes (including the first gate electrode plate 220) and the non-floating gate electrodes (including the second gate electrode plate 320) have the same material composition and the same thickness.

[0072] In one embodiment, each floating gate electrode (including the first gate electrode plate 220) can be spaced apart from the top surface of a dielectric material layer (such as the lower via level dielectric layer 12 and / or the second interconnection level dielectric material layer 620) in a vertical direction by the back gate dielectric 218, and the back gate dielectric 218 contacts a first section of the top surface of the dielectric material layer (for example, the lower via level dielectric layer 12 and / or the second interconnection level dielectric material layer 620). In one embodiment, each non-floating gate electrode (including the second gate electrode plate 320) contacts a second section of the top surface of the dielectric material layer. In one embodiment, the sidewall of each floating gate electrode (including the first gate electrode plate 220) coincides with the sidewall of the corresponding underlying back gate dielectric 218 in the vertical direction.

[0073] Each front gate dielectric 240 contacts the first semiconductor channel 250 of the first memory transistor 221. Each non-hysteretic gate dielectric 340 contacts the second semiconductor channel 350 of the first non-hysteretic transistor 321. The front gate dielectric 240 and the non-hysteretic gate dielectric 340 have the same material composition and the same thickness. In one embodiment, within each memory transistor (221, 222), one of the front gate dielectric 240 and the back gate dielectric 218 includes a tunneling dielectric layer that provides charge tunneling therethrough, and the other of the front gate dielectric 240 and the back gate dielectric 218 includes a blocking dielectric layer that inhibits charge tunneling therethrough. Thus, during the operation of the memory transistor (221, 222), charge tunneling can occur through the front gate dielectric 240 or through the back gate dielectric 218.

[0074] FIG. 5A to FIG. 5DAre various views of regions of a first exemplary structure after formation of a contact-level dielectric layer 70 and contact via structures (72, 741, 742, 78) in accordance with a first embodiment of the present disclosure. Figure 5A Is a vertical cross-sectional view of a first memory transistor 221. Figure 5B Is a vertical cross-sectional view of a second memory transistor 222. Figure 5C Is a vertical cross-sectional view of a first non-hysteretic transistor 321. Figure 5D Is a vertical cross-sectional view of a second non-hysteretic transistor 322.

[0075] Refer to jointly Figure 1 With FIG. 5A to FIG. 5D , a contact-level dielectric layer 70 may be formed over layer stacks {(218, 220, 240, 250), (320, 340, 350)}. The contact-level dielectric layer 70 includes an interlayer dielectric (ILD) material such as undoped silicate glass, doped silicate glass, organosilicate glass, or a combination thereof. In one embodiment, the contact-level dielectric layer 70 may include a self-planarizing dielectric material or a planarizable dielectric material (such as undoped silicate glass or doped silicate glass). Optionally, a planarization process may be performed to planarize the top surface of the contact-level dielectric layer 70. In one embodiment, the top surface of the contact-level dielectric layer 70 may be planar (i.e., may lie in a horizontal plane).

[0076] Via cavities may be formed through the contact-level dielectric layer 70. Two end portions of each semiconductor channel (250, 350) may be physically exposed to a respective via cavity extending through the contact-level dielectric layer 70. In one embodiment, a first via cavity 741 selected from the via cavities may continuously extend between a first end portion of a first semiconductor channel 250 of a first memory transistor 221 and a first end portion of a second semiconductor channel 350 of a first non-hysteretic transistor 321; and a second via cavity 742 selected from the via cavities may continuously extend between a first end portion of a first semiconductor channel 250 of a second memory transistor 222 and a first end portion of a second semiconductor channel 350 of a second non-hysteretic transistor 322. The bottom surface of the via cavity may be formed above a horizontal plane including the top surface of a first gate electrode (including a first gate electrode plate 220).

[0077] At least one conductive material (e.g., at least one metal material) can be deposited in the via cavity. In one embodiment, the at least one conductive material can include a metal barrier material (e.g., TiN, TaN, MoN, WN, or a stack thereof) and a metal fill material (e.g., W, Ti, Ta, Co, Mo, Ru, Cu, etc.). The excess portion of the at least one conductive material can be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 70 by a planarization process (e.g., a chemical mechanical polishing process).

[0078] The remaining portion of the at least one conductive material that fills the first via cavity constitutes a first contact via structure 741, and the first contact via structure 741 serves as the first source / drain structure of the first memory transistor 221 and the first source / drain structure of the first non-hysteretic transistor 321 and provides an electrical connection between the first memory transistor 221 and the first non-hysteretic transistor 321. The remaining portion of the at least one conductive material that fills the second via cavity constitutes a second contact via structure 742, and the second contact via structure 742 serves as the first source / drain structure of the second memory transistor 222 and the first source / drain structure of the second non-hysteretic transistor 322 and provides an electrical connection between the second memory transistor 222 and the second non-hysteretic transistor 322.

[0079] Each via cavity that overlies the memory transistors (221, 222) and is not filled by the first contact via structure 741 or the second contact via structure 742 is filled by a third contact via structure 72, and the third contact via structure 72 serves as the second source / drain structure of the corresponding memory transistor (221, 222). Each via cavity that overlies the non-hysteretic transistors (321, 322) and is not filled by the first contact via structure 741 or the second contact via structure 742 can be filled by a fourth contact via structure 78, and the fourth contact via structure 78 serves as the second source / drain structure of the corresponding non-hysteretic transistor (321, 322). The four-transistor ternary content addressable memory cell C_mn can include a first contact via structure 741, a second contact via structure 742, two third contact via structures 72, and two fourth contact via structures 78.

[0080] Generally, a first memory transistor 221, a second memory transistor 222, a first non-hysteretic transistor 321, and a second non-hysteretic transistor 322 can be formed for a four-transistor ternary content addressable memory cell C_mn. The first memory transistor 221 includes a first memory component (such as a floating gate electrode 220 or a ferroelectric gate dielectric 230) configured to store a first binary bit, and the second memory transistor 222 includes a second memory component (such as a floating gate electrode 220 or a ferroelectric gate dielectric 230) configured to store a second binary bit. A first series connection portion of the first memory transistor 221 and the first non-hysteretic transistor 321 can be formed, for example, by a first contact via structure 741. A second series connection portion of the second memory transistor 222 and the second non-hysteretic transistor 322 can be formed, for example, by a second contact via structure 742. In one embodiment, the first contact via structure 741 can be directly formed on the first memory transistor 221 and the first non-hysteretic transistor 321 to provide the first series connection portion; and the second contact via structure 742 can be directly formed on the second memory transistor 222 and the second non-hysteretic transistor 322 to provide the second series connection portion.

[0081] In one embodiment, the first memory transistor 221 includes a first semiconductor channel 250; the first non-hysteretic transistor 321 includes a second semiconductor channel 350; and the first semiconductor channel 250 and the second semiconductor channel 350 have the same material composition and the same thickness. In one embodiment, the first memory transistor 221 includes a floating gate electrode (including a first gate electrode plate 220); the first non-hysteretic transistor 321 includes a non-floating gate electrode (including a second gate electrode plate 320); and the floating gate electrode (including the first gate electrode plate 220) and the non-floating gate electrode (including the second gate electrode plate 320) have the same material composition and the same thickness.

[0082] In one embodiment, the floating gate electrode (including the first gate electrode plate 220) is spaced apart from the top surface of a dielectric material layer (such as a lower via level dielectric layer 12 and / or a second interconnect level dielectric material layer 620) in a vertical direction by a backside gate dielectric 218, and the backside gate dielectric 218 contacts a first section of the top surface of the dielectric material layer; and the non-floating gate electrode (including the second gate electrode plate 320) contacts a second section of the top surface of the dielectric material layer. In one embodiment, the sidewalls of the floating gate electrode (including the first gate electrode plate 220) coincide with the sidewalls of the backside gate dielectric 218 in the vertical direction.

[0083] In one embodiment, the first memory transistor 221 includes a front gate dielectric 240 in contact with a first semiconductor channel 250 of the first memory transistor 221; the first non-hysteretic transistor 321 includes a non-hysteretic gate dielectric 340 in contact with a second semiconductor channel 350 of the first non-hysteretic transistor 321; and the front gate dielectric 240 and the non-hysteretic gate dielectric 340 have the same material composition and the same thickness. In one embodiment, one of the front gate dielectric 240 and the backside gate dielectric 218 includes a tunneling dielectric layer that provides charge tunneling therethrough; and the other of the front gate dielectric 240 and the backside gate dielectric 218 includes a blocking dielectric layer that inhibits charge tunneling therethrough.

[0084] In one embodiment, the first memory transistor 221 includes a first gate electrode (including a first gate electrode plate 220), a first gate dielectric (such as the front gate dielectric 240 or the ferroelectric gate dielectric 230), and a first semiconductor channel 250; and the sidewalls of the first gate electrode (including the first gate electrode plate 220), the sidewalls of the first gate dielectric (such as the front gate dielectric 240 or the ferroelectric gate dielectric 230), and the sidewalls of the first semiconductor channel 250 overlap each other in the vertical direction. In one embodiment, the first non-hysteretic transistor 321 includes a second gate electrode (including a second gate electrode plate 320), a second gate dielectric (such as the non-hysteretic gate dielectric 340), and a second semiconductor channel 350; the first semiconductor channel 250 and the second semiconductor channel 350 have the same semiconductor material composition and the same semiconductor material thickness; and the first gate electrode (including the first gate electrode plate 220) and the second gate electrode (including the second gate electrode plate 320) have the same conductive material composition and the same conductive material thickness.

[0085] In one embodiment, a first contact via structure 741 can be formed within a second dielectric material layer (such as a contact-level dielectric layer 70) and can contact each of the first non-hysteretic transistor 321 and the first memory transistor 221; and a second contact via structure 742 can be formed within the second dielectric material layer (such as a contact-level dielectric layer 70) and can contact each of the second non-hysteretic transistor 322 and the second memory transistor 222.

[0086] FIG. 6A to FIG. 6D Are various views of a region of a first exemplary structure after forming a via-level dielectric layer, connecting via structures, a line-level dielectric layer, and metal lines according to a first embodiment of the present disclosure. Fig. 6A Is a vertical cross-sectional view of the first memory transistor 221. Figure 6B Is a vertical cross-sectional view of the second memory transistor 222. Figure 6C Is a vertical cross-sectional view of the first non-hysteretic transistor 321. Fig.6Dis a vertical cross-sectional view of the second non-hysteretic transistor 322.

[0087] Collective reference Figure 1 With FIG. 6A to FIG. 6D , a via-level dielectric layer can be formed over the contact-level dielectric layer 70. The via-level dielectric layer is referred to herein as the upper via-level dielectric layer 80. Via cavities can be formed through the upper via-level dielectric layer 80 over the third contact via structure 72 and the fourth contact via structure 78 and can be filled with at least one conductive material to form the first connection via structure 82 and the second connection via structure 88. Each first connection via structure 82 can contact the top surface of a corresponding third contact via structure 72, and each second connection via structure 88 can contact the top surface of a corresponding fourth contact via structure 78.

[0088] A line-level dielectric layer 90 can be formed over the upper via-level dielectric layer 80. Line cavities can be formed through the line-level dielectric layer 90 such that the top surfaces of the connection via structures (82, 88) are physically exposed. A word line 92 and a match line 98 can be formed in the line cavities. The word line 92 can contact the top surface of the first connection via structure 82, and the match line 98 can contact the top surface of the second connection via structure 88. Generally, the match line 98 (MLm) and the word line 92 (WLm) can be formed such that a first series connection and a second series connection can be connected in parallel between the match line 98 (MLm) and the word line 92 (WLm). Thus, a four-transistor ternary content-addressable memory cell C_mn can be formed.

[0089] 7A to 7D are various views of a region of an alternative configuration of a first exemplary structure after the formation of a via-level dielectric layer, connection via structures, a line-level dielectric layer, and metal lines according to a first embodiment of the present disclosure. Fig. 7A is a vertical cross-sectional view of the first memory transistor 221. Figure 7B is a vertical cross-sectional view of the second memory transistor 222. Figure 7C is a vertical cross-sectional view of the first non-hysteretic transistor 321. Fig.7D is a vertical cross-sectional view of the second non-hysteretic transistor 322.

[0090] Collective reference Figure 1 With 7A to 7D , can be from FIG. 6A to FIG. 6DThe first alternative configuration of the first exemplary structure is obtained from the first exemplary structure shown. In various embodiments, the two ferroelectric transistors serving as memory transistors can be ferroelectric thin film transistors. In this embodiment, the first memory component configured to store the first binary bit in the first memory transistor 221 can include a first ferroelectric gate dielectric 230, and the second memory component configured to store the second binary bit in the second memory transistor 222 can include a second ferroelectric gate dielectric 230.

[0091] The first alternative configuration of the first exemplary structure can be formed by forming a first dielectric material layer (such as the lower via level dielectric layer 12 and / or the second interconnection level dielectric material layer 620) over the substrate 8. Figure 2 The first exemplary structure shown in FIG. 3A to FIG. 3D can be used without forming the lower via level dielectric layer 12 and the via hole structures (215, 315) shown in FIG. 3A to FIG. 3D As an alternative, the first exemplary structure shown in FIG. 3A to FIG. 3D can be used. A gate electrode material layer is formed over the first dielectric material layer (such as the lower via level dielectric layer 12 and / or the second interconnection level dielectric material layer 620). A ferroelectric dielectric layer is formed over the gate electrode material layer in the first region for forming the memory transistors (221, 222) without covering the second region for forming the non-hysteretic transistors (321, 322). A gate dielectric layer can be formed over the gate electrode material layer in the second region without covering the first region. Subsequently, a semiconductor material layer can be formed over the ferroelectric dielectric layer and the gate dielectric layer.

[0092] The gate electrode material layer can be the same as the gate electrode material layer described with reference to FIG. 4A to FIG. 4D Generally, any ferroelectric material known in the art can be used for the ferroelectric dielectric layer. For example, the ferroelectric dielectric layer includes, for example, the following ferroelectric dielectric materials and / or consists essentially of, for example, the following ferroelectric dielectric materials: titanium oxide (TiO2), lead zirconate titanate (Pb[Zr,Ti]O3 or PZT), barium titanate (BaTiO3), lead titanate (PbTiO3), lithium niobate (LiNbO3), strontium titanate (SrTiO3), potassium niobate (KNbO3), potassium sodium niobate (NaNbO3-KNbO3 or NKN), bismuth titanate (Bi4Ti3O 12 or BIT), lithium tantalate (LiTaO3), potassium titanyl phosphate (KTiOPO4 or KTP), lanthanum-doped lead zirconate titanate (Pb 1-x La x [Zr,Ti]O3 or PLZT), sodium tungstate (Na2WO4), calcium copper titanate (CaCu3Ti4O 12 or CCTO), potassium sodium bismuth titanate (K 0.5 Na0.5 Bi4Ti4O 15 or KNBT) and its doped derivatives. In one embodiment, the ferroelectric dielectric layer comprises a doped hafnium oxide layer and / or consists essentially of a doped hafnium oxide layer, the doped hafnium oxide layer being doped with at least one doping substance selected from Al, In, Si, Ge, alkaline earth metals (Mg, Sr, etc.), transition metals (Zr, Ta, etc.), and rare earth metals (Y, Gd, La, etc.). In one embodiment, the ferroelectric dielectric layer comprises a tantalum-doped hafnium oxide layer and / or consists essentially of a tantalum-doped hafnium oxide layer. The thickness of the ferroelectric dielectric layer can range from 1 nanometer to 100 nanometers, but smaller and larger thicknesses can also be used. The gate dielectric layer can comprise any gate dielectric material known in the art. The semiconductor material layer can be the same as the semiconductor material layer described with reference to FIG. 4A to FIG. 4D The semiconductor material layer described is the same.

[0093] The semiconductor material layer, the gate dielectric layer, the ferroelectric dielectric layer, and the gate electrode material layer can be patterned to form a first layer stack of a first gate electrode plate 220, a ferroelectric gate dielectric 230, and a first semiconductor channel 250 in each region for the memory transistors (221, 222); and a second layer stack of a second gate electrode plate 320, a non-hysteretic gate dielectric 340, and a second semiconductor channel 350 in each region for the non-hysteretic transistors (321, 322). Thus, the first memory transistor 221 and the second memory transistor 222 include a first patterned portion of the semiconductor material layer, a first patterned portion of the gate electrode material layer, and a patterned portion of the ferroelectric dielectric layer, and the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322 include a second patterned portion of the semiconductor material layer, a second patterned portion of the gate electrode material layer, and a patterned portion of the gate dielectric layer.

[0094] Subsequently, the processing steps described with reference to FIG. 5A to FIG. 5D and FIG. 6A to FIG. 6D can be performed to form the four-transistor ternary content-addressable memory cell C_mn. A first series connection of the first memory transistor 221 (including the first ferroelectric thin-film transistor) and the first non-hysteretic transistor 321 can be formed; and a second series connection of the second memory transistor 222 (including the second ferroelectric thin-film transistor) and the second non-hysteretic transistor 322 can be formed. A match line MLm and a word line WLm can be formed. The first series connection and the second series connection can be connected in parallel between the match line 98 (MLm) and the word line 92 (WLm).

[0095] In 7A to 7DIn an alternative configuration of the first exemplary structure shown, the first memory transistor 221 includes a ferroelectric gate dielectric 230, a first semiconductor channel 250, and a first gate electrode (including a first gate electrode plate 220); and the first non-hysteretic transistor 321 includes a non-hysteretic gate dielectric 340, a second semiconductor channel 350, and a second gate electrode (including a second gate electrode plate 320). In one embodiment, the first memory transistor 221 includes a first gate electrode (including a first gate electrode plate 220), a first gate dielectric (such as a ferroelectric gate dielectric 230), and a first semiconductor channel 250; and the sidewalls of the first gate electrode (including the first gate electrode plate 220), the sidewalls of the first gate dielectric (such as a front gate dielectric 240 or a ferroelectric gate dielectric 230), and the sidewalls of the first semiconductor channel 250 overlap each other in the vertical direction.

[0096] Generally, the first memory transistor 221, the second memory transistor 222, the first non-hysteretic transistor 321, and the second non-hysteretic transistor 322 can be formed over a substrate 8. Each of the memory transistors (221, 222) and the non-hysteretic transistors (321, 322) can be a thin film transistor. The first memory transistor 221 includes a first memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a first binary bit, and the second memory transistor 222 includes a second memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a second binary bit.

[0097] Figure 8 is a schematic diagram of a device structure including a four-transistor ternary content addressable memory cell C_mn, the four-transistor ternary content addressable memory cell C_Mn using the example of a transistor described with reference to FIG. 6A to FIG. 6D or using the example of a transistor described with reference to 7A to 7D described.

[0098] Collectively referring to Figure 1 , FIG. 6A to FIG. 6D , 7A to 7D and Figure 8, for each four-transistor ternary content addressable memory cell C_mn, the main bit line BLn is connected to (and thus, electrically shorted to (i.e., electrically coupled to)) the gate electrode (including the first gate electrode plate 220) of the first memory transistor 221; and the complementary bit line BLn* is connected to (and thus, electrically shorted to (i.e., electrically coupled to)) the gate electrode (including another first gate electrode plate 220) of the second memory transistor 222 and is configured to be biased with a complementary voltage of the voltage at the main bit line BLn. For each four-transistor ternary content addressable memory cell C_mn, the main search line SLn is connected to (and thus, electrically shorted to (i.e., electrically coupled to)) the gate electrode of the second non-hysteretic transistor 322; and the complementary search line SLn* is connected to (and thus, electrically shorted to (i.e., electrically coupled to)) the gate electrode of the first non-hysteretic transistor 321.

[0099] 9A to 16C Illustrates a manufacturing sequence for forming a second exemplary structure, which can be obtained from the first exemplary structure by re-arranging the layout of the various components in the first exemplary structure shown in Figures 2 to 7D Although the second exemplary structure is illustrated for an embodiment in which the memory transistors (221, 222) are formed as flash memory transistors, embodiments in which the memory transistors (221, 222) are formed as ferroelectric memory transistors as described with reference to 7A to 7D are expressly contemplated herein.

[0100] Fig. 9A and Fig. 9B are views of regions of a second exemplary structure after forming the search lines and bit lines, according to a second embodiment of the present disclosure. Fig. 9A is a vertical cross-sectional view. Fig. 9B is a top view. Fig. 9B The vertical plane A-A' in Fig. 9A is the cutting plane of the vertical cross-sectional view shown.

[0101] Referring to Fig. 9A and Fig. 9B , the second exemplary structure can be obtained from the first exemplary structure by modifying the layout of the main search line SLn, the complementary search line SLn*, the main bit line BLn, and the complementary bit line BLn*. Specifically, the main search line SLn, the complementary search line SLn*, the main bit line BLn, and the complementary bit line BLn* can be formed as a second metal line structure 628, which is formed within the second interconnection level dielectric material layer 620, spaced laterally along a first horizontal direction hd1, and extending laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Figure 2

[0102] The pitch of the second metal line structure 628 serving as the main search line SLn, complementary search line SLn*, main bit line BLn, and complementary bit line BLn* can be uniform and can be approximately four times the width of the second metal line structure 628 along the first horizontal direction hd1. The width of each second metal line structure 628 can range from 10 nanometers to 200 nanometers (e.g., from 20 nanometers to 60 nanometers), but smaller and larger widths can also be used. The lateral dimension of the unit cell UC along the first horizontal direction hd1 can be four times the pitch of the second metal line structure 628 along the first horizontal direction hd1. The lateral dimension of the unit cell UC along the second horizontal direction hd2 can be twice the pitch of the metal line structure that will subsequently be formed into the word line and match line, and can be approximately four times the width of each metal line structure that will subsequently be used as the word line and match line. The transistors for the unit cell UC can then be formed as a 4×1 array of thin film transistors.

[0103] Fig. 10A and Fig. 10B is a view of a region of a second exemplary structure after forming the back gate dielectric layer according to the second embodiment of the present disclosure. Fig. 10A is a vertical cross-sectional view. Fig. 10B is a top view. Fig. 10B The vertical plane A-A’ in Fig. 10A is the cutting plane of the vertical cross-sectional view shown.

[0104] Referring to FIG. 10A to FIG. 10B , a first subset of the processing steps described with reference to FIG. 4A to FIG. 4D can be performed to form the back gate dielectric layer 218L. Generally, a first dielectric material layer (e.g., the lower via level dielectric layer 12 and / or the second interconnection level dielectric material layer 620) can be formed on the substrate 8. In the second embodiment, the first dielectric material layer can be the second interconnection level dielectric material layer 620. The back gate dielectric layer 218L can be formed on the first region of the first dielectric material layer without covering the second region of the first dielectric material layer (e.g., the second interconnection level dielectric material layer 620). Specifically, the first region is the region that will subsequently be used to form the memory transistors (221, 222) and covers the entire main bit line BLn and complementary bit line BLn*. The second region is the region that will subsequently be used to form the non-hysteresis transistors (321, 322) and covers the entire main search line SLn and complementary search line SLn*.

[0105] Fig.11A and Fig. 11B is a view of a region of a second exemplary structure after forming the patterned layer stack according to the second embodiment of the present disclosure. Fig.11A is a vertical cross-sectional view. Fig. 11B is a top view. Fig. 11B The vertical plane A-A’ in Fig.11A is the cutting plane of the vertical cross-sectional view shown.

[0106] With common reference to Figure 1 , Figure 8 , Fig.11A and Fig. 11B , a second subset of the processing steps described with reference to FIG. 4A to FIG. 4D can be executed to form a layer stack of a gate electrode material layer, a front gate dielectric layer, and a semiconductor material layer in the first region and the second region (i.e., in the entire region for forming a four-transistor ternary content-addressable memory array). The layer stack and the back gate dielectric layer can be patterned to form the patterned layer stack described with reference to FIG. 4A to FIG. 4D .

[0107] As discussed with reference to FIG. 4A to FIG. 4D , the layer stack and the back gate dielectric layer can be patterned by, for example, applying a photoresist layer over the semiconductor material layer and patterning the photoresist layer and performing an anisotropic etching process that transfers the pattern in the photoresist layer through the layer stack and the back gate dielectric layer. A first patterned portion of the layer stack and a patterned portion of the back gate dielectric layer are formed in the regions for the first memory transistor 221 and the second memory transistor 222. A second patterned portion of the layer stack is formed in the regions for the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322.

[0108] A first vertical stack of a back gate dielectric 218, a first gate electrode plate 220, a front gate dielectric 240, and a first semiconductor channel 250 can be formed in each region for the first memory transistor 221 and the second memory transistor 222. The sidewalls of the back gate dielectric 218, the sidewalls of the first gate electrode plate 220, the sidewalls of the front gate dielectric 240, and the sidewalls of the first semiconductor channel 250 can coincide with each other in the vertical direction within each first vertical stack. A second vertical stack of a second gate electrode plate 320, a non-hysteretic gate dielectric 340, and a second semiconductor channel 350 can be formed in each region for the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322. The sidewalls of the second gate electrode plate 320, the sidewalls of the non-hysteretic gate dielectric 340, and the sidewalls of the second semiconductor channel 350 can coincide with each other in the vertical direction within each second vertical stack.

[0109] Each back gate dielectric 218 can be a patterned portion of the back gate dielectric layer 218L and can always have a uniform thickness. Each first gate electrode plate 220 and each second gate electrode plate 320 are patterned portions of a gate electrode material layer and can have the same conductive material composition and the same thickness. Each front gate dielectric 240 and each non-hysteretic gate dielectric 340 are patterned portions of a front gate dielectric layer and can have the same dielectric material composition and the same thickness. Each first semiconductor channel 250 and each second semiconductor channel 350 are patterned portions of a semiconductor material layer and can have the same semiconductor material composition and the same thickness.

[0110] The first memory transistor 221 and the second memory transistor 222 include a first patterned portion of the layer stack and a patterned portion of the back gate dielectric layer, and the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322 include a second patterned portion of the layer stack.

[0111] Fig. 12A and Fig. 12B is a view of a region of a second exemplary structure after forming a contact-level dielectric layer according to a second embodiment of the present disclosure. Fig. 12A is a vertical cross-sectional view. Fig. 12B is a top view. Fig. 12B The vertical plane A-A' in Fig. 12A is the cutting plane of the vertical cross-sectional view shown.

[0112] Referring to Fig. 12A and Fig. 12B it is possible to perform a first subset of the processing steps described with reference to FIG. 5A to FIG. 5D to form the contact-level dielectric layer 70.

[0113] Fig.13A and Fig. 13B is a view of a region of a second exemplary structure after forming a contact via structure according to a second embodiment of the present disclosure. Fig.13A is a vertical cross-sectional view. Fig. 13B is a top view. Fig. 13B The vertical plane A-A' in Fig.13A is the cutting plane of the vertical cross-sectional view shown.

[0114] Referring to Fig.13A and Fig. 13B it is possible to perform a first subset of the processing steps described with reference to FIG. 5A to FIG. 5DA second subset of the described processing steps is performed to form various contact via structures (741, 742, 72, 78). The various contact via structures (741, 742, 72, 78) serve as source / drain structures for the various transistors (221, 222, 321, 322). Generally, a first memory transistor 221, a second memory transistor 222, a first non-hysteretic transistor 321, and a second non-hysteretic transistor 322 can be formed. The first memory transistor 221 includes a first memory component (e.g., Fig. 7A and Figure 7B the floating gate electrode or ferroelectric gate dielectric 230 shown in Fig. 7A and Figure 7B ) configured to store a first binary digit, and the second memory transistor 222 includes a second memory component (e.g.,

[0115] the floating gate electrode or ferroelectric gate dielectric 230 shown in Fig. 7A and Figure 7B ) configured to store a second binary digit.

[0115] A first series connection of the first memory transistor 221 and the first non-hysteretic transistor 321 can be formed by the first contact via structure 741. A second series connection of the second memory transistor 222 and the second non-hysteretic transistor 322 can be formed by the second contact via structure 742. The first contact via structure 741 can be formed directly on the first memory transistor 221 and the first non-hysteretic transistor 321 to provide the first series connection; and the second contact via structure 742 can be formed directly on the second memory transistor 222 and the second non-hysteretic transistor 322 to provide the second series connection.

[0116] In a second exemplary structure, the first memory transistor 221 and the first non-hysteretic transistor 321 are adjacent transistors laterally spaced apart along a first horizontal direction hd1 within a unit cell UC, and the first contact via structure 741 serves as a first source / drain structure for the first memory transistor 221 and a first source / drain structure for the first non-hysteretic transistor 321. The first contact via structure 741 also serves as a conductive path connecting the first source / drain structure of the first memory transistor 221 and the first source / drain structure of the first non-hysteretic transistor 321.

[0117] In addition, the second memory transistor 222 and the second non-hysteretic transistor 322 are adjacent transistors laterally spaced apart along the first horizontal direction hd1 within the unit cell UC, and the second contact via structure 742 serves as a first source / drain structure for the second memory transistor 222 and a first source / drain structure for the second non-hysteretic transistor 322. The second contact via structure 742 also serves as a conductive path connecting the first source / drain structure of the second memory transistor 222 and the first source / drain structure of the second non-hysteretic transistor 322.

[0118] In one embodiment, the first memory transistor 221 includes a first semiconductor channel 250; the first non-hysteretic transistor 321 includes a second semiconductor channel 350; and the first semiconductor channel 250 and the second semiconductor channel 350 have the same material composition and the same thickness. In one embodiment, the first memory transistor 221 includes a floating gate electrode (including a first gate electrode plate 220); the first non-hysteretic transistor 321 includes a non-floating gate electrode (including a second gate electrode plate 320); and the floating gate electrode (including the first gate electrode plate 220) and the non-floating gate electrode (including the second gate electrode plate 320) have the same material composition and the same thickness.

[0119] In one embodiment, the floating gate electrode (including the first gate electrode plate 220) is spaced apart from the top surface of the dielectric material layer (such as the second interconnect level dielectric material layer 620) in a vertical direction by a backside gate dielectric 218, and the backside gate dielectric 218 contacts a first section of the top surface of the dielectric material layer; and the non-floating gate electrode (including the second gate electrode plate 320) contacts a second section of the top surface of the dielectric material layer. In one embodiment, the sidewalls of the floating gate electrode (including the first gate electrode plate 220) coincide with the sidewalls of the backside gate dielectric 218 in a vertical direction.

[0120] In one embodiment, the first memory transistor 221 includes a front gate dielectric 240 in contact with the first semiconductor channel 250 of the first memory transistor 221; the first non-hysteretic transistor 321 includes a non-hysteretic gate dielectric 340 in contact with the second semiconductor channel 350 of the first non-hysteretic transistor 321; and the front gate dielectric 240 and the non-hysteretic gate dielectric 340 have the same material composition and the same thickness. In one embodiment, one of the front gate dielectric 240 and the backside gate dielectric 218 includes a tunneling dielectric layer that provides charge tunneling therethrough; and the other of the front gate dielectric 240 and the backside gate dielectric 218 includes a blocking dielectric layer that inhibits charge tunneling therethrough.

[0121] FIG. 14A to FIG. 14C is a view of a region of a second exemplary structure after forming a via level dielectric layer and a connecting via structure according to a second embodiment of the present disclosure. Fig.14A is a first vertical cross-sectional view. Fig. 14B is a top view. Fig. 14C is a second vertical cross-sectional view. Fig. 14B The vertical plane A-A' in Fig.14A is the cutting plane of the vertical cross-sectional view shown. Fig. 14B The vertical plane C-C' in Fig. 14C is the cutting plane of the vertical cross-sectional view shown.

[0122] Reference FIG. 14A to FIG. 14C , a first subset of the processing steps described in the reference 7A to 7D may be executed to form the upper via-level dielectric layer 80. Via cavities may be formed through the upper via-level dielectric layer 80 above the third contact via structure 72 and the fourth contact via structure 78 and may be filled with at least one conductive material to form the first connection via structure 82 and the second connection via structure 88. Each first connection via structure 82 may contact the top surface of a corresponding third contact via structure 72, and each second connection via structure 88 may contact the top surface of a corresponding fourth contact via structure 78.

[0123] FIG. 15A to FIG. 15C is a view of a region of a second exemplary structure after forming the line-level dielectric layer, the matching line MLm, and the word line WLm according to a second embodiment of the present disclosure. Fig.15A is a first vertical cross-sectional view. Fig. 15B is a top view. Fig. 15C is a second vertical cross-sectional view. Fig. 15B The vertical plane A-A' in Fig.15A is the cutting plane of the vertical cross-sectional view shown. Fig. 15B The vertical plane C-C' in Fig. 15C is the cutting plane of the vertical cross-sectional view shown.

[0124] Reference Figure 1 , Figure 8 and FIG. 15A to FIG. 15C , a second subset of the processing steps described in the reference 7A to 7D may be executed to form the line-level dielectric layer 90 above the upper via-level dielectric layer 80. Line cavities may be formed through the line-level dielectric layer 90 such that the top surfaces of the connection via structures (82, 88) are physically exposed. A word line 92 and a matching line 98 may be formed in the line cavities. The word line 92 may contact the top surface of the first connection via structure 82, and the matching line 98 may contact the top surface of the second connection via structure 88. Generally, the matching line 98 and the word line 92 may be formed such that the first series connection portion 741 and the second series connection portion 742 may be connected in parallel between the matching line 98 and the word line 92 within each unit cell UC. Four-transistor ternary content-addressable memory cells C_mn may be formed within each unit cell. FIG. 15A to FIG. 15CShows three unit cells electrically connected to the (m - 1)th character line WL(m - 1), the (m - 1)th matching line ML(m - 1), the mth character line WLm, the mth matching line MLm, the (m + 1)th character line WL(m + 1), and the (m + 1)th matching line ML(m + 1). In one embodiment, each matching line 98 and each character line 92 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2. In one embodiment, the matching line 98 and the character line 92 may include a third metal line structure, and the line-level dielectric layer 90 may be used as a component of the third interconnection-level dielectric material layer.

[0125] Generally, a four-transistor ternary content-addressable memory cell C_mn can be formed by forming the matching line MLm and the character line WLm and by connecting the first series connection portion 741 and the second series connection portion 742 in parallel between the matching line MLm and the character line WLm. In one embodiment, the main bit line BLn may be connected to the gate electrode (including the first gate electrode plate 220) of the first memory transistor 221; and the complementary bit line BLn* may be connected to the gate electrode (including another first gate electrode plate 220) of the second memory transistor 222. In one embodiment, the main search line SLn may be connected to the gate electrode of the second non-hysteretic transistor 322; and the complementary search line SLn* may be connected to the gate electrode of the first non-hysteretic transistor 321.

[0126] FIG. 16A to FIG. 16C Is a view of a region of an alternative configuration of a second exemplary structure after forming the line-level dielectric layer, the matching line MLm, and the character line WLm according to the second embodiment of the present disclosure. Fig.16A Is a first vertical cross-sectional view. Fig. 16B Is a top view. Fig. 16C Is a second vertical cross-sectional view. Fig. 16B The vertical plane A - A’ in Fig.16A Is the cutting plane of the vertical cross-sectional view shown. Fig. 16B The vertical plane C - C’ in Fig. 16C Is the cutting plane of the vertical cross-sectional view shown.

[0127] Refer to FIG. 16A to FIG. 16C, an alternative configuration of the second exemplary structure can be obtained from the second exemplary structure by a single third contact via structure 72 that forms contact with the second end portion of the first semiconductor channel 250 of the first memory transistor 221 and with the second end portion of the first semiconductor channel 250 of the second memory transistor 222. In this embodiment, the unit cell includes a first contact via structure 741, a second contact via structure 742, a third contact via structure 72, and two fourth contact via structures 78. In this embodiment, a single first connection via structure 82 can be used to electrically connect the third contact via structure 72 to the word line 92. The third contact via structure 72 serves as the second source / drain structure of the first memory transistor 221 and the second source / drain structure of the second memory transistor 222. In addition, the third contact via structure 72 provides a conductive path between the second source / drain structure of the first memory transistor 221 and the second source / drain structure of the second memory transistor 222.

[0128] FIG. 17A to FIG. 25E Shows the manufacturing sequence for forming the third exemplary structure, which can be obtained from the first exemplary structure by rearranging the layout of the various components in the first exemplary structure shown in Figures 2 to 7D . Although the third exemplary structure is shown for an embodiment in which the memory transistors (221, 222) are formed as flash transistors, embodiments in which the memory transistors (221, 222) are formed as ferroelectric memory transistors as described with reference to 7A to 7D are expressly contemplated herein.

[0129] FIG. 17A to FIG. 17C is a view of a region of the third exemplary structure after forming the search line and the bit line according to the third embodiment of the present disclosure. Fig.17A is a first vertical cross-sectional view. Fig. 17B is a top view. Fig. 17C is a second vertical cross-sectional view. Fig. 17B The vertical plane A-A' in Fig.17A is the cutting plane of the vertical cross-sectional view shown. Fig. 17B The vertical plane C-C' in Fig. 17C is the cutting plane of the vertical cross-sectional view shown.

[0130] Referring to FIG. 17A to FIG. 17C , it can be obtained from Figure 2The first exemplary structure shown in results in the third exemplary structure. Specifically, the main search lines SLn, complementary search lines SLn*, main bit lines BLn, and complementary bit lines BLn* may be formed as a second metal line structure 628 that is formed within the second interconnection level dielectric material layer 620, is laterally spaced along a first horizontal direction hd1, and extends laterally along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1.

[0131] The pitch of the second metal line structure 628 serving as the main search lines SLn, complementary search lines SLn*, main bit lines BLn, and complementary bit lines BLn* may be uniform and may be approximately twice the width of the second metal line structure 628 along the first horizontal direction hd1. The width of each second metal line structure 628 may be in the range from 10 nanometers to 200 nanometers (e.g., from 20 nanometers to 60 nanometers), although smaller and larger widths may also be used. The lateral dimension of the unit cell UC along the first horizontal direction hd1 may be four times the pitch of the second metal line structure 628 along the first horizontal direction hd1. The lateral dimension of the unit cell UC along the second horizontal direction hd2 may be twice the pitch of the metal line structures that are subsequently to be formed as word lines and match lines and may be approximately eight times the width of each metal line structure to be used as word lines and match lines. The transistors for the unit cell UC may then be formed as a 2×2 array of thin film transistors.

[0132] 18A to 18C is a view of a region of the third exemplary structure after forming the via level dielectric layer and via hole structures, in accordance with a third embodiment of the present disclosure. Fig.18A is a first vertical cross-sectional view. Fig.18B is a top view. Fig.18C is a second vertical cross-sectional view. Fig.18B The vertical plane A-A' in is Fig.18A the cutting plane of the vertical cross-sectional view shown in . Fig.18B The vertical plane C-C' in is Fig.18C the cutting plane of the vertical cross-sectional view shown in .

[0133] Referring to 18A to 18C and, reference may be made to FIG. 3A to FIG. 3DThe described processing steps form a first via structure 215 and a second via structure 315 formed within a first dielectric material layer (which may include a lower via level dielectric layer 12). Thus, the first via structure 215 and the second via structure 315 may be formed within the first dielectric material layer (e.g., the lower via level dielectric layer 12). The first via structure 215 and the second via structure 315 may be alternated along a second horizontal direction. Each first via structure 215 may be formed directly on a main bit line BLn or directly on a complementary bit line BLn*. Each second via structure 315 may be formed directly on a main search line SLn or directly on a complementary search line SLn*.

[0134] FIG. 19A to FIG. 19C is a view of a region of a third exemplary structure after forming a back gate dielectric layer according to a third embodiment of the present disclosure. Fig.19A is a first vertical cross-sectional view. Fig.19B is a top view. Fig.19C is a second vertical cross-sectional view. Fig.19B The vertical plane A-A' in Fig.19A is the cutting plane of the vertical cross-sectional view shown. Fig.19B The vertical plane C-C' in Fig.19C is the cutting plane of the vertical cross-sectional view shown.

[0135] Referring to FIG. 19A to FIG. 19C and, a first subset of the processing steps described in FIG. 4A to FIG. 4D may be performed to form a back gate dielectric layer 218L. Generally, a first dielectric material layer (e.g., a lower via level dielectric layer 12 and / or a second interconnection level dielectric material layer 620) may be formed over a substrate 8. In the third embodiment, the first dielectric material layer may be the lower via level dielectric layer 12. The back gate dielectric layer 218L may be formed by depositing a blanket gate dielectric layer and patterning the blanket gate dielectric layer to cover each first region of the first dielectric material layer (e.g., the lower via level dielectric layer 12) without covering any second region of the first dielectric material layer. Specifically, the first regions are then regions for forming memory transistors (221, 222) and include strip regions overlapping corresponding sets of the first via structures 215. The second regions are regions for forming non-hysteretic transistors (321, 322) and include strip regions overlapping corresponding subsets of the second via structures 315.

[0136] Accordingly, the back gate dielectric layer 218L can be formed as discrete strips that have a uniform width along the second horizontal direction hd2 and extend laterally along the first horizontal direction hd1. The back gate dielectric layer 218L covers each of the first vias structures 215 and does not cover any of the second vias structures 315. The back gate dielectric layer 218L is formed directly on the first vias structures 215 and does not cover the second vias structures 315.

[0137] FIG. 20A to FIG. 20C is a view of a region of a third exemplary structure after formation of a patterned layer stack, in accordance with a third embodiment of the present disclosure. Fig. 20A is a first vertical cross-sectional view. Fig. 20B is a top view. Fig. 20C is a second vertical cross-sectional view. Fig. 20B The vertical plane A-A’ in Fig. 20A is the cutting plane of the vertical cross-sectional view shown. Fig. 20B The vertical plane C-C’ in Fig. 20C is the cutting plane of the vertical cross-sectional view shown.

[0138] With joint reference to Figure 1 , Figure 8 and FIG. 20A to FIG. 20C , a second subset of the processing steps set forth with reference to FIG. 4A to FIG. 4D can be performed to form a layer stack of a gate electrode material layer, a front gate dielectric layer, and a semiconductor material layer in the first region and the second region (i.e., in the entire region for forming a four-transistor ternary content-addressable memory array). The gate electrode material layer is formed directly on the second vias structures 315 and is spaced apart from the first vias structures 215. The layer stack and the back gate dielectric layer can be patterned to form the patterned layer stack set forth with reference to FIG. 4A to FIG. 4D .

[0139] As discussed with reference to FIG. 4A to FIG. 4D , the layer stack and the back gate dielectric layer can be patterned by, for example, applying a photoresist layer over the semiconductor material layer and patterning the photoresist layer and performing an anisotropic etching process that transfers the pattern in the photoresist layer through the layer stack and the back gate dielectric layer. The first patterned portion of the layer stack and the patterned portion of the back gate dielectric layer are formed in the regions for the first memory transistor 221 and the second memory transistor 222. The second patterned portion of the layer stack is formed in the regions for the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322.

[0140] A first vertical stack of a back gate dielectric 218, a first gate electrode plate 220, a front gate dielectric 240, and a first semiconductor channel 250 can be formed within each region for the first memory transistor 221 and the second memory transistor 222. Sidewalls of the back gate dielectric 218, sidewalls of the first gate electrode plate 220, sidewalls of the front gate dielectric 240, and sidewalls of the first semiconductor channel 250 can coincide with each other in a vertical direction within each first vertical stack. A second vertical stack of a second gate electrode plate 320, a non-hysteretic gate dielectric 340, and a second semiconductor channel 350 can be formed within each region for the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322. Sidewalls of the second gate electrode plate 320, sidewalls of the non-hysteretic gate dielectric 340, and sidewalls of the second semiconductor channel 350 can coincide with each other in a vertical direction within each second vertical stack.

[0141] Each back gate dielectric 218 is a patterned portion of the back gate dielectric layer 218L and can always have a uniform thickness. Each first gate electrode plate 220 and each second gate electrode plate 320 are patterned portions of a gate electrode material layer and can have the same conductive material composition and the same thickness. Each front gate dielectric 240 and each non-hysteretic gate dielectric 340 are patterned portions of a front gate dielectric layer and can have the same dielectric material composition and the same thickness. Each first semiconductor channel 250 and each second semiconductor channel 350 are patterned portions of a semiconductor material layer and can have the same semiconductor material composition and the same thickness.

[0142] The first memory transistor 221 and the second memory transistor 222 include a first patterned portion of a layer stack and a patterned portion of the back gate dielectric layer, and the first non-hysteretic transistor 321 and the second non-hysteretic transistor 322 include a second patterned portion of a layer stack. Each second vias structure 315 can contact a peripheral portion of a bottom surface of a corresponding second gate electrode plate 320 and is eccentric with respect to the corresponding second gate electrode plate 320 in a plan view. Each first vias structure 215 can contact a peripheral portion of a bottom surface of a corresponding back gate dielectric 218 and is eccentric with respect to the corresponding back gate dielectric 218 in a plan view.

[0143] FIG. 21A to FIG. 21C is a view of a region of a third exemplary structure after forming a contact level dielectric layer and a contact via structure according to a third embodiment of the present disclosure. Fig.21A is a first vertical cross-sectional view. Fig. 21B is a top view. Fig. 21C is a second vertical cross-sectional view. Fig. 21B The vertical plane A-A’ in Fig.21A is a cutting plane of the vertical cross-sectional view shown. Fig. 21BThe vertical plane C-C’ in Fig. 21C is the sectional plane of the vertical sectional view shown.

[0144] With joint reference Figure 1 、 Figure 8 and FIG. 21A to FIG. 21C ,a second subset of the processing steps described in FIG. 5A to FIG. 5D can be executed to form various contact via structures (741, 742, 72, 78). The various contact via structures (741, 742, 72, 78) serve as source / drain structures for the various transistors (221, 222, 321, 322). Generally, a first memory transistor 221, a second memory transistor 222, a first non-hysteretic transistor 321 and a second non-hysteretic transistor 322 can be formed. The first memory transistor 221 includes a first memory component (such as Fig. 7A and Figure 7B the floating gate electrode or ferroelectric gate dielectric 230 shown in Fig. 7A and Figure 7B ) configured to store a first binary digit, and the second memory transistor 222 includes a second memory component (such as

[0145] the floating gate electrode or ferroelectric gate dielectric 230 shown in

[0146] A first series connection of the first memory transistor 221 and the first non-hysteretic transistor 321 can be formed by the first contact via structure 741. A second series connection of the second memory transistor 222 and the second non-hysteretic transistor 322 can be formed by the second contact via structure 742. The first contact via structure 741 can be directly formed on the first memory transistor 221 and the first non-hysteretic transistor 321 to provide the first series connection; and the second contact via structure 742 can be directly formed on the second memory transistor 222 and the second non-hysteretic transistor 322 to provide the second series connection.

[0147] In addition, the second memory transistor 222 and the second non-hysteretic transistor 322 are neighboring transistors that are laterally spaced apart along a second horizontal direction hd2 within the unit cell UC, and the second contact via structure 742 serves as the first source / drain structure of the second memory transistor 222 and the first source / drain structure of the second non-hysteretic transistor 322. The second contact via structure 742 also serves as a conductive path for connecting the first source / drain structure of the second memory transistor 222 and the first source / drain structure of the second non-hysteretic transistor 322.

[0148] In one embodiment, the first memory transistor 221 includes a first semiconductor channel 250; the first non-hysteretic transistor 321 includes a second semiconductor channel 350; and the first semiconductor channel 250 and the second semiconductor channel 350 have the same material composition and the same thickness. In one embodiment, the first memory transistor 221 includes a floating gate electrode (including a first gate electrode plate 220); the first non-hysteretic transistor 321 includes a non-floating gate electrode (including a second gate electrode plate 320); and the floating gate electrode (including the first gate electrode plate 220) and the non-floating gate electrode (including the second gate electrode plate 320) have the same material composition and the same thickness.

[0149] In one embodiment, the floating gate electrode (including the first gate electrode plate 220) is vertically spaced apart from the top surface of the dielectric material layer (such as the lower via level dielectric layer 12) by a backside gate dielectric 218, and the backside gate dielectric 218 contacts a first section of the top surface of the dielectric material layer; and the non-floating gate electrode (including the second gate electrode plate 320) contacts a second section of the top surface of the dielectric material layer. In one embodiment, the sidewalls of the floating gate electrode (including the first gate electrode plate 220) coincide vertically with the sidewalls of the backside gate dielectric 218.

[0150] In one embodiment, the first memory transistor 221 includes a front gate dielectric 240 that contacts the first semiconductor channel 250 of the first memory transistor 221; the first non-hysteretic transistor 321 includes a non-hysteretic gate dielectric 340 that contacts the second semiconductor channel 350 of the first non-hysteretic transistor 321; and the front gate dielectric 240 and the non-hysteretic gate dielectric 340 have the same material composition and the same thickness. In one embodiment, one of the front gate dielectric 240 and the backside gate dielectric 218 includes a tunneling dielectric layer that provides charge tunneling therethrough; and the other of the front gate dielectric 240 and the backside gate dielectric 218 includes a blocking dielectric layer that inhibits charge tunneling therethrough.

[0151] FIG. 22A to FIG. 22CA view of a region of a third exemplary structure after forming a via-level dielectric layer and connecting via structures, according to a third embodiment of the present disclosure. Fig.22A Is a first vertical cross-sectional view. Fig. 22B Is a top view. Fig. 22C Is a second vertical cross-sectional view. Fig. 22B The vertical plane A-A' in Fig.22A Is the cutting plane of the vertical cross-sectional view shown. Fig. 22B The vertical plane C-C' in Fig. 22C Is the cutting plane of the vertical cross-sectional view shown.

[0152] Referring to Figures 22A to 22C , a first subset of the processing steps described with reference to Figures 7A to 7D May be performed to form an upper via-level dielectric layer 80. Via cavities may be formed through the upper via-level dielectric layer 80 above the third contact via structure 72 and the fourth contact via structure 78 and may be filled with at least one conductive material to form a first connecting via structure 82 and a second connecting via structure 88. Each first connecting via structure 82 may contact the top surface of a corresponding third contact via structure 72, and each second connecting via structure 88 may contact the top surface of a corresponding fourth contact via structure 78.

[0153] Figures 23A to 23C A view of a region of a third exemplary structure after forming a line-level dielectric layer, word lines WLm, and match lines MLm, according to a third embodiment of the present disclosure. Figure 23A Is a first vertical cross-sectional view. Figure 23B Is a top view. Figure 23C Is a second vertical cross-sectional view. Figure 23B The vertical plane A-A' in Figure 23A Is the cutting plane of the vertical cross-sectional view shown. Figure 23B The vertical plane C-C' in Figure 23C Is the cutting plane of the vertical cross-sectional view shown.

[0154] Referring to Figure 1 , Figure 8 And Figures 23A to 23C , a first subset of the processing steps described with reference to Figures 7A to 7DA second subset of the processing steps described forms the line-level dielectric layer 90 over the upper via-level dielectric layer 80. A line cavity may be formed through the line-level dielectric layer 90 such that the top surfaces of the connection via structures (82, 88) are physically exposed. A word line 92 and a match line 98 may be formed in the line cavity. The word line 92 may contact the top surface of the first connection via structure 82, and the match line 98 may contact the top surface of the second connection via structure 88. Generally, the match line 98 and the word line 92 may be formed such that the first series connection portion 741 and the second series connection portion 742 may be connected in parallel between the match line 98 and the word line 92 within each unit cell UC. A four-transistor ternary content-addressable memory cell C_mn may be formed within each unit cell. Figures 23A to 23C Shows a portion of a unit cell electrically connected to the (m-1)th match line ML(m-1), a unit cell UC electrically connected to the mth word line WLm and the mth match line MLm, and a portion of a unit cell electrically connected to the (m+1)th word line WL(m+1). In one embodiment, each match line 98 and each word line 92 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2. In one embodiment, the match line 98 and the word line 92 may include a third metal line structure, and the line-level dielectric layer 90 may serve as a component of a third interconnection-level dielectric material layer.

[0155] Generally, a four-transistor ternary content-addressable memory cell C_mn may be formed by forming the match line MLm and the word line WLm and by connecting the first series connection portion and the second series connection portion in parallel between the match line MLm and the word line WLm. In one embodiment, the main bit line BLn may be connected to the gate electrode (including the first gate electrode plate 220) of the first memory transistor 221; and the complementary bit line BLn* may be connected to the gate electrode (including another first gate electrode plate 220) of the second memory transistor 222. In one embodiment, the main search line SLn may be connected to the gate electrode of the second non-hysteretic transistor 322; and the complementary search line SLn* may be connected to the gate electrode of the first non-hysteretic transistor 321.

[0156] Figures 24A to 24E Is a view of a region of an alternative configuration of a third exemplary structure after forming the via-level dielectric layer and the connection via structures according to a third embodiment of the present disclosure. Figure 24A Is a first vertical cross-sectional view. Figure 24B Is a top view. Figure 24C Is a second vertical cross-sectional view. Figure 24D Is a third vertical cross-sectional view. Figure 24E Is a fourth vertical cross-sectional view. Figure 24B The vertical plane A-A’ in Figure 24AThe cutting plane of the vertical cross-sectional view shown. Figure 24B The vertical plane C-C' in Figure 24C is the cutting plane of the vertical cross-sectional view shown. Figure 24B The vertical plane D-D' in Figure 24D is the cutting plane of the vertical cross-sectional view shown. Figure 24B The vertical plane E-E' in Figure 24E is the cutting plane of the vertical cross-sectional view shown.

[0157] Referring to Figures 24A to 24E , an alternative configuration of the third exemplary structure can be obtained from the third exemplary structure shown in Figures 22A to 22C by forming a first pair of contact via structures (74, 76) to replace the first contact via structure 741 and by forming a second pair of contact via structures (74, 76) to replace the second contact via structure 742. Each first contact via structure 74 contacts a first end portion of the first semiconductor channel 250 of the first memory transistor 221 or a first end portion of the first semiconductor channel 250 of the second memory transistor 222. The two first contact via structures 74 in each unit cell UC are laterally spaced apart from each other along a first horizontal direction hd1. The third contact via structure 72 can be staggered with the first contact via structure 74 along the first horizontal direction hd1.

[0158] Each second contact via structure 76 contacts a first end portion of the second semiconductor channel 350 of the first non-hysteretic transistor 321 or a first end portion of the second semiconductor channel 350 of the second non-hysteretic transistor 322. The two second contact via structures 76 in each unit cell UC are laterally spaced apart from each other along a second horizontal direction hd2. The fourth contact via structure 78 can be staggered with the second contact via structure 76.

[0159] A first subset of the processing steps described with reference to Figures 7A to 7D can be performed to form an upper via-level dielectric layer 80. Via cavities can be formed through the upper via-level dielectric layer 80 above the contact via structures (74, 76, 72, 78) and can be filled with at least one conductive material to form a first connection via structure 82, a second connection via structure 88, and additional connection via structures including a third connection via structure 84 and a fourth connection via structure 86. Each first connection via structure 82 can contact the top surface of a corresponding third contact via structure 72, and each second connection via structure 88 can contact the top surface of a corresponding fourth contact via structure 78. Each third connection via structure 84 can contact the top surface of a corresponding first contact via structure 74, and each fourth connection via structure 86 can contact the top surface of a corresponding second contact via structure 76.

[0160] Figures 25A to 25EIt is a view of a region of an alternative configuration of a third exemplary structure after forming a line-level dielectric layer, a word line WLm, and a match line MLm according to a third embodiment of the present disclosure. Figure 25A It is a first vertical cross-sectional view. Figure 25B It is a top view. Figure 25C It is a second vertical cross-sectional view. Figure 25D It is a third vertical cross-sectional view. Figure 25E It is a fourth vertical cross-sectional view. Figure 25B The vertical plane A-A' in Figure 25A is the cutting plane of the vertical cross-sectional view shown. Figure 25B The vertical plane C-C' in Figure 25C is the cutting plane of the vertical cross-sectional view shown. Figure 25B The vertical plane D-D' in Figure 25D is the cutting plane of the vertical cross-sectional view described. Figure 25B The vertical plane E-E' in Figure 25E is the cutting plane of the vertical cross-sectional view shown.

[0161] Referring to Figure 1 、 Figure 8 and Figures 25A to 25E , a second subset of the processing steps described with reference to Figures 7A to 7D can be performed to form a line-level dielectric layer 90 over the upper via-level dielectric layer 80. A line cavity can be formed through the line-level dielectric layer 90 such that the top surfaces of the connection via structures (82, 88, 84, 86) are physically exposed. A word line 92 and a match line 98 can be formed in the line cavity. The word line 92 can contact the top surface of the first connection via structure 82, and the match line 98 can contact the top surface of the second connection via structure 88.

[0162] A first metal line structure 941 can contact the top surface of the third connection via structure 84 that contacts the third contact via structure 74 of the first memory transistor 221 and can contact the top surface of the fourth connection via structure 86 that contacts the fourth contact via structure 76 of the first non-latch transistor 321. The first metal line structure 941 serves as part of a first conductive path for electrically connecting the first memory transistor 221 and the first non-latch transistor 321. A second metal line structure 942 serving as a second conductive path can contact the top surface of the third connection via structure 84 that contacts the third contact via structure 74 of the second memory transistor 222 and can contact the top surface of the fourth connection via structure 86 that contacts the fourth contact via structure 76 of the second non-latch transistor 322. The second metal line structure 942 serves as part of a second conductive path for electrically connecting the second memory transistor 222 and the second non-latch transistor 322.

[0163] Generally, the matching line 98 and the character line 92 can be formed such that the first series connection portion 941 and the second series connection portion 942 can be connected in parallel between the matching line 98 and the character line 92 within each unit cell UC. A four-transistor ternary content-addressable memory cell C_mn can be formed within each unit cell. Figures 25A to 25E Shows a part of a unit cell electrically connected to the (m - 1)th matching line ML(m - 1), a unit cell UC electrically connected to the mth character line WLm and the mth matching line MLm, and a part of a unit cell electrically connected to the (m + 1)th character line WL(m + 1). In one embodiment, each matching line 98 and each character line 92 can extend laterally along a first horizontal direction hd1 and can be laterally spaced apart along a second horizontal direction hd2. In one embodiment, the matching line 98, the character line 92, the first metal line structure 941, and the second metal line structure 942 can include a third metal line structure, and the line-level dielectric layer 90 can be used as a component of a third interconnection-level dielectric material layer.

[0164] Generally, a four-transistor ternary content-addressable memory cell C_mn can be formed by forming the matching line MLm and the character line WLm and by connecting the first series connection portion and the second series connection portion in parallel between the matching line MLm and the character line WLm. In one embodiment, the main bit line BLn can be connected to the gate electrode (including the first gate electrode plate 220) of the first memory transistor 221; and the complementary bit line BLn* can be connected to the gate electrode (including another first gate electrode plate 220) of the second memory transistor 222 and is configured to be biased with a complementary voltage of the voltage at the main bit line BLn. In one embodiment, the main search line SLn can be connected to the gate electrode of the second non-hysteretic transistor 322; and the complementary search line SLn* can be connected to the gate electrode of the first non-hysteretic transistor 321.

[0165] Figures 26A to 29F Shows the manufacturing sequence for forming a fourth exemplary structure, which can be obtained from the third exemplary structure shown in Figures 20A to 20C Although the fourth exemplary structure is shown for an embodiment in which the memory transistors (221, 222) are formed as flash memory transistors, embodiments in which the memory transistors (221, 222) are formed as ferroelectric memory transistors as described with reference to Figures 7A to 7D are expressly contemplated herein.

[0166] Figures 26A to 26C Is a view of a region of a fourth exemplary structure after forming a patterned layer stack according to a fourth embodiment of the present disclosure. Figure 26A Is a first vertical cross-sectional view. Figure 26B Is a top view. Figure 26C Is a second vertical cross-sectional view.Figure 26B The vertical plane A-A' in Figure 26A is the sectional plane of the vertical sectional view shown. Figure 26B The vertical plane C-C' in Figure 26C is the sectional plane of the vertical sectional view shown.

[0167] Referring to Figures 26A to 26C , the fourth exemplary structure according to the fourth embodiment of the present disclosure can be the same as Figures 20A to 20C the third exemplary structure shown in

[0168] Figures 27A to 27F is a view of the region of the fourth exemplary structure after forming the contact-level dielectric layer and the contact via structure according to the fourth embodiment of the present disclosure. Figure 27A is a first vertical sectional view. Figure 27B is a top view. Figure 27C is a second vertical sectional view. Figure 27D is a third vertical sectional view. Figure 27E is a fourth vertical sectional view. Figure 27F is a fifth vertical sectional view. Figure 27B The vertical plane A-A' in Figure 27A is the sectional plane of the vertical sectional view shown. Figure 27B The vertical plane C-C' in Figure 27C is the sectional plane of the vertical sectional view shown. Figure 27B The vertical plane D-D' in Figure 27D is the sectional plane of the vertical sectional view shown. Figure 27B The vertical plane E-E' in Figure 27E is the sectional plane of the vertical sectional view shown. Figure 27B The vertical plane F-F' in Figure 27F is the sectional plane of the vertical sectional view shown.

[0169] Referring jointly to Figure 1 , Figure 8 and Figures 27A to 27F , one can perform the reference to Figures 5A to 5DThe described processing steps form the contact-level dielectric layer 70 and form various contact via structures (741, 742, 72, 78). The various contact via structures (741, 742, 72, 78) serve as source / drain structures for the various transistors (221, 222, 321, 322). Each of the transistors (221, 222, 321, 322) can be a thin-film transistor. Generally, a first memory transistor 221, a second memory transistor 222, a first non-hysteretic transistor 321, and a second non-hysteretic transistor 322 can be formed. The first memory transistor 221 includes a first memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a first binary bit, and the second memory transistor 222 includes a second memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a second binary bit.

[0170] A first series connection of the first memory transistor 221 and the first non-hysteretic transistor 321 can be formed by the first contact via structure 741. A second series connection of the second memory transistor 222 and the second non-hysteretic transistor 322 can be formed by the second contact via structure 742. The first contact via structure 741 can be directly formed on the first memory transistor 221 and the first non-hysteretic transistor 321 to provide the first series connection; and the second contact via structure 742 can be directly formed on the second memory transistor 222 and the second non-hysteretic transistor 322 to provide the second series connection.

[0171] In a fourth exemplary structure, the first memory transistor 221 and the first non-hysteretic transistor 321 are adjacent transistors laterally spaced apart along a second horizontal direction hd2 within a unit cell UC, and the first contact via structure 741 serves as the first source / drain structure of the first memory transistor 221 and the first source / drain structure of the first non-hysteretic transistor 321. The first contact via structure 741 also serves as a conductive path connecting the first source / drain structure of the first memory transistor 221 and the first source / drain structure of the first non-hysteretic transistor 321 along the second horizontal direction hd2.

[0172] In addition, the second memory transistor 222 and the second non-hysteretic transistor 322 are adjacent transistors laterally spaced apart along a second horizontal direction hd2 within a unit cell UC, and the second contact via structure 742 serves as the first source / drain structure of the second memory transistor 222 and the first source / drain structure of the second non-hysteretic transistor 322. The second contact via structure 742 also serves as a conductive path connecting the first source / drain structure of the second memory transistor 222 and the first source / drain structure of the second non-hysteretic transistor 322 along the second horizontal direction hd2.

[0173] In one embodiment, the first memory transistor 221 includes a first semiconductor channel 250; the first non-hysteretic transistor 321 includes a second semiconductor channel 350; and the first semiconductor channel 250 and the second semiconductor channel 350 have the same material composition and the same thickness. In one embodiment, the first memory transistor 221 includes a floating gate electrode (including a first gate electrode plate 220); the first non-hysteretic transistor 321 includes a non-floating gate electrode (including a second gate electrode plate 320); and the floating gate electrode (including the first gate electrode plate 220) and the non-floating gate electrode (including the second gate electrode plate 320) have the same material composition and the same thickness.

[0174] In one embodiment, the floating gate electrode (including the first gate electrode plate 220) is spaced apart in a vertical direction from the top surface of the dielectric material layer (such as the lower via level dielectric layer 12) by a backside gate dielectric 218, and the backside gate dielectric 218 contacts a first section of the top surface of the dielectric material layer; and the non-floating gate electrode (including the second gate electrode plate 320) contacts a second section of the top surface of the dielectric material layer. In one embodiment, the sidewall of the floating gate electrode (including the first gate electrode plate 220) coincides with the sidewall of the backside gate dielectric 218 in the vertical direction.

[0175] In one embodiment, the first memory transistor 221 includes a front gate dielectric 240 in contact with the first semiconductor channel 250 of the first memory transistor 221; the first non-hysteretic transistor 321 includes a non-hysteretic gate dielectric 340 in contact with the second semiconductor channel 350 of the first non-hysteretic transistor 321; and the front gate dielectric 240 and the non-hysteretic gate dielectric 340 have the same material composition and the same thickness. In one embodiment, one of the front gate dielectric 240 and the backside gate dielectric 218 includes a tunneling dielectric layer that provides charge tunneling therethrough; and the other of the front gate dielectric 240 and the backside gate dielectric 218 includes a blocking dielectric layer that inhibits charge tunneling therethrough.

[0176] Figures 28A to 28F is a view of a region of a fourth exemplary structure after forming a via level dielectric layer, a connecting via structure, a line level dielectric layer, a word line WLm, and a matching line MLm according to a fourth embodiment of the present disclosure. Figure 28A is a first vertical cross-sectional view. Figure 28B is a top view. Figure 28C is a second vertical cross-sectional view. Figure 28D is a third vertical cross-sectional view. Figure 28E is a fourth vertical cross-sectional view. Figure 28F is a fifth vertical cross-sectional view. Figure 28B The vertical plane A-A' in Figure 28AThe cutting plane of the vertical cross-sectional view shown. Figure 28B The vertical plane C-C' in Figure 28C is the cutting plane of the vertical cross-sectional view shown. Figure 28B The vertical plane D-D' in Figure 28D is the cutting plane of the vertical cross-sectional view shown. Figure 28B The vertical plane E-E' in Figure 28E is the cutting plane of the vertical cross-sectional view shown. Figure 28B The vertical plane F-F' in Figure 28F is the cutting plane of the vertical cross-sectional view shown.

[0177] Refer jointly to Figure 1 , Figure 8 and Figures 28A to 28F , and the processing steps described in Figures 7A to 7D can be executed to form the upper via-level dielectric layer 80. Via cavities can be formed through the upper via-level dielectric layer 80 above the third contact via structure 72 and the fourth contact via structure 78 and can be filled with at least one conductive material to form the first connection via structure 82 and the second connection via structure 88. Each first connection via structure 82 can contact the top surface of the corresponding third contact via structure 72, and each second connection via structure 88 can contact the top surface of the corresponding fourth contact via structure 78.

[0178] A line-level dielectric layer 90 can be formed above the upper via-level dielectric layer 80. Line cavities can be formed through the line-level dielectric layer 90 such that the top surfaces of the connection via structures (82, 88) are physically exposed. A character line 92 and a match line 98 can be formed in the line cavities. The character line 92 can contact the top surface of the first connection via structure 82, and the match line 98 can contact the top surface of the second connection via structure 88. Generally, the match line 98 and the character line 92 can be formed such that a first series connection portion and a second series connection portion can be connected in parallel between the match line 98 and the character line 92 within each unit cell UC. A four-transistor ternary content-addressable memory cell C_mn can be formed within each unit cell. Figures 28A to 28F Shows a part of a unit cell electrically connected to the (m-1)th match line ML(m-1), a unit cell UC electrically connected to the mth character line WLm and the mth match line MLm, and a part of a unit cell electrically connected to the (m+1)th character line WL(m+1). In one embodiment, each match line 98 and each character line 92 can extend laterally along a first horizontal direction hd1 and can be laterally spaced apart along a second horizontal direction hd2. In one embodiment, the match line 98 and the character line 92 can include a third metal line structure, and the line-level dielectric layer 90 can be used as a component of a third interconnection-level dielectric material layer.

[0179] In general, a four-transistor ternary content addressable memory cell C_mn may be formed by forming a match line MLm and a word line WLm and by connecting a first series connection portion and a second series connection portion in parallel between the match line MLm and the word line WLm. In one embodiment, the main bit line BLn may be connected to the gate electrode (including the first gate electrode plate 220) of the first memory transistor 221; and the complementary bit line BLn* may be connected to the gate electrode (including another first gate electrode plate 220) of the second memory transistor 222 and is configured to be biased with a complementary voltage to the voltage at the main bit line BLn. In one embodiment, the main search line SLn may be connected to the gate electrode of the second non-hysteresis transistor 322; and the complementary search line SLn* may be connected to the gate electrode of the first non-hysteresis transistor 321.

[0180] Figures 29A to 29F is a view of a region of an alternative embodiment of the fourth exemplary structure after forming a via-level dielectric layer, connecting via structures, a line-level dielectric layer, word lines WLm, and match lines MLm according to the fourth embodiment of the present disclosure. Figure 29A is the first vertical cross-sectional view. Figure 29B It is a top view. Figure 29C is a second vertical cross-sectional view. Figure 29D is the third vertical sectional view. Figure 29E is the fourth vertical sectional view. Figure 29F is the fifth vertical sectional view. Figure 29B The vertical plane A-A' is Figure 29A The cutting plane of the vertical section view shown. Figure 29B The vertical plane C-C' is Figure 29C The cutting plane of the vertical section view shown. Figure 29B The vertical plane D-D' is Figure 29D The cutting plane of the vertical section view shown. Figure 29B The vertical plane E-E' is Figure 29E The cutting plane of the vertical section view shown. Figure 29B The vertical plane F-F' in Figure 29F The cutting plane of the vertical section view shown.

[0181] Common Reference Figure 1 , Figure 8 and Figures 29A to 29F , which can be referenced by using Figures 24A to 24E and Figures 25A to 25E The electrical wiring scheme described Figures 27A to 27FThe fourth exemplary structure shown in [Figure 0] obtains an alternative configuration of the fourth exemplary structure. Specifically, within each unit cell UC, a first pair of contact via structures (74, 76) may be formed to replace the first contact via structure 741, and a second pair of via structures (74, 76) may be formed to replace the second contact via structure 742. Each first contact via structure 74 contacts a first end portion of the first semiconductor channel 250 of the first memory transistor 221 or the second memory transistor 222. The two first contact via structures 74 in each unit cell UC are laterally spaced apart from each other along a first horizontal direction hd1. The third contact via structure 72 may be staggered with the first contact via structure 74 along the first horizontal direction hd1.

[0182] Each second contact via structure 76 contacts a first end portion of the second semiconductor channel 350 of the first non-hysteretic transistor 321 or the second non-hysteretic transistor 322. The two second contact via structures 76 in each unit cell UC are laterally spaced apart from each other along the first horizontal direction hd1. The fourth contact via structure 78 may be staggered with the second contact via structure 76.

[0183] An upper via level dielectric layer 80 may be formed over the contact level dielectric layer 70. A first connection via structure 82, a second connection via structure 88, and additional connection via structures including a third connection via structure 84 and a fourth connection via structure 86 are formed through the upper via level dielectric layer 80. Each first connection via structure 82 may contact the top surface of a corresponding third contact via structure 72, and each second connection via structure 88 may contact the top surface of a corresponding fourth contact via structure 78. Each third connection via structure 84 may contact the top surface of a corresponding first contact via structure 74, and each fourth connection via structure 86 may contact the top surface of a corresponding second contact via structure 76.

[0184] A line level dielectric layer 90 may be formed over the upper via level dielectric layer 80. A line cavity may be formed through the line level dielectric layer 90 such that the top surfaces of the connection via structures (82, 88, 84, 86) are physically exposed. A word line 92 and a match line 98 may be formed in the line cavity. The word line 92 may contact the top surface of the first connection via structure 82, and the match line 98 may contact the top surface of the second connection via structure 88.

[0185] The first metal line structure 941 can contact the top surface of the third connection via structure 84 that contacts the third contact via structure 74 of the first memory transistor 221 and can contact the top surface of the fourth connection via structure 86 that contacts the fourth contact via structure 76 of the first non-hysteretic transistor 321. The first metal line structure 941 serves as a part of the first conductive path for electrically connecting the first memory transistor 221 and the first non-hysteretic transistor 321. The second metal line structure 942 serving as the second conductive path can contact the top surface of the third connection via structure 84 that contacts the third contact via structure 74 of the second memory transistor 222 and can contact the top surface of the fourth connection via structure 86 that contacts the fourth contact via structure 76 of the second non-hysteretic transistor 322. The second metal line structure 942 serves as a part of the second conductive path for electrically connecting the second memory transistor 222 and the second non-hysteretic transistor 322.

[0186] Generally, the match line 98 and the character line 92 can be formed such that the first series connection portion and the second series connection portion can be connected in parallel between the match line 98 and the character line 92 within each unit cell UC. A four-transistor ternary content addressable memory cell C_mn can be formed within each unit cell. Figures 25A to 25E A part of the unit cell electrically connected to the (m - 1)th match line ML(m - 1), the unit cell UC electrically connected to the mth character line WLm and the mth match line MLm, and a part of the unit cell electrically connected to the (m + 1)th character line WL(m + 1) are shown. In one embodiment, each match line 98 and each character line 92 can extend laterally along a first horizontal direction hd1 and can be laterally spaced apart along a second horizontal direction hd2. In one embodiment, the match line 98, the character line 92, the first metal line structure 941, and the second metal line structure 942 can include a third metal line structure, and the line-level dielectric layer 90 can be used as a component of the third interconnection-level dielectric material layer.

[0187] Generally, a four-transistor ternary content addressable memory cell C_mn can be formed by forming the match line MLm and the character line WLm and by connecting the first series connection portion and the second series connection portion in parallel between the match line MLm and the character line WLm. In one embodiment, the main bit line BLn can be connected to the gate electrode (including the first gate electrode plate 220) of the first memory transistor 221; and the complementary bit line BLn* can be connected to the gate electrode (including another first gate electrode plate 220) of the second memory transistor 222. In one embodiment, the main search line SLn can be connected to the gate electrode of the second non-hysteretic transistor 322; and the complementary search line SLn* can be connected to the gate electrode of the first non-hysteretic transistor 321.

[0188] Refer toFigure 30 , Figure 30 shows an exemplary structure after forming at least one upper-level dielectric layer and an upper-level metal interconnect structure according to embodiments of the present disclosure. The exemplary structure shown in Figure 30 can be obtained from any of the first exemplary structure, the second exemplary structure, the third exemplary structure, and the fourth exemplary structure and their alternative embodiments. Specifically, an M×N array 300 of four-transistor ternary content addressable memory cells (only a part of the M×N array 300 is shown) is formed as a structure formed within the layer of a third-level interconnect dielectric material layer 630, which includes an optional lower via-level dielectric layer 12, a contact-level dielectric layer 70 (which may also be referred to as a memory-level dielectric layer), an upper via-level dielectric layer 80, and a line-level dielectric layer 90. A second metal via structure 632 and a third metal line structure 638 can be formed in the third-level interconnect dielectric material layer 630. The word lines 92 and the match lines 98 can include a subset of the third metal line structure 638.

[0189] The at least one upper-level dielectric layer can include, for example, a fourth-level interconnect dielectric material layer 640. The upper-level metal interconnect structure can include, for example, a third metal via structure 642 and a fourth metal line structure 648.

[0190] Although embodiments in which the search lines SLn, SLn* and the bit lines BLn, BLn* (1 < n < N) are formed as a subset of the second metal line structure 628 and in which the word lines WLm, WLm* and the match lines MLm, MLm* (1 < m < M) are formed as a subset of the third metal line structure 638 are used to illustrate the present disclosure, embodiments are explicitly contemplated herein in which the M×N array 300 of four-transistor ternary content addressable memory cells is shifted up or down in level and formed at different metal interconnect levels. In addition, when Figure 30 showing the case of a single array 300, multiple arrays 300 can be stacked on top of each other.

[0191] In one embodiment, the substrate 8 can be a semiconductor substrate including a single-crystalline semiconductor material within a semiconductor material layer 9, and a field-effect transistor 701 can be formed on the semiconductor material layer 9. The field-effect transistor 701 can include a semiconductor channel that contains a part of the single-crystalline semiconductor material (such as in the embodiment of a planar field-effect transistor of a fin field-effect transistor) or contains the same material as the single-crystalline semiconductor material (such as in the embodiment of a fully-depleted surround gate field-effect transistor). A dielectric material layer (such as the lower via-level dielectric layer 12 and / or the second-level interconnect dielectric material layer 620) can overlie the field-effect transistor 701. The four-transistor ternary content addressable memory cell C_mn can be formed above the dielectric material layer.

[0192] Figure 31 It is a table showing the programming conditions and search conditions that can be used during the operation of the four-transistor ternary content-addressable memory cell C_mn of the present disclosure. As discussed above, three states are used for the ternary bit operation of each four-transistor ternary content-addressable memory cell C_mn. The operation of the four-transistor ternary content-addressable memory cell C_mn can be performed in the same manner as other transistor ternary content-addressable memory cells known in the art. However, the four-transistor ternary content-addressable memory cell C_mn uses only four transistors. Compared with the ten or more transistors required in previously known ternary content-addressable memory cells, the four-transistor ternary content-addressable memory cell C_mn of the present disclosure requires a smaller number of transistors, and thus occupies a smaller area and provides a higher device density.

[0193] Referring to Figure 1 and Figure 31 , the first memory transistor 221 of the memory cell C_mn can be programmed to a low-resistance "1" state by applying an appropriate voltage (e.g., a large positive voltage) between BLn and WLm. As an alternative, the first memory transistor 221 of the memory cell C_mn can be programmed to a high-resistance "0" state by applying an appropriate voltage (e.g., a large negative voltage) between BLn and WLm. The second memory transistor 222 of the memory cell C_mn can be programmed to a low-resistance "1" state by applying an appropriate voltage (e.g., a large positive voltage) between BLn* and WLm. As an alternative, the second memory transistor 222 of the memory cell C_mn can be programmed to a high-resistance "0" state by applying an appropriate voltage (e.g., a large negative voltage) between BLn* and WLm. Thus, the cell can be programmed to four states represented by the corresponding states of the first memory transistor 221 and the corresponding states of the second memory transistor 222. In an application as a ternary content-addressable memory cell, the state in which both the memory transistors 221 and 222 are programmed to "0" can be referred to as "X" or "don't care". The state in which both the memory transistors 221 and 222 are programmed to "1" may not be utilized (i.e., the cell may never be programmed to this state).

[0194] During a search operation, the match line MLm can be precharged. Search patterns can be applied to SLn and SLn* (SLn = SLn* = "0"; SLn = "0"; SLn* = "1"; SLn = "1"; SLn* = "0"; the fourth search pattern SLn = SLn* = "1" can again be unused). If the search pattern does not match the programmed pattern, the match line MLm can be discharged. If the search pattern matches the programmed pattern or if either the programmed pattern or the search pattern is in the "X" state or the "don't care" state, the match line can remain undischarged. In an N×M array, the match line MLm can be discharged by any one of the cells in column n (1 < n < N). The discharge of the match line MLm can be detected by a sense amplifier.

[0195] Figure 32 is a flowchart showing a set of processing steps that can be used to form a device structure according to an embodiment of the present disclosure.

[0196] Referring to steps 3210 and Figures 1 to 5D 、 Figures 7A to 7D 、 Figure 8 、 Figures 9A to 13B 、 Figures 16A to 21C 、 Figures 24A to 24E 、 Figures 26A to 27F 、 Figures 29A to 29F and Figure 30 ,a first memory transistor 221, a second memory transistor 222, a first non-hysteretic transistor 321, and a second non-hysteretic transistor 322 can be formed. In some embodiments, each of the first memory transistor 221, the second memory transistor 222, the first non-hysteretic transistor 321, and the second non-hysteretic transistor 322 can be a thin film transistor. The first memory transistor 221 includes a first memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a first binary bit, and the second memory transistor 222 includes a second memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a second binary bit.

[0197] Referring to steps 3220 and Figures 5A to 5D 、 Figures 7A to 7D 、 Figure 13A and Figure 13B 、 Figures 16A to 16C 、 Figures 21A to 21C 、 Figures 24A to 25E 、 Figures 27A to 27F 、 Figures 29A to 29F and Figure 30 ,a first series connection of the first memory transistor 221 and the first non-hysteretic transistor 321 can be formed.

[0198] Referring to steps 3230 and Figures 5A to 5D 、 Figures 7A to 7D 、Figure 13A and Figure 13B 、 Figures 16A to 16C 、 Figures 21A to 21C 、 Figures 24A to 25E 、 Figures 27A to 27F 、 Figures 29A to 29F and Figure 30 , a second series connection part of the second memory transistor 222 and the second non-hysteretic transistor 322 can be formed.

[0199] Referring to step 3240 and Figures 6A to 6D 、 Figures 7A to 7D 、 Figures 14A to 16C 、 Figures 22A to 25E 、 Figures 28A to 29F and Figure 30 , a four-transistor ternary content addressable memory cell C_mn can be formed by forming the match line MLm and the word line WLm and by parallelly connecting the first series connection part and the second series connection part between the match line MLm and the word line WLm.

[0200] Referring to all the figures and according to various embodiments of the present disclosure, a device structure including a four-transistor ternary content addressable memory cell C_mn is provided. The four-transistor ternary content addressable memory cell C_mn includes: a first series connection part of a first non-hysteretic transistor 321 and a first memory transistor 221, the first memory transistor 221 including a first memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a first binary bit; and a second series connection part of a second non-hysteretic transistor 322 and a second memory transistor 222, the second memory transistor 222 including a second memory component (which may be a floating gate electrode including a first gate electrode plate 220 or a ferroelectric gate dielectric 230) configured to store a second binary bit, wherein the first series connection part and the second series connection part are parallelly connected between the match line MLm and the word line WLm.

[0201] In one embodiment, the first memory transistor 221 includes a first semiconductor channel 250; the first non-hysteretic transistor 321 includes a second semiconductor channel 350; and the first semiconductor channel 250 and the second semiconductor channel 350 have the same material composition and the same thickness. In one embodiment, the first memory transistor 221 includes a floating gate electrode (including a first gate electrode plate 220); the first non-hysteretic transistor 321 includes a non-floating gate electrode (including a second gate electrode plate 320); and the floating gate electrode (including a first gate electrode plate 220) and the non-floating gate electrode (including a second gate electrode plate 320) have the same material composition and the same thickness.

[0202] In one embodiment, the floating gate electrode (including the first gate electrode plate 220) is vertically spaced apart from the top surface of the dielectric material layer (e.g., the lower via-level dielectric layer 12 and / or the second interconnection-level dielectric material layer 620) by the backside gate dielectric 218, and the backside gate dielectric 218 contacts a first section of the top surface of the dielectric material layer; and the non-floating gate electrode (including the second gate electrode plate 320) contacts a second section of the top surface of the dielectric material layer.

[0203] In one embodiment, the sidewalls of the floating gate electrode (including the first gate electrode plate 220) coincide with the sidewalls of the backside gate dielectric 218 in the vertical direction. In one embodiment, the first memory transistor 221 includes a front gate dielectric

[0204] 240 that contacts the first semiconductor channel 250 of the first memory transistor 221; the first non-hysteretic transistor 321 includes a non-hysteretic gate dielectric 340 that contacts the second semiconductor channel 350 of the first non-hysteretic transistor 321; and the front gate dielectric 240 and the non-hysteretic gate dielectric 340 have the same material composition and the same thickness.

[0205] In one embodiment, one of the front gate dielectric 240 and the backside gate dielectric 218 includes a tunneling dielectric layer that provides charge tunneling therethrough; and the other of the front gate dielectric 240 and the backside gate dielectric 218 includes a blocking dielectric layer that inhibits charge tunneling therethrough.

[0206] In one embodiment, the first memory transistor 221 includes a ferroelectric gate dielectric 230, a first semiconductor channel 250, and a first gate electrode (including the first gate electrode plate 220); and the first non-hysteretic transistor 321 includes a non-hysteretic gate dielectric 340, a second semiconductor channel 350, and a second gate electrode (including the second gate electrode plate 320).

[0207] In one embodiment, the device structure further includes: a main bit line BLn connected to the gate electrode (including the first gate electrode plate 220) of the first memory transistor 221; and a complementary bit line BLn* connected to the gate electrode (including another first gate electrode plate 220) of the second memory transistor 222. In one embodiment, the device structure includes: a main search line SLn connected to the gate electrode of the second non-hysteretic transistor 322; and a complementary search line SLn* connected to the gate electrode of the first non-hysteretic transistor 321.

[0208] In one embodiment, the device structure includes: a semiconductor substrate including a single-crystalline semiconductor material; a field-effect transistor 701 including a semiconductor channel containing a portion of the single-crystalline semiconductor material or including the same material as the single-crystalline semiconductor material; and a dielectric material layer (such as the lower via-level dielectric layer 12 and / or the second interconnect-level dielectric material layer 620) overlying the field-effect transistor 701, wherein the four-transistor ternary content-addressable memory cell C_mn is located above the dielectric material layer.

[0209] According to another aspect of the present disclosure, a device structure is provided, the device structure including: a first dielectric material layer (such as the lower via-level dielectric layer 12 and / or the second interconnect-level dielectric material layer 620) overlying a substrate 8; a first series connection portion of a first non-hysteretic transistor 321 and a first memory transistor 221, the first memory transistor 221 including a first memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a first binary bit, the first series connection portion overlying the dielectric material layer; a second series connection portion of a second non-hysteretic transistor 322 and a second memory transistor 222, the second memory transistor 222 including a second memory component (such as a floating gate electrode or a ferroelectric gate dielectric 230) configured to store a second binary bit, wherein the first non-hysteretic transistor 321, the first memory transistor 221, the second non-hysteretic transistor 322, and the second memory transistor 222 are formed in a second dielectric material layer (such as the contact-level dielectric layer 70); and a match line MLm and a word line WLm, which may be formed in a third dielectric material layer (such as the line-level dielectric layer 90), wherein the first series connection portion and the second series connection portion are connected in parallel between the match line MLm and the word line WLm.

[0210] In one embodiment, the first memory transistor 221 includes a first gate electrode (including a first gate electrode plate 220), a first gate dielectric (such as a front gate dielectric 240 or a ferroelectric gate dielectric 230), and a first semiconductor channel 250; and sidewalls of the first gate electrode (including the first gate electrode plate 220), sidewalls of the first gate dielectric (such as the front gate dielectric 240 or the ferroelectric gate dielectric 230), and sidewalls of the first semiconductor channel 250 overlap each other in a vertical direction.

[0211] In one embodiment, the first non-hysteretic transistor 321 includes a second gate electrode (including a second gate electrode plate 320), a second gate dielectric (such as a non-hysteretic gate dielectric 340), and a second semiconductor channel 350; the first semiconductor channel 250 and the second semiconductor channel 350 have the same semiconductor material composition and the same semiconductor material thickness; and the first gate electrode (including the first gate electrode plate 220) and the second gate electrode (including the second gate electrode plate 320) have the same conductive material composition and the same conductive material thickness.

[0212] In one embodiment, the device structure includes: a first contact via structure 741 formed within a second dielectric material layer (such as a contact-level dielectric layer 70) and contacting each of the first non-hysteretic transistor 321 and the first memory transistor 221; and a second contact via structure 742 formed within a second dielectric material layer (such as a contact-level dielectric layer 70) and contacting each of the second non-hysteretic transistor 322 and the second memory transistor 222.

[0213] According to another aspect of the present disclosure, a method of forming a device structure is provided, the method including: forming a first memory transistor, a second memory transistor, a first non-hysteretic transistor, and a second non-hysteretic transistor, wherein the first memory transistor includes a first memory component configured to store a first binary bit, and the second memory transistor includes a second memory component configured to store a second binary bit; forming a first series connection portion of the first memory transistor and the first non-hysteretic transistor; forming a second series connection portion of the second memory transistor and the second non-hysteretic transistor; and forming a four-transistor ternary content-addressable memory cell by forming a match line and a character line and by connecting the first series connection portion and the second series connection portion in parallel between the match line and the character line.

[0214] In one embodiment, the method further includes: forming a first dielectric material layer over a substrate; forming a backside gate dielectric layer over a first region of the first dielectric material layer without covering a second region of the first dielectric material layer; forming a layer stack of a gate electrode material layer, a front gate dielectric layer, and a semiconductor material layer in the first region and the second region; and patterning the layer stack and the backside gate dielectric layer, wherein the first memory transistor and the second memory transistor include a first patterned portion of the layer stack and a patterned portion of the backside gate dielectric layer, and the first non-hysteretic transistor and the second non-hysteretic transistor include a second patterned portion of the layer stack.

[0215] In one embodiment, the method further includes forming a first vias structure and a second vias structure in the first dielectric material layer, wherein: the back gate dielectric layer is directly formed on the first vias structure; and the gate electrode material layer is directly formed on the second vias structure.

[0216] In one embodiment, the method further includes: forming a first dielectric material layer over a substrate; forming a gate electrode material layer over the first dielectric material layer; forming a ferroelectric dielectric layer over the gate electrode material layer in a first region; forming a gate dielectric layer over the gate electrode material layer in a second region; forming a semiconductor material layer over the ferroelectric dielectric layer and the gate dielectric layer; and patterning the semiconductor material layer, the gate dielectric layer, the ferroelectric dielectric layer, and the gate electrode material layer, wherein: the first memory transistor and the second memory transistor include a first patterned portion of the semiconductor material layer, a first patterned portion of the gate electrode material layer, and a patterned portion of the ferroelectric dielectric layer, and the first non-hysteretic transistor and the second non-hysteretic transistor include a second patterned portion of the semiconductor material layer, a second patterned portion of the gate electrode material layer, and a patterned portion of the gate dielectric layer.

[0217] In one embodiment, the method further includes: directly forming a first contact via structure on the first memory transistor and the first non-hysteretic transistor to provide the first series connection; and directly forming a second contact via structure on the second memory transistor and the second non-hysteretic transistor to provide the second series connection.

[0218] The various embodiments of the present disclosure can be used to provide a memory array 300 of four-transistor ternary content addressable memory cells C_mn, which can address the four-transistor ternary content addressable memory cells C_mn through search lines, bit lines, word lines, and match lines. Each four-transistor ternary content addressable memory cell can be used as a ternary content addressable memory cell known in the art. However, the four-transistor ternary content addressable memory cell is configured with four transistors, and thus provides a very compact device footprint. In addition, the four-transistor ternary content addressable memory cell can be formed in the back-end metal interconnect level, and thus does not occupy any footprint at the front-end device level. Therefore, the four-transistor ternary content addressable memory cell provides a compact and cost-effective solution for the manufacture of ternary content addressable memory cells.

[0219] The foregoing has outlined features of several embodiments in order that those skilled in the art may better understand aspects of the present disclosure. Unless explicitly disclosed otherwise herein, each embodiment set forth using the term "comprises" inherently discloses additional embodiments in which the term "comprises" is replaced with "consists essentially of" or the term "consists of". Whenever two or more components are recited as alternatives in the same paragraph or different paragraphs, a Markush group including the recited list of the two or more components is also implicitly disclosed. Whenever the auxiliary verb "can" is used in the present disclosure to recite forming a component or performing a processing step, embodiments in which such a component or such a processing step is not performed are also explicitly contemplated, provided that the resulting device or apparatus can provide equivalent results. Thus, whenever forming a component or a processing step can be omitted to provide the same or equivalent results, the auxiliary verb "can" applied to forming such a component or performing such a processing step should also be construed as "may" or "may, or may not", and the equivalent results include results that are better to some extent and results that are worse to some extent. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A device structure comprising a four-transistor ternary content addressable memory cell, characterized in that: The four-transistor ternary content addressable memory cell comprises: a first series connection of a first non-hysteresis transistor and a first memory transistor, the first memory transistor comprising a first memory element configured to store a first binary bit; and a second series connection of a second non-hysteresis transistor and a second memory transistor, the second memory transistor comprising a second memory element configured to store a second binary bit, The first series connection part and the second series connection part are connected in parallel between the match line and the word line.

2. The device structure according to claim 1, characterized in that: The first memory transistor includes a floating gate electrode; The first non-hysteresis transistor includes a non-floating gate electrode; and The floating gate electrode and the non-floating gate electrode have the same material composition and the same thickness.

3. The device structure according to claim 2, characterized in that: The floating gate electrode is vertically spaced apart from a top surface of the dielectric material layer by a backside gate dielectric that contacts a first section of the top surface of the dielectric material layer; and The non-floating gate electrode contacts a second section of the top surface of the dielectric material layer.

4. The device structure according to claim 1, characterized in that: The first memory transistor includes a ferroelectric gate dielectric, a first semiconductor channel, and a first gate electrode; and The first non-hysteresis transistor includes a non-hysteresis gate dielectric, a second semiconductor channel and a second gate electrode.

5. The device structure according to claim 1, characterized in that: Also includes: a main bit line connected to the gate electrode of the first memory transistor; as well as The complementary bit line is connected to the gate electrode of the second memory transistor.

6. The device structure according to claim 1, characterized in that: Also includes: a main search line connected to the gate electrode of the second non-hysteresis transistor; as well as A complementary search line is connected to the gate electrode of the first non-hysteresis transistor.

7. The device structure according to claim 1, characterized in that: Also includes: a semiconductor substrate comprising a single crystal semiconductor material; A field effect transistor comprising a semiconductor channel, the semiconductor channel comprising a portion of the single crystalline semiconductor material or comprising the same material as the single crystalline semiconductor material; as well as A dielectric material layer is overlying the field effect transistor, wherein the four-transistor ternary content addressable memory cell is located above the dielectric material layer.

8. A device structure, characterized in that: include: A first dielectric material layer overlying the substrate; a first series connection of a first non-hysteresis transistor and a first memory transistor, the first memory transistor comprising a first memory element configured to store a first binary bit, the first series connection overlying the first dielectric material layer; a second series connection of a second non-hysteresis transistor and a second memory transistor, the second memory transistor comprising a second memory element configured to store a second binary bit, wherein the first non-hysteresis transistor, the first memory transistor, the second non-hysteresis transistor, and the second memory transistor are embedded in a second dielectric material layer; as well as The matching line and the word line are embedded in the third dielectric material layer, wherein the first series connection part and the second series connection part are connected in parallel between the matching line and the word line.

9. The device structure according to claim 8, characterized in that: The first memory transistor includes a first gate electrode, a first gate dielectric and a first semiconductor channel; and The sidewall of the first gate electrode, the sidewall of the first gate dielectric and the sidewall of the first semiconductor channel overlap each other in a vertical direction.

10. The device structure according to claim 8, characterized in that: Also includes: a first contact via structure formed in the second dielectric material layer and contacting each of the first non-hysteresis transistor and the first memory transistor; as well as A second contact via structure is formed in the second dielectric material layer and contacts each of the second non-hysteresis transistor and the second memory transistor.

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