Display substrate and display device

Abstract

The embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a plurality of sub-pixels, a plurality of data lines, a plurality of data line leads and a plurality of bonding pads, wherein the sub-pixels, the data lines and the data line leads are located in a display area, and the bonding pads are located in a first frame area. The bonding pad comprises a first insulating layer, a first metal layer and a second insulating layer, the first insulating layer is provided with a first opening, the first metal layer is electrically connected with the plurality of data line leads through the first opening, the first metal layer comprises a first bottom and a step part surrounding the first bottom, the first bottom is electrically connected with the plurality of data line leads, and the step part surrounds the first bottom. The step portion includes a first step portion and a second step portion, the second step portion connecting the first bottom portion and the first step portion, and the second insulating layer includes a second opening exposing at least a portion of the first bottom portion. According to the technical scheme provided by the embodiment of the invention, dark spots formed by short circuit of the anode and the cathode in the display area can be reduced or avoided.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Currently, display substrates have a technical problem of dark spots being formed due to short circuits between the anode and cathode in the display area. Utility Model Content

[0004] The problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a display device to solve the technical problem that dark spots are formed in the display area due to the short circuit between the anode and the cathode in the existing display substrate.

[0005] In order to solve the above technical problems, in a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] A base substrate, the base substrate comprising a display area and a first frame area located on at least one side of the display area;

[0007] A plurality of sub-pixels are located on one side of the base substrate and in the display area;

[0008] a plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels;

[0009] a plurality of data line leads, located in the first frame area and electrically connected to the plurality of data lines;

[0010] A plurality of pads are located in the first frame area and are electrically connected to the plurality of data line leads; wherein,

[0011] At least one of the plurality of pads comprises:

[0012] a first insulating layer located on a side of the plurality of data line leads facing away from the base substrate, the first insulating layer comprising a first opening exposing at least a portion of at least one data line lead among the plurality of data line leads;

[0013] a first metal layer, located on a side of the plurality of data line leads facing away from the base substrate, and electrically connected to at least one of the plurality of data line leads through the first opening; wherein the first metal layer includes a first bottom portion and a step portion surrounding the first bottom portion, an orthographic projection of the first bottom portion on the base substrate being located within an orthographic projection of the first opening on the base substrate, the first bottom portion being electrically connected to at least one of the plurality of data line leads, the step portion including a first step portion located on a side of the first insulating layer away from the base substrate, and a second step portion forming an angle with the first step portion, the second step portion connecting the first bottom portion and the first step portion, and an orthographic projection of the second step portion on the base substrate being located within an orthographic projection of the first opening on the base substrate;

[0014] A second insulating layer is located on a side of the first metal layer and the first insulating layer facing away from the substrate, wherein the second insulating layer includes a second opening exposing at least a portion of the first bottom of the first metal layer.

[0015] In an exemplary embodiment, a side of the first step portion away from the base substrate is uniformly covered by the second insulating layer.

[0016] In an exemplary embodiment, an orthographic projection of the first step portion on the base substrate and an orthographic projection of the second insulating layer on the base substrate do not overlap, and an orthographic projection of the second opening on the base substrate covers orthographic projections of the first opening, the first step portion, and the first bottom portion on the base substrate;

[0017] Alternatively, the orthographic projection of the first step portion on the base substrate is covered by the orthographic projection of the second insulating layer on the base substrate, and the orthographic projection of the second opening on the base substrate is within the range of the orthographic projection of the first opening on the base substrate.

[0018] In an exemplary embodiment, the display substrate further includes:

[0019] a second metal layer located on a side of the first metal layer and the second insulating layer facing away from the base substrate, wherein the second metal layer is electrically connected to the first metal layer through the second opening, and an orthographic projection of the second metal layer on the base substrate at least partially overlaps with an orthographic projection of the second opening on the base substrate.

[0020] In an exemplary embodiment, the orthographic projection of the second metal layer on the base substrate covers the orthographic projections of the first metal layer and the second opening on the base substrate; or,

[0021] The orthographic projection of the second metal layer on the base substrate does not overlap with the orthographic projection of the first step portion of the first metal layer on the base substrate, and the orthographic projection of the second metal layer on the base substrate covers the orthographic projection of the second opening on the base substrate; or

[0022] The orthographic projection of the second metal layer on the base substrate does not overlap with the orthographic projection of the first step portion of the first metal layer on the base substrate, and the orthographic projection of the second metal layer on the base substrate is within the range of the orthographic projection of the second opening on the base substrate.

[0023] In an exemplary embodiment, the display substrate further includes:

[0024] The third metal layer is located on a side of the second metal layer away from the base substrate, wherein the third metal layer is electrically connected to the second metal layer, and the orthographic projection of the third metal layer on the base substrate covers the orthographic projection of the second metal layer on the base substrate.

[0025] In an exemplary embodiment, the display substrate further includes:

[0026] a third insulating layer, located on a side of the third metal layer facing away from the substrate, the third insulating layer comprising a third opening;

[0027] The orthographic projection of the third opening on the base substrate is located within the orthographic projections of the first opening and the second opening on the base substrate; or

[0028] The orthographic projections of the first opening and the second opening on the base substrate are located within the orthographic projection of the third opening on the base substrate; or,

[0029] The orthographic projection of the third opening on the base substrate is within the range of the orthographic projection of the second opening on the base substrate, and the orthographic projection of the first opening on the base substrate is within the range of the orthographic projection of the third opening on the base substrate.

[0030] In example embodiments, the third insulating layer includes at least one of an inorganic insulating layer and an organic insulating layer.

[0031] In an exemplary embodiment, the third insulating layer includes a first insulating sublayer and a second insulating sublayer, and the second insulating sublayer is located on a side of the first insulating sublayer facing away from the base substrate;

[0032] The material of the first insulating sublayer is an organic material, the material of the second insulating sublayer is an inorganic material, the orthographic projection of the first insulating sublayer on the base substrate does not overlap with the orthographic projection of at least part of the step portion on the base substrate, and the orthographic projection of the second insulating sublayer on the base substrate covers the orthographic projection of at least part of the step portion on the base substrate.

[0033] In an exemplary embodiment, the display substrate further includes:

[0034] a fourth metal layer located on a side of the third metal layer and the third insulating layer facing away from the base substrate, wherein the fourth metal layer is electrically connected to the third metal layer through the third opening, and an orthographic projection of the fourth metal layer on the base substrate at least partially overlaps with an orthographic projection of the third metal layer on the base substrate.

[0035] In an exemplary embodiment, the display substrate further includes:

[0036] A fourth insulating layer, in a direction perpendicular to the plane of the base substrate, the fourth insulating layer is located between the third insulating layer and the fourth metal layer, wherein the fourth insulating layer includes a fourth opening, the orthographic projection of the fourth opening on the base substrate is located within the orthographic projection of the third opening on the base substrate, and the fourth metal layer is electrically connected to the third metal layer through the third opening and the fourth opening.

[0037] In an exemplary embodiment, the first metal layer further includes a second bottom portion surrounding the step portion, the step portion further includes a third step portion forming an angle with the first step portion, the third step portion connecting the second bottom portion and the first step portion, and the orthographic projection of the second insulating layer on the base substrate at least partially overlaps with the orthographic projection of the second bottom portion on the base substrate.

[0038] In an exemplary embodiment, the orthographic projection of the second insulating layer on the base substrate partially overlaps with the orthographic projection of the first bottom portion on the base substrate, and the orthographic projection of the second opening on the base substrate is located within the orthographic projection of the first opening on the base substrate; or

[0039] The orthographic projection of the second insulating layer on the base substrate does not overlap with the orthographic projections of the first bottom portion and the step portion on the base substrate, and the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0040] In an exemplary embodiment, a dimension of the first opening along the width direction is 3 micrometers to 11 micrometers.

[0041] In an exemplary embodiment, a dimension of the first opening along the width direction is 5 micrometers to 8 micrometers.

[0042] In an exemplary embodiment, the third metal layer is a single-layer structure, or the third metal layer is a multi-layer composite structure;

[0043] In a structure in which the third metal layer is a single layer, the metal activity of the metal layer closest to the third metal layer in the second metal layer is not less than the metal activity of the third metal layer;

[0044] In a multi-layer composite structure of the third metal layer, in a direction perpendicular to the plane of the substrate, the metal activity of the metal layer farthest from the second metal layer in the third metal layer is not greater than the metal activity of the metal layer between the farthest metal layer and the second metal layer.

[0045] In an exemplary embodiment, the base substrate includes a packaging area and an edge area located around the packaging area, the edge area includes a binding area on a side of at least one edge of the base substrate, and the binding area is located in the first border area;

[0046] A plurality of inorganic film layers are located on one side of the base substrate and are stacked;

[0047] a plurality of first grooves located in the edge region and spaced apart in a direction away from the packaging region and partially surrounding the packaging region, wherein each of the first grooves penetrates at least one of the plurality of inorganic film layers, and an orthographic projection of the plurality of first grooves on the base substrate does not overlap with the binding region;

[0048] The organic layer covers the plurality of first grooves.

[0049] In an exemplary embodiment, the organic layer includes: a first flat layer and a second flat layer stacked in sequence in a direction away from the base substrate, the first flat layer covers the plurality of first grooves, and the second flat layer is located on a side of the first flat layer away from the base substrate.

[0050] In an exemplary embodiment, the first insulating layer includes: a gate insulating layer and an interlayer dielectric layer sequentially stacked in a direction away from the base substrate, and the at least one inorganic film layer includes the gate insulating layer and the interlayer dielectric layer.

[0051] In an exemplary embodiment, the inorganic film layer between each two adjacent first grooves constitutes a blocking portion; the multiple inorganic film layers also include: a buffer layer located between the base substrate and the gate insulating layer in a direction perpendicular to the plane of the base substrate, and the at least one inorganic film layer also includes at least a portion of the buffer layer.

[0052] In an exemplary embodiment, the plurality of inorganic film layers further include: a barrier layer located between the base substrate and the buffer layer in a direction perpendicular to the plane of the base substrate, and the at least one inorganic film layer further includes at least a portion of the barrier layer.

[0053] In an exemplary embodiment, the display area of ​​the display substrate includes a gate metal layer located on the base substrate, a gate insulating layer located on a side of the gate metal layer facing away from the base substrate, and a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially arranged on a side of the gate insulating layer facing away from the base substrate;

[0054] In a direction perpendicular to the plane of the substrate, the first planar layer is located between the first source-drain metal layer and the second source-drain metal layer, and the second planar layer is located between the second source-drain metal layer and the third source-drain metal layer;

[0055] The multiple data line leads are arranged in the same layer as the gate metal layer, the first insulating layer is arranged in the same layer as the gate insulating layer, the first metal layer is arranged in the same layer as the first source and drain metal layer, the second metal layer is arranged in the same layer as the second source and drain metal layer, and the third metal layer is arranged in the same layer as the third source and drain metal layer.

[0056] In a second aspect, the present disclosure further provides a display device comprising the display substrate described in any of the above embodiments.

[0057] In a third aspect, an embodiment of the present disclosure further provides a method for manufacturing the display substrate described in any of the above embodiments, which may include:

[0058] Providing a base substrate, the base substrate comprising a display area and a first frame area located on at least one side of the display area;

[0059] preparing a plurality of sub-pixels, a plurality of data lines, and a plurality of data line leads on one side of the base substrate, wherein the plurality of sub-pixels and the plurality of data lines are located in the display area and the plurality of sub-pixels are electrically connected to the plurality of data lines, and the plurality of data line leads are located in the first frame area and are electrically connected to the plurality of data lines;

[0060] A plurality of pads are formed in the first frame area, and the step of forming at least one of the plurality of pads includes:

[0061] forming a first insulating layer on a side of the plurality of data line leads facing away from the base substrate, wherein the first insulating layer comprises a first opening exposing at least a portion of at least one data line lead among the plurality of data line leads;

[0062] A first metal layer is formed on a side of the plurality of data line leads facing away from the base substrate, the first metal layer being electrically connected to at least one of the plurality of data line leads through the first opening, wherein the first metal layer includes a first bottom portion and a step portion surrounding the first bottom portion, the orthographic projection of the first bottom portion on the base substrate being located within the orthographic projection of the first opening on the base substrate, the first bottom portion being electrically connected to at least one of the plurality of data line leads, the step portion including a first step portion located on a side of the first insulating layer away from the base substrate, and a second step portion forming an angle with the first step portion, the second step portion connecting the first bottom portion and the first step portion, and the orthographic projection of the second step portion on the base substrate being located within the orthographic projection of the first opening on the base substrate;

[0063] A second insulating layer is formed on the side of the first metal layer and the first insulating layer facing away from the base substrate, wherein the second insulating layer includes a second opening exposing at least a portion of the first bottom of the first metal layer, and the first step portion is covered by the second insulating layer in the same manner as the side away from the base substrate.

[0064] In an exemplary embodiment, the orthographic projection of the first step portion on the base substrate and the orthographic projection of the second insulating layer on the base substrate do not overlap, and the orthographic projection of the second opening on the base substrate covers the orthographic projections of the first opening, the first step portion, and the first bottom portion on the base substrate; or, the orthographic projection of the first step portion on the base substrate is covered by the orthographic projection of the second insulating layer on the base substrate, and the orthographic projection of the second opening on the base substrate is within the range of the orthographic projection of the first opening on the base substrate.

[0065] In an exemplary embodiment, the method further comprises:

[0066] forming a second metal layer on a side of the first metal layer and the second insulating layer facing away from the base substrate, wherein the second metal layer is electrically connected to the first metal layer through the second opening, and an orthographic projection of the second metal layer on the base substrate at least partially overlaps with an orthographic projection of the second opening on the base substrate;

[0067] A third metal layer is formed on a side of the second metal layer facing away from the base substrate, wherein the third metal layer is electrically connected to the second metal layer, and an orthographic projection of the third metal layer on the base substrate covers an orthographic projection of the second metal layer on the base substrate.

[0068] In an exemplary embodiment, the method further comprises:

[0069] forming a third insulating layer on a side of the third metal layer facing away from the substrate, wherein the third insulating layer includes a third opening;

[0070] The orthographic projection of the third opening on the substrate is located within the orthographic projections of the first opening and the second opening on the substrate; or, the orthographic projections of the first opening and the second opening on the substrate are located within the orthographic projection of the third opening on the substrate; or, the orthographic projection of the third opening on the substrate is located within the range of the orthographic projection of the second opening on the substrate, and the orthographic projection of the first opening on the substrate is located within the range of the orthographic projection of the third opening on the substrate.

[0071] In an exemplary embodiment, the method further comprises:

[0072] forming a third insulating layer on a side of the third metal layer facing away from the base substrate, the third insulating layer including a third sub-opening, an orthographic projection of the third insulating layer on the base substrate covering the step portion and a portion of the orthographic projection of the first bottom portion on the base substrate, and an orthographic projection of the third sub-opening on the base substrate being located within an orthographic projection of the first opening on the base substrate;

[0073] forming an anode conductive layer on a side of the third insulating layer away from the base substrate, wherein the anode conductive layer includes a plurality of anodes;

[0074] A fourth insulating layer is formed on a side of the anode conductive layer away from the base substrate, and a third opening corresponding to the third sub-opening is formed in the third insulating layer. The fourth insulating layer includes a fourth opening, and the orthographic projection of the fourth opening on the base substrate is located within the orthographic projection of the third opening on the base substrate. The orthographic projection of the third sub-opening on the base substrate is located within the orthographic projection of the corresponding third opening on the base substrate.

[0075] In an exemplary embodiment, a width of the third sub-opening is 2 micrometers to 5 micrometers, and a width of the third opening is 5 micrometers to 9 micrometers.

[0076] In an exemplary embodiment, the first metal layer further includes a second bottom portion surrounding the step portion, the step portion further includes a third step portion forming an angle with the first step portion, the third step portion connecting the second bottom portion and the first step portion, and the orthographic projection of the second insulating layer on the base substrate at least partially overlaps with the orthographic projection of the second bottom portion on the base substrate.

[0077] In an exemplary embodiment, the orthographic projection of the second insulating layer on the base substrate partially overlaps with the orthographic projection of the first bottom portion on the base substrate, and the orthographic projection of the second opening on the base substrate is located in the orthographic projection of the first opening on the base substrate; or, the orthographic projection of the second insulating layer on the base substrate does not overlap with the orthographic projections of the first bottom portion and the step portion on the base substrate, and the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first opening on the base substrate.

[0078] In an exemplary embodiment, the base substrate includes a packaging area and an edge area located around the packaging area, the edge area includes a binding area on a side of at least one edge of the base substrate, and the binding area is located in the first border area; the method further includes:

[0079] forming a plurality of stacked inorganic film layers on one side of the base substrate using an inorganic material;

[0080] A plurality of first grooves are formed in the edge region and in a direction away from the packaging region, and are sequentially spaced and extend along the periphery of the base substrate, each of the first grooves penetrates at least one inorganic film layer among the plurality of inorganic film layers, and the orthographic projections of the plurality of first grooves on the base substrate do not overlap with the binding region;

[0081] An organic layer covering the plurality of first grooves is formed by using an organic material.

[0082] In an exemplary embodiment, the organic layer includes: a first flat layer and a second flat layer stacked in sequence in a direction away from the base substrate, the first flat layer and the second flat layer being located on a side of the plurality of inorganic film layers away from the base substrate;

[0083] The first insulating layer includes: a gate insulating layer and an interlayer dielectric layer stacked in sequence in a direction away from the base substrate, and the at least one inorganic film layer includes the gate insulating layer and the interlayer dielectric layer.

[0084] The display substrate and display device provided by the embodiments of the present disclosure include a plurality of data lines and a plurality of sub-pixels located in the display area, and a plurality of data line leads and a plurality of pads located in the first frame area. The plurality of data lines are electrically connected to the plurality of sub-pixels, and the plurality of data line leads are electrically connected to the plurality of data lines and the plurality of pads. At least one of the plurality of pads includes a first insulating layer, a first metal layer, and a second insulating layer stacked in sequence on a side of the data line lead facing away from the base substrate. The first insulating layer is provided with a first opening. The first metal layer is electrically connected to at least one of the plurality of data line leads through the first opening. The first metal layer includes a first bottom and a surrounding The step portion of the first bottom portion, the orthographic projection of the first bottom portion on the base substrate is located within the orthographic projection of the first opening on the base substrate, the first bottom portion is electrically connected to at least one data line lead among the multiple data line leads, the step portion includes a first step portion and a second step portion at an angle to the first step portion, the second step portion connects the first bottom portion and the first step portion, the orthographic projection of the second step portion on the base substrate is located within the orthographic projection of the first opening on the base substrate, and the second insulating layer includes a second opening exposing at least a portion of the first bottom portion; the technical solution provided by the embodiment of the present disclosure can, to a certain extent, reduce or avoid the short circuit between the anode and the cathode in the display area to form dark spots.

[0085] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0087] Figure 1a A schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0088] Figure 1b is another schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0089] Figure 2 for Figure 1a The schematic cross-sectional view of the display area of ​​the display substrate taken along line aa' is shown;

[0090] Figure 3 This is a partial schematic diagram of a first signal access area according to an embodiment of the present disclosure;

[0091] Figure 4 for Figure 2 Detailed enlarged view of the middle region S;

[0092] Figure 5a for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0093] Figure 5b for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0094] Figure 5c for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0095] Figure 6 for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0096] Figure 7 for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0097] Figure 8a for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0098] Figure 8b for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0099] Figure 8c for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0100] Figure 9a for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0101] Figure 9b for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0102] Figure 9c for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0103] Figure 9d for Figure 4 A schematic diagram of a cross-sectional structure at the AA position;

[0104] Figure 10a A schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0105] Figure 10b A schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0106] Figure 11a for Figure 10a and Figure 10bA schematic diagram of a cross-sectional structure at the M1-M1 position;

[0107] Figure 11b for Figure 10a and Figure 10b A schematic diagram of a cross-sectional structure at the M1-M1 position;

[0108] Figure 11c for Figure 10a and Figure 10b A schematic diagram of a cross-sectional structure at the M1-M1 position;

[0109] Figure 11d for Figure 10a and Figure 10b A schematic diagram of a cross-sectional structure at the M1-M1 position;

[0110] Figure 12a for Figure 10a and Figure 10b A schematic diagram of a cross-sectional structure at the M2-M2 position;

[0111] Figure 12b for Figure 10a and Figure 10b A schematic diagram of a cross-sectional structure at the M2-M2 position;

[0112] Figure 12c for Figure 10a and Figure 10b A schematic diagram of a cross-sectional structure at the M2-M2 position;

[0113] Figure 13a It is a schematic diagram of the cross-sectional structure after the first insulating layer is formed in the pad;

[0114] Figure 13b It is a schematic diagram of the cross-sectional structure after the first metal layer is formed in the pad;

[0115] Figure 13c It is a schematic diagram of the cross-sectional structure after the second insulating layer is formed in the pad;

[0116] Figure 13d It is a schematic diagram of the cross-sectional structure after the second metal layer is formed in the pad;

[0117] Figure 13e A schematic diagram of the cross-sectional structure after the third metal layer is formed in the pad;

[0118] Figure 13f Schematic diagram of the cross-sectional structure after the third insulating layer is formed in the pad;

[0119] Figure 13g Schematic diagram of the cross-sectional structure after the fourth insulating layer is formed in the pad;

[0120] Figure 14Schematic diagram of the cross-sectional structure after the fourth insulating layer is formed in the pad;

[0121] Figure 15 Shown is a schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0122] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0123] It will be understood that the various figures in the embodiments of the present disclosure are only used to schematically illustrate the connection relationship between the various components. The sizes of the various components in the figures are not drawn to scale, and their relative positions do not necessarily correspond completely to the actual positions.

[0124] In this disclosure, unless otherwise specified or limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in this disclosure can be understood according to the specific circumstances.

[0125] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0126] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0127] The "patterning process" mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching and stripping the photoresist. Deposition can be performed by any one or more selected from sputtering, evaporation and chemical vapor deposition, coating can be performed by any one or more selected from spray coating and spin coating, and etching can be performed by any one or more selected from dry etching and wet etching. "Thin film" refers to a thin film made by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". When the "thin film" still requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0128] Figure 1a A schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1b FIG. 4 is another schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1a and Figure 1b All shown are planar schematic diagrams of display substrates before the bending process is performed.

[0129] In some examples, such as Figure 1a and Figure 1b As shown, the display substrate may include: a display area AA, and a border area BB surrounding the display area AA. For example, the border area BB may include: a first border area B1 located on one side of the display area AA, and border areas located on other sides of the display area AA (for example, including a second border area B2, a third border area B3, and a fourth border area B4). The first border area B1 may be, for example, the bottom border of the display substrate, the second border area B2 may be, for example, the top border of the display substrate, the third border area B3 may be, for example, the left border of the display substrate, and the fourth border area B4 may be, for example, the right border of the display substrate.

[0130] In some examples, such as Figure 1a and Figure 1b As shown, the display area AA can be a flat area that includes multiple sub-pixels PX that make up the pixel array. The multiple sub-pixels PX can be configured to display dynamic images or still images. The display area AA can be referred to as the active area. In some examples, the display area AA can be rectangular. However, this embodiment is not limited to this. For example, the display area AA can be another shape, such as circular or elliptical. In some examples, the display substrate can be a flexible panel, and thus the display substrate can be deformable, such as curling, bending, folding, or rolling.

[0131] In some examples, such as Figure 1a and Figure 1bAs shown, the display area AA may include at least: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions, and a sub-pixel PX may be provided in each sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signal may include a scan signal and a light-emitting control signal, or may include a scan signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0132] In some examples, such as Figure 1a and Figure 1b As shown, the first direction X may be the extending direction (e.g., the row direction) of the gate lines GL in the display area AA, and the second direction Y may be the extending direction (e.g., the column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may intersect each other, for example, may be perpendicular to each other.

[0133] In some examples, a pixel unit in display area AA may include three sub-pixels, where the three sub-pixels are red, green, and blue. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, where the four sub-pixels are red, green, blue, and white.

[0134] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0135] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit (e.g., Figure 1a Please note that for simplicity, Figure 1a(The light-emitting element L is shown only in one sub-pixel PX, which does not limit the present disclosure). The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. However, this embodiment is not limited to this.

[0136] In some examples, multiple transistors in a pixel circuit may utilize low-temperature polysilicon (LTPS) thin-film transistors and oxide thin-film transistors. The active layer of the LTPS thin-film transistor utilizes low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor utilizes an oxide semiconductor (Oxide). LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS thin-film transistors and oxide thin-film transistors on a single display substrate, namely an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0137] In some examples, the light-emitting element can be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element can be an OLED, which can emit red light, green light, blue light, or white light when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element can include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0138] In some examples, a display substrate can integrate a touchscreen structure. The display substrate can include an organic light-emitting diode (OLED) display structure, a plasma display structure, or an electrophoretic display structure. For example, the display substrate can include an OLED display structure and a touchscreen structure. The touchscreen structure can be disposed on the encapsulation layer of the display structure, forming a touch-on-thin-film encapsulation (TFE) structure. The integrated display and touchscreen structures offer advantages such as lightness, thinness, and foldability, meeting product requirements for flexible folding and narrow bezels.

[0139] In some examples, the touch control structure on the thin film package mainly includes a flexible multi-layer on-cell (FMLOC) structure and a flexible single-layer on-cell (FSLOC) structure. The FMLOC structure works based on the principle of mutual capacitance detection. Generally, two layers of metal are used to form the drive (Tx) electrode and the sense (Rx) electrode. The integrated circuit (IC) realizes touch control by detecting the mutual capacitance between the drive and sense electrodes. The FSLOC structure works based on the principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The IC realizes touch control by detecting the self-capacitance (or voltage) of the touch electrode.

[0140] Figure 2 for Figure 1a The figure shows a schematic cross-sectional view of the display area of ​​the display substrate taken along line aa'. Figure 2 The structure of a sub-pixel in the display area is used as an example for illustration. In this example, the multiple transistors in the pixel circuit are of the same type. For example, the multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or all use oxide thin-film transistors. In other examples, the multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. In addition, this example uses the display substrate integrated mutual capacitance touch structure to form an FMLOC structure as an example for illustration.

[0141] In some examples, such as Figure 2As shown, in the direction Z perpendicular to the display substrate, the display area of ​​the display substrate may include: a base substrate 100, and a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50, and a color filter layer 60 sequentially arranged on the base substrate 100. The display structure layer may include at least the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 30 may include at least: light-emitting elements for multiple sub-pixels.

[0142] In some examples, Figure 2 The following example illustrates a thin film transistor 21 and a capacitor 22 included in each sub-pixel. In some examples, the circuit structure layer 20 in the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, disposed on the base substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be provided between the semiconductor layer and the first gate metal layer, a second gate insulating layer 202 may be provided between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 203 may be provided between the second gate metal layer and the first source / drain metal layer, a passivation layer 204 and a first planarizing layer 205 may be provided between the first source / drain metal layer and the second source / drain metal layer, a second planarizing layer 206 may be provided between the second source / drain metal layer and the third source / drain metal layer, and a third planarizing layer 207 may be provided on the side of the third source / drain metal layer away from the base substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, and the first planarizing layer 205, the second planarizing layer 206, and the third planarizing layer 207 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer may be provided on the side of the semiconductor layer close to the base substrate. The buffer layer may prevent harmful substances in the base substrate from invading the interior of the display substrate and may also increase the adhesion of the film layer in the display substrate to the base substrate. In other examples, a bottom shielding metal layer (BSM) may be provided on the side of the buffer layer close to the base substrate. The bottom shielding metal layer may be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to prevent external light from affecting the performance of the thin film transistor. In other examples, the passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the first planar layer may be provided between the first source-drain metal layer and the second source-drain metal layer.

[0143] In some examples, such as Figure 2 As shown, the semiconductor layer in the display area may include at least the active layer 210 of the thin film transistor 21. The active layer 210 of the thin film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin film transistor 21 and the first plate 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin film transistor 21 on the substrate 100 may overlap the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 100. The second gate metal layer may include at least the second plate 222 of the capacitor 22. The orthographic projections of the second plate 222 and the first plate 221 of the capacitor 22 on the substrate 100 may at least partially overlap, for example, they may coincide. The first source and drain metal layer may include at least the source 211 and drain 212 of the thin film transistor 21. The interlayer insulating layer 203 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source electrode 211 of the thin-film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain electrode 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transfer electrode 231. The first transfer electrode 231 can be electrically connected to the drain electrode 212 of the thin-film transistor 21 in the pixel circuit through a third pixel via hole defined in the passivation layer 204 and the first planar layer 205. The third source-drain metal layer can include at least a second transfer electrode 232. The second transfer electrode 232 can be electrically connected to the first transfer electrode 231 located in the second source-drain metal layer through a fourth pixel via hole defined in the second planar layer 206. The second transfer electrode 232 can be electrically connected to the first electrode 301 (e.g., the anode) of the light-emitting element through a fifth pixel via hole defined in the third planar layer 207. In this example, the first transfer electrode 231 and the second transfer electrode 232 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0144] In some examples, the gate lines of the display area may be located in the first gate metal layer or the second gate metal layer, the data lines of the display area may be located in the second source-drain metal layer or the third source-drain metal layer, and the high-potential power lines of the display area may be located in at least one of the second source-drain metal layer and the third source-drain metal layer. This embodiment is not limited to this. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging a large number of traces within a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0145] In some examples, such as Figure 2 As shown, the light-emitting structure layer 30 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. The first electrode 301 may be disposed on the third planar layer 207 and electrically connected to the second transfer electrode 232 through a fifth pixel via provided in the third planar layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planar layer 207. The pixel definition layer 304 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 may be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on and connected to the organic light-emitting layer 302. Driven by the first electrode 301 and the second electrode 303, the organic light-emitting layer 302 may emit light of a corresponding color. An isolation column layer may be further provided on a side of the pixel definition layer 304 away from the base substrate 100 . The isolation column layer may include a plurality of isolation columns (PS).

[0146] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML), and one or more layers selected from the group consisting of a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage applied by the first electrode 301 and the second electrode 303, the organic material's luminescence properties can be utilized to produce light of varying grayscales.

[0147] In some examples, the light-emitting layers of light-emitting elements of different colors can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce processing complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be a common layer, while the electron injection layer and electron transport layer on the other side can be a common layer. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated using a single process (single evaporation process or single inkjet printing process), and can be isolated by surface step differences or surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or open mask, or by inkjet printing.

[0148] In some examples, such as Figure 2 As shown, in a direction perpendicular to the base substrate, the encapsulation structure layer 40 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 402 may be made of an organic material and may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 402 may be made of an organic material, for example, a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress in the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a desiccant or other absorbent material to absorb intruding water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0149] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected via the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected via the second connecting portions.

[0150] In some examples, such as Figure 2As shown, in a direction perpendicular to the base substrate, the touch structure layer 50 in the display area may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, arranged in sequence. The touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, such as SiNx layers. For example, the first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be interconnected and integrally formed. The second touch conductive layer 512 may include a plurality of second connecting portions. The second connecting portions may be connected to adjacent second touch electrodes via vias defined in the touch interlayer insulating layer. However, this embodiment is not limited to this. In other examples, the first touch conductive layer may include: multiple first touch electrodes, multiple second touch electrodes, and multiple second connecting portions. The second touch electrodes and the second connecting portions may be interconnected as an integral structure. The second touch conductive layer may include multiple first connecting portions, each of which may be interconnected with adjacent first touch electrodes via vias defined in the touch interlayer insulating layer. In some examples, the first touch electrodes may be drive (Tx) electrodes, and the second touch electrodes may be sense (Rx) electrodes. Alternatively, the first touch electrodes may be sense (Rx) electrodes, and the second touch electrodes may be drive (Tx) electrodes. This embodiment is not limited to this.

[0151] In some examples, the first touch electrode and the second touch electrode may have a rhombus shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first touch electrode and the second touch electrode may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygonal shapes, which are not limited in the embodiments of the present disclosure.

[0152] In some examples, the first and second touch electrodes may be transparent conductive electrodes. In other examples, the first and second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include multiple mesh patterns, and the mesh pattern may be a polygon formed by multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0153] In some examples, such as Figure 2As shown, in a direction perpendicular to the substrate, the color filter layer (Color filter On Encapsulation, COE) 60 may include: an insulating layer 601, a color filter layer and an OC film (overcoat) 602 arranged in sequence, wherein the color filter layer includes a black matrix 610 and a color filter unit 611 arranged between the black matrix 610, and the color filter unit 611 may be, for example, a red filter unit, a green filter unit or a blue filter unit.

[0154] In some examples, such as Figure 1a As shown, the first frame area B1 of the display substrate may include: a fan-out wiring area B11 and a signal access area B12 which are sequentially arranged in a direction away from the display area AA. Figure 1a In the figure, only a number of lines in the first frame area are shown for illustration. This example does not limit the number of lines in the first frame area.

[0155] In some examples, such as Figure 1a As shown, the fan-out routing area B11 can be connected between the display area AA and the signal access area B12. The fan-out routing area B11 can be provided with at least a plurality of data fan-out lines 42. The plurality of data fan-out lines 42 can be electrically connected to the plurality of data lines DL in the display area AA. For example, the plurality of data fan-out lines 42 and the plurality of data lines DL can be electrically connected one-to-one. The plurality of data fan-out lines 42 can extend to the signal access area B12 in a fan-out routing manner. The plurality of data fan-out lines 42 and the plurality of data lines DL can be located in different film layers, and the data fan-out lines 42 can be connected to the data lines DL through vias opened in the insulating layer.

[0156] In some examples, such as Figure 1a As shown, the signal access area B12 may include at least one first signal access area B121. This example uses one first signal access area as an example for illustration and explanation. In other examples, the display substrate is a large-size panel, and the display substrate may include multiple first signal access areas, and the multiple first signal access areas may be arranged sequentially along the first direction X.

[0157] In some examples, such as Figure 1aAs shown, the first signal access area B121 can also be referred to as a driver chip (IC) setting area. The first signal access area B121 can be provided with a plurality of pads 31, and the plurality of pads 31 can be configured to be bound and connected to at least one driver chip. The driver chip can be configured to generate the driving signal required to drive the sub-pixels and provide the driving signal to the data line DL of the display area AA. For example, the driving signal can be a data signal that drives the sub-pixels. In some examples, the driver chip can be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the driver chip can also include hardware circuits and computer executable code. The hardware circuit can include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit can also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0158] In some examples, such as Figure 1a As shown, the signal access area B12 can be provided with at least a plurality of data line leads 101, and the plurality of data line leads 101 can be electrically connected to the plurality of data fan-out lines 42 of the fan-out routing area B11, for example, in a one-to-one electrical connection. For example, the data line leads 101 and the connected data fan-out lines 42 can be an integrated structure connected to each other. That is, the plurality of data line leads 101 are electrically connected to the plurality of data lines DL through the plurality of data fan-out lines 42, for example, in a one-to-one electrical connection. The plurality of data line leads 101 can extend into the first signal access area B121 and be electrically connected to the plurality of pads 31 in the first signal access area B121. For example, the plurality of data line leads 101 can be electrically connected to the plurality of pads 31 in a one-to-one electrical connection, or one data line lead 101 can be electrically connected to at least one pad 31. The data line leads 101 and the data fan-out lines 42 can transmit the data signals provided by the driver chip to the data lines DL of the display area.

[0159] In some examples, such as Figure 1b As shown, the first frame area B1 of the display substrate may include: a fan-out routing area B11, a bending area B13 and a signal access area B12 which are sequentially arranged in a direction away from the display area AA. Figure 1b In the figure, only a number of lines in the first frame area are shown for illustration. This example does not limit the number of lines in the first frame area.

[0160] In some examples, such as Figure 1bAs shown, the bending area B13 can be connected between the fan-out routing area B11 and the signal access area B12, and can be configured to bend the signal access area B12 to the back of the display area AA. The bending area B13 can be provided with at least a plurality of data bending connection lines 43. One end of the data bending connection line 43 can be connected to the data fan-out line 42 in the fan-out routing area B11, and the other end can be connected to the data line lead 101 in the signal access area B12. The multiple data bending connection lines 43 can be a same-layer structure, for example, located in the first source and drain metal layer or the second source and drain metal layer. The remaining structure of the first border area B1 of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0161] like Figure 1a and Figure 1b As shown, the signal access area B12 may also include a second signal access area B122. A plurality of contact pads 32 are provided in the second signal access area B122 for bonding to the flexible circuit board. The pads described below in this disclosure refer to the pads 31 of the first signal access area B121, which are used to bond to at least one driver chip.

[0162] Figure 3 FIG is a partial enlarged view of the first signal access area of ​​the embodiment of the present disclosure. In some examples, such as Figure 3 As shown, the multiple pads 31 of the first signal access area B121 can be arranged in multiple rows (for example, four rows). The multiple pads 31 included in each row can be arranged sequentially along the first direction X, and the multiple rows of pads 31 can be arranged sequentially along the second direction Y. The pads 31 of two adjacent rows can be staggered in the first direction X. However, this embodiment is not limited to this. In other examples, the multiple pads of the first signal access area B121 can be arranged in a row.

[0163] In some examples, the plurality of pads 31 in the first signal access area may be divided into at least a plurality of groups (eg, two groups). Figure 3Two groups of pads (e.g., a first group of pads 31A and a second group of pads 31B) are used as an example for illustration and description. The second group of pads 31B can be located on a side of the first group of pads 31A away from the display area. The first group of pads 31A can include three rows of multiple pads 311 arranged along a first direction X. The second group of pads 31B can include a row of multiple pads 312 arranged along the first direction X. In some examples, the second group of pads 31B is used to input signals, which are converted by the bonded IC and then output to the first group of pads 31A. The first group of pads 31A then transmits the signals (e.g., data signals) to multiple sub-pixels PX via multiple signal lines (e.g., multiple data lines DL). The first and second groups of pads 31A, 31B can be staggered in the first direction X. For example, the pads within the first and second groups of pads 31A, 31B can be misaligned in the second direction Y. Spaces can exist between adjacent pads within the same group, and between pads in adjacent groups. In some embodiments, a group of pads may be one row of pads, two rows of pads, or three rows of pads. The present disclosure does not limit the number of pad rows and the number of pads in each row.

[0164] Figure 4 for Figure 3 Detailed enlarged view of region S. In some examples, such as Figure 4 As shown, a plurality of data line leads 101 may extend substantially along the second direction Y between the plurality of pads 31. For example, two data line leads 101 may be provided between two adjacent pads 31 of a group of pads. One data line lead 101 may be electrically connected to at least one pad 31, for example, one data line lead 101 may be connected to one pad 31.

[0165] As the number of signal lines in display substrates increases, achieving a narrow bezel requires layering the signal lines. For example, three source and drain metal layers are prepared. This allows signal lines to be routed separately in each of the three source and drain metal layers, reducing the load on the single-layer signal line routing and effectively reducing the bezel size. Within the bezel area of ​​the display substrate, some pads used to connect to the driver chip (driver IC) are fabricated simultaneously during the fabrication of the three source and drain metal layers. During the fabrication of the display substrate, cracks can easily form in the third source and drain metal layer within the pads, exposing metal (e.g., aluminum) at the cracks in the third source and drain metal layer. The aluminum displaces silver ions (Ag+) in the wet etching solution of the first electrode 301, forming silver particles. During the wet etching process of the first electrode 301 (which can serve as an anode) and subsequent water washing processes (e.g., cleaning the completed anode), the silver particles are washed to the anode (i.e., first electrode 301) opening (i.e., pixel opening), causing a short circuit between the anode (i.e., first electrode 301) and the cathode (i.e., second electrode 302) within the display area, forming dark spots.

[0166] The present disclosure provides a display substrate, which may include:

[0167] A base substrate, the base substrate comprising a display area and a first frame area located on at least one side of the display area;

[0168] A plurality of sub-pixels are located on one side of the base substrate and in the display area;

[0169] a plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels;

[0170] a plurality of data line leads, located in the first frame area and electrically connected to the plurality of data lines;

[0171] A plurality of pads are located in the first frame area and are electrically connected to the plurality of data line leads; wherein,

[0172] At least one of the plurality of pads comprises:

[0173] a first insulating layer located on a side of the plurality of data line leads facing away from the base substrate, the first insulating layer comprising a first opening exposing at least a portion of at least one data line lead among the plurality of data line leads;

[0174] a first metal layer, located on a side of the plurality of data line leads facing away from the base substrate, and electrically connected to at least one of the plurality of data line leads through the first opening; wherein the first metal layer includes a first bottom portion and a step portion surrounding the first bottom portion, an orthographic projection of the first bottom portion on the base substrate being located within an orthographic projection of the first opening on the base substrate, the first bottom portion being electrically connected to at least one of the plurality of data line leads, the step portion including a first step portion located on a side of the first insulating layer away from the base substrate, and a second step portion forming an angle with the first step portion, the second step portion connecting the first bottom portion and the first step portion, and an orthographic projection of the second step portion on the base substrate being located within an orthographic projection of the first opening on the base substrate;

[0175] A second insulating layer is located on a side of the first metal layer and the first insulating layer facing away from the substrate, wherein the second insulating layer includes a second opening exposing at least a portion of the first bottom of the first metal layer.

[0176] In an exemplary embodiment, a side of the first step portion away from the base substrate is uniformly covered by the second insulating layer.

[0177] The display substrate provided by the embodiment of the present disclosure includes a plurality of data lines and a plurality of sub-pixels located in the display area and a plurality of data line leads and a plurality of pads located in the first frame area. The plurality of data lines are electrically connected to the plurality of sub-pixels, and the plurality of data line leads are electrically connected to the plurality of data lines and the plurality of pads. At least one of the plurality of pads includes a first insulating layer, a first metal layer, and a second insulating layer stacked in sequence on a side of the data line lead facing away from the base substrate. The first insulating layer is provided with a first opening. The first metal layer is electrically connected to at least one of the plurality of data line leads through the first opening. The first metal layer includes a first bottom and a first metal layer surrounding the first bottom. The step portion, the orthographic projection of the first bottom portion on the base substrate is located within the orthographic projection of the first opening on the base substrate, the first bottom portion is electrically connected to at least one data line lead among the multiple data line leads, the step portion includes a first step portion and a second step portion that forms an angle with the first step portion, the second step portion connects the first bottom portion and the first step portion, the orthographic projection of the second step portion on the base substrate is located within the orthographic projection of the first opening on the base substrate, and the second insulating layer includes a second opening that exposes at least a portion of the first bottom portion; the technical solution provided by the embodiment of the present disclosure can, to a certain extent, reduce or avoid the short circuit between the anode and the cathode in the display area to form dark spots.

[0178] like Figure 1a 、 Figure 1b 、 Figures 3 to 9b As shown, Figure 1a 、 Figure 1b Schematic diagram of the planar structure of the display substrate. Figure 3 for Figure 1a and Figure 1b A partially enlarged schematic diagram of the first signal access area B121, Figure 4 Shown Figure 3 The enlarged view of the middle area S, Figures 5a to 9b for Figure 4 Schematic diagram of several cross-sectional structures at the AA position, such as 1A, Figure 1b 、 Figures 3 to 9b As shown, the display substrate may include:

[0179] The base substrate 100 may include a display area AA and a first frame area B1 located on at least one side of the display area AA;

[0180] A plurality of sub-pixels PX are located on one side of the base substrate 100 and in the display area AA;

[0181] a plurality of data lines DL located in the display area AA and electrically connected to the plurality of sub-pixels PX;

[0182] A plurality of data line leads 101 are located in the first border area B1 and are electrically connected to the plurality of data lines DL;

[0183] A plurality of pads 31 are located in the first frame area B1 and are electrically connected to a plurality of data line leads 101; wherein,

[0184] At least one of the plurality of pads 31 includes:

[0185] A first insulating layer 102 is located on a side of the plurality of data line leads 101 facing away from the base substrate 100 , and the first insulating layer 102 includes a first opening 110 exposing at least a portion of at least one data line lead 101 among the plurality of data line leads 101 ;

[0186] The first metal layer 1031 is located on a side of the plurality of data line leads 101 away from the base substrate 100 and is electrically connected to at least one of the plurality of data line leads 101 through the first opening 110; wherein the first metal layer 1031 includes a first bottom portion 1031a and a step portion surrounding the first bottom portion 1031a, the orthographic projection of the first bottom portion 1031a on the base substrate 100 is located within the orthographic projection of the first opening 110 on the base substrate 100, and the first bottom portion 1031a is electrically connected to the first metal layer 1031a. At least one of the plurality of data line leads 101 is electrically connected, and the step portion includes a first step portion 1031b located on a side of the first insulating layer 102 away from the base substrate 100 and a second step portion 1031c that forms an angle with the first step portion 1031b, the second step portion 1031c connecting the first bottom portion 1031a and the first step portion 1031b, and an orthographic projection of the second step portion 1031c on the base substrate 100 is located in the orthographic projection of the first opening 110 on the base substrate 100;

[0187] The second insulating layer 104 is located on a side of the first metal layer 1031 and the first insulating layer 102 facing away from the substrate 100 , wherein the second insulating layer 104 includes a second opening 120 exposing at least a portion of the first bottom 1031 a of the first metal layer 1031 .

[0188] In an exemplary embodiment, the first step portion 1031 b is uniformly covered by the second insulating layer 104 on a side away from the base substrate 100 .

[0189] In an exemplary embodiment, Figures 5a to 7 、 Figures 9a to 9b As shown, there is no overlapping area between the orthographic projection of the first step portion 1031b on the base substrate 100 and the orthographic projection of the second insulating layer 104 on the base substrate 100, and the orthographic projection of the second opening 120 on the base substrate 100 covers the orthographic projections of the first opening 110, the first step portion 1031b and the first bottom portion 1031a on the base substrate 100.

[0190] In an exemplary embodiment, Figures 8a to 8cAs shown, the orthographic projection of the first step portion 1031 b on the base substrate 100 is covered by the orthographic projection of the second insulating layer 104 on the base substrate 100 , and the orthographic projection of the second opening 120 on the base substrate 100 is within the range of the orthographic projection of the first opening 110 on the base substrate 100 .

[0191] exist Figures 5a to 9b In the structure shown, the first step portion 1031b is covered by the second insulating layer 104 in the same manner as the side away from the base substrate 100 (for example, Figures 5a to 7 、 Figures 9a to 9b The side of the first step portion 1031b away from the base substrate 100 is covered by the second insulating layer 104. Figures 8a to 8c The side of the first step portion 1031b away from the base substrate 100 is not covered by the second insulating layer 104). The side of the first step portion 1031b away from the base substrate is basically flat and has no protrusions. This can prevent the subsequently formed metal layer (such as the subsequently formed second metal layer and the third metal layer) from causing cracks due to the protrusions on the surface of the first step portion 1031b, thereby preventing the subsequently formed metal layer from exposing the metal layer on the side close to the base substrate 100 through the cracks. For example, it can prevent the cracks formed in the third metal layer from exposing the metal of the second metal layer or the metal of the intermediate film layer of the third metal layer. This can prevent the metal material of the second metal layer (such as aluminum) from being replaced with the silver ions in the wet etching solution to form silver particles during the anode etching process, and prevent the silver particles from being washed into the display area during the anode etching process and the subsequent water washing process, causing a short circuit between the anode and the cathode to form dark spots.

[0192] In an exemplary embodiment, Figures 5a to 9b As shown, the display substrate may further include:

[0193] The second metal layer 1032 is located on the side of the first metal layer 1031 and the second insulating layer 104 facing away from the base substrate 100, wherein the second metal layer 1032 is electrically connected to the first metal layer 1031 through the second opening 120, and the orthographic projection of the second metal layer 1032 on the base substrate 100 at least partially overlaps with the orthographic projection of the second opening 120 on the base substrate 100.

[0194] In an exemplary embodiment, Figure 5a to Figure 5b 、 Figures 6 to 8a 、 Figures 9a to 9b As shown, the orthographic projection of the second metal layer 1032 on the base substrate 100 may cover the orthographic projections of the first metal layer 1031 and the second opening 120 on the base substrate 100 .

[0195] In an exemplary embodiment, Figure 5c 、 8b to Figure 8cAs shown, the orthographic projection of the second metal layer 1032 on the base substrate 100 does not overlap with the orthographic projection of the first step portion 1031b of the first metal layer 1031 on the base substrate 100; in an exemplary embodiment, as shown in FIG. Figures 8b to 8c As shown, the orthographic projection of the second metal layer 1032 on the base substrate 100 covers the orthographic projection of the second opening 120 on the base substrate 100; in an exemplary embodiment, as shown in FIG. Figure 5c As shown, the orthographic projection of the second metal layer 1032 on the base substrate 100 is located within the range of the orthographic projection of the second opening 120 on the base substrate 100 .

[0196] In an exemplary embodiment, Figures 5a to 9b As shown, the display substrate may further include:

[0197] The third metal layer 1033 is located on the side of the second metal layer 1032 facing away from the base substrate 100 , wherein the third metal layer 1033 is electrically connected to the second metal layer 1032 , and the orthographic projection of the third metal layer 1033 on the base substrate 100 covers the orthographic projection of the second metal layer 1032 on the base substrate 100 .

[0198] In an exemplary embodiment, Figures 5a to 9b As shown, the display substrate may further include:

[0199] A third insulating layer 106 is located on a side of the third metal layer 1033 facing away from the substrate 100 , and the third insulating layer 106 includes a third opening 130 ;

[0200] Among them, Figure 5b 、 Figure 6 and Figure 7 As shown, the orthographic projection of the third opening 130 on the base substrate 100 is located within the orthographic projections of the first opening 110 and the second opening 120 on the base substrate 100; or, as shown Figures 8a to 8c As shown, the orthographic projections of the first opening 110 and the second opening 120 on the base substrate 100 are located within the orthographic projection of the third opening 130 on the base substrate 100; or, as shown Figure 5a 、 Figure 5c 、 Figures 9a to 9b As shown, the orthographic projection of the third opening 130 on the base substrate 100 is within the range of the orthographic projection of the second opening 120 on the base substrate 100 , and the orthographic projection of the first opening 110 on the base substrate 100 is within the range of the orthographic projection of the third opening 130 on the base substrate 100 .

[0201] In example embodiments, the third insulating layer 106 may include at least one of an inorganic insulating layer and an organic insulating layer.

[0202] In an exemplary embodiment, Figures 5a to 8b 、 Figures 9a to 9b As shown, the first metal layer 1031 may further include a second bottom portion 1031e surrounding the step portion, and the step portion may further include a third step portion 1031d forming an angle with the first step portion 1031b, the third step portion 1031d connecting the second bottom portion 1031e and the first step portion 1031b, and the orthographic projection of the second insulating layer 104 on the base substrate 100 at least partially overlaps with the orthographic projection of the second bottom portion 1031e on the base substrate 100.

[0203] In an exemplary embodiment, Figure 9a and Figure 9b As shown, the third insulating layer 106 may include a first insulating sublayer 1061 and a second insulating sublayer 1062 . The second insulating sublayer 1062 is located on a side of the first insulating sublayer 1061 facing away from the base substrate 100 .

[0204] In an exemplary embodiment, Figure 9a As shown, the material of the first insulating sublayer 1061 can be an organic material, and the material of the second insulating sublayer 1062 can be an inorganic material. The orthographic projection of the first insulating sublayer 1061 on the base substrate 100 does not overlap with the orthographic projection of the step portion (for example, the first step portion 1031b, the second step portion 1031c and the third step portion 1031d among the step portions) on the base substrate 100, and the orthographic projection of the second insulating sublayer 1062 on the base substrate 100 covers the orthographic projection of at least part of the step portion (for example, the first step portion 1031b and part of the third step portion 1031d among the step portions) on the base substrate 100.

[0205] In an exemplary embodiment, Figure 9b As shown, the materials of the first insulating sublayer 1061 and the second insulating sublayer 1062 can be organic materials, the orthographic projection of the first insulating sublayer 1061 on the base substrate 100 does not overlap with the orthographic projection of at least part of the step portion (for example, the first step portion 1031b and the second step portion 1031c among the step portions) on the base substrate 100, and the orthographic projection of the second insulating sublayer 1062 on the base substrate 100 covers the orthographic projection of at least part of the step portion (for example, the first step portion 1031b and the third step portion 1031d among the step portions) on the base substrate 100.

[0206] In an exemplary embodiment, Figure 9a As shown, the orthographic projection of the first insulating sublayer 1061 on the base substrate 100 may not overlap with the orthographic projection of the second bottom 1031e on the base substrate 100; Figure 9bAs shown, the orthographic projection of the first insulating sublayer 1061 on the base substrate 100 may overlap with the orthographic projection of the second bottom portion 1031 e and at least a portion of the third step portion 1031 d on the base substrate 100 .

[0207] In an exemplary embodiment, Figure 5a 、 Figures 5c to 9b As shown, the display substrate may further include:

[0208] The fourth metal layer 108 is located on the side of the third metal layer 1033 and the third insulating layer 106 away from the base substrate 100, wherein the fourth metal layer 108 can be electrically connected to the third metal layer 1033 through the third opening 130, and the orthographic projection of the fourth metal layer 108 on the base substrate 100 at least partially overlaps with the orthographic projection of the third metal layer 1033 on the base substrate 100. For example, the orthographic projection of the fourth metal layer 108 on the base substrate 100 can cover the orthographic projection of the third metal layer 1033 on the base substrate 100.

[0209] In an exemplary embodiment, Figure 5a 、 Figures 5c to 9b As shown, the display substrate may further include:

[0210] The fourth insulating layer 107 can be located between the third insulating layer 106 and the fourth metal layer 108 in the direction Z perpendicular to the plane of the base substrate 100, wherein the fourth insulating layer 107 can include a fourth opening 140, and the orthographic projection of the fourth opening 140 on the base substrate 100 is located within the orthographic projection of the third opening 130 on the base substrate 100, and the fourth metal layer 108 can be electrically connected to the third metal layer 1033 through the third opening 130 and the fourth opening 140.

[0211] In an exemplary embodiment, as shown in FIG8 c , it is a schematic structural diagram of the first metal layer 1031 without the second bottom portion 1031 e and the third step portion 1031 d .

[0212] In an exemplary embodiment, Figures 8a to 8c As shown, the orthographic projection of the second insulating layer 104 on the base substrate 100 partially overlaps with the orthographic projection of the first bottom 1031 a on the base substrate 100 , and the orthographic projection of the second opening 120 on the base substrate 100 is located in the orthographic projection of the first opening 110 on the base substrate 100 .

[0213] In an exemplary embodiment, Figures 5a to 7 、 Figures 9a to 9bAs shown, the orthographic projection of the second insulating layer 104 on the base substrate 100 does not overlap with the orthographic projection of the first bottom 1031 a and the step portion on the base substrate 100 , and the orthographic projection of the second opening 120 on the base substrate 100 covers the orthographic projection of the first opening 110 on the base substrate 100 .

[0214] In an exemplary embodiment, Figures 5a to 9b As shown, a dimension d1 of the first opening 110 along the width direction (ie, along the first direction X) may be 3 micrometers to 11 micrometers.

[0215] In an exemplary embodiment, Figures 5a to 6 、 Figures 8a to 9b As shown, the dimension d1 of the first opening 110 along the width direction may be 3 micrometers to 6 micrometers. For example, the dimension d1 of the first opening 110 along the width direction may be 6.8 micrometers.

[0216] In an exemplary embodiment, Figure 7 As shown, the dimension d1 of the first opening 110 along the width direction may be 5 micrometers to 8 micrometers. For example, the dimension d1 of the first opening 110 along the width direction may be 6.8 micrometers. Figure 7 In the structure shown, the dimension d1 of the first opening 110 along the width direction is Figures 5a to 6 、 Figures 8a to 9b The width dimension d1 of the first opening 110 shown is enlarged compared to the first metal layer 1031, so that the stacking structure of the third metal layer 1033 formed subsequently to the first metal layer 1031 in the pad 31 at the step portion (such as the first step portion 1031b and the second step portion 1031c) is consistent, avoiding cracks in the second metal layer 1032 and the third metal layer 1033 formed after the first metal layer 1031 due to the process waveguide, and trying to avoid the cracks in the third metal layer 1033 causing the second metal layer 1032 to be exposed.

[0217] In an exemplary embodiment, in a direction Z perpendicular to the plane of the base substrate 100, the metal particles in the metal film layer closest to the first electrode 301 among the multiple metal film layers in the bonding pad 31 located between the base substrate 100 and the first electrode 301 (anode) have the lowest activity. This prevents the metal film layer closest to the first electrode 301 from being replaced with corresponding metal particles during the etching process of the first electrode 301 (for example, replacing silver ions in the wet etching solution with silver particles). In an exemplary embodiment, the metal particle activity of the metal film layer closest to the first electrode 301 is no greater than the activity of the metal ions in the wet etching solution used to etch the first electrode 301. For example, if the metal film layer closest to the first electrode 301 is the third metal layer 1033, the metal particle activity of the metal layer of the third metal layer 1033 closest to the first electrode 301 is no greater than the activity of the metal corresponding to the metal ions in the subsequent wet etching solution for the first electrode 301 (for example, silver corresponding to the silver ions in the wet etching solution).

[0218] In an exemplary embodiment, the third metal layer 1033 may have a single-layer structure, and the metal activity of the metal layer closest to the third metal layer 1033 in the second metal layer 1032 is no less than the metal activity of the third metal layer 1033. For example, in a structure where the first metal layer 1031, the second metal layer 1032, and the third metal layer 1033 are all single-layer structures, the activity of the metal particles in the third metal layer 1033 is less than the activity of the metal particles in the first metal layer 1031 and the second metal layer 1032. For example, the first metal layer 1031 and the second metal layer 1032 may be made of aluminum, and the third metal layer 1033 may be made of titanium or molybdenum. In a structure in which the first metal layer 1031 and the second metal layer 1032 are a multi-layer composite structure and the third metal layer 1033 is a single layer, the metal activity in the third metal layer 1033 is not greater than the metal activity in the metal layer closest to the third metal layer 1033 in the second metal layer 1032. For example, the first metal layer 1031 and the second metal layer 1032 are a multi-layer composite structure using Ti / Al / Ti, and the material of the third metal layer 1033 can be titanium or molybdenum.

[0219] In an exemplary embodiment, the third metal layer 1033 may be a multi-layer complex structure, and in a direction Z perpendicular to the plane of the substrate, the metal activity of the metal layer farthest from the second metal layer 1032 in the third metal layer 1033 is not greater than the metal activity of the metal layer between the farthest metal layer and the second metal layer 1032. Figure 9dAs shown, third metal layer 1033 may include a first third metal sub-layer 10331, a second third metal sub-layer 10332, and a third third metal sub-layer 10333. The metal activity in third third metal sub-layer 10333 is no greater than the metal activity in first third metal sub-layer 10331 and second third metal sub-layer 10332. For example, the metal activity in first third metal sub-layer 10331 is less than the metal activity in second third metal sub-layer 10332. In an exemplary embodiment, the metal of first third metal sub-layer 10331 and third third metal sub-layer 10333 may be titanium (Ti), and the metal of second third metal sub-layer 10332 may be aluminum (Al). That is, third metal layer 1033 has a multi-layer composite structure of Ti / Al / Ti. In an exemplary embodiment, the activity of the metal material in the metal layer of the third metal layer 1033 closest to the first electrode 301 is no greater than the activity of the metal ions in the wet etching solution for etching the anode, thereby preventing the metal in the metal layer of the third metal layer 1033 closest to the first electrode 301 from being replaced by the metal ions in the wet etching solution with corresponding metal particles, thereby preventing the replaced metal particles from being washed into the display area during the etching of the anode and the subsequent water washing process (such as cleaning the completed anode), causing a short circuit between the anode and the cathode.

[0220] like Figure 9c and Figure 9d In the structure shown, a bump structure (Bump) formed by stacking the first metal layer 1031, the second metal layer 1032, and the third metal layer 1033 is formed around the edge of the first opening 110. The surface of the first step portion 1031b on the side away from the base substrate 100 is covered by the second insulating layer 104 in an inconsistent manner, that is, a portion of the surface of the first step portion 1031b on the side away from the base substrate 100 is covered by the second insulating layer 104 and a portion is not covered by the second insulating layer 104, resulting in a large step difference in the third metal layer 1033 at the edge of the first opening 110 (also near the first step portion 1031b), which makes it easy for the third metal layer 1033 to form a crack Q1 on the first step portion 1031b, exposing the second metal layer 1032 (as shown in FIG. Figure 9c As shown) or expose the metal layer with greater activity in the middle of the third metal layer 1033 (as shown Figure 9d As shown), the exposed second metal layer 1032 or the exposed third metal layer 1033 with a relatively high activity is replaced by the silver ions in the wet etching solution during the anode manufacturing process to form silver particles. The silver particles flow to the anode opening position of the display area AA under the flushing of the wet etching solution or the subsequent flushing of the anode washing solution, causing the anode (i.e., the first electrode 301) and the cathode (i.e., the second electrode 302) in the display area to short-circuit and form dark spots. In the embodiment of the present disclosure, by Figures 5a to 9bIn the structure shown, the surface of the first step portion 1031b away from the base substrate 100 is covered by the second insulating layer 104 in the same manner, which can largely avoid the problem of cracks in the third metal layer 1033 due to the large step difference in the position of the first step 1031b, thereby reducing the risk of dark spots in the display area AA caused by cracks in the third metal layer 1033.

[0221] In an exemplary embodiment, Figure 2 、 Figures 5a to 9b As shown, the first insulating layer 102 can be provided in the same layer as the interlayer insulating layer 203 and the second gate insulating layer 202, the second insulating layer 104 can be provided in the same layer as the passivation layer 204, the third insulating layer 106 can be provided in the same layer as the third planar layer 207, and the fourth insulating layer 107 can be provided in the same layer as at least one of the touch interlayer insulating layer 502 and the pixel definition layer 304. For example, a barrier layer, a buffer layer, etc. can also be arranged between the substrate and the plurality of data line leads (i.e., the gate metal layer). Figures 5a to 9b The first metal layer 1031 can be provided in the same layer as the first source-drain metal layer, the second metal layer 1032 can be provided in the same layer as the second source-drain metal layer, the third metal layer 1033 can be provided in the same layer as the third source-drain metal layer, and the fourth metal layer 108 can be provided in the same layer as one of the first touch conductive layer and the second touch conductive layer. In an exemplary embodiment, the third insulating layer 106 is not limited to being provided in the same layer as the third planar layer 207. For example, Figure 9a and Figure 9b As shown, the first insulating sublayer 1061 can be provided on the same layer as the third flat layer 207 (the opening of the third flat layer 207 at the position of the pad 31 covers the second opening 120 of the second insulating sublayer 1062 at the position of the pad 31), or, in the direction Z perpendicular to the plane of the base substrate 100, the first insulating sublayer 1061 can be located between the third flat layer 207 and the second insulating sublayer 1062; Figures 5a to 8c As shown, the third insulating layer 106 can be provided on the same layer as the third planar layer 207 , or, in a direction Z perpendicular to the plane of the substrate 100 , the third insulating layer 106 can be located between the third planar layer 207 and the first electrode 301 (ie, the anode).

[0222] In an exemplary embodiment, the base substrate 100 may be a flexible substrate, such as PEN resin, silicone resin, or polyimide. The first, second, and third insulating layers may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single, multi-layer, or composite layers. The first, second, and third planarizing layers may be made of organic materials, such as PEN resin, silicone resin, or polyimide. The data line lead, the first metal layer, the second metal layer, the third metal layer and the fourth metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Cu / Mo, etc.; in an exemplary embodiment, the first metal layer, the second metal layer and the third metal layer are single-layer structures, the metal activity of the third metal layer is not greater than the metal activity of the first metal layer and the second metal layer, and the metal activity of the third metal layer is not greater than the activity of the metal ions in the wet etching solution for making the anode. For example, the first metal layer and the second metal layer can be made of aluminum, and the third metal layer can be made of silver. In a multi-layer composite structure of the first, second, and third metal layers, if the third metal layer is a two-layer structure, the metal activity in the film layer facing away from the second metal layer is less than the metal activity in the film layer facing closer to the second metal layer. If the third metal layer is a three-layer structure, the metal activity in the middle metal film layer is greater than the metal activity in the metal film layers on either side in a direction perpendicular to the plane of the substrate. For example, in a direction perpendicular to the plane of the substrate, the third metal layer may include a titanium (Ti) film layer, an aluminum (Al) film layer, and a titanium (Ti) film layer sequentially disposed on the side of the second metal layer facing away from the substrate, i.e., the third metal layer may have a Ti-Al-Ti three-layer composite structure. In an exemplary embodiment, the first, second, and third metal layers may all have a Ti-Al-Ti three-layer composite structure, and the data line lead 101 may have a molybdenum (Mo) or aluminum (Al) single-layer structure.

[0223] In an exemplary embodiment, metal activity refers to the tendency of a metal element to lose electrons to form metal cations in an aqueous solution. The easier it is for a metal to lose electrons to form metal cations, the greater the activity of the metal. For example, the activity of silver (Ag) is less than that of titanium (Ti), and the activity of titanium (Ti) is less than that of aluminum (Al).

[0224] In an exemplary embodiment, Figures 10a to 12b As shown, Figure 10a and Figure 10b Schematic diagram of a planar structure of a display substrate. Figures 11a to 11d for Figure 10a and Figure 10b Schematic diagrams of several cross-sectional structures at the M1-M1 position. Figures 12a to 12c for Figure 10a and Figure 10b Schematic diagrams of several cross-sectional structures at the position M2-M2, the base substrate 100 may include a packaging area A1 and an edge area BB2 located around the packaging area A1, the edge area BB2 includes a binding area B0 on ​​the side of at least one edge of the base substrate 100, and the binding area B0 is located in the first border area B1;

[0225] A plurality of inorganic film layers are located on one side of the base substrate 100 and are stacked;

[0226] A plurality of first grooves C1 are located in the edge area BB2 and are sequentially spaced apart in a direction away from the packaging area A1 and partially surround the packaging area A1, wherein each first groove C1 penetrates at least one inorganic film layer among the plurality of inorganic film layers, and the orthographic projections of the plurality of first grooves C1 on the base substrate 100 do not overlap with the binding area;

[0227] The organic layer 03 covers the plurality of first grooves C1 .

[0228] In an exemplary embodiment, Figure 10a As shown, the binding area B0 may include a fan-out routing area B11 and a signal access area B12. Figure 10b As shown, the binding area B0 may include a fan-out routing area B11 , a signal access area B12 and a bending area B13 .

[0229] In an exemplary embodiment, Figure 12a As shown, the organic layer 03 may include: a first flat layer 205 and a second flat layer 206 stacked in sequence along a direction Z away from the base substrate 100, the first flat layer 205 covers a plurality of first grooves C1, and the second flat layer 206 is located on a side of the first flat layer 205 away from the base substrate 100.

[0230] In an exemplary embodiment, Figure 12b As shown, the organic layer 03 covering the first groove C1 only has the first flat layer 205, and no second flat layer 206. There is usually a residue ML of the first metal layer 1031 at the position of the first groove C1. If the thickness of the first flat layer 205 is not enough, the residue ML will pierce the first flat layer 205 and be exposed. During the etching of the first electrode 301 (anode), the residue ML replaces the silver ions in the wet etching solution to form silver particles. The silver particles will be washed to the opening position of the anode during the etching of the first electrode 301 and the subsequent washing process (such as cleaning the completed anode), causing a short circuit between the anode and the cathode in the display area to form dark spots. Figure 12a and Figure 12c In the structure shown, the organic layer 03 covering the first groove C1 may include a first flat layer 205 and a second flat layer 206. The residue ML is generally unable to pierce the second flat layer 206 (which can avoid exposure of the residue ML), thereby avoiding exposure of the residue ML at the position of the first groove C1 and reducing the risk of a short circuit between the anode and the cathode forming a dark spot due to the residue in the first groove C1.

[0231] In an exemplary embodiment, Figure 11b and Figure 12a As shown, the first insulating layer 102 may include: a gate insulating layer (which may include a second gate insulating layer 202) and an interlayer dielectric layer 203 stacked in sequence along a direction Z away from the base substrate 100, and at least one inorganic film layer may include a gate insulating layer (which may include a first gate insulating layer 201 and a second gate insulating layer 202) and an interlayer dielectric layer 203.

[0232] In an exemplary embodiment, Figures 11a to 12a As shown, the inorganic film layer between each two adjacent first grooves C1 constitutes a blocking portion ZL; the multiple inorganic film layers may also include: a buffer layer 1502 located between the base substrate 100 and the gate insulating layer 201 in a direction Z perpendicular to the plane of the base substrate 100, as shown in FIG. Figure 11c and Figure 11d As shown, the at least one inorganic film layer may further include at least a portion of a buffer layer 1502 .

[0233] In this exemplary embodiment, because the multiple first grooves C1 are located within the edge region BB2, there is a gap between them and the encapsulation region A1. Therefore, these first grooves C1 can block cracks that appear at the edge of the display substrate, preventing them from extending toward the encapsulation region A1. Because these first grooves C1 can block the extension of cracks, the inorganic film layer between two adjacent first grooves C1 forms a barrier ZL, also known as a crack dam.

[0234] In an exemplary embodiment, Figures 11a to 12a As shown, the plurality of inorganic film layers may further include: a barrier layer 1501 located between the base substrate 100 and the buffer layer in a direction Z perpendicular to the plane where the base substrate 100 is located, as shown in FIG. Figure 11d As shown, at least one inorganic film layer may also include at least a partial barrier layer. By first forming a barrier layer 1501 made of an inorganic material on the side away from the base substrate 100, water vapor or oxygen can be effectively blocked from entering the base substrate 100, thereby improving the water barrier, oxygen barrier, and scratch resistance of the base substrate 100.

[0235] refer to Figures 10a to 10bIt can be seen that the orthographic projection of each first groove C1 on the base substrate 01 may be a ring with an opening k0 (ie, the first groove C1 does not overlap with the binding area B0, and the opening k0 is formed in the binding area B0). Figures 10a to 10b , which shows a first groove C1 including two annular grooves with openings, Figures 11a to 12a The number of first grooves C1 shown is five. The number of first grooves C1 is not limited to two or five and can be set according to the actual product. The number of first grooves C1 at different locations in the edge area BB2 can be the same or different (for example, the number of first grooves C1 in the edge area BB2 of the second border area B2 can be the same as or different from the number of first grooves C1 in the edge area BB2 of the third border area B3 and the fourth border area BB2). Each ring (i.e., each first groove C1) can surround the packaging area A1, and the orthographic projection of each opening k0 on the base substrate 100 can at least partially overlap with the binding area B0, i.e., the width of each opening (the dimension along the first direction X) can be greater than the width of the binding area B0. In an exemplary embodiment, the first groove C1 can be disconnected at the opening k0 (i.e., the first groove C1 can be disconnected in the binding area B0), and the area outside the opening k0 of the first groove C1 can also be disconnected.

[0236] In an exemplary embodiment, Figure 2 As shown, the display area of ​​the display substrate may include: a gate metal layer located on a base substrate 100, a gate insulating layer (201, 202) located on a side of the gate metal layer facing away from the base substrate 100, and a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially arranged on a side of the gate insulating layer (201, 202) facing away from the base substrate 100;

[0237] In a direction Z perpendicular to the plane of the base substrate 100 , the first planar layer 205 may be located between the first source-drain metal layer and the second source-drain metal layer, and the second planar layer may be located between the second source-drain metal layer and the third source-drain metal layer.

[0238] In an exemplary embodiment, Figure 2 As shown, multiple data line leads 101 can be set in the same layer as the gate metal layer, the first insulating layer 102 can be set in the same layer as the gate insulating layer, the first metal layer 1031 can be set in the same layer as the first source and drain metal layer, the second metal layer 1032 can be set in the same layer as the second source and drain metal layer, and the third metal layer 1033 can be set in the same layer as the third source and drain metal layer.

[0239] In an exemplary embodiment, Figures 10a to 12aAs shown, the multiple first grooves C1 in the display substrate can be arranged at equal intervals, that is, the interval between each two adjacent first grooves C1 can be a fixed value. By arranging multiple first grooves C1 at intervals, the extension of cracks can be further effectively avoided, thereby ensuring the quality of the display substrate.

[0240] In an exemplary embodiment, Figure 12a and Figure 2 The difference is that Figure 12a The third source / drain metal layer and the third planar layer 207 are not provided. Figure 12a In the structure shown, the third source / drain metal layer is not provided, and the corresponding structure of the pad 31 may include a first metal layer 1031 and a second metal layer 1032 .

[0241] In an exemplary embodiment, Figure 10a 、 Figure 10b and Figure 12a As shown, the packaging area A1 may include a display area AA and a peripheral area BB1 surrounding the display area AA, and the frame area BB may include a peripheral area BB1 and an edge area BB2. The peripheral area BB1 may be provided with a peripheral circuit, and the edge area BB2 may be provided with a first groove C1. Figure 12a In the figure, T1 is one of the transistors located in the display area AA, T2 and T3 are two transistors located in the peripheral area BB1, 22-1 and 22-2 are two capacitors located in the peripheral area BB1, and in the peripheral area BB1: the low voltage line VGL is electrically connected to the second electrode 303 through the third switching electrode 233 and the fourth switching electrode 234.

[0242] In an exemplary embodiment, Figure 10a 、 Figure 10b and Figure 12a As shown, a barrier dam 04 can be provided in the peripheral area BB1. The barrier dam 04 can also be made of an organic material. The orthographic projection of the organic layer 03 on the base substrate 01 and the orthographic projection of the barrier dam 04 on the base substrate 01 do not need to overlap. Because the barrier dam 04 is located within the peripheral area BB1, a gap D11 exists between the barrier dam 04 and the display area AA. This effectively prevents the organic material from flowing out of the encapsulation area AA when the organic material is used to form the organic encapsulation film layer in the encapsulation film. This effectively prevents moisture from entering the display area due to the hydrophilic nature of the organic material, thereby affecting the quality of the display area. This further ensures the quality of the display substrate.

[0243] In an exemplary embodiment, Figure 10a 、 Figure 10b and Figure 12aAs shown, the barrier dam 04 may include at least one closed annular structure 041, and each annular structure 041 may surround the display area AA of the base substrate 100. By surrounding the display area AA with the annular structure 041, effective protection may be achieved around the display area AA.

[0244] In an exemplary embodiment, Figure 10a 、 Figure 10b and Figure 12a As shown, the barrier dam 04 may include a plurality of spaced annular structures 041. For example, Figure 10a 、 Figure 10b Each embodiment shows a barrier dam 04 comprising two annular structures 041. Furthermore, the multiple annular structures 041 can be arranged at equal intervals, i.e., the spacing between each two adjacent annular structures 041 can be a fixed value. By spacing multiple annular structures 041, effective protection of the display area AA can be further enhanced. For example, the barrier dam 04 can be formed by deposition.

[0245] In the embodiment of the present disclosure, the base substrate 100 may be made of a flexible material, such as polyimide (PI), which has good properties such as high temperature resistance, low temperature resistance, and oxidation resistance.

[0246] In an exemplary embodiment, Figure 10a and Figure 10b As shown, the edge region BB2 of the base substrate 100 may also be provided with a cutting line L1 surrounding the first groove C1. After forming an inorganic film layer having multiple first grooves C1 on one side of the base substrate 01, the substrate can be cut along the cutting line L1 to obtain a display substrate. Accordingly, the annular first groove C1 may be designed to follow the shape of the cutting line L1. Since cracks are prone to forming at the edge of the display substrate during cutting, designing the first groove C1 along the shape of the cutting line L1 can effectively block any cracks generated during the cutting operation, effectively preventing any cracks from extending during the cutting operation.

[0247] by Figure 5a As an example, the method for preparing the pad 31 in the display substrate is described as follows: a metal film, such as a gate metal film, is prepared on one side of the base substrate 100, and a patterning process is performed to form a metal film such as a gate metal film. Figure 13aThe data line lead 101 shown is then formed by preparing a first insulating layer 102. The first insulating layer 102 may be, for example, an insulating layer composed of a gate insulating layer and an interlayer insulating layer. A first opening 110 exposing at least a portion of the data line lead is formed by etching on the first insulating layer 102. Next, a first source and drain metal film is formed on the side of the data line lead 101 and the first insulating layer 102 facing away from the base substrate 100. The first source and drain metal film is patterned by a patterning process to form the following structure: Figure 13b Next, the sidewalls of the first metal layer 1031 are formed as shown in FIG. Figure 13c The second insulating layer 104 shown in the figure prevents the metal elements (such as Al) in the first metal layer from being exposed and causing corrosion or dark spots and other abnormalities. The second insulating layer 104 is provided with a second opening 120 that exposes the first metal layer 1031. Next, a second source and drain metal film is formed, and the second source and drain metal film is patterned by a patterning process to form the following Figure 13d Next, a third source-drain metal film is formed, and the third source-drain metal film is patterned by a patterning process to form a second metal layer 1032 as shown. Figure 13e Next, a third metal layer 1033 is prepared on the side of the third metal layer 1033 away from the substrate 100. Figure 13f The third insulating layer 106 shown in the figure can be provided on the same layer as the third flat layer. A third sub-opening 1301 exposing the third metal layer 1033 is etched on the third insulating layer 106. The orthographic projection of the third sub-opening 1301 on the base substrate 100 is located within the range of the first opening 110 on the base substrate 100. Next, the light-emitting structure layer 30, the encapsulation structure layer 40, and the touch structure layer 50 in the display area AA are prepared on the side of the third insulating layer 106 away from the base substrate 100. In the process of forming the pixel definition layer 304 of the light-emitting structure layer 30 or in the process of forming the touch interlayer insulating layer (TLD) 502 of the touch structure layer 50, the following is formed. Figure 13g The fourth insulating layer 107 in the pad 31 is shown, and the third opening 130 is formed while forming the fourth opening 140 in the fourth insulating layer 107. The second touch conductive layer 512 in the touch structure layer 50 is formed as shown. Figure 5a The fourth metal layer 108 is shown. Figures 13a to 13fIn the preparation process shown, before forming the anode, the third insulating layer 106 can wrap the third metal layer 1033 at the position corresponding to the first step 1301b, so as to avoid the second metal layer 1032 exposed by the cracks in the third metal layer 1033 during the preparation of the anode, or the metal film layer with higher activity in the middle of the exposed third metal layer 1033 being replaced with the metal ions in the anode wet etching solution to form metal particles, thereby preventing the metal particles from scouring the display area and causing a short circuit between the anode and the cathode to form dark spots.

[0248] by Figure 6 Taking the structure in FIG. 1 as an example, the preparation method of the pad 31 in the display substrate is described: the method of forming the data line lead 101 to forming the third insulating layer 106 is the same as that of FIG. Figures 13a to 13f same, Figure 13f The third sub-opening 1301 in the display area AA can be used as the third opening 130, and the light emitting structure layer 30, the encapsulation structure layer 40, and the touch structure layer 50 are prepared on the side of the third insulating layer 106 away from the base substrate 100. In the process of forming the pixel definition layer 304 of the light emitting structure layer 30 or in the process of forming the touch interlayer insulating layer (TLD) 502 of the touch structure layer 50, the following is formed: Figure 14 The fourth insulating layer 107 in the pad 31 is shown, and a fourth opening 140 is formed on the fourth insulating layer 107. In the process of preparing the second touch conductive layer 512 in the touch structure layer 50, the following is formed. Figure 6 The fourth metal layer 108 is shown. The orthographic projection of the third opening 130 on the substrate is within the range of the orthographic projection of the first opening 110 on the substrate. Before forming the anode, the third insulating layer 106 can wrap the third metal layer 1033 at the position corresponding to the first step 1301b. This can prevent the second metal layer 1032 exposed by cracks in the third metal layer 1033 during the preparation of the anode, or the exposed metal film layer with a higher activity in the middle of the third metal layer 1033 from replacing the metal ions in the anode wet etching solution to form metal particles, thereby preventing the metal particles from scouring the display area and causing a short circuit between the anode and the cathode to form dark spots.

[0249] The present disclosure also provides a method for manufacturing the display substrate described in any of the above embodiments, forming a display substrate as shown in FIG. Figure 1a 、 Figure 1b 、 Figures 3 to 9b The display substrate shown, the method may include:

[0250] Providing a base substrate 100, the base substrate 100 includes a display area AA and a first frame area B1 located on at least one side of the display area AA;

[0251] A plurality of sub-pixels PX, a plurality of data lines DL, and a plurality of data line leads 101 are prepared on one side of a base substrate 100. The plurality of sub-pixels PX and the plurality of data lines DL are located in a display area AA and the plurality of sub-pixels PX are electrically connected to the plurality of data lines DL. The plurality of data line leads 101 are located in a first frame area B1 and are electrically connected to the plurality of data lines DL.

[0252] A plurality of pads 31 are formed in the first frame area B1, and the steps of forming at least one of the plurality of pads 31 include:

[0253] A first insulating layer 102 is formed on a side of the plurality of data line leads 101 facing away from the base substrate 100 , wherein the first insulating layer 102 includes a first opening 110 exposing at least a portion of at least one data line lead 101 among the plurality of data line leads 101 ;

[0254] A first metal layer 1031 is formed on a side of the plurality of data line leads 101 facing away from the base substrate 100. The first metal layer 1031 is electrically connected to at least one of the plurality of data line leads 101 through the first opening 110. The first metal layer 1031 includes a first bottom portion 1031a and a step portion surrounding the first bottom portion 1031a. The orthographic projection of the first bottom portion 1031a on the base substrate 100 is located within the orthographic projection of the first opening 110 on the base substrate 100. 031a is electrically connected to one of the multiple data line leads 101, and the step portion includes a first step portion 1031b located on a side of the first insulating layer 102 away from the base substrate 100 and a second step portion 1031c forming an angle with the first step portion 1031b, the second step portion 1031c connects the first bottom portion 1031a and the first step portion 1031b, and the orthographic projection of the second step portion 1031c on the base substrate 100 is located in the orthographic projection of the first opening 110 on the base substrate 100;

[0255] A second insulating layer 104 is formed on the side of the first metal layer 1031 and the first insulating layer 102 facing away from the base substrate 100, wherein the second insulating layer 104 includes a second opening 120 exposing at least a portion of the first bottom 1031a of the first metal layer 1031, and the first step portion 1031b is covered by the second insulating layer 104 in the same manner as the side away from the base substrate 100.

[0256] In an exemplary embodiment, Figures 5a to 7 、 Figures 9a to 9bAs shown, there is no overlapping area between the orthographic projection of the first step portion 1031b on the base substrate 100 and the orthographic projection of the second insulating layer 104 on the base substrate 100, and the orthographic projection of the second opening 120 on the base substrate 100 covers the orthographic projections of the first opening 110, the first step portion 1031b and the first bottom portion 1031a on the base substrate 100.

[0257] In an exemplary embodiment, Figures 8a to 8c As shown, the orthographic projection of the first step portion 1031 b on the base substrate 100 is covered by the orthographic projection of the second insulating layer 104 on the base substrate 100 , and the orthographic projection of the second opening 120 on the base substrate 100 is within the range of the orthographic projection of the first opening 110 on the base substrate 100 .

[0258] In an exemplary embodiment, the method may further include:

[0259] A second metal layer 1032 is formed on the side of the first metal layer 1031 and the second insulating layer 104 facing away from the base substrate 100, wherein the second metal layer 1032 is electrically connected to the first metal layer 1031 through the second opening 120, and the orthographic projection of the second metal layer 1032 on the base substrate 100 at least partially overlaps with the orthographic projection of the second opening 120 on the base substrate 100, forming a display substrate such as Figures 5a to 9b shown.

[0260] In an exemplary embodiment, the method may further include:

[0261] A third metal layer 1033 is formed on the side of the second metal layer 1032 facing away from the base substrate 100, wherein the third metal layer 1033 is electrically connected to the second metal layer 1032, and the orthographic projection of the third metal layer 1033 on the base substrate 100 covers the orthographic projection of the second metal layer 1032 on the base substrate 100, forming a display substrate such as Figures 5a to 9b shown.

[0262] In an exemplary embodiment, the method may further include:

[0263] A third insulating layer 106 is formed on a side of the third metal layer 1033 facing away from the substrate 100 , wherein the third insulating layer 106 includes a third opening 130 ;

[0264] Among them, Figure 5b 、 Figure 6 and Figure 7 As shown, the orthographic projection of the third opening 130 on the base substrate 100 is located within the orthographic projections of the first opening 110 and the second opening 120 on the base substrate 100; or, as shown Figures 8a to 8cAs shown, the orthographic projections of the first opening 110 and the second opening 120 on the base substrate 100 are located within the orthographic projection of the third opening 130 on the base substrate 100; or, as shown Figure 5a 、 Figure 5c 、 Figures 9a to 9b As shown, the orthographic projection of the third opening 130 on the base substrate 100 is within the range of the orthographic projection of the second opening 120 on the base substrate 100 , and the orthographic projection of the first opening 110 on the base substrate 100 is within the range of the orthographic projection of the third opening 130 on the base substrate 100 .

[0265] In an exemplary embodiment, the method may further include:

[0266] On the side of the third metal layer 1033 facing away from the substrate 100, a Figure 13f The third insulating layer 106 shown includes a third sub-opening 1301. The orthographic projection of the third insulating layer 106 on the base substrate 100 covers the step portions (for example, the first step portion 1031b, the second step portion 1031c, and the third step portion 1031d) and the orthographic projection of a portion of the first bottom portion 1031a on the base substrate 100. The orthographic projection of the third sub-opening 1301 on the base substrate 100 is located within the orthographic projection of the first opening 110 on the base substrate 100.

[0267] An anode conductive layer is formed on a side of the third insulating layer 106 away from the base substrate 100 , wherein the anode conductive layer includes a plurality of anodes (ie, first electrodes 301 );

[0268] On the side of the anode conductive layer away from the base substrate 100, a Figure 13g The fourth insulating layer 107 shown and the third opening 130 corresponding to the third sub-opening 1301 are formed in the third insulating layer 106. The fourth insulating layer 107 includes a fourth opening 140. The orthographic projection of the fourth opening 140 on the base substrate 100 is located within the orthographic projection of the third opening 130 on the base substrate 100. The orthographic projection of the third sub-opening 1301 on the base substrate 100 is located within the orthographic projection of the corresponding third opening 130 on the base substrate 100.

[0269] In an exemplary embodiment, the orthographic projection of the third sub-opening 1301 on the base substrate 100 is located within the orthographic projection of the corresponding third opening 130 on the base substrate 100. During the process of manufacturing the anode (i.e., the first electrode 301), the third insulating layer 106 can wrap the third metal layer 1033 at the position corresponding to the first step 1301b, which can prevent the second metal layer 1032 exposed by the cracks in the third metal layer 1033 during the preparation of the anode, or the exposed third metal layer 1033 with a higher activity in the middle, from replacing the metal ions in the anode wet etching solution to form metal particles, thereby preventing the metal particles from scouring the display area and causing a short circuit between the anode and the cathode to form dark spots.

[0270] In an exemplary embodiment, Figure 13f As shown, the width dimension d3 of the third sub-opening 1301 may be 2 microns to 5 microns. Figure 13g and Figure 5a As shown, the width dimension d4 of the third opening 130 may be 5 micrometers to 9 micrometers.

[0271] In an exemplary embodiment, Figure 6 and Figure 5b In the structure shown, the width dimension d4 of the third opening 130 may be 2 microns to 6 microns.

[0272] In an exemplary embodiment, Figures 5a to 8b 、 Figures 9a to 9b As shown, the first metal layer 1031 may further include a second bottom portion 1031e surrounding the step portion, and the step portion further includes a third step portion 1031d forming an angle with the first step portion 1031b, the third step portion 1031d connecting the second bottom portion 1031e and the first step portion 1031b, and the orthographic projection of the second insulating layer 104 on the base substrate 100 at least partially overlaps with the orthographic projection of the second bottom portion 1031e on the base substrate 100.

[0273] In an exemplary embodiment, Figures 8a to 8c As shown, the orthographic projection of the second insulating layer 104 on the base substrate 100 partially overlaps with the orthographic projection of the first bottom 1031 a on the base substrate 100 , and the orthographic projection of the second opening 120 on the base substrate 100 is located in the orthographic projection of the first opening 110 on the base substrate 100 .

[0274] In an exemplary embodiment, Figures 5a to 7 、 Figures 9a to 9bAs shown, the orthographic projection of the second insulating layer 104 on the base substrate 100 does not overlap with the orthographic projection of the first bottom 1031a and the step portion (for example, the first step portion 1031b, the second step portion 1031c and the third step portion 1031d of the step portion) on the base substrate 100, and the orthographic projection of the second opening 120 on the base substrate 100 covers the orthographic projection of the first opening 110 on the base substrate 100.

[0275] In an exemplary embodiment, Figures 10a to 12b As shown, the base substrate 100 may include a packaging area A1 and an edge area BB2 located around the packaging area A1, the edge area BB2 includes a binding area on the side where at least one edge of the base substrate 100 is located, and the binding area is located in the first border area B1; the method may further include:

[0276] A plurality of stacked inorganic film layers are formed on one side of the base substrate 100 using an inorganic material;

[0277] A plurality of first grooves C1 are formed in the edge area BB2 and are spaced apart from each other in a direction away from the packaging area A1 and extend along the periphery of the base substrate 100. Each first groove C1 penetrates at least one inorganic film layer among the plurality of inorganic film layers. The orthographic projections of the plurality of first grooves C1 on the base substrate 100 do not overlap with the binding area.

[0278] An organic layer 03 covering the plurality of first grooves C1 is formed using an organic material.

[0279] In an exemplary embodiment, Figure 12a As shown, the organic layer 03 may include: a first flat layer 205 and a second flat layer 206 sequentially stacked along a direction Z away from the base substrate 100, and the first flat layer 205 and the second flat layer 206 are located on a side of the plurality of inorganic film layers away from the base substrate 100;

[0280] The first insulating layer 102 may include: a gate insulating layer (201 / 202) and an interlayer dielectric layer (203) stacked in sequence along a direction Z away from the base substrate 100, and at least one inorganic film layer may include the gate insulating layer (201 / 202) and the interlayer dielectric layer 203.

[0281] The present disclosure also provides a display device, such as Figure 15 As shown, the display device may include: a display substrate. The display substrate may be the display substrate provided by any of the above embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0282] In an exemplary embodiment, the display device may be a liquid crystal display (LCD), an organic light emitting diode (OLED), or a light emitting diode (LED) display device. The display device may be any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0283] The display substrate and display device provided by the embodiments of the present disclosure include a plurality of data lines and a plurality of sub-pixels located in the display area, and a plurality of data line leads and a plurality of pads located in the first frame area. The plurality of data lines are electrically connected to the plurality of sub-pixels, and the plurality of data line leads are electrically connected to the plurality of data lines and the plurality of pads. At least one of the plurality of pads includes a first insulating layer, a first metal layer, and a second insulating layer stacked in sequence on a side of the data line lead facing away from the base substrate. The first insulating layer is provided with a first opening. The first metal layer is electrically connected to at least one of the plurality of data line leads through the first opening. The first metal layer includes a first bottom and a surrounding The step portion of the first bottom portion, the orthographic projection of the first bottom portion on the base substrate is located within the orthographic projection of the first opening on the base substrate, the first bottom portion is electrically connected to at least one data line lead among the multiple data line leads, the step portion includes a first step portion and a second step portion at an angle to the first step portion, the second step portion connects the first bottom portion and the first step portion, the orthographic projection of the second step portion on the base substrate is located within the orthographic projection of the first opening on the base substrate, and the second insulating layer includes a second opening exposing at least a portion of the first bottom portion; the technical solution provided by the embodiment of the present disclosure can, to a certain extent, reduce or avoid the short circuit between the anode and the cathode in the display area to form dark spots.

[0284] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0285] In the absence of conflict, the embodiments of the present disclosure, i.e., features in the embodiments, can be combined with each other to form new embodiments.

[0286] Although the embodiments disclosed in the present disclosure are as described above, the contents described are only embodiments adopted to facilitate understanding of the embodiments of the present disclosure and are not intended to limit the embodiments of the present disclosure. Any person skilled in the art in the field to which the embodiments of the present disclosure belong may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the embodiments of the present disclosure, but the scope of patent protection of the embodiments of the present disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, characterized in that: include: A base substrate, the base substrate comprising a display area and a first frame area located on at least one side of the display area; A plurality of sub-pixels are located on one side of the base substrate and in the display area; a plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels; a plurality of data line leads, located in the first frame area and electrically connected to the plurality of data lines; A plurality of pads are located in the first frame area and are electrically connected to the plurality of data line leads; wherein, At least one of the plurality of pads comprises: a first insulating layer located on a side of the plurality of data line leads facing away from the base substrate, the first insulating layer comprising a first opening exposing at least a portion of at least one data line lead among the plurality of data line leads; a first metal layer, located on a side of the plurality of data line leads facing away from the base substrate, and electrically connected to at least one of the plurality of data line leads through the first opening; wherein the first metal layer includes a first bottom portion and a step portion surrounding the first bottom portion, an orthographic projection of the first bottom portion on the base substrate being located within an orthographic projection of the first opening on the base substrate, the first bottom portion being electrically connected to at least one of the plurality of data line leads, the step portion including a first step portion located on a side of the first insulating layer away from the base substrate, and a second step portion forming an angle with the first step portion, the second step portion connecting the first bottom portion and the first step portion, and an orthographic projection of the second step portion on the base substrate being located within an orthographic projection of the first opening on the base substrate; A second insulating layer is located on a side of the first metal layer and the first insulating layer facing away from the substrate, wherein the second insulating layer includes a second opening exposing at least a portion of the first bottom of the first metal layer.

2. The display substrate according to claim 1, wherein: The orthographic projection of the first step portion on the base substrate does not overlap with the orthographic projection of the second insulating layer on the base substrate, and the orthographic projection of the second opening on the base substrate covers the orthographic projections of the first opening, the first step portion, and the first bottom portion on the base substrate; Alternatively, the orthographic projection of the first step portion on the base substrate is covered by the orthographic projection of the second insulating layer on the base substrate, and the orthographic projection of the second opening on the base substrate is within the range of the orthographic projection of the first opening on the base substrate.

3. The display substrate according to claim 1, wherein Also includes: a second metal layer located on a side of the first metal layer and the second insulating layer facing away from the base substrate, wherein the second metal layer is electrically connected to the first metal layer through the second opening, and an orthographic projection of the second metal layer on the base substrate at least partially overlaps with an orthographic projection of the second opening on the base substrate.

4. The display substrate according to claim 3, wherein: The orthographic projection of the second metal layer on the base substrate covers the orthographic projections of the first metal layer and the second opening on the base substrate; or, The orthographic projection of the second metal layer on the base substrate does not overlap with the orthographic projection of the first step portion of the first metal layer on the base substrate, and the orthographic projection of the second metal layer on the base substrate covers the orthographic projection of the second opening on the base substrate; or, The orthographic projection of the second metal layer on the base substrate does not overlap with the orthographic projection of the first step portion of the first metal layer on the base substrate, and the orthographic projection of the second metal layer on the base substrate is within the range of the orthographic projection of the second opening on the base substrate.

5. The display substrate according to claim 3, wherein: Also includes: The third metal layer is located on a side of the second metal layer away from the base substrate, wherein the third metal layer is electrically connected to the second metal layer, and the orthographic projection of the third metal layer on the base substrate covers the orthographic projection of the second metal layer on the base substrate.

6. The display substrate according to claim 5, wherein: Also includes: a third insulating layer, located on a side of the third metal layer facing away from the substrate, the third insulating layer comprising a third opening; The orthographic projection of the third opening on the base substrate is located within the orthographic projections of the first opening and the second opening on the base substrate; or The orthographic projections of the first opening and the second opening on the base substrate are located within the orthographic projection of the third opening on the base substrate; or, The orthographic projection of the third opening on the base substrate is within the range of the orthographic projection of the second opening on the base substrate, and the orthographic projection of the first opening on the base substrate is within the range of the orthographic projection of the third opening on the base substrate.

7. The display substrate according to claim 6, wherein: The third insulating layer includes at least one of an inorganic insulating layer and an organic insulating layer.

8. The display substrate according to claim 7, wherein: The third insulating layer includes a first insulating sublayer and a second insulating sublayer, wherein the second insulating sublayer is located on a side of the first insulating sublayer away from the substrate; The material of the first insulating sublayer is an organic material, the material of the second insulating sublayer is an inorganic material, the orthographic projection of the first insulating sublayer on the base substrate does not overlap with the orthographic projection of at least part of the step portion on the base substrate, and the orthographic projection of the second insulating sublayer on the base substrate covers the orthographic projection of at least part of the step portion on the base substrate.

9. The display substrate according to claim 6, wherein: Also includes: a fourth metal layer located on a side of the third metal layer and the third insulating layer facing away from the base substrate, wherein the fourth metal layer is electrically connected to the third metal layer through the third opening, and an orthographic projection of the fourth metal layer on the base substrate at least partially overlaps with an orthographic projection of the third metal layer on the base substrate.

10. The display substrate according to claim 9, wherein: Also includes: A fourth insulating layer, in a direction perpendicular to the plane of the base substrate, the fourth insulating layer is located between the third insulating layer and the fourth metal layer, wherein the fourth insulating layer includes a fourth opening, the orthographic projection of the fourth opening on the base substrate is located within the orthographic projection of the third opening on the base substrate, and the fourth metal layer is electrically connected to the third metal layer through the third opening and the fourth opening.

11. The display substrate according to any one of claims 1 to 6, characterized in that: The first metal layer also includes a second bottom portion surrounding the step portion, and the step portion also includes a third step portion forming an angle with the first step portion, the third step portion connecting the second bottom portion and the first step portion, and the orthographic projection of the second insulating layer on the base substrate at least partially overlaps with the orthographic projection of the second bottom portion on the base substrate.

12. The display substrate according to claim 11, wherein: The orthographic projection of the second insulating layer on the base substrate partially overlaps with the orthographic projection of the first bottom on the base substrate, and the orthographic projection of the second opening on the base substrate is located in the orthographic projection of the first opening on the base substrate; or, The orthographic projection of the second insulating layer on the base substrate does not overlap with the orthographic projections of the first bottom portion and the step portion on the base substrate, and the orthographic projection of the second opening on the base substrate covers the orthographic projection of the first opening on the base substrate.

13. The display substrate according to any one of claims 1 to 6, characterized in that: The first opening has a size in a width direction of 3 micrometers to 11 micrometers.

14. The display substrate according to claim 13, wherein: The first opening has a size in a width direction of 5 micrometers to 8 micrometers.

15. The display substrate according to any one of claims 1 to 6, characterized in that: The third metal layer is a single-layer structure, or the third metal layer is a multi-layer composite structure; In a structure in which the third metal layer is a single layer, the metal activity of the metal layer closest to the third metal layer in the second metal layer is not less than the metal activity of the third metal layer; In a multi-layer composite structure of the third metal layer, in a direction perpendicular to the plane of the substrate, the metal activity of the metal layer farthest from the second metal layer in the third metal layer is not greater than the metal activity of the metal layer between the farthest metal layer and the second metal layer.

16. The display substrate according to any one of claims 1 to 6, characterized in that: The base substrate includes a packaging area and an edge area located around the packaging area, the edge area includes a binding area on a side where at least one edge of the base substrate is located, and the binding area is located in the first frame area; A plurality of inorganic film layers are located on one side of the base substrate and are stacked; a plurality of first grooves located in the edge region and spaced apart in a direction away from the packaging region and partially surrounding the packaging region, wherein each of the first grooves penetrates at least one of the plurality of inorganic film layers, and an orthographic projection of the plurality of first grooves on the base substrate does not overlap with the binding region; The organic layer covers the plurality of first grooves.

17. The display substrate according to claim 16, wherein: The organic layer includes a first flat layer and a second flat layer stacked in sequence in a direction away from the base substrate. The first flat layer covers the plurality of first grooves, and the second flat layer is located on a side of the first flat layer away from the base substrate.

18. The display substrate according to claim 17, wherein: The first insulating layer includes: a gate insulating layer and an interlayer dielectric layer stacked in sequence in a direction away from the base substrate, and the at least one inorganic film layer includes the gate insulating layer and the interlayer dielectric layer.

19. The display substrate according to claim 18, wherein The inorganic film layer between each two adjacent first grooves constitutes a blocking portion; the multiple inorganic film layers also include: a buffer layer located between the base substrate and the gate insulation layer in a direction perpendicular to the plane where the base substrate is located, and the at least one inorganic film layer also includes at least part of the buffer layer.

20. The display substrate according to claim 19, wherein The plurality of inorganic film layers further include: a barrier layer located between the base substrate and the buffer layer in a direction perpendicular to the plane of the base substrate, and the at least one inorganic film layer further includes at least a portion of the barrier layer.

21. The display substrate according to claim 17, wherein The display area of ​​the display substrate includes a gate metal layer located on the base substrate, a gate insulating layer located on a side of the gate metal layer facing away from the base substrate, and a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer arranged in sequence on a side of the gate insulating layer facing away from the base substrate; In a direction perpendicular to the plane of the substrate, the first planar layer is located between the first source-drain metal layer and the second source-drain metal layer, and the second planar layer is located between the second source-drain metal layer and the third source-drain metal layer; The multiple data line leads are arranged in the same layer as the gate metal layer, the first insulating layer is arranged in the same layer as the gate insulating layer, the first metal layer is arranged in the same layer as the first source and drain metal layer, the second metal layer is arranged in the same layer as the second source and drain metal layer, and the third metal layer is arranged in the same layer as the third source and drain metal layer.

22. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 21.

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