Half-bridge drive interlocking circuit

Abstract

The utility model provides a half-bridge drive interlocking circuit, in which a logic circuit is provided with a logic gate; two input ends of the logic circuit respectively receive two control signals; the two control signals are in one-to-one correspondence with two switch tubes in the half-bridge circuit; when the two control signals are turn-on signals, the two output ends of the logic circuit output turn-off signals. A first output end of the logic circuit is connected with a control end of a first switching tube in the half-bridge circuit through a first driving circuit; a second output end of the logic circuit is connected with a control end of a second switching tube in the half-bridge circuit through a second driving circuit; namely, the logic circuit is built through the logic gate, the phenomenon of high-temperature attenuation caused by the adoption of an optical device is avoided, the logic circuit is not affected by the high-temperature environment, good performance stability can still be kept in the high-temperature environment, the signal transmission efficiency is high, and the driving accuracy and the reliability and safety of the system are improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of power electronics, and more specifically, relates to a half-bridge drive interlocking circuit. Background Art

[0002] As the global energy transition accelerates and the era of electrification fully arrives, high-power converters, the critical link between clean energy and end applications, are becoming increasingly important. Applications such as new energy electric drives, port shore power, and future electric aircraft are placing increasing demands on high-power converters for higher power and greater intelligence. High-power intelligent power modules, at their core, must not only deliver robust drive capabilities but also integrate comprehensive protection mechanisms to ensure efficient and stable system operation. Currently, high-voltage power supply and high-frequency operation strategies are being employed to improve conversion efficiency, with silicon carbide (SiC) switches being the preferred choice due to their low resistance and high frequency characteristics. However, efficiently driving SiC switches, especially at high bus voltages, presents a key challenge in designing isolated drive circuits to prevent bridge arm shoot-through and ensure system safety.

[0003] Currently, the interlocking function of primary-side optocouplers is being used to address the complementary drive signal and shoot-through prevention issues in high-power converters. This is achieved by connecting two optocouplers in series to achieve complementary signal control. Specifically, the low-end of optocoupler 1 is connected to the high-end of optocoupler 2, forming an interlocking link. Only when only one of PWM signal 1 or PWM signal 2 is high will the corresponding optocoupler be activated and turned on. This ensures that the upper and lower switches in the same bridge arm are not turned on simultaneously, effectively preventing shoot-through.

[0004] Although this method can achieve the expected complementary effect of driving signals, the performance stability of the optocoupler is poor when working in a high-temperature environment for a long time, resulting in reduced signal transmission efficiency and even attenuation, which may eventually cause driving failure and affect the reliability and safety of the entire system. Utility Model Content

[0005] In view of this, an object of the present invention is to provide a half-bridge drive interlock circuit for improving drive accuracy, system reliability and safety.

[0006] The present application discloses a half-bridge drive interlock circuit, comprising: a logic circuit, a first drive circuit, a second drive circuit and a half-bridge circuit;

[0007] The logic circuit is provided with a logic gate;

[0008] The two input terminals of the logic circuit receive two control signals respectively; the two control signals correspond one-to-one to the two switch tubes in the half-bridge circuit; when the two control signals are both on signals, the two output terminals of the logic circuit output off signals;

[0009] The first output terminal of the logic circuit is connected to the control terminal of the first switch tube in the half-bridge circuit through the first driving circuit;

[0010] The second output end of the logic circuit is connected to the control end of the second switch tube in the half-bridge circuit through the second drive circuit.

[0011] Optionally, the logic circuit includes: a first logic sub-circuit and a second logic sub-circuit;

[0012] The first input terminal of the first logic sub-circuit and the first input terminal of the second logic sub-circuit respectively receive a first control signal;

[0013] The second input terminal of the first logic sub-circuit and the second input terminal of the second logic sub-circuit respectively receive a second control signal;

[0014] The output terminal of the first logic sub-circuit is connected to the third input terminal of the second logic sub-circuit;

[0015] The two output terminals of the second logic sub-circuit serve as the two output terminals of the logic circuit respectively;

[0016] The first logic sub-circuit adopts OR logic, and the second logic sub-circuit adopts XOR logic.

[0017] Optionally, the first logic sub-circuit includes a logic OR gate;

[0018] The first input terminal of the logic OR gate serves as the first input terminal of the first logic sub-circuit;

[0019] The second input terminal of the logic OR gate serves as the second input terminal of the second logic sub-circuit;

[0020] The output end of the logic OR gate serves as the output end of the first logic sub-circuit.

[0021] Optionally, the second logic sub-circuit includes: a first logic XOR gate and a second logic XOR gate;

[0022] The first input terminal of the first logic XOR gate serves as the first input terminal of the second logic sub-circuit;

[0023] The first input terminal of the second logic XOR gate serves as the second input terminal of the second logic sub-circuit;

[0024] The second input terminal of the first logic XOR gate is connected to the second input terminal of the second logic XOR gate, and the connection point serves as the third input terminal of the second logic sub-circuit;

[0025] The output end of the first logic XOR gate serves as the first output end of the second logic sub-circuit;

[0026] The output end of the second logic XOR gate serves as the second output end of the second logic sub-circuit.

[0027] Optionally, a pull-up circuit is also included;

[0028] Both input terminals of the logic circuit are connected to a power supply through the pull-up circuit.

[0029] Optionally, the pull-up circuit includes: a first pull-up resistor and a second pull-up resistor;

[0030] The first input terminal of the logic circuit is connected to the power supply through the first pull-up resistor;

[0031] The second input terminal of the logic circuit is connected to the power supply through the second pull-up resistor.

[0032] Optionally, it also includes: a filtering circuit;

[0033] The filter circuit is arranged at two input terminals of the logic circuit.

[0034] Optionally, the filtering circuit includes: a first filtering sub-circuit and a second filtering sub-circuit;

[0035] The first filtering subcircuit is provided between the first input terminal of the first logic subcircuit and the first input terminal of the second logic subcircuit in the logic circuit;

[0036] The second filtering sub-circuit is provided between the second input terminal of the first logic sub-circuit and the second input terminal of the second logic sub-circuit in the logic circuit.

[0037] Optionally, the first filtering subcircuit includes: a first filtering capacitor and a first filtering resistor;

[0038] One end of the first filter resistor is connected to the first input end of the first logic sub-circuit;

[0039] One end of the first filter capacitor is connected to the other end of the first filter resistor, and a connection point is connected to the first input end of the second logic sub-circuit;

[0040] The other end of the first filter capacitor is grounded.

[0041] Optionally, the second filtering subcircuit includes: a second filtering capacitor and a second filtering resistor;

[0042] One end of the second filter resistor is connected to the second input end of the first logic sub-circuit;

[0043] One end of the second filter capacitor is connected to the other end of the second filter resistor, and a connection point is connected to the second input end of the second logic sub-circuit;

[0044] The other end of the second filter capacitor is grounded.

[0045] It can be seen from the above technical solution that the utility model provides a half-bridge drive interlock circuit, wherein a logic gate is provided in the logic circuit; the two input ends of the logic circuit respectively receive two control signals; the two control signals correspond one-to-one to the two switch tubes in the half-bridge circuit; when the two control signals are both on signals, the two output ends of the logic circuit both output off signals; the first output end of the logic circuit is connected to the control end of the first switch tube in the half-bridge circuit through the first drive circuit; the second output end of the logic circuit is connected to the control end of the second switch tube in the half-bridge circuit through the second drive circuit; that is, the logic circuit is constructed by means of logic gates to avoid the attenuation phenomenon caused by high temperature caused by the use of optical devices. The logic circuit is not affected by the high temperature environment and can still maintain good performance stability in the high temperature environment. The signal transmission efficiency is high, thereby improving the driving accuracy, system reliability and safety. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 This is a schematic diagram of a half-bridge drive interlock circuit provided by an embodiment of the present utility model;

[0048] Figure 2 This is a schematic diagram of another half-bridge drive interlock circuit provided by an embodiment of the present utility model;

[0049] Figure 3 This is a schematic diagram of another half-bridge drive interlock circuit provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0050] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0051] In the present application, the term "comprise", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprising a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. In addition, the terms "first", "second", "third", "fourth" etc. (if present) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein, for example, can be implemented in an order other than those illustrated or described herein.

[0052] An embodiment of the present application provides a half-bridge drive interlock circuit, which is used to solve the problem in the prior art that the performance stability of the optocoupler used in a long-term operation in a high-temperature environment is poor, resulting in a decrease in signal transmission efficiency and even attenuation, which may eventually cause drive failure and affect the reliability and safety of the entire system.

[0053] See also Figure 1 The half-bridge drive interlock circuit includes: a logic circuit 10, a first drive circuit 20, a second drive circuit 30 and a half-bridge circuit 40.

[0054] Logic circuit 10 is provided with logic gates. Logic gates are hardware devices; that is, logic circuit 10 can be constructed by using corresponding logic gates. Commonly used logic gates include an AND gate, an OR gate, and a NOT gate; there are also XOR gates and XNOR gates, etc., which will not be detailed here. The actual use of logic gates will be determined, and all are within the scope of protection of this application.

[0055] The two input terminals of the logic circuit 10 receive two control signals respectively.

[0056] The two control signals correspond one-to-one to the two switching transistors in the half-bridge circuit 40 .

[0057] Specifically, a first input terminal of the logic circuit 10 receives a first control signal PWM1, which is used to control the on / off switching of the second switch Q2 in the half-bridge circuit 40. A second input terminal of the logic circuit 10 receives a second control signal PWM2, which is used to control the on / off switching of the first switch Q1 in the half-bridge circuit 40. The first switch Q1 can be an upper switch, and the second switch Q2 can be a lower switch. Both the first control signal PWM1 and the second control signal PWM2 can be PWM (Pulse Width Modulation) signals, for example, the first control signal PWM1 is PWM signal 1, and the second control signal PWM2 is PWM signal 2.

[0058] In the half-bridge circuit 40, one end of the first switch tube Q1 is connected to the power supply VDD; the control end of the first switch tube Q1 serves as the first control end of the half-bridge circuit 40 and is connected to the output end of the first drive circuit 20; the other end of the first switch tube Q1 is connected to one end of the second switch tube Q2; the other end of the second switch tube Q2 is grounded; and the control end of the second switch tube Q2 serves as the second control end of the half-bridge circuit 40.

[0059] When both control signals are on signals, both output terminals of the logic circuit 10 output off signals.

[0060] That is to say, when both control signals are on signals, if the upper and lower tubes of the half-bridge circuit 40 are turned on according to the control signals, the upper and lower tubes of the half-bridge circuit 40 will be directly connected, that is, the bridge arm will be directly connected, causing system damage or failure; therefore, when both control signals are on signals, the logic circuit 10 transforms the control signal and outputs a shutdown signal to turn off the upper and lower tubes of the half-bridge circuit 40 to avoid the situation where the bridge arm is directly connected.

[0061] The first output end of the logic circuit 10 is connected to the control end of the first switch tube Q1 in the half-bridge circuit 40 through the first drive circuit 20; specifically, the first output end of the logic circuit 10 is connected to one end of the first drive circuit 20, and the other end of the first drive circuit 20 is connected to the control end of the first switch tube Q1.

[0062] The second output terminal of the logic circuit 10 is connected to the control terminal of the second switch Q2 in the half-bridge circuit 40 through the second drive circuit 30. Specifically, the second output terminal of the logic circuit 10 is connected to one end of the second drive circuit 30, and the other end of the second drive circuit 30 is connected to the control terminal of the second switch Q2.

[0063] Specifically, when the two control signals are not both on-state signals, the signal output by the output terminal of the logic circuit 10 is consistent with the signal output by the input terminal, that is, the output signal tracks the input signal. For example, the signal output by the first output terminal of the logic circuit 10 is named the first output signal, and the signal output by the second output terminal of the logic circuit 10 is named the second output signal. When the two control signals are not both on-state signals, the first output signal tracks the second control signal PWM2, and the first output signal and the second control signal PWM2 are consistent. The second output signal tracks the first control signal PWM1, and the second output signal and the first control signal PWM1 are consistent. The specific logic of the logic circuit 10 is shown in Table 1:

[0064] Table 1: Input and output logic of logic circuit 10

[0065]

[0066] Among them, 1 represents the on signal, that is, high level turns on, and 0 represents the off signal, that is, low level turns off. In other words, when the pulse signals of the upper and lower tubes are both high, the logic circuit 10 performs a logical operation to interlock the upper and lower tubes, thereby playing a protective role.

[0067] This half-bridge drive interlock circuit can be used in situations where the bus voltage is relatively high and the operating power requirement is high, such as in high-power converters, to solve the driving circuit situation where the upper and lower tubes of the same bridge arm of the high-power converter have a shoot-through phenomenon; of course, it is not ruled out that it can be used in other fields, which will not be elaborated here.

[0068] In this embodiment, a logic gate is provided in the logic circuit 10; the two input terminals of the logic circuit 10 receive two control signals respectively; the two control signals correspond one-to-one to the two switch tubes in the half-bridge circuit 40; when the two control signals are both on signals, the two output terminals of the logic circuit 10 both output off signals; the first output terminal of the logic circuit 10 is connected to the control terminal of the first switch tube Q1 in the half-bridge circuit 40 through the first drive circuit 20; the second output terminal of the logic circuit 10 is connected to the control terminal of the second switch tube Q2 in the half-bridge circuit 40 through the second drive circuit 30; that is, by constructing the logic circuit 10 through logic gates, the attenuation phenomenon caused by the use of optical devices when exposed to high temperatures is avoided. The logic circuit 10 is not affected by the high temperature environment and can still maintain good performance stability in the high temperature environment, with high signal transmission efficiency, thereby improving the driving accuracy, system reliability and safety.

[0069] It should be noted that the existing technology relies on two optocouplers to achieve signal isolation and interlocking, which increases the complexity and cost of the system. Moreover, since each optocoupler requires sufficient driving capability to work properly, this further increases the difficulty of designing the driving circuit.

[0070] In this embodiment, isolation and interlocking can be achieved by using logic gates and drive circuits, reducing the complexity and cost of the system. In addition, the circuit does not require a large drive capability, and conventional drive signals can achieve drive, reducing the difficulty of designing the drive circuit.

[0071] Optional, see Figure 2 The logic circuit 10 includes a first logic sub-circuit 11 and a second logic sub-circuit 12 .

[0072] The first input terminal of the first logic sub-circuit 11 and the first input terminal of the second logic sub-circuit 12 receive the first control signal PWM1 , respectively.

[0073] Specifically, the first input terminal of the first logic sub-circuit 11 is connected to the first input terminal of the second logic sub-circuit 12 , and the connection point serves as the first input terminal of the logic circuit 10 to receive the first control signal PWM1 .

[0074] The second input terminal of the first logic sub-circuit 11 and the second input terminal of the second logic sub-circuit 12 receive the second control signal PWM2 respectively.

[0075] Specifically, the second input terminal of the first logic sub-circuit 11 is connected to the second input terminal of the second logic sub-circuit 12 , and the connection point serves as the second input terminal of the logic circuit 10 to receive the second control signal PWM2 .

[0076] The output terminal of the first logic sub-circuit 11 is connected to the third input terminal of the second logic sub-circuit 12 ; that is, the output signal of the first logic sub-circuit 11 affects the output signal of the second logic sub-circuit 12 .

[0077] The two output ends of the second logic sub-circuit 12 serve as the two output ends of the logic circuit 10 respectively; specifically, the first output end of the second logic sub-circuit 12 serves as the first output end of the logic circuit 10 and is connected to the control end of the first switch tube Q1 through the first drive circuit 20; the second output end of the second logic sub-circuit 12 serves as the second output end of the logic circuit 10 and is connected to the control end of the second switch tube Q2 through the second drive circuit 30.

[0078] The first logic sub-circuit 11 adopts OR logic, and the second logic sub-circuit 12 adopts XOR logic.

[0079] That is, when at least one of the first control signal PWM1 and the second control signal PWM2 is an on signal, the first logic sub-circuit 11 outputs the on signal. In the second logic sub-circuit 12, the signal at the first output terminal is obtained by performing an exclusive OR operation on the first control signal PWM1 and the signal output by the first logic sub-circuit 11; and the signal at the second output terminal is obtained by performing an exclusive OR operation on the second control signal PWM1 and the signal output by the first logic sub-circuit 11.

[0080] Specifically, the logic of the first logic sub-circuit 11 is shown in Table 2:

[0081] Table 2: Input and output logic of the first logic sub-circuit 11

[0082]

[0083] Specifically, the logic of the second logic sub-circuit 12 is shown in Table 3:

[0084] Table 3: Input and output logic of the second logic sub-circuit 12

[0085]

[0086] That is, the output signal of the second logic sub-circuit 12 tracks the control signal.

[0087] Optional, see Figure 3 , the first logic sub-circuit 11 includes a logic OR gate U1.

[0088] The first input terminal of the logic OR gate U1 serves as the first input terminal of the first logic sub-circuit 11 and receives the first control signal PWM1. The second input terminal of the logic OR gate U1 serves as the second input terminal of the second logic sub-circuit 12 and receives the second control signal PWM2. The output terminal of the logic OR gate U1 serves as the output terminal of the first logic sub-circuit 11 and is connected to the third input terminal of the second logic sub-circuit 12.

[0089] Specifically, in the logic OR gate U1, when one of its inputs is 1, its output is 1; when all inputs are 0, its output is 0. This logic chip implements the logic OR function. Its logic formula is: Y1 = A1 + B1; where Y1 is the output signal of the logic OR gate U1; A1 is one of the input signals of the logic OR gate U1, which can be the first control signal PWM1; B1 is the other input signal of the logic OR gate U1, which can be the second control signal PWM2.

[0090] The truth table of the logic OR gate U1 is shown in Table 4:

[0091] Table 4: Truth table of logic OR gate U1

[0092]

[0093] That is to say, the specific logic of Table 4 is the same as that of Table 2.

[0094] Optional, see Figure 3 The second logic sub-circuit 12 includes: a first logic XOR gate U2 and a second logic XOR gate U3.

[0095] The first input terminal of the first logic XOR gate U2 serves as the first input terminal of the second logic sub-circuit 12 and receives the first control signal PWM1 .

[0096] The first input terminal of the second logic XOR gate U3 serves as the second input terminal of the second logic sub-circuit 12 and receives the second control signal PWM2.

[0097] The second input terminal of the first logic XOR gate U2 is connected to the second input terminal of the second logic XOR gate U3 , and the connection point serves as the third input terminal of the second logic sub-circuit 12 for receiving the output signal of the first logic sub-circuit 11 .

[0098] The output end of the first logic XOR gate U2 serves as the first output end of the second logic sub-circuit 12 and is connected to the control end of the first switch tube Q1 through the first drive circuit 20 .

[0099] The output end of the second logic XOR gate U3 serves as the second output end of the second logic sub-circuit 12 and is connected to the control end of the second switch tube Q2 through the second drive circuit 30 .

[0100] That is, the second logic sub-circuit 12 includes two logic chips, and the two logic chips have the same function. Specifically, for any logic chip in the second logic sub-circuit 12, if the logic states of its two input terminals remain different, the output terminal outputs high; if the logic states of its two input terminals are the same, for example, both high or both low, the output is 0 (low level). The logic formula is:

[0101]

[0102] Among them, Y1 is the output signal of the logic OR gate U1; A1 is the first control signal PWM1, B1 is the signal after the first control signal PWM1 is processed by logic negation; B2 is the second control signal PWM2; is the signal after the second control signal PWM2 is logically negated; Y2 is the output signal of the first logic XOR gate U2; Y3 is the output signal of the second logic XOR gate U3.

[0103] In this embodiment, logic gates are used so that after the digital logic circuit 10 conditions the signal, the two output ends of the logic circuit 10 drive the switch tubes through two driving circuits respectively, that is, the driving signals of the two switch tubes are isolated by different driving circuits respectively. A digital isolator with capacitive isolation can be used in the driving circuit for isolation, avoiding the use of optical devices. There is no phenomenon of optical devices attenuating when encountering high temperatures, which increases the reliability of the driving circuit in a complex environment, thereby improving the stability of the entire system.

[0104] The following is based on Figure 3The circuit diagram shown in the figure explains the working process of the half-bridge drive interlock circuit:

[0105] When the first control signal PWM1 is at a high level and the second control signal PWM2 is at a low level, the logic formula Y1=A1+B1 shows that Y1 is at a high level. Therefore, Y2=0, the first switch Q1 is turned off. Therefore, Y3=1, and the second switch tube Q2 is turned on.

[0106] When the first control signal PWM1 is at a low level and the second control signal PWM2 is at a high level, the logic formula Y1=A1+B1 shows that Y1 is at a high level. Therefore, Y2=1, Q1 is turned on, because Therefore, Y3=0, Q2 is turned off.

[0107] When the first control signal PWM1 is at a high level and the second control signal PWM2 is at a high level, the logic formula Y1=A1+B1 shows that Y1 is at a high level. Therefore, Y2=0, the first switch Q1 is turned off. Therefore, Y3 = 0, and the second switch tube Q2 is turned off.

[0108] When the first control signal PWM1 is at a low level and the second control signal PWM2 is at a low level, the logic formula Y1=A1+B1 shows that Y1 is at a low level. Therefore, Y2=0, the first switch Q1 is turned off. Therefore, Y3 = 0, and the second switch tube Q2 is turned off.

[0109] Optionally, a pull-up circuit is also included.

[0110] Both input terminals of the logic circuit 10 are connected to the power supply VCC through a pull-up circuit.

[0111] Specifically, the first input terminal of the logic circuit 10 is connected to the first terminal of the pull-up circuit, and the second terminal of the pull-up circuit is connected to the power supply VCC; the second input terminal of the logic circuit 10 is connected to the third terminal of the pull-up circuit, and the fourth terminal of the pull-up circuit is connected to the power supply VCC.

[0112] Optional, see Figure 3 The pull-up circuit includes: a first pull-up resistor R1 and a second pull-up resistor R2.

[0113] The first input terminal of the logic circuit 10 is connected to the power supply VCC through the first pull-up resistor R1 . Specifically, the first input terminal of the logic circuit 10 is connected to one end of the first pull-up resistor R1 , and the other end of the first pull-up resistor R1 is connected to the power supply VCC.

[0114] The second input terminal of the logic circuit 10 is connected to the power supply VCC through the second pull-up resistor R2 . Specifically, the second input terminal of the logic circuit 10 is connected to one end of the second pull-up resistor R2 , and the other end of the second pull-up resistor R2 is connected to the power supply VCC.

[0115] The first pull-up resistor R1 and the second pull-up resistor R2 play a pull-up role, mainly to prevent the switch tube from being mis-turned on when there are interference signals in the input first control signal PWM1 and the second control signal PWM2; the two pull-up resistors can be low-power resistors with a resistance of 5k to 10k, of course, resistors of other resistance values ​​are not excluded.

[0116] Optionally, it also includes: a filtering circuit.

[0117] The filter circuit is provided at two input terminals of the logic circuit 10. The filter circuit is used to filter out interference from two control signals of the logic circuit 10.

[0118] The role of the filter circuit is reflected in the following aspects:

[0119] Noise Removal: Filter circuits effectively remove noise from signals. This noise can come from sources such as power supply fluctuations, electromagnetic interference, and crosstalk during signal transmission. By removing this noise, filter circuits can significantly improve the signal-to-noise ratio, enabling subsequent circuits to more accurately process and analyze the signal.

[0120] Signal Shaping: In some cases, signals may be distorted due to problems in the transmission path or the source signal itself. Filter circuits, through their specific frequency response characteristics, can reshape the signal to a shape closer to the original, thereby ensuring signal integrity and accuracy.

[0121] Frequency selection: Filter circuits have a frequency-selective function, allowing them to selectively pass or block signals within a specific frequency range. This is particularly important for applications such as signal separation and frequency band division, allowing signals of different frequencies to be processed or transmitted in a predetermined manner.

[0122] Protection circuit: In some cases, filter circuits can also play a role in protecting circuits. For example, adding a filter circuit to the power input can filter out high-frequency noise and surge voltage in the power supply, protecting subsequent circuits from damage.

[0123] Improved system performance: By properly designing filter circuits, the performance of the entire electronic system can be optimized. For example, in communication systems, precisely controlling the bandwidth and attenuation characteristics of filter circuits can improve signal transmission efficiency and reception quality. In control systems, filter circuits can ensure the stability and accuracy of control signals, thereby improving system control precision and response speed.

[0124] The setting of the filtering circuit ensures that the logic circuit 10 can receive pure and stable signal input, thereby effectively avoiding the adverse effects of external noise or signal distortion on circuit performance, and ensuring the stable operation and accurate judgment of the logic circuit 10.

[0125] Optionally, the filtering circuit includes: a first filtering sub-circuit and a second filtering sub-circuit.

[0126] The first filtering sub-circuit is provided between the first input terminal of the first logic sub-circuit 11 and the first input terminal of the second logic sub-circuit 12 in the logic circuit 10 .

[0127] Specifically, one end of the first filtering sub-circuit is connected to the first input end of the first logic sub-circuit 11 ; the other end of the first filtering sub-circuit is connected to the first input end of the second logic sub-circuit 12 .

[0128] The second filtering sub-circuit is provided between the second input terminal of the first logic sub-circuit 11 and the second input terminal of the second logic sub-circuit 12 in the logic circuit 10 .

[0129] Specifically, one end of the second filtering sub-circuit is connected to the second input end of the first logic sub-circuit 11 ; the other end of the second filtering sub-circuit is connected to the second input end of the second logic sub-circuit 12 .

[0130] That is, the first filtering sub-circuit and the second filtering sub-circuit perform filtering processing on the first control signal PWM1 and the second control signal PWM2 respectively.

[0131] Optional, see Figure 3 The first filtering sub-circuit includes: a first filtering capacitor C1 and a first filtering resistor R3.

[0132] One end of the first filter resistor R3 is connected to the first input end of the first logic sub-circuit 11 .

[0133] One end of the first filter capacitor C1 is connected to the other end of the first filter resistor R3 , and the connection point is connected to the first input end of the second logic sub-circuit 12 .

[0134] The other end of the first filter capacitor C1 is grounded.

[0135] That is, the first filter resistor R3 and the first filter capacitor C1 form a first RC filter network, which is mainly used to eliminate interference signals in the driving signal (control signal) to ensure the purity and stability of the signal.

[0136] Optional, see Figure 3 The second filtering sub-circuit includes: a second filtering capacitor C2 and a second filtering resistor R4.

[0137] One end of the second filter resistor R4 is connected to the second input end of the first logic sub-circuit 11 .

[0138] One end of the second filter capacitor C2 is connected to the other end of the second filter resistor R4 , and the connection point is connected to the second input end of the second logic sub-circuit 12 .

[0139] The other end of the second filtering capacitor C2 is grounded.

[0140] That is, the second filter resistor R4 and the second filter capacitor C2 form a second RC filter network, which is mainly used to eliminate interference signals in the drive signal (control signal), ensure the purity and stability of the signal, and provide the system with a clearer and more reliable signal input.

[0141] The features described in the various embodiments of this specification can be replaced or combined with each other. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment. The system and system embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without expending creative work.

[0142] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0143] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A half-bridge drive interlock circuit, characterized in that: include: a logic circuit, a first drive circuit, a second drive circuit, and a half-bridge circuit; The logic circuit is provided with a logic gate; The two input terminals of the logic circuit receive two control signals respectively; the two control signals correspond one-to-one to the two switch tubes in the half-bridge circuit; when the two control signals are both on signals, the two output terminals of the logic circuit output off signals; The first output terminal of the logic circuit is connected to the control terminal of the first switch tube in the half-bridge circuit through the first driving circuit; The second output end of the logic circuit is connected to the control end of the second switch tube in the half-bridge circuit through the second drive circuit.

2. The half-bridge drive interlock circuit according to claim 1, characterized in that: The logic circuit includes: a first logic sub-circuit and a second logic sub-circuit; The first input terminal of the first logic sub-circuit and the first input terminal of the second logic sub-circuit respectively receive a first control signal; The second input terminal of the first logic sub-circuit and the second input terminal of the second logic sub-circuit respectively receive a second control signal; The output terminal of the first logic sub-circuit is connected to the third input terminal of the second logic sub-circuit; The two output terminals of the second logic sub-circuit serve as the two output terminals of the logic circuit respectively; The first logic sub-circuit adopts OR logic, and the second logic sub-circuit adopts XOR logic.

3. The half-bridge drive interlock circuit according to claim 2, characterized in that: The first logic subcircuit includes a logic OR gate; The first input terminal of the logic OR gate serves as the first input terminal of the first logic sub-circuit; The second input terminal of the logic OR gate serves as the second input terminal of the second logic sub-circuit; The output end of the logic OR gate serves as the output end of the first logic sub-circuit.

4. The half-bridge drive interlock circuit according to claim 2, characterized in that: The second logic sub-circuit includes: a first logic XOR gate and a second logic XOR gate; The first input terminal of the first logic XOR gate serves as the first input terminal of the second logic sub-circuit; The first input terminal of the second logic XOR gate serves as the second input terminal of the second logic sub-circuit; The second input terminal of the first logic XOR gate is connected to the second input terminal of the second logic XOR gate, and the connection point serves as the third input terminal of the second logic sub-circuit; The output end of the first logic XOR gate serves as the first output end of the second logic sub-circuit; The output end of the second logic XOR gate serves as the second output end of the second logic sub-circuit.

5. The half-bridge drive interlock circuit according to claim 1, characterized in that: It also includes a pull-up circuit; Both input terminals of the logic circuit are connected to a power supply through the pull-up circuit.

6. The half-bridge drive interlock circuit according to claim 5, characterized in that: The pull-up circuit includes: a first pull-up resistor and a second pull-up resistor; The first input terminal of the logic circuit is connected to the power supply through the first pull-up resistor; The second input terminal of the logic circuit is connected to the power supply through the second pull-up resistor.

7. The half-bridge drive interlock circuit according to claim 1, characterized in that: Also includes: filter circuit; The filter circuit is arranged at two input terminals of the logic circuit.

8. The half-bridge drive interlock circuit according to claim 7, characterized in that: The filtering circuit includes: a first filtering subcircuit and a second filtering subcircuit; The first filtering subcircuit is provided between the first input terminal of the first logic subcircuit and the first input terminal of the second logic subcircuit in the logic circuit; The second filtering sub-circuit is provided between the second input terminal of the first logic sub-circuit and the second input terminal of the second logic sub-circuit in the logic circuit.

9. The half-bridge drive interlock circuit according to claim 8, characterized in that: The first filtering subcircuit includes: a first filtering capacitor and a first filtering resistor; One end of the first filter resistor is connected to the first input end of the first logic sub-circuit; One end of the first filter capacitor is connected to the other end of the first filter resistor, and a connection point is connected to the first input end of the second logic sub-circuit; The other end of the first filter capacitor is grounded.

10. The half-bridge drive interlock circuit according to claim 8, characterized in that: The second filtering subcircuit includes: a second filtering capacitor and a second filtering resistor; One end of the second filter resistor is connected to the second input end of the first logic sub-circuit; One end of the second filter capacitor is connected to the other end of the second filter resistor, and a connection point is connected to the second input end of the second logic sub-circuit; The other end of the second filter capacitor is grounded.

Images