Progressive network engineering comprehensive experiment box

Abstract

The utility model provides a progressive network engineering comprehensive experiment box, comprising a main control unit and an expansion circuit board, the main control unit is integrated with a main power supply, a core board, an Ethernet port, a USB interface and a GPIO button; the expansion circuit board comprises an expansion board power supply and an expansion board unit. The core board is further connected with a USB interface, a GPIO key, an Ethernet port and the like. The expansion board unit adopts a 2 * 12 female header design and integrates an I2C interface, an SPI interface, a UART interface, an I2S interface, an RTC circuit, a FLASH module, a remote I / O expansion module, an I2C Switch module and an I2C expansion interface, and through stable power supply management, reliable connection design, rich integration and expansion functions and a portable and flexible core module, comprehensive experiment content is provided, and the experiment efficiency is improved. And the operational ability and theoretical knowledge level of students can be effectively improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to experimental equipment technical field, especially, relate to a progressive network engineering comprehensive experiment box. BACKGROUND

[0002] The experiment of network engineering major relies on the teaching of actual router, switch and high integration embedded development board. However, these devices are expensive and limited in quantity, which leads to the fact that each student cannot have his own device for practice, which limits the students' practical operation experience. In addition, due to the large size and inconvenience of carrying of these devices, students can only experiment in designated laboratories, which further limits their learning time and place, making it difficult for students to use their spare time for in-depth research or self-exploration. This limitation not only reduces the students' practice opportunities, but also reduces their interest and enthusiasm for network technology. In addition, the experimental steps of network engineering major experiment are usually fixed, following the pre-set guidelines, lacking sufficient flexibility and openness, which limits the development of students' innovative thinking and practical ability. Although fixed steps help students master basic operation skills, they cannot effectively cultivate students' adaptability and creative problem-solving ability, which are essential for solving complex real-world problems. In addition, the experiments of operating system, network program design and simple network management protocol courses usually rely on virtual machine environment on personal computers. Although this method provides convenience, it fails to provide the same experience as real systems and network environments, making it difficult for students to fully understand the working principle and complexity of actual network systems. SUMMARY

[0003] The purpose of the utility model embodiment is to provide a progressive network engineering comprehensive experiment box to solve the problems of uneven resource allocation, time and space limitation, fixed experimental steps lacking flexibility and differences between simulation environment and real system in network engineering major experiment teaching, and improve the integration of experimental devices.

[0004] To solve the above technical problems, the utility model adopts the technical scheme of a progressive network engineering comprehensive experiment box, a main control unit and an expansion circuit board, the main control unit is integrated with a total power supply, a core board, an Ethernet port, a USB interface and a GPIO button; the expansion circuit board includes an expansion board power supply and an expansion board unit. Among them, the total power supply is connected with the core board and the expansion board power supply; the expansion board power supply is connected with the expansion board unit;

[0005] The core board is also connected with the expansion board unit, the USB interface, the GPIO button and the Ethernet port;

[0006] The expansion board unit is a 2*12 female header, and the expansion board unit is integrated with an I2C interface, an SPI interface, a UART interface, an I2S interface, an RTC circuit, a FLASH module, a remote I / O expansion module, an I2C switch module and an I2C expansion interface.

[0007] In addition, the core board is a PCB circuit board, and the core board is integrated with a master control chip, a memory chip and a flash memory; the master control chip is an MT7628an chip, and is connected to the core board in a manner that the male header is inserted into the female header.

[0008] In addition, the total power supply includes an input module, a DC / DC step-down module and a total power supply chip.

[0009] The P1 interface of the input module is connected to the output power supply of a 12V-1A adapter, a filter capacitor is connected in a copper paving manner, and is connected to the No.1 pin of the DC / DC step-down module.

[0010] The total power supply chip is an AMS1117-3.3 chip, the VIN end of the total power supply chip is connected to the No.3 pin of the DC / DC step-down module, the No.2 pin of the total power supply chip is connected to the pin 24 of the core board to supply power to the master control chip, and a group of parallel 10µF and 0.1µF capacitors are arranged at the input and output ends of the total power supply chip.

[0011] One end of the GPIO button is connected to the ground of the master control chip, and the other end is connected to the No.27 pin of the master control chip.

[0012] The USB interface includes a metal shell, the No.4 pin and the two side pins of the USB interface are grounded, the No.1 pin is connected to the No.3 pin of the DC / DC step-down module, and the No.2 and No.3 pins of the USB interface are respectively connected to the No.23 and No.22 pins of the master control chip.

[0013] Further, the Ethernet port includes a J1 socket, a J2 socket and ports WAN1, LAN1, LAN2, LAN3 and LAN4; the Ethernet port further includes resistors R1, R2, R3, R4 and R5 and signal lines LINK0, LINK1, LINK2, LINK3 and LINK4.

[0014] The J1 socket is a single RJ45 socket, and the J2 socket is an RJ45 1x4 socket. Among them, one end of R1, R2, R3, R4 and R5 is connected to the No. 2 pin of the total power supply chip, and the other end is connected to the No. 12 pin of the J1 socket, the No. 48, 36, 24 and 12 pins of the J2 socket respectively, LINK0, LINK1, LINK2, LINK3 and LINK4 are connected to the No. 37, 36, 35, 34 and 33 pins of the main control chip respectively; the No. 1, 3, 4 and 6 ports of WAN1, LAN1, LAN2, LAN3 and LAN4 are connected to the No. 4, 3, 2, 1, 6, 5, 8, 7, 12, 11, 10, 9, 14, 13, 16, 15, 20, 19, 18 and 17 ports of the main control chip respectively.

[0015] The expansion board power supply includes an expansion power supply chip and a pin power supply, and the pin power supply is five groups of pin power supplies.

[0016] The expansion power supply chip is specifically an AMS1117-3.3 chip; the VIN end of the expansion power supply chip is connected to a 5V power supply, and the VOUT end outputs a stable 3.3V voltage, and a group of 10µF and 0.1µF capacitors are arranged in parallel at the input and output ends; the No. 3 pin of the expansion power supply chip is connected to the No. 1 and No. 3 pins of the expansion board unit.

[0017] The No. 1, 3, 5, 7 and 9 pins of the pin power supply are grounded, the No. 2, 4 and 6 pins are connected to the No. 2 pin of the expansion power supply chip, and the No. 8 and No. 10 pins are connected to the No. 1 and No. 3 pins of the expansion board unit.

[0018] The I2C Switch module includes a Switch module chip and an H16 pin, and the Switch module chip is specifically a PCA9548A chip, and the H16 pin is a 3x4 pin; the reset pin and the address pin of the Switch module chip are connected to the No. 2, 5, 8 and 11 pins of the H16 pin respectively; the No. 1, 4, 7 and 10 pins of the H16 pin are connected to the ground wire, and the No. 3, 6, 9 and 12 pins of the H16 pin are connected to the +3.3V voltage.

[0019] The I2C extension interface includes extension I2C protocols I2C_E0~7; the 9th-24th pins of the Switch module chip are respectively 0th-7th I2C buses of the I2C extension interface, wherein the 9th, 11th, 13th, 15th, 17th, 19th, 21st and 23rd pins of the Switch module chip are respectively connected to the 2nd pins of the extension I2C protocols I2C_E0~7; the 10th, 12th, 14th, 16th, 18th, 20th, 22nd and 24th pins of the Switch module chip are respectively connected to the 3rd pins of the extension I2C protocols I2C_E0~7; the 1st pin of the extension I2C protocols I2C_E0~7 is connected to a ground wire; and the 4th pin of the extension I2C protocols I2C_E0~7 is connected to a +3.3V voltage.

[0020] The remote I / O extension module includes an extension module chip and an H1 pin array; the extension module chip is specifically a PCF8575 chip, and the H1 pin array is a 2*10 pin array; wherein the 5th, 7th, 9th, 11th, 13th, 15th, 17th and 19th pins of the H1 pin array are respectively connected to the 13th, 14th, 15th, 16th, 17th, 18th, 19th and 20th pins of the extension module chip; the 1st and 2nd pins of the H1 pin array are connected to a ground wire, the 3rd and 4th pins of the H1 pin array are connected to a +3.3V voltage; and the I2C port of the remote I / O extension module is connected through a terminal wire.

[0021] Further, the RTC module includes a DS1307 clock chip, an AT24C32 chip and an H13 pin array; wherein a crystal oscillator is arranged on the DS1307 clock chip, and the two ends of the crystal oscillator are respectively connected to the 1st and 2nd pins of the DS1307 clock chip; a power decoupling capacitor is connected to the 8th pin of the DS1307 clock chip; the 5th and 6th pins of the DS1307 clock chip are respectively connected to pull-up resistors R5 and R6, and the other ends of the pull-up resistors R5 and R6 are respectively connected to the 3rd and 4th pins of the H13 pin array; the DS1307 clock chip is further provided with a CR1220 battery connected to the 3rd and 4th pins of the DS1307 clock chip.

[0022] The 5th and 6th pins of the AT24C32 chip are respectively connected to pull-up resistors R8 and R9, and the other ends of the pull-up resistors R8 and R9 are respectively connected to the 1st and 2nd pins of the H13 pin array; and an 8th pin of the AT24C32 chip is connected to a power decoupling capacitor.

[0023] The UART interface includes a UART1 interface and a UART0 interface; and the I2S interface includes a clock line, a data frame synchronization line and a data line.

[0024] The I2C interface, the UART0 interface, the UART1 interface and the No. 2 pin of the extended power supply chip are connected, the No. 6 pin of the I2C interface and the No. 2 pin of the extended power supply chip are connected, the No. 14 pin of the extension board unit and the No. 2 pin of the I2C interface are connected, the No. 12 pin of the extension board unit and the No. 3 pin of the I2C interface are connected, the No. 21 pin of the extension board unit and the No. 2 pin of the UART0 interface are connected, the No. 19 pin of the extension board unit and the No. 3 pin of the UART0 interface are connected, the No. 15 pin of the extension board unit and the No. 2 pin of the UART1 interface are connected, the No. 13 pin of the extension board unit and the No. 3 pin of the UART1 interface are connected, the No. 24 pin of the extension board unit and the No. 2 pin of the SPI interface are connected, the No. 22 pin of the extension board unit and the No. 3 pin of the SPI interface are connected, the No. 20 pin of the extension board unit and the No. 4 pin of the SPI interface are connected, the No. 16 pin of the extension board unit and the No. 5 pin of the SPI interface are connected, the No. 10 pin of the extension board unit and the No. 2 pin of the I2S interface are connected, the No. 8 pin of the extension board unit and the No. 3 pin of the I2S interface are connected, the No. 6 pin of the extension board unit and the No. 4 pin of the I2S interface are connected, and the No. 4 pin of the extension board unit and the No. 5 pin of the I2S interface are connected.

[0025] Compared with the prior art, the beneficial effects of the utility model include:

[0026] 1. Power management and connection reliability: the master control unit adopts DC / DC step-down module and AMS1117-3.3 chip to realize multi-stage voltage conversion from 12V to 5V to 3.3V, which ensures that the master control unit and the extension circuit board can obtain stable power supply in different experimental scenes, avoiding experimental failure caused by unstable voltage. The master control unit and the extension circuit board are connected by long pin and pin female and fixed by copper column. This design can effectively avoid short circuit caused by contact between the master control unit and the extension circuit board, and the long pin can also ensure close connection with the pin female and the stability of signal transmission. Three groups of VCC and ground wire are mutually redundant backup, which provide stable power supply for the extension board.

[0027] 2. Integration and expansion capability: the master control unit integrates total power supply, MT7628an core board, Ethernet port, USB interface and GPIO button function. The extension circuit board provides rich interfaces and modules, such as I2C, SPI, UART, I2S interface, RTC, FLASH module, remote I / O expansion module and I2C switch module. Direct insertion components are used to reduce welding difficulty and improve experimental success rate.

[0028] 3. Portability and flexibility: the core function is integrated on a 10cm*10cm circuit board, effectively reducing the cost and improving the portability. Whether to use the extension circuit board and its modules can be selected according to the needs, meeting different experimental needs.

[0029] 4. Experimental content and teaching effect: the experimental box covers security experiments from physical layer hardware design to network layer configuration to application layer service, the experimental content is rich, which is convenient for students to understand and operate, effectively improving the practical ability and theoretical knowledge of students.

[0030] In summary, the utility model circuit is simple, reasonable in design and easy to weld, and can effectively improve the students' practical ability and theoretical knowledge level. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description, obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without creative labor.

[0032] Figure 1 It is the experimental box circuit principle block diagram of the utility model.

[0033] Figure 2 It is the total power supply circuit structure diagram of the utility model.

[0034] Figure 3 It is the main control chip circuit structure diagram of the utility model.

[0035] Figure 4 It is the GPIO button circuit structure diagram of the utility model.

[0036] Figure 5 It is the USB interface circuit structure diagram of the utility model.

[0037] Figure 6 It is the Ethernet port circuit structure diagram of the utility model.

[0038] Figure 7 It is the extension board unit interface circuit structure diagram of the utility model.

[0039] Figure 8 It is the extension board power supply circuit structure diagram of the utility model.

[0040] Figure 9 It is the I2C Switch module circuit structure diagram of the utility model.

[0041] Figure 10 It is the remote I / O expansion module circuit structure diagram of the utility model.

[0042] Figure 11 It is the RTC module circuit structure diagram of the utility model.

[0043] Figure 12 It is the Flash module circuit structure diagram of the utility model.

[0044] In the figure, 1, main control chip; 2, memory chip; 3, flash memory; 4, core board; 5, total power supply; 501, input module; 502, DC / DC voltage reduction module; 503, total power supply chip; 6, Ethernet port; 601, J1 socket; 602, J2 socket; 7, GPIO button; 8, USB interface; 9, main control unit; 10, expansion board power supply; 1001, expansion power supply chip; 1002, pin power supply; 11, I2C interface; 12, SPI interface; 13, UART interface; 1301, UART0 interface; 1302, UART1 interface; 14, I2S interface; 15, RTC module; 1501, AT24C32 chip; 1502, DS1307 clock chip; 1503, H13 pin; 16, FLASH module, 1601, SPIFlash memory; 1602, H12 pin; 17, remote I / O expansion module; 1701, H1 pin; 1702, expansion module chip; 18, I2C Switch module; 1801, Switch module chip; 1802, H16 pin; 19, I2C expansion interface; 20, expansion board unit; 21, expansion circuit board. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.

[0046] As Figures 1-12 , the embodiment provides a progressive network engineering comprehensive experiment box, which comprises a main control unit 9 and an expansion circuit board 21; in some specific embodiments, the main control unit 9 and the expansion circuit board 21 are connected using pin and pin female; in actual use, the main control unit 9 can be used alone or in connection with the expansion circuit board 21.

[0047] In some specific embodiments, the main control unit 9 is provided with a total power supply 5, a core board 4, an Ethernet port 6, a USB interface 8 and a GPIO button 7.

[0048] In some specific embodiments, the total power supply 5 comprises an input module 501, a DC / DC voltage reduction module 502 and a total power supply chip 503.

[0049] In some possible embodiments, the total power supply chip 503 is specifically an AMS1117-3.3 chip, which is a linear voltage regulator that can stabilize the input voltage to 3.3V. The input module 501 of the total power supply 5 is connected to the output power supply of a 12V-1A adapter through a DC005 5.5-2.1 (P1) interface, and the output is connected to the positive electrode of a filter capacitor (C1) and the No. 1 pin of the DC / DC voltage reduction module 502 through a self-locking switch and a copper paving mode, so as to ensure the stability of the power supply.

[0050] In some specific embodiments, the AMS1117-3.3 is a linear voltage regulator that can stabilize the input voltage to 3.3V. The VIN end of the total power supply chip 503 is connected to the No. 3 pin of the DC / DC voltage reduction module 502 in a common mode, which is used for stable power supply, and the No. 2 pin outputs a stable 3.3V voltage. In some possible embodiments, the No. 2 pin of the total power supply chip 503 is connected to the pin 24 of the core board 4 to supply power to the main control chip 1. The input and output ends of the total power supply chip 503 are respectively provided with 10µF (C2, C4) and 0.1µF (C3, C5) capacitors. The main function of these capacitors is to filter and eliminate high-frequency interference and transient spikes in the power supply, so as to ensure the smoothness and stability of the voltage output.

[0051] In some possible embodiments, the core board 4 is a PCB circuit board, and the core board 4 is provided with the main control chip 1, the memory chip 2 and the flash memory 3. The memory chip 2 is used for temporarily storing data and programs, so that the main control chip 1 can quickly access and process, and the size of the memory directly affects the number of programs that can be run simultaneously by the device and the speed of processing data. The flash memory 3 is a 32M Flash Memory, and the function of the flash memory 3 is to provide non-volatile storage for storing firmware or operating systems. When the device is powered off, the data in the flash memory 3 will not be lost, and the capacity and performance of the flash memory 3 will also affect the startup speed of the device and the convenience of firmware upgrade. Therefore, in some possible embodiments, a larger flash memory 3 is selected to be connected through an SPI interface 12 to store a larger volume of firmware.

[0052] In some possible embodiments, the main control chip 1 is specifically an MT7628an chip, which is connected to the core board 4 through a pin and female pin insertion mode.

[0053] In some specific embodiments, the core board 4 is further provided with a GPIO button 7 and a USB interface 8, the USB interface 8 comprising a metal shell; wherein one end of the GPIO button 7 is connected to the ground wire of the main control chip 1, and the other end is connected to the 27th pin of the main control chip 1; the 4th pin and the two side pins of the USB interface 8 are grounded, i.e. the metal shell of the USB interface 8 is grounded, the 1st pin of the USB interface 8 is connected to the 3rd pin of the DC / DC step-down module 502, and the 2nd and 3rd pins of the USB interface 8 are respectively connected to the 23rd and 22nd pins of the main control chip 1.

[0054] In some specific embodiments, the Ethernet port 6 comprises a J1 socket 601, a J2 socket 602, and ports WAN1, LAN1, LAN2, LAN3, and LAN4; the Ethernet port 6 further comprises resistors R1, R2, R3, R4, and R5, and signal lines LINK0, LINK1, LINK2, LINK3, and LINK4. Wherein one end of R1, R2, R3, R4, and R5 is connected to the 2nd pin of the total power supply chip 503, and the other end is respectively connected to the 12th pin of the J1 socket 601, the 48th, 36th, 24th, and 12th pins of the J2 socket 602, LINK0, LINK1, LINK2, LINK3, and LINK4 are respectively connected to the 37th, 36th, 35th, 34th, and 33rd pins of the main control chip 1. The 1st, 3rd, 4th, and 6th ports of WAN1, LAN1, LAN2, LAN3, and LAN4 are respectively connected to the 4th, 3rd, 2nd, 1st, 6th, 5th, 8th, 7th, 12th, 11th, 10th, 9th, 14th, 13th, 16th, 15th, 20th, 19th, 18th, and 17th ports of the main control chip 1.

[0055] In some possible embodiments, the J1 socket 601 is a single RJ45 socket, and the J2 socket 602 is an RJ45 1x4 socket.

[0056] In some possible embodiments, the signal lines LINK0, LINK1, LINK2, LINK3, and LINK4 are connected with indicator LEDs for indicating the connection status or active status of the corresponding network ports (such as WAN or LAN ports). In some possible embodiments, when the network cable is correctly connected and the link is established, the corresponding LINK LED will light up, indicating that the device has successfully connected to the network.

[0057] In some specific embodiments, the ports WAN1, LAN1, LAN2, LAN3, LAN4 are used for coupling of signal levels, while achieving isolation of input and output to enhance anti-interference ability and protect the chip; in addition, the ports WAN1, LAN1, LAN2, LAN3, LAN4 can ensure the normal operation of the device when accessing different level network interfaces, and enable the network signal to be transmitted over a longer distance by enhancing the signal output strength. Resistors R1, R2, R3, R4, R5 are used for current limiting, voltage dividing, and as termination resistors to prevent signal reflection, thereby ensuring the quality of data transmission.

[0058] In some specific embodiments, the expansion circuit board 21 is provided with an expansion board power supply 10 and an expansion board unit 20; the expansion board unit 20 is provided with an I2C interface 11, an SPI interface 12, a UART interface 13, an I2S interface 14, an RTC circuit, a FLASH module 16, a remote I / O expansion module 17, an I2C Switch module 18, and an I2C expansion interface 19.

[0059] In some specific embodiments, the I2C interface 11 is a serial communication protocol that allows multiple devices to share the same bus and communicate through data line SDA and clock line SCL. In some possible embodiments, it is used to connect the RTC module 15 and the radio module.

[0060] The SPI interface 12 is a high-speed full-duplex communication protocol used for communication between microcontrollers and various peripheral devices, which requires four lines for data transmission, namely master selection line (CS), clock line (SCLK), master input / slave output line (MOSI), and master output / slave input line (MISO). In some possible embodiments, it is used to connect the Flash module, TFTLCD screen,

[0061] The UART interface 13 is a serial communication interface, including UART1 interface 1302 and UART0 interface 1301, used for asynchronous communication, and is usually used for data transmission between a computer and external devices, which requires two lines for data transmission: transmission line (TX) and reception line (RX). In some possible embodiments, it is used to connect USB storage devices, USB cameras, and other USB devices.

[0062] The I2S interface 14 is a serial communication protocol specifically used for audio data transmission, which supports stereo audio data transmission and includes clock line (BCLK), data frame synchronization line (LRCLK), and data line (SDIN / SDOUT). In some possible embodiments, it is used to connect the audio module.

[0063] RTC circuit is a kind of clock circuit, used to provide real-time clock function, even in the case of system power failure, can keep time. In the present embodiment contains a battery-powered clock and a calendar function.

[0064] FLASH module 16 is a kind of non-volatile memory, used to store data and program code. Even after power failure, data will not be lost. In the present utility model, for storing larger system image.

[0065] Remote I / O expansion module 17, used to provide more input / output interface for the present embodiment.

[0066] I2C Switch module 18 is a special I2C device, which can connect multiple I2C devices and allow communication with them through a single I2C bus. In some possible embodiments, it is used to solve the case of connecting multiple I2C devices with the same address.

[0067] I2C expansion interface 19 is used to connect additional I2C devices to the system, increasing the communication capability and device number of the system. In some possible embodiments, I2C expansion interface 19 includes 7 expansion I2C protocols.

[0068] In some possible embodiments, the expansion board power supply 10 includes an expansion power supply chip 1001 and a pin power supply 1002, which is five groups of pin power supply 1002; wherein the expansion power supply chip 1001 is specifically AMS1117-3.3 chip, AMS1117-3.3 is a linear voltage regulator, which can stabilize the input voltage to 3.3V. The expansion power supply chip 1001 VIN end is connected to 5V power supply, and the VOUT end outputs stable 3.3V voltage. 10µF (C2, C4) and 0.1µF (C3, C5) capacitors are respectively arranged at the input and output ends, and the main function of these capacitors is filtering, eliminating high-frequency interference and transient spikes in the power supply, ensuring the smoothness and stability of voltage output.

[0069] In some possible embodiments, the pin power supply 1002 is used to provide additional power supply for some modules in some possible embodiments, the 1, 3, 5, 7, 9 pins are grounded, the 2, 4, 6 pins are connected with the 2 pin of the expansion power supply chip 1001 to provide +3.3V power supply, and the 8, 10 pins are connected with the 1, 3 pins of the expansion board unit 20 to provide +5V voltage.

[0070] In some possible implementation manners, the I2C Switch module 18 comprises a Switch module chip 1801 and an H16 pin 1802, the Switch module chip 1801 is specifically a PCA9548A chip, and the H16 pin 1802 is a 3×4 pin; a No. 5 pin (reset pin) and No. 6, 7, 8 pins (address pins) of the Switch module chip 1801 are connected with No. 2, 5, 8, 11 pins of the H16 pin 1802 respectively; No. 1, 4, 7, 10 pins of the H16 pin 1802 are connected with ground wires, and No. 3, 6, 9, 12 pins of the H16 pin 1802 are connected with +3.3V voltage.

[0071] In some possible implementation manners, the Switch module chip 1801 allows to be reset by a jumper cap to reinitialize the device or clear the error state, or to change the address of the Switch module chip 1801 by the jumper cap when the I2C address conflicts, thereby enhancing the scalability of the system.

[0072] In some specific implementation manners, No. 9-24 pins of the Switch module chip 1801 are respectively No. 0-7 I2C buses of the I2C expansion interface 19, an SDx interface (No. 9, 11, 13, 15, 17, 19, 21, 23 pins) of the Switch module chip 1801 is connected with No. 2 pin of an extended I2C protocol I2C_Ex (x is an integer from 0 to 7), an SCx interface (No. 10, 12, 14, 16, 18, 20, 22, 24) of the Switch module chip 1801 is connected with No. 3 pin of the extended I2C protocol I2C_Ex (x is an integer from 0 to 7), No. 1 pin of the extended I2C protocol I2C_Ex is connected with a ground wire (x is an integer from 0 to 7), and No. 4 pin of the extended I2C protocol I2C_Ex is connected with +3.3V (x is an integer from 0 to 7). The extended I2C protocol I2C_Ex is a 2.55 mm terminal port, which can be conveniently connected with I2C devices (x is an integer from 0 to 7) in some possible implementation manners.

[0073] In some possible implementation manners, the remote I / O expansion module 17 comprises an expansion module chip 1702 and an H1 pin 1701; the expansion module chip 1702 is specifically a PCF8575 chip, and the H1 pin 1701 is a 2×10 pin; the remote I / O expansion module 17 adopts the PCF8575 chip to expand GPIO.

[0074] In some embodiments, the 5th, 7th, 9th, 11th, 13th, 15th, 17th, and 19th pins of the H1 pin header 1701 are connected to the P00-7 interface (13th, 14th, 15th, 16th, 17th, 18th, 19th, and 20th pins) of the expansion module chip 1702; the 1st and 2nd pins of the H1 pin header 1701 are connected to the ground, and the 3rd and 4th pins are +3.3V. The I2C port of the remote I / O expansion module 17 is not on the expansion circuit board 21, but is directly connected by terminal wires in some possible embodiments.

[0075] In some possible embodiments, the RTC module 15 includes a DS1307 clock chip 1502, an AT24C32 chip 1501 (a serial EEPROM), and an H13 pin header 1503. The DS1307 clock chip 1502 is the core of the RTC module 15, and the two ends of the crystal oscillator (X1) are connected to the 1st and 2nd pins of the DS1307 clock chip 1502, respectively. A power decoupling capacitor (C10, 100nF) is connected to the 8th pin of the DS1307 clock chip 1502 to filter out power noise and ensure stable operation of the chip. The 5th and 6th pins of the DS1307 clock chip 1502 are connected to pull-up resistors (R5 and R6, 4.7kΩ) to ensure that the signal line remains at a high level in the idle state, and are then connected to the 3rd and 4th pins of the H13 pin header 1503 to be connected to the I2C interface 11 or the I2C expansion interface 19 in some possible embodiments. A CR1220 battery (U18) provides a backup power source and is connected to the 3rd and 4th pins of the DS1307 clock chip 1502 to maintain the operation of the RTC when the main power is off, ensuring time continuity.

[0076] The AT24C32 chip 1501 is used to store data. One end of the pull-up resistors (R8 and R9, 4.7kΩ) of the AT24C32 chip 1501 is connected to the 5th and 6th pins of the AT24C32 chip 1501, respectively, to ensure that the signal line remains at a high level in the idle state, and is then connected to the 1st and 2nd pins of the H13 pin header to be connected to the I2C interface 11 or the I2C expansion interface 19 in some possible embodiments. A power decoupling capacitor (C8, 100nF) is connected to the 8th pin of the AT24C32 chip 1501 to filter out power noise and ensure stable operation of the chip.

[0077] In some possible embodiments, the FLASH module 16 comprises an SPI Flash memory 1601 and an H12 pin array 1602, the No.1, 2, 5, 6 pins of the SPI Flash memory 1601 are collectively standard SPI pins, which correspond to the No.4, 2, 1, 3 pins of the H12 pin array respectively, so as to be connected with the SPI interface 12 in some possible embodiments; a decoupling capacitor (C6) is connected with the No.8 pin of the SPI Flash memory 1601, to ensure the stability of the power supply. A chip selection pin (WS_CS) is used to enable the SPI Flash memory 1601, data is bidirectionally transmitted through a data input pin (WS_DI) and a data output pin (WS_DO), and a clock pin (WS_CLK) provides a synchronous clock signal.

[0078] In some possible embodiments, the extension circuit board 21 further comprises a 2*12 pin array female, which is used to connect the related pins of the master control chip 1 from the master control circuit board to the extension circuit board 21. The No.1, 3 pins of the extension board unit 20 are connected with the No.3 pin of the extension power supply chip 1001 of the extension power supply 10 and the No.8, 10 pins of the pin power supply 1002.

[0079] In some specific embodiments, the I2C interface 11, the UART0 interface 1301 and the UART1 interface 1302 are all connected with the No.2 pin of the extension power supply chip 1001, and the No.6 pins of the SPI interface 12 and the I2C interface 11 are all connected with the No.2 pin of the extension power supply chip 1001. The No.14, 12 pins of the extension board unit 20 are respectively connected with the No.2, 3 pins of the I2C interface 11, the No.21, 19 pins of the extension board unit 20 are respectively connected with the No.2, 3 pins of the UART0 interface 1301, the No.15, 13 pins of the extension board unit 20 are respectively connected with the No.2, 3 pins of the UART1 interface 1302, the No.24, 22, 20, 16 pins of the extension board unit 20 are respectively connected with the No.2, 3, 4, 5 pins of the SPI interface 12, and the No.10, 8, 6, 4 pins of the extension board unit 20 are respectively connected with the No.2, 3, 4, 5 pins of the I2S interface 14.

[0080] In some possible embodiments, in the master control unit 9 and the extension circuit board 21, all the ground wires are connected through copper paving.

[0081] The above merely describes the preferred embodiments of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A progressive network engineering integrated experimental box, comprising a main control unit (9) and an expansion circuit board (21), characterized in that, The main control unit (9) integrates a main power supply (5), a core board (4), an Ethernet port (6), a USB interface (8), and a GPIO button (7); the expansion circuit board (21) includes an expansion board power supply (10) and an expansion board unit (20). Among them, the main power supply (5) is connected to the core board (4) and the expansion board power supply (10); the expansion board power supply (10) is connected to the expansion board unit (20); The core board (4) is also connected to the expansion board unit (20), USB interface (8), GPIO button (7), and Ethernet port (6); The expansion board unit (20) is a busbar, and the expansion board unit (20) integrates an I2C interface (11), an SPI interface (12), a UART interface (13), an I2S interface (14), an RTC circuit, a FLASH module (16), a remote I / O expansion module (17), an I2C Switch module (18), and an I2C expansion interface (19). The core board (4) is specifically a PCB circuit board, and the core board (4) integrates a main control chip (1), a memory chip (2) and a flash memory (3); the main control chip (1) is specifically an MT7628an chip, which is connected to the core board (4) by means of pin header and socket header; The main power supply (5) includes an input module (501), a DC / DC step-down module (502), and a main power supply chip (503). The P1 interface of the input module (501) is connected to the output power of a 12V-1A adapter, a filter capacitor is connected by copper pouring, and it is connected to pin 1 of the DC / DC step-down module (502). The main power chip (503) is specifically an AMS1117-3.3 chip. The VIN terminal of the main power chip (503) is connected to pin 3 of the DC / DC step-down module (502), and pin 2 of the main power chip (503) is connected to pin 24 of the core board (4) to supply power to the main control chip (1). A set of parallel 10µF and 0.1µF capacitors are set at both the input and output ends of the main power chip (503). One end of the GPIO button (7) is connected to the ground wire of the main control chip (1), and the other end is connected to pin 27 of the main control chip (1); The USB interface (8) includes a metal casing. Pin 4 and the pins on both sides of the USB interface (8) are grounded. Pin 1 is connected to pin 3 of the DC / DC step-down module (502). Pins 2 and 3 of the USB interface (8) are connected to pins 23 and 22 of the main control chip (1), respectively.

2. The progressive network engineering integrated experimental box according to claim 1, characterized in that, The Ethernet port (6) includes J1 socket (601), J2 socket (602) and ports WAN1, LAN1, LAN2, LAN3, and LAN4; the Ethernet port (6) also includes resistors R1, R2, R3, R4, and R5 and signal lines LINK0, LINK1, LINK2, LINK3, and LINK4. The J1 socket (601) is a single RJ45 socket, and the J2 socket (602) is an RJ45 1×4 socket; Among them, R1, R2, R3, R4, and R5 are connected to pin 2 of the main power chip (503) at one end, and to pin 12 of J1 socket (601) and pins 48, 36, 24, and 12 of J2 socket (602) at the other end, respectively. LINK0, LINK1, LINK2, LINK3, and LINK4 are connected to pins 37, 36, 35, 34, and 33 of the main control chip (1) respectively. Ports 1, 3, 4, and 6 of WAN1, LAN1, LAN2, LAN3, and LAN4 are connected to ports 4, 3, 2, 1, 6, 5, 8, 7, 12, 11, 10, 9, 14, 13, 16, 15, 20, 19, 18, and 17 of the main control chip (1) respectively.

3. The progressive network engineering integrated experimental box according to claim 1, characterized in that, The expansion board power supply (10) includes an expansion power chip (1001) and a pin power supply (1002), wherein the pin power supply (1002) consists of five sets of pin power supplies (1002). The extended power chip (1001) is specifically an AMS1117-3.3 chip; the extended power chip (1001) has a 5V power supply connected to its VIN terminal and a stable 3.3V voltage output at its VOUT terminal. A set of parallel 10µF and 0.1µF capacitors are set at both the input and output terminals; pin 3 of the extended power chip (1001) is connected to pins 1 and 3 of the expansion board unit (20); The pin power supply (1002) pins 1, 3, 5, 7 and 9 are grounded, pins 2, 4 and 6 are connected to pin 2 of the extended power supply chip (1001), and pins 8 and 10 are connected to pins 1 and 3 of the expansion board unit (20).

4. The progressive network engineering integrated experimental box according to claim 1, characterized in that, The I2C Switch module (18) includes a Switch module chip (1801) and an H16 header (1802). The Switch module chip (1801) is specifically a PCA9548A chip, and the H16 header (1802) is a 3×4 header. The reset pin and address pin of the Switch module chip (1801) are connected to pins 2, 5, 8, and 11 of the H16 header (1802), respectively. Pins 1, 4, 7, and 10 of the H16 header (1802) are connected to ground, and pins 3, 6, 9, and 12 of the H16 header (1802) are connected to a +3.3V voltage.

5. A progressive network engineering integrated experimental box according to claim 1 or 4, characterized in that, The I2C expansion interface (19) includes the extended I2C protocol I2C_E0~7; pins 9-24 of the Switch module chip (1801) are the I2C buses 0-7 of the I2C expansion interface (19), wherein pins 9, 11, 13, 15, 17, 19, 21, and 23 of the Switch module chip (1801) are connected to pin 2 of the extended I2C protocol I2C_E0~7 respectively; pins 10, 12, 14, 16, 18, 20, 22, and 24 of the Switch module chip (1801) are connected to pin 3 of the extended I2C protocol I2C_E0~7 respectively; pin 1 of the extended I2C protocol I2C_E0~7 is connected to ground; pin 4 of the extended I2C protocol I2C_E0~7 is connected to +3.3V voltage.

6. A progressive network engineering integrated experimental box according to claim 1 or 4, characterized in that, The remote I / O expansion module (17) includes an expansion module chip (1702) and an H1 header (1701); the expansion module chip (1702) is specifically a PCF8575 chip, and the H1 header (1701) is a 2×10 header; pins 5, 7, 9, 11, 13, 15, 17, and 19 of the H1 header (1701) are connected to pins 13, 14, 15, 16, 17, 18, 19, and 20 of the expansion module chip (1702), respectively; pins 1 and 2 of the H1 header (1701) are connected to ground, and pins 3 and 4 of the H1 header (1701) are connected to a +3.3V voltage; the I2C port of the remote I / O expansion module (17) is connected via a terminal line.

7. The progressive network engineering integrated experimental box according to claim 1, characterized in that, The RTC module (15) includes a DS1307 clock chip (1502), an AT24C32 chip (1501), and an H13 header (1503). The DS1307 clock chip (1502) has a crystal oscillator connected to pins 1 and 2 of the DS1307 clock chip (1502). Pin 8 of the DS1307 clock chip (1502) is connected to a power decoupling capacitor. Pins 5 and 6 of the DS1307 clock chip (1502) are connected to pull-up resistors R5 and R6, respectively, with the other ends of R5 and R6 connected to pins 3 and 4 of the H13 header (1503). The DS1307 clock chip (1502) also has a CR1220 battery connected to pins 3 and 4. Pins 5 and 6 of the AT24C32 chip (1501) are connected to pull-up resistors R8 and R9, respectively. The other ends of the pull-up resistors R8 and R9 are connected to pins 1 and 2 of the H13 header (1503), respectively. Pin 8 of the AT24C32 chip (1501) is connected to a power supply decoupling capacitor.

8. A progressive network engineering integrated experimental box according to any one of claims 1 and 4, characterized in that, The UART interface (13) includes a UART1 interface (1302) and a UART0 interface (1301); the I2S interface (14) includes a clock line, a data frame synchronization line, and a data line; The I2C interface (11), UART0 interface (1301), and UART1 interface (1302) are connected to pin 2 of the extended power chip (1001). The SPI interface (12) and pin 6 of the I2C interface (11) are both connected to pin 2 of the extended power chip (1001). Pins 14 and 12 of the expansion board unit (20) are connected to pins 2 and 3 of the I2C interface (11), respectively. Pins 21 and 19 of the expansion board unit (20) are connected to pins 2 and 3, respectively. The expansion board unit (20) is connected to pins 2 and 3 of the UART0 interface (1301), pins 15 and 13 of the expansion board unit (20) are connected to pins 2 and 3 of the UART1 interface (1302) respectively, pins 24, 22, 20 and 16 of the expansion board unit (20) are connected to pins 2, 3, 4 and 5 of the SPI interface (12) respectively, and pins 10, 8, 6 and 4 of the expansion board unit (20) are connected to pins 2, 3, 4 and 5 of the I2S interface (14) respectively.

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