Intelligent power distribution system for transportation mode

Abstract

The utility model provides an intelligent power distribution system for a transportation mode. The intelligent power distribution system comprises a high-drive chip U1, a pre-drive chip U2, an MCU chip U3, an MOS tube Q1, an MOS tube Q2, a diode D1, a voltage-regulator tube D2, a comparator U4 and a resistor R5. The drain electrode of the MOS tube Q1 and the positive electrode of the diode D1 are electrically connected with a working voltage, the source electrode of the MOS tube Q1 is electrically connected with a load through the high-drive chip U1, the grid electrode of the MOS tube Q1 is electrically connected with the MCU chip U3 through the pre-drive chip U2, the negative electrode of the diode D1 is electrically connected with the input end of the comparator U4, the source electrode of the MOS tube Q2 and the negative electrode of the voltage-regulator tube D2, the output end of the comparator U4 is electrically connected with the MCU chip U3, and the output end of the voltage-regulator tube D2 is electrically connected with the MCU chip U3. The grid electrode of the MOS tube Q2 is electrically connected with the positive electrode of the voltage-regulator tube D2, the enabling end of the MCU chip U3 and one end of the resistor R5, and the drain electrode of the MOS tube Q2 is electrically connected with a load.

Description

Technical Field

[0001] This utility model relates to the field of power distribution system technology, and more specifically, to an intelligent power distribution system for transportation modes. Background Technology

[0002] With the globalization of automobile manufacturing and the development of the shipping industry, more and more cars need to be shipped to destinations around the world. During long-distance transportation, the vehicle's battery can become depleted due to power consumption by downstream controllers. Currently, in long-term storage and transportation modes, to minimize static current and avoid battery depletion after prolonged storage and transportation, a memory fuse is typically installed in the front compartment electrical box or instrument panel electrical box. This fuse circuit connects to loads that require static current to be cut off during long-term storage and transportation (such as audio systems, instrument panels, air conditioning, and other comfort-type loads). Before loading the vehicle onto the ship, the memory fuse is removed. At this time, the powertrain can operate normally, and the lights and alarm devices can work, but the air conditioning, audio system, etc., will not work properly in this mode. After arriving at the destination, the fuse is reinserted, and the vehicle's electrical functions return to normal. In existing technologies, fuses need to be removed before long-distance transportation begins and then reinstalled upon arrival at the destination. This increases labor costs and carries the risk of fuse damage or loss during the removal and installation process. Furthermore, not all downstream loads need to be powered off during transportation, such as powertrains, monitoring equipment, and positioning devices. Utility Model Content

[0003] This application provides an intelligent power distribution system for transportation modes, which solves the problem of needing to remove and install fuses in transportation modes in the prior art.

[0004] According to an embodiment of this application, an intelligent power distribution system for transportation modes is provided. The intelligent power distribution system includes: a high-drive chip U1, a pre-drive chip U2, an MCU (Micro Controller Unit) chip U3, a MOSFET Q1, a MOSFET Q2, a diode D1, a Zener diode D2, a comparator U4, and a resistor R5.

[0005] The drain of the MOSFET Q1 and the anode of the diode D1 are electrically connected to the operating voltage Vdd, respectively. The high-drive chip U1 is electrically connected to the source of the MOSFET Q1 and the load, respectively. The pre-drive chip U2 is electrically connected to the gate of the MOSFET Q1 and the enable terminal of the MCU chip U3, respectively. The cathode of the diode D1 is electrically connected to the input terminal of the comparator U4, the source of the MOSFET Q2, and the cathode of the Zener diode D2, respectively. The output terminal of the comparator U4 is electrically connected to the input terminal of the MCU chip U3. The gate of the MOSFET Q2 is electrically connected to the anode of the Zener diode D2, the enable terminal of the MCU chip U3, and one end of the resistor R5, respectively. The drain of the MOSFET Q2 is electrically connected to the load, and the other end of the resistor R5 is grounded.

[0006] In some embodiments of this application, the intelligent power distribution system further includes: a logic processing module, wherein the enable terminal of the MCU chip U3 is electrically connected to the gate of the MOS transistor Q2, the positive terminal of the Zener diode D2, and one end of the resistor R5 through the logic processing module.

[0007] In some embodiments of this application, the logic processing module includes transistor Q3, transistor Q4, diode D3, diode D4, latch U4, MOSFET Q5, resistor R1, resistor R2, resistor R3, and resistor R4.

[0008] The emitter of transistor Q4 is electrically connected to the negative terminal of Zener diode D2. The collector of transistor Q4 is electrically connected to the positive terminal of Zener diode D2, one end of resistor R5, and the gate of MOSFET Q2. The base of transistor Q4 is electrically connected to the collector of transistor Q3. The emitter of transistor Q3 is grounded. The base of transistor Q3 is electrically connected to the positive terminal of diode D3 and the output Y pin of latch U4. The A pin of latch U4 is electrically connected to the negative terminal of diode D3 and one end of resistor R2. The other end of resistor R2... One end of the latch is electrically connected to the cathode of the diode D4 and the drain of the MOSFET Q5. The anode of the diode D4 is electrically connected to the MCU_CTL1 signal of the MCU chip U3. The gate of the MOSFET Q5 is electrically connected to the MCU_CTL3 signal of the MCU chip U3 through the resistor R3. The MCU_CTL2 signal of the MCU chip U3 is electrically connected to one end of the resistor R4 and one end of the resistor R1. The OE pin of the latch U4 is electrically connected to the other end of the resistor R4. The other end of the resistor R1 and the source of the MOSFET Q5 are both grounded.

[0009] In some embodiments of this application, transistor Q3 is an NPN transistor and transistor Q4 is a PNP transistor.

[0010] In some embodiments of this application, the MOS transistor Q5 is an N-channel MOS transistor.

[0011] In some embodiments of this application, the latch U4 is model 74AUP1G125GW.

[0012] In some embodiments of this application, the high-drive chip U1 is one of TPS1HB08, TPS1HA08, TPS1HB35, and TPS1HB50, and / or the pre-drive chip U2 is one of DRV8718, TLE92108, L99DZ300, LM74500, and TLE9261.

[0013] In some embodiments of this application, the MCU chip U3 is one of S32K324, TC 377, or FC7300.

[0014] In some embodiments of this application, the comparator U4 is either TLV9022 or LM2903.

[0015] In some embodiments of this application, the MOS transistor Q1 is an N-channel MOS transistor.

[0016] In some embodiments of this application, the MOS transistor Q2 is a P-channel MOS transistor.

[0017] The beneficial effects of the embodiments of this application are as follows:

[0018] This intelligent power distribution system uses a power distribution latching switching circuit, which not only solves the problem of needing to remove and install fuses in the transportation mode in the existing technology, avoiding the complicated process of removing fuses before long-term transportation and then installing them after arriving at the destination, but also effectively reduces battery power consumption in long-term transportation mode and prevents battery damage due to excessive discharge. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the components of an intelligent power distribution system for transportation modes provided in Embodiment 1 of this application;

[0021] Figure 2This is a schematic diagram of the components of an intelligent power distribution system for transportation modes provided in Embodiment 2 of this application;

[0022] Figure 3 This is a schematic diagram of the circuit principle of a logic processing module in a smart power distribution system for transportation modes, provided in Embodiment 2 of this application.

[0023] Figure 4 This is a schematic diagram of the logic flow of an intelligent power distribution system for transportation modes provided in Embodiment 2 of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0025] It should be noted that the terms "comprising" and "having," and any variations thereof, in the embodiments and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, it may include a series of structures, without being limited to the structures listed, but may optionally include structures not listed, or may optionally include other components inherent to these structures.

[0026] This application discloses an intelligent power distribution system for transportation modes, which solves the problem of needing to remove and install fuses in transportation modes. Detailed explanations follow.

[0027] Example 1

[0028] Figure 1 An intelligent power distribution system for transportation modes is shown according to Embodiment 1 of this application. Figure 1As shown, the intelligent power distribution system mainly includes: a high-drive chip U1, a pre-drive chip U2, an MCU chip U3, MOSFETs Q1 and Q2, a diode D1, a Zener diode D2, a comparator U4, and a resistor R5. MOSFETs Q1 and D1 are used for reverse power supply protection. The pre-drive chip U2 generates a charge pump to drive MOSFET Q1. The MCU chip U3 enables the pre-drive chip U2, receives and processes the wake-up signal, and enables MOSFET Q2. MOSFET Q2 is used for the BYPASS power supply path in sleep mode. Diode D1 is used for reverse protection. The Zener diode D2 ensures that MOSFET Q2 can meet the conduction conditions in sleep mode. The comparator U4 wakes up the MCU chip U3 and opens the main power distribution circuit after the current exceeds a certain threshold. Resistor R5 forms the operating current loop required by the Zener diode D2. The high-drive chip U1 is used for main power distribution. Specifically, the drain (D) of MOSFET Q1 and the anode of diode D1 are electrically connected to the operating voltage Vdd. High-drive chip U1 is electrically connected to the source (S) of MOSFET Q1 and the load. Pre-drive chip U2 is electrically connected to the gate (G) of MOSFET Q1 and the enable terminal of MCU chip U3. The cathode of diode D1 is electrically connected to the input of comparator U4, the source (S) of MOSFET Q2, and the cathode of Zener diode D2. The output of comparator U4 is electrically connected to the input of MCU chip U3. The gate (G) of MOSFET Q2 is electrically connected to the anode of Zener diode D2, the enable terminal of MCU chip U3, and one end of resistor R5. The drain (D) of MOSFET Q2 is electrically connected to the load, and the other end of resistor R5 is grounded. This circuit is a Bypass circuit, which provides sleep current to the downstream load when the main power distribution circuit is off in sleep mode. More specifically, MOSFET Q1 is an N-channel MOSFET, and MOSFET Q2 is a P-channel MOSFET.

[0029] In some specific embodiments, the high-drive chip U1 is one of TPS1HB08, TPS1HA08, TPS1HB35, and TPS1HB50, and the pre-drive chip U2 is one of DRV8718, TLE92108, L99DZ300, LM74500, and TLE9261. Furthermore, the MCU chip U3 is one of S32K324, TC377, and FC7300, and the comparator U4 is one of TLV9022 and LM2903.

[0030] The above describes the various components of the intelligent power distribution system for transportation modes provided in Embodiment 1 and their interconnections. The following section will discuss further details. Figure 1 The working principle of intelligent power distribution systems used in transportation modes is described in detail:

[0031] In the Normal mode of vehicle driving, the MCU chip U3 sends an enable signal to the pre-drive chip U2, which controls the pre-drive chip U2 to turn on the MOSFET Q1, so that the reverse connection protection power (i.e., the battery operating voltage Vdd) is supplied to the high-drive chip U1. The output of the high-drive chip U1 serves as the main power distribution to supply power to the downstream load. At the same time, the MCU chip U3 enables and controls the MOSFET Q2 to turn off, thereby ensuring that the BYPASS circuit is disconnected.

[0032] In the vehicle's Sleep mode, the downstream load is also in Sleep mode, requiring less current. At this time, MCU chip U3 is not operating, and high-speed drive chip U1 has no output. Simultaneously, the constant current (operating voltage Vdd) breaks down the Zener diode D2, creating a voltage difference between the drain (D) and gate (G) of MOSFET Q2, thus turning on MOSFET Q2 and providing the Sleep mode current requirement to the downstream load through the BYPASS circuit.

[0033] When the downstream load is awakened, the required current increases significantly. The current monitoring circuit, via comparator U4, wakes up the MCU chip U3. After MCU chip U3 initializes, it turns on the high-speed drive chip U1. At this point, both the main power distribution and the BYPASS circuit simultaneously power the downstream load. Then, MCU chip U3 turns off MOSFET Q2, achieving power switching between the main power distribution and the BYPASS circuit.

[0034] Embodiment 1 of this application adopts a power distribution switching mode of main power distribution and BYPASS circuit. By utilizing the configurable feature of intelligent power distribution switch, it solves the problem of needing to remove and install fuses in the transportation mode in the prior art.

[0035] Example 2

[0036] Figure 2 An intelligent power distribution system for transportation modes is shown according to Embodiment 2 of this application. Figure 2As shown, the intelligent power distribution system includes: a high-drive chip U1, a pre-drive chip U2, an MCU chip U3, MOSFETs Q1 and Q2, a diode D1, a Zener diode D2, a comparator U4, a resistor R5, and a logic processing module S1. MOSFETs Q1 and D1 are used for reverse power supply protection. The pre-drive chip U2 generates a charge pump to drive MOSFET Q1. The MCU chip U3 enables the pre-drive chip U2, receives and processes the wake-up signal, and enables MOSFET Q2. MOSFET Q2 is used for the BYPASS power supply path in sleep mode. Diode D1 is used for reverse protection. The Zener diode D2 ensures that MOSFET Q2 can meet the conduction conditions in sleep mode. The comparator U4 wakes up the MCU chip U3 and opens the main power distribution circuit after the current exceeds a certain threshold. Resistor R5 forms the operating current loop required by the Zener diode D2. The high-drive chip U1 is used for main power distribution. Specifically, the drain (D) of MOSFET Q1 and the anode of diode D1 are electrically connected to the operating voltage Vdd, respectively. The high-drive chip U1 is electrically connected to the source (S) of MOSFET Q1 and the load, respectively. The pre-drive chip U2 is electrically connected to the gate (G) of MOSFET Q1 and the enable terminal of MCU chip U3, respectively. The cathode of diode D1 is electrically connected to the input terminal of comparator U4, the source (S) of MOSFET Q2, and the cathode of Zener diode D2, respectively. The output terminal of comparator U4 is electrically connected to the input terminal of MCU chip U3. The enable terminal of MCU chip U3 is electrically connected to the gate (G) of MOSFET Q2, the anode of Zener diode D2, and one end of resistor R5 through logic processing module S1, respectively. The drain (D) of MOSFET Q2 is electrically connected to the load, and the other end of resistor R5 is grounded. This circuit is a Bypass circuit. When the main power distribution circuit is off in sleep mode, the Bypass circuit provides sleep current to the downstream load. More specifically, MOSFET Q1 is an N-channel MOSFET, and MOSFET Q2 is a P-channel MOSFET.

[0037] In some embodiments, such as Figure 2 and Figure 3As shown, the logic processing module S1 includes transistors Q3 and Q4, diodes D3 and D4, latch U4, MOSFET Q5, and resistors R1, R2, R3, and R4. Transistor Q3 controls the output of latch U4 to turn it on, and transistor Q4, when turned on, turns off MOSFET Q2. Diode D3 synchronizes the active-high signal of latch U4 to its input, and diode D4 is used for reverse protection. Latch U4 latches the instructions given before sleep mode after sleep mode begins. It includes an OE (Output Enable) pin, an A (input) pin, and an output Y (output) pin. MOSFET Q5, when turned on, pulls down the voltage at input A of latch U4. Resistor R1 provides a pull-down resistor, giving the OE pin of latch U4 a fixed state. Resistors R2, R3, and R4 are used for current limiting. The emitter (E) of transistor Q4 is electrically connected to the negative terminal of Zener diode D2. The collector (C) of transistor Q4 is electrically connected to the positive terminal of Zener diode D2, one end of resistor R5, and the gate (G) of MOSFET Q2. The base (B) of transistor Q4 is electrically connected to the collector (C) of transistor Q3. The emitter (E) of transistor Q3 and the other end of resistor R5 are both grounded. The base (B) of transistor Q3 is electrically connected to the positive terminal of diode D3 and the output Y pin of latch U4. The A pin of latch U4 is electrically connected to the negative terminal of diode D3 and one end of resistor R2. The other end of R2 is electrically connected to the cathode of diode D4 and the drain (D) of MOSFET Q5. The anode of diode D4 is electrically connected to the MCU_CTL1 signal of MCU chip U3. The gate (G) of MOSFET Q5 is electrically connected to the MCU_CTL3 signal of MCU chip U3 through resistor R3. The MCU_CTL2 signal of MCU chip U3 is electrically connected to one end of resistor R4 and one end of resistor R1. The OE pin of latch U4 is electrically connected to the other end of resistor R4. The other end of resistor R1 and the source (S) of MOSFET Q5 are both grounded. Furthermore, transistor Q3 is an NPN transistor, transistor Q4 is a PNP transistor, and MOSFET Q5 is an N-channel MOSFET.

[0038] In some specific embodiments, the high-drive chip U1 is one of TPS1HB08, TPS1HA08, TPS1HB35, and TPS1HB50; the pre-drive chip U2 is one of DRV8718, TLE92108, L99DZ300, LM74500, and TLE9261. Furthermore, the MCU chip U3 is one of S32K324, TC377, and FC7300; the comparator U4 is one of TLV9022 and LM2903; and the latch U4 is 74AUP1G125GW.

[0039] Embodiment 1 of this application utilizes the configurable feature of the intelligent power distribution switch to solve the problem of needing to remove and install fuses during transportation. However, its low-current channel (i.e., the BYPASS circuit) is open by default in Sleep mode and cannot be turned off. This causes the intelligent power distribution to fail to shut off constant power in transportation mode, resulting in downstream loads continuing to consume battery current during long-term transportation, leading to battery depletion. Embodiment 2 of this application adopts an intelligent power distribution latching switching method. It uses the logic processing module S1 to perform intelligent logic control of power distribution. When the MCU chip U3 is about to power down, the logic control of the MCU chip U3's IO is used to pre-set whether the BYPASS circuit remains open or closed in Sleep mode. This allows for flexible configuration of whether downstream loads maintain power distribution in transportation mode according to different load requirements.

[0040] The above describes the various components of the intelligent power distribution system for transportation modes provided in Embodiment 2 and their interconnections. The following section will discuss further details. Figure 2 – Figure 4 The working principle of the intelligent power distribution system used in transportation modes is described in detail.

[0041] like Figure 4 As shown, the workflow of this intelligent power distribution system includes the following steps:

[0042] Step S101: The system enters the power-down process;

[0043] Step S102: Determine whether power is needed after hibernation;

[0044] When no power supply is required, proceed from step S102 to step S103; when power supply is required, proceed from step S102 to step S108.

[0045] Step S103: Power off after hibernation;

[0046] Step S104: Pull MCU_CTL2 low, pull MCU_CTL3 low, and pull MCU_CTL1 high;

[0047] Step S105: Pull MCU_CTL1 low;

[0048] Step S106: Determine if BYPASS is turned off;

[0049] If not, return from step S106 to step S104; otherwise, proceed from step S106 to step S107.

[0050] Step S107: MCU power off, system enters sleep mode, power-down ends;

[0051] Step S108: Maintain power supply after hibernation;

[0052] Step S109: Pull MCU_CTL1 low, pull MCU_CTL3 high, and pull MCU_CTL2 low;

[0053] Step S10: Pull MCU_CTL3 low;

[0054] Step S111: Determine if BYPASS is turned off;

[0055] If so, return from step S111 to step S109; otherwise, proceed from step S111 to step S107.

[0056] When the downstream load needs to maintain power supply in sleep mode, before entering sleep mode, first set the MCU_CTL1 signal to low and the MCU_CTL3 signal to high to turn on MOSFET Q5, ensuring that the A pin of latch U4 is low. Then set the MCU_CTL2 signal to low to ensure that the OE pin of latch U4 is low. At this time, the output Y pin of latch U4 is low. Then set the MCU_CTL3 signal to low, and the MCU chip U3 is powered down. After the MCU chip U3 is powered down, the output Y pin of latch U4 remains low, transistor Q3 is cut off, causing transistor Q4 to also be cut off. At this time, MOSFET Q2 is turned on, and the operating voltage Vdd supplies power to the downstream load through diode D1 and MOSFET Q2 as a bypass circuit.

[0057] To reduce sleep current in transport mode, when the downstream load is not powered in sleep mode, before entering sleep mode, the MCU_CTL2 and MCU_CTL3 signals are first set to low level, and then the MCU_CTL1 signal is set to high level. At this time, the A pin of latch U4 is high level, and the output Y pin is also high level. Then, the MCU_CTL1 signal is pulled low. Due to the reverse cutoff of diode D4 and the forward conduction of diode D3, after the MCU chip U3 is powered off, the A pin and the output Y pin of latch U4 will still remain high level. Therefore, after the sleep MCU chip U3 is powered off, the output Y pin of latch U4 remains high level, transistor Q3 is turned on, and transistor Q4 is also turned on. At this time, the voltage of the gate G and drain D of MOSFET Q2 is basically the same, so MOSFET Q2 is turned off, and thus BYPASS has no power supply in sleep mode.

[0058] In summary, this application discloses an intelligent power distribution system for transportation mode, which adopts a power distribution latching switching circuit. This not only solves the problem of needing to remove and install fuses in transportation mode in the prior art, avoiding the complicated process of removing fuses before long-term transportation and then reinstalling them after arriving at the destination, but also effectively reduces battery power consumption in long-term transportation mode and prevents excessive battery depletion and damage.

[0059] It will be understood by those skilled in the art that the accompanying drawings are merely schematic diagrams of one embodiment, and the components shown in the drawings are not necessarily essential for implementing this invention. It should also be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0060] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances. Furthermore, in the description of the embodiments of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0061] Finally, it should be noted that the above-described embodiments are merely specific implementations of this utility model, used to illustrate the technical solution of this utility model, and not to limit it. The protection scope of this utility model is not limited thereto. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this utility model. These modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope described in the claims.

Claims

1. An intelligent power distribution system for transportation modes, characterized in that, The intelligent power distribution system includes: high-drive chip U1, pre-drive chip U2, MCU chip U3, MOSFET Q1, MOSFET Q2, diode D1, Zener diode D2, comparator U4, and resistor R5; The drain of the MOSFET Q1 and the anode of the diode D1 are electrically connected to the operating voltage Vdd, respectively. The high-drive chip U1 is electrically connected to the source of the MOSFET Q1 and the load, respectively. The pre-drive chip U2 is electrically connected to the gate of the MOSFET Q1 and the enable terminal of the MCU chip U3, respectively. The cathode of the diode D1 is electrically connected to the input terminal of the comparator U4, the source of the MOSFET Q2, and the cathode of the Zener diode D2, respectively. The output terminal of the comparator U4 is electrically connected to the input terminal of the MCU chip U3. The gate of the MOSFET Q2 is electrically connected to the anode of the Zener diode D2, the enable terminal of the MCU chip U3, and one end of the resistor R5, respectively. The drain of the MOSFET Q2 is electrically connected to the load, and the other end of the resistor R5 is grounded.

2. The intelligent power distribution system for transportation modes according to claim 1, characterized in that, The intelligent power distribution system further includes a logic processing module, wherein the enable terminal of the MCU chip U3 is electrically connected to the gate of the MOS transistor Q2, the positive terminal of the Zener diode D2, and one end of the resistor R5 through the logic processing module.

3. The intelligent power distribution system for transportation modes according to claim 2, characterized in that, The logic processing module includes transistor Q3, transistor Q4, diode D3, diode D4, latch U4, MOSFET Q5, resistor R1, resistor R2, resistor R3, and resistor R4. The emitter of transistor Q4 is electrically connected to the negative terminal of Zener diode D2. The collector of transistor Q4 is electrically connected to the positive terminal of Zener diode D2, one end of resistor R5, and the gate of MOSFET Q2. The base of transistor Q4 is electrically connected to the collector of transistor Q3. The emitter of transistor Q3 is grounded. The base of transistor Q3 is electrically connected to the positive terminal of diode D3 and the output Y pin of latch U4. The A pin of latch U4 is electrically connected to the negative terminal of diode D3 and one end of resistor R2. The other end of resistor R2... One end of the latch is electrically connected to the cathode of the diode D4 and the drain of the MOSFET Q5. The anode of the diode D4 is electrically connected to the MCU_CTL1 signal of the MCU chip U3. The gate of the MOSFET Q5 is electrically connected to the MCU_CTL3 signal of the MCU chip U3 through the resistor R3. The MCU_CTL2 signal of the MCU chip U3 is electrically connected to one end of the resistor R4 and one end of the resistor R1. The OE pin of the latch U4 is electrically connected to the other end of the resistor R4. The other end of the resistor R1 and the source of the MOSFET Q5 are both grounded.

4. The intelligent power distribution system for transportation modes according to claim 3, characterized in that, Transistor Q3 is an NPN transistor, and transistor Q4 is a PNP transistor.

5. The intelligent power distribution system for transportation modes according to claim 3, characterized in that, The MOSFET Q5 is an N-channel MOSFET.

6. The intelligent power distribution system for transportation modes according to claim 3, characterized in that, The latch U4 is model number 74AUP1G125GW.

7. The intelligent power distribution system for transportation modes according to claim 1, characterized in that, The high-drive chip U1 is one of TPS1HB08, TPS1HA08, TPS1HB35, and TPS1HB50, and / or the pre-drive chip U2 is one of DRV8718, TLE92108, L99DZ 300, LM74500, and TLE9261.

8. The intelligent power distribution system for transportation modes according to claim 1, characterized in that, The MCU chip U3 is one of the following: S32K324, TC377, or FC7300.

9. The intelligent power distribution system for transportation modes according to claim 1, characterized in that, The MOSFET Q1 is an N-channel MOSFET.

10. The intelligent power distribution system for transportation modes according to claim 1, characterized in that, The MOSFET Q2 is a P-channel MOSFET.

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