Chip test circuit and chip test board card

Abstract

The embodiment of the utility model provides a chip test circuit and a chip test board card, a first alarm link is designed for a target detection link, voltage value detection is performed through the first alarm link, and a preset level is transmitted to a test control chip through a matrix alarm circuit under the condition that the voltage of the target detection link is abnormal. A test control chip is triggered to determine a target detection link with abnormal voltage through a matrix alarm circuit, a corresponding power supply module is controlled to be powered off, alarm information is generated, the test control chip can independently control an abnormal power supply channel to be powered off, and other power supply channels working normally are not affected. The chip testing safety and the chip testing efficiency can be improved, an MCU is replaced by a framework of combining the testing control chip with the matrix warning circuit to perform anomaly detection and warning, a communication link and a peripheral circuit among a plurality of MCUs do not need to be designed, the number of needed chips is small, the circuit structure is simple, and the cost is low. And the complexity and the design and manufacturing cost of the chip test circuit are reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of automated testing technology, and in particular to a chip testing circuit and a chip testing board card. BACKGROUND

[0002] Semiconductor automated testing refers to detecting various parameter indicators of a device under test (DUT) by using automatic test equipment (ATE), and after the finished product testing is completed, a customer will further perform an aging test on a chip with normal parameters to eliminate aging failure devices, so as to control the quality of semiconductor devices.

[0003] Currently, chip aging testing usually connects various detection voltages to a microcontroller unit (MCU), and detects the voltages through an analog to digital converter (ADC) of the MCU. When an abnormal voltage of a certain path occurs, the MCU is responsible for judging the path and the type of the abnormal voltage, generating an alarm information and powering down the corresponding power module of the path. Since chip testing is usually performed on a large number of chips, the related technology mainly switches the paths by using multiple MCUs in combination with multiple path selector switches, and polls the voltages of the paths corresponding to the to-be-tested chips.

[0004] However, the direct control of the MCU on the power module to power down will cause the entire test board card to be powered down, so that the normally working power paths cannot continue to perform chip testing, and when multiple MCUs are used for alarm detection, a communication link between the MCUs and a peripheral link of the MCUs need to be designed, resulting in a relatively complex circuit structure. Practical new type content

[0005] Embodiments of the present disclosure provide a chip testing circuit and a chip testing board card, which can reduce the complexity of the chip testing circuit and the design and manufacturing costs.

[0006] In one aspect of the embodiments of the present disclosure, a chip testing circuit is provided, which includes a control module, a first alarm module, a matrix alarm circuit and at least one power module, the control module includes a test control chip, the first alarm module includes at least one first alarm link;

[0007] The power module is connected to a power supply end of a pin of a to-be-tested chip through a first link and connected to a detection end of the pin of the to-be-tested chip through a second link, and the power module is configured to supply power to the to-be-tested chip.

[0008] An input end of the first alarm link is connected with the target detection link, and an output end of the first alarm link is connected with the test control chip through the matrix alarm circuit, the first alarm link is used for comparing a voltage value of the target detection link with a preset voltage threshold, and when a relationship between the voltage value of the target detection link and the preset voltage threshold meets a preset alarm condition, the first alarm link sends a preset level to the matrix alarm circuit, the target detection link includes at least one of the first link and the second link;

[0009] The test control chip is connected with the power module, and is used for determining a target detection link with voltage abnormality through the matrix alarm circuit when the preset level is received, controlling the power module corresponding to the target detection link with voltage abnormality to be powered off and generating alarm information, and when the preset level sent by at least two first alarm links is received, the test control chip is used for controlling the power modules corresponding to the target detection links connected with the at least two first alarm links to be powered off in parallel.

[0010] Optionally, a comparator is arranged in the first alarm link, an input end of the comparator includes a first input end and a second input end, the first input end is connected with at least one of the first link and the second link, and the second input end is connected with a digital-to-analog converter, and the digital-to-analog converter is used for outputting a voltage according to the preset voltage threshold;

[0011] An output end of the comparator is connected with the matrix alarm circuit, and the comparator is used for outputting the preset level when a relationship between a voltage value of the first input end and a voltage value of the second input end meets the preset alarm condition.

[0012] Optionally, a power sampling resistor is arranged in the first link, each first alarm link includes at least one first alarm sub-link, the first alarm sub-link includes at least one of an overcurrent alarm link, an overvoltage alarm link, an undervoltage alarm link and an open circuit alarm link, and a comparator is arranged in the first alarm sub-link;

[0013] An output end of the comparator of each first alarm sub-link is connected with the test control chip through the matrix alarm circuit;

[0014] The matrix alarm circuit, each first alarm sublink corresponds to at least two diode branches, the at least two diode branches include an alarm diode branch and an alarm type diode branch, the alarm diode branch is used for connecting the output end of the comparator and the link judgment pin of the test control chip, and different first alarm links correspond to different link judgment pins, the alarm type diode branch is used for connecting the output end of the comparator and the type judgment pin of the test control chip, and different first alarm sublinks of different alarm types correspond to different type judgment pins;

[0015] The test control chip is used for determining the target detection link with voltage anomaly based on the link judgment pin receiving the preset level, and determining the alarm type based on the type judgment pin receiving the preset level.

[0016] Optionally, the over-current alarm link is provided with a first amplifier and a first comparator, two input ends of the first amplifier are connected with two ends of the power sampling resistor respectively, and the output end of the first amplifier is connected with the first input end of the first comparator, and the first amplifier is used for amplifying the voltage of the power sampling resistor.

[0017] The first input end of the second comparator in the over-voltage alarm link is connected with the second link;

[0018] The first input end of the third comparator in the under-voltage alarm link is connected with the second link;

[0019] The open-circuit alarm link is provided with a second amplifier and a fourth comparator, two input ends of the second amplifier are connected with the second link and the first link respectively, the output end of the second amplifier is connected with the first input end of the fourth comparator, and the second amplifier is used for amplifying the voltage difference between the second link and the first link.

[0020] Optionally, the chip to be tested is arranged in an aging test board, and the circuit further comprises a second alarm module, the second alarm module comprises a second alarm link, and the second alarm link comprises at least one of a ground alarm link and an over-temperature alarm link.

[0021] The third amplifier and the fifth comparator are arranged in the ground alarm link, two input ends of the third amplifier are connected with a ground circuit of the chip test circuit and a ground circuit of the aging test board respectively, an output end of the third amplifier is connected with a first input end of the fifth comparator, the digital-to-analog converter is connected with a second input end of the fifth comparator, an output end of the fifth comparator is connected with the test control chip through the matrix alarm circuit, and the third amplifier is used for amplifying a ground voltage difference of the chip test circuit and the aging test board.

[0022] The sixth comparator is arranged in the over-temperature alarm link, a first input end of the sixth comparator is connected with an over-temperature protection circuit of the power module, the digital-to-analog converter is connected with a second input end of the sixth comparator, an output end of the sixth comparator is connected with the test control chip through the matrix alarm circuit, and the sixth comparator is used for outputting the preset level when a voltage value of the first input end of the sixth comparator is greater than a voltage value of the second input end of the sixth comparator.

[0023] Optionally, the control module further comprises a processor and a controller.

[0024] The processor is used for receiving the alarm information sent by the test control chip and sending the alarm information to an upper computer.

[0025] The processor is further used for receiving and analyzing a chip test instruction sent by the upper computer and forwarding the chip test instruction to the controller, and the chip test instruction is used for indicating a corresponding power supply voltage of a chip to be tested.

[0026] The controller is connected with a front-stage power supply of the power module and is used for controlling the front-stage power supply to supply power to the power module based on the chip test instruction.

[0027] Optionally, the first link and the second link are connected with at least one chip to be tested through a golden finger connector.

[0028] Optionally, a first relay switch is arranged in the first link, the first relay switch is connected with the golden finger connector, the test control chip is used for controlling opening and closing states of each switch channel of the first relay switch, and different switch channels of the first relay switch are used for connecting different chips to be tested.

[0029] Optionally, a second relay switch and an analog switch are arranged in the second link.

[0030] The second relay switch is connected with the golden finger connector, the processor is configured to control the opening and closing state of each switch channel in the second relay switch, and different switch channels of the second relay switch are configured to connect different chips to be tested.

[0031] The analog switch is connected with the at least one power module, and the test control chip is configured to control the opening and closing state of the analog switch to select the chip to be tested for feedback voltage measurement, and adjust the output voltage of the at least one power module according to the measured feedback voltage value.

[0032] In another aspect of the embodiments of the present disclosure, a chip test board card is provided, and the chip test board card is deployed with the chip test circuit according to the above aspect.

[0033] According to the embodiments of the present disclosure, a first alarm link is designed for the target detection link, voltage value detection is performed through the first alarm link, and in the case of voltage abnormality of the target detection link, a preset level is transmitted to the test control chip through the matrix alarm circuit, the test control chip determines the target detection link with voltage abnormality through the matrix alarm circuit, controls the corresponding power module to power off, and generates alarm information. Compared with the protection mechanism of directly controlling the resource board card to power off through the MCU, the test control chip can control the abnormal power channel to power off independently and does not affect other normally working power channels, which can improve the safety and efficiency of chip testing. Moreover, the architecture of the test control chip combined with the matrix alarm circuit is used to replace the MCU for abnormal detection and alarm, without the need to design a communication link and peripheral circuit among multiple MCUs, so that the number of chips required is small, the circuit structure is simple, the complexity of the chip test circuit and the design and manufacturing cost are reduced.

[0034] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which form a part of the specification, illustrate the embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0036] The present disclosure can be more clearly understood with reference to the following detailed description in conjunction with the accompanying drawings, in which:

[0037] Figure 1 A structural schematic diagram of a chip test circuit according to an exemplary embodiment of the present disclosure is provided;

[0038] Figure 2 A structural schematic diagram of a first alarm module and a second alarm module according to an exemplary embodiment of the present disclosure is provided;

[0039] Figure 3A schematic diagram of two diode shunts corresponding to one first alarm sub-link of an exemplary embodiment of the present disclosure;

[0040] Figure 4 A schematic diagram of two diode shunts corresponding to one first alarm sub-link of an exemplary embodiment of the present disclosure;

[0041] Figure 5 A schematic diagram of a structure of a chip test circuit according to another exemplary embodiment of the present disclosure;

[0042] Figure 6 A schematic diagram of a structure of a chip test circuit according to another exemplary embodiment of the present disclosure;

[0043] Figure 7 A schematic diagram of a structure of a first link according to an exemplary embodiment of the present disclosure;

[0044] Figure 8 A schematic diagram of a structure of a second link according to an exemplary embodiment of the present disclosure.

[0045] Reference signs are as follows:

[0046] Control module-1; first alarm module-2; power module-3; matrix alarm circuit-4; first link-5; second link-6; slow start DAC-7; potentiometer-8; digital-to-analog converter-9; second alarm module-10; ADC-11; golden finger connector-12;

[0047] Test control chip-101; processor-102; controller-103; first alarm link-201; power sampling resistor-501; first relay switch-502; second relay switch-601; analog switch-602; operational amplifier link-603; instrument amplifier link-604, second alarm link 1001;

[0048] First comparator-201a; second comparator-201b; third comparator-201c; fourth comparator-201d; first amplifier-201e; second amplifier-201f; fifth comparator-1001a; sixth comparator-1001b; third amplifier-1001c. DETAILED DESCRIPTION

[0049] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. Note that the relative arrangement, numerical expressions, and numerical values of components and steps set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0050] Those skilled in the art can understand that the terms "first", "second" and the like in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, and do not represent any specific technical meaning, nor indicate their logical order.

[0051] It should also be understood that in the embodiments of the present disclosure, "multiple" can mean two or more, and "at least one" can mean one, two or more.

[0052] It should also be understood that for any component, data or structure mentioned in the embodiments of the present disclosure, it can be understood as one or more in general, without explicit limitation or in the context of the opposite indication.

[0053] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the front and rear associated objects.

[0054] It should also be understood that the description of various embodiments of the present disclosure focuses on the differences between various embodiments, and the same or similar parts can be referred to each other, and for the sake of brevity, will not be repeated.

[0055] At the same time, it should be understood that in order to facilitate the description, the size of each part shown in the drawings is not drawn according to the actual proportional relationship.

[0056] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application or uses.

[0057] Techniques and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but in appropriate cases, the techniques and devices should be considered as part of the specification.

[0058] It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0059] Figure 1 is a structural block diagram of a chip test circuit provided by an exemplary embodiment of the present disclosure. As shown in Figure 1 The chip test circuit includes a control module 1, a first alarm module 2, a matrix alarm circuit 4 and at least one power supply module 3, the control module 1 includes a test control chip 101, and the first alarm module 2 includes at least one first alarm link 201. The chip test circuit is arranged in a resource board card.

[0060] The power module 3 is connected with the power supply end of the pin of the corresponding chip under test through the first link 5 and connected with the detection end of the pin of the corresponding chip under test through the second link 6, and the power module 3 is used to supply power to the chip under test. Optionally, the chip under test is arranged in a burn-in board (BIB), and at least one power module 3 can be connected with the power supply end (force end) of the corresponding number of chips under test in the BIB through at least one first link 5, that is, the force link; correspondingly, at least one power module 3 can be connected with the detection end (sense end) of the corresponding number of chips under test in the BIB through at least one second link 6, that is, the sense link.

[0061] The input end of the first alarm link 201 is connected with the target detection link, and the output end of the first alarm link 201 is connected with the test control chip 101 through the matrix alarm circuit 4, and the first alarm link 201 is used to compare the voltage value of the target detection link with the preset voltage threshold value, and send the preset level to the matrix alarm circuit 4 when the relationship between the voltage value of the target detection link and the preset voltage threshold value meets the preset alarm condition, and the target detection link includes at least one of the first link 5 and the second link 6. One first link 5 and one second link 6 constitute a power supply channel of a chip under test, different chips under test correspond to different power supply channels, and the connection mode of the first alarm link and the power supply channel is different for different types of abnormal detection, which can be connected with only the first link 5 in the power supply channel (that is, the target detection link of the power supply channel is the first link 5), or connected with the second link 6 in the power supply channel (that is, the target detection link of the power supply channel is the second link 6), or connected with the first link 5 and the second link 6 at the same time (that is, the target detection link of the power supply channel is the first link 5 and the second link 6).

[0062] The test control chip 101 is connected with the power module 3, and is used to determine the target detection link with voltage abnormality through the matrix alarm circuit 4 when receiving the preset level, control the power module 3 corresponding to the target detection link with voltage abnormality to be powered off and generate alarm information, wherein when receiving the preset level sent by at least two first alarm links 201, the test control chip 101 is used to control the power module 3 corresponding to the target detection link connected by the at least two first alarm links 201 to be powered off in parallel.

[0063] Optionally, the matrix alarm link 4 can be built with a diode matrix. If the links in the matrix alarm link 4 are regarded as links in two dimensions of rows and columns, the links in different rows can correspond to different abnormal alarm types (such as overcurrent alarm, overvoltage alarm, undervoltage alarm, etc.), and the links in different columns correspond to different first alarm links 201 (or the links in different columns correspond to different abnormal alarm types, and the links in different rows correspond to different first alarm links 201), so that the test control chip 101 can determine the abnormal alarm type and the first alarm link 201 and the corresponding target detection link according to the output of the preset level of the row and the column, and further generate alarm information. Compared with the voltage detection and abnormal alarm mode using multiple MCUs for polling, no matter which power supply channel or which type of abnormality, the test control chip 101 can quickly locate the corresponding target detection link and power module 3, improve the efficiency of abnormal detection and alarm response speed in the chip test process, and reduce the complexity of the circuit.

[0064] Based on the embodiments of the present disclosure, the first alarm link is designed for the target detection link, the voltage value is detected through the first alarm link, and in the case of voltage abnormality of the target detection link, the preset level is transmitted to the test control chip through the matrix alarm circuit, triggering the test control chip to determine the target detection link with voltage abnormality through the matrix alarm circuit, controlling the corresponding power module to power off and generating alarm information. Compared with the protection mechanism of directly controlling the resource board card to power off by the MCU, the test control chip can control the abnormal power channel to power off and does not affect other normally working power channels, which can improve the safety and efficiency of chip testing. Moreover, the architecture of the test control chip combined with the matrix alarm circuit is used to replace the MCU for abnormal detection and alarm, without the need to design communication links and peripheral circuits among multiple MCUs, which requires fewer chips, simple circuit structure, reduces the complexity of chip test circuit and design and manufacturing cost.

[0065] In a possible implementation, as shown in Figure 2 The first alarm link 201 is provided with a comparator, the input end of the comparator includes a first input end and a second input end, the first input end is connected with at least one of the first link 5 and the second link 6, and the second input end is connected with a digital-to-analog converter (DAC) 9, and the digital-to-analog converter 9 is used to output voltage according to a preset voltage threshold.

[0066] The output end of the comparator is connected with the matrix alarm circuit 4, and the comparator is used to output a preset level when the relationship between the voltage value of the first input end and the voltage value of the second input end meets a preset alarm condition. For example, when the voltage value of the first input end is greater than the voltage value of the second input end, the comparator outputs a preset level (low level).

[0067] By setting the digital-to-analog converter 9 and the comparator in the chip test circuit, the voltage of the target detection link is compared with the voltage output by the digital-to-analog converter 9 through the comparator, the preset level is triggered automatically when the voltage of the target detection link is abnormal, and the abnormal alarm can be performed without polling the specific voltage values of each first link 5 and second link 6 through the ADC, so that the speed of abnormal response can be improved.

[0068] In a possible implementation, the chip test circuit provided by the embodiments of the present disclosure can implement at least one of the following alarm types: over current protection (OCP) alarm, over voltage protection (OVP) alarm, under voltage protector (UVP) alarm, and open circuit alarm. Figure 2 As shown, the power sampling resistor 501 is arranged in the first link 5, each first alarm link 201 includes at least one first alarm sub-link, the first alarm sub-link includes at least one of the over current alarm link, the over voltage alarm link, the under voltage alarm link, and the open circuit alarm link, a comparator is arranged in each first alarm sub-link, and the output end of the comparator of each first alarm sub-link is connected with the test control chip 101 through the matrix alarm circuit 4. Figure 2 Only the first alarm sub-link in the first alarm link 201 is shown, and in the actual application process, the chip test circuit can include the first alarm sub-link corresponding to the plurality of first alarm links 201.

[0069] In the matrix alarm circuit 4, each first alarm sub-link corresponds to at least two diode branches, and the at least two diode branches include an alarm channel diode branch and an alarm type diode branch. Figure 3Two diode shunts corresponding to a first alarm sub-link are shown, wherein the alarm channel diode shunt is used to connect the output end of the comparator and the link judgment pin of the test control chip 101, and different first alarm links 201 correspond to different link judgment pins. The output ends of the alarm channel diode shunts corresponding to all first alarm sub-links in the same first alarm link 201 are connected to the same link judgment pin. Therefore, the test control chip 101 can determine the power supply channel (first link 5 and / or second link 6) where the abnormality occurs according to the link judgment pin receiving the preset level, and further control the power supply module 3 corresponding to the power supply channel to power off. The alarm type diode shunt is used to connect the output end of the comparator and the type judgment pin of the test control chip 101, and different first alarm sub-links of different alarm types correspond to different type judgment pins. The first alarm sub-links of the same alarm type in each first alarm link 201 correspond to the same type judgment pin. Therefore, the test control chip 101 can determine the abnormal type of the abnormal power supply channel according to the type judgment pin receiving the preset level, and generate an alarm information.

[0070] The test control chip 101 is used to determine the target detection link with voltage abnormality based on the link judgment pin receiving the preset level, and determine the alarm type based on the type judgment pin receiving the preset level. Figure 4 The connection mode of the first alarm sub-link of the two power supply channels and the matrix alarm circuit 4 and the test control chip 101 is shown. As shown in the figure, in the first alarm link 201 corresponding to the power supply channel 0, the alarm channel diode shunts of all first alarm sub-links are connected to the Y0 pin of the test control chip 101; in the first alarm link 201 corresponding to the power supply channel 1, the alarm channel diode shunts of all first alarm sub-links are connected to the Y1 pin of the test control chip 101; in the two first alarm links 201 corresponding to the power supply channel 0 and the power supply channel 1, the alarm type diode shunts corresponding to the overcurrent alarm link are connected to the X0 pin of the test control chip 101, the alarm type diode shunts corresponding to the overvoltage alarm link are connected to the X1 pin of the test control chip 101, the alarm type diode shunts corresponding to the undervoltage alarm link are connected to the X2 pin of the test control chip 101, and the alarm type diode shunts corresponding to the open circuit alarm link are connected to the X3 pin of the test control chip 101. If the Y0 pin and the X3 pin of the test control chip 101 simultaneously receive the preset level, it can be judged that the power supply channel 0 exists in the open circuit condition.

[0071] The power module 3 supplies power to the chip under test in the BIB board, and the chip under test forms a load current as a load, which generates a voltage drop on the power sampling resistor 501 in the first link 5. Since the resistance level of the power sampling resistor 501 is mΩ, the voltage drop generated is usually only a few mV, and the comparator cannot reliably sense the voltage change for overcurrent warning. Open circuit warning is to detect the voltage difference between the first link 5 and the second link 6 to determine whether there is a power supply abnormality. During chip testing, the connector may be damaged after being plugged in and out several times, resulting in increased impedance and thus a larger voltage division. Therefore, open circuit warning detection is needed. Although the voltage drop value of the connector is small when it is abnormal, it is usually around 200mV, but it is fatal to the chip under test, which may cause the chip under test to fail to work or be damaged. Therefore, the voltage difference needs to be accurately detected. To solve the above problems, in a possible implementation, for the overcurrent warning link and the open circuit warning link, an amplifier can be arranged therein, the input end of the amplifier is connected with the target detection link, and the output end of the amplifier is connected with the first input end of the comparator, so that the amplifier can amplify the voltage to be detected, and the comparator can accurately and quickly sense the voltage change.

[0072] In a possible implementation, as shown in Figure 2 The first amplifier 201e and the first comparator 201a are arranged in the overcurrent warning link. The two input ends of the first amplifier 201e are respectively connected with the two ends of the power sampling resistor 501, the output end of the first amplifier 201e is connected with the first input end of the first comparator 201a, and the first amplifier 201e is used for amplifying the voltage of the power sampling resistor 501. When the voltage across the power sampling resistor 501 is greater than the preset voltage threshold value output by the digital-to-analog converter 9 for overcurrent warning, the first comparator 201a outputs a preset level to the matrix warning circuit 4, and the matrix warning circuit 4 sends the preset level to the corresponding type judgment pin and link judgment pin in the test control chip 101, so as to trigger the test control chip 101 to control the corresponding power module 3 to power off and generate warning information.

[0073] The first input end of the second comparator 201b in the overvoltage alarm link is connected with the second link 6. The first input end of the third comparator 201c in the undervoltage alarm link is connected with the second link 6. The overvoltage alarm and the undervoltage alarm are to detect the remote sense voltage, and when there is an abnormality (for example, the voltage at the first input end of the second comparator 201b is higher than the voltage at the second input end of the second comparator 201b / the voltage at the first input end of the third comparator 201c is lower than the voltage at the second input end of the third comparator 201c), the second comparator 201b / the third comparator 201c outputs a preset level (low level) to the matrix alarm circuit 4, thereby triggering the test control chip 101 to perform corresponding abnormality alarm processing.

[0074] The second amplifier 201f and the fourth comparator 201d are arranged in the open circuit alarm link. The two input ends of the second amplifier 201f are respectively connected with the second link 6 and the first link 5. The output end of the second amplifier 201f is connected with the first input end of the fourth comparator 201d. The second amplifier 201f is used to amplify the voltage difference between the second link 6 and the first link 5. The open circuit alarm is to judge whether there is a power supply abnormality by detecting the voltage difference between the first link 5 and the second link 6. When there is an abnormality (for example, the voltage at the first input end of the fourth comparator 201d is higher than the voltage at the second input end of the fourth comparator 201d), the fourth comparator 201d outputs a preset level (low level) to the matrix alarm circuit 4, thereby triggering the test control chip 101 to perform corresponding abnormality alarm processing.

[0075] In a possible implementation, the chip test circuit provided by the embodiment of the present disclosure further has the functions of over temperature protection (OTP) alarm and ground protection alarm. As shown in FIG. 1, the OTP alarm link includes a fifth comparator 201e and a sixth comparator 201f. The two input ends of the fifth comparator 201e are respectively connected with the first link 5 and the second link 6. The output end of the fifth comparator 201e is connected with the first input end of the sixth comparator 201f. The sixth comparator 201f is used to detect the voltage difference between the first link 5 and the second link 6. Figure 5As shown, the to-be-tested chip is arranged in an aging test board, i.e., a BIB board, and the chip test circuit further includes a second alarm module 10, which includes at least one second alarm link 1001, and the second alarm link 1001 includes at least one second alarm sub-link of ground alarm link and over-temperature alarm link. Optionally, each second alarm sub-link is provided with a comparator, the output end of the comparator is connected with the above-mentioned matrix alarm circuit, and the comparator is used to output a preset level when the relationship between the voltage value at the first input end and the voltage value at the second input end satisfies a preset alarm condition. Moreover, each second alarm link corresponds to at least two diode branches, and the at least two diode branches include an alarm channel diode branch and an alarm type diode branch. The alarm channel diode branch is used to connect the output end of the comparator and the link judgment pin of the test control chip 101, and different second alarm links 1001 correspond to different link judgment pins. The output ends of the alarm channel diode branches corresponding to all second alarm sub-links in the same second alarm link 1001 are connected to the same link judgment pin, so that the test control chip 101 can determine the power supply channel in which the abnormality occurs according to the link judgment pin receiving the preset level, and further control the power supply module 3 corresponding to the power supply channel to power off. The alarm type diode branch is used to connect the output end of the comparator and the type judgment pin of the test control chip 101, and different second alarm sub-links of different alarm types correspond to different type judgment pins. The second alarm sub-links of the same alarm type of each second alarm link 1001 correspond to the same type judgment pin, and the test control chip 101 is used to determine the target detection link of voltage abnormality based on the link judgment pin receiving the preset level, and determine the alarm type based on the type judgment pin receiving the preset level.

[0076] As Figure 2As shown, a third amplifier 1001c (amplifier in the ground alarm link) and a fifth comparator 1001a (comparator in the ground alarm link) are arranged in the ground alarm link, two input ends of the third amplifier 1001c are connected with a ground circuit of the chip test circuit and a ground circuit of the burn-in test board (BIB board) respectively, an output end of the third amplifier 1001c is connected with a first input end of the fifth comparator 1001a, a digital-to-analog converter 9 is connected with a second input end of the fifth comparator 1001a, and an output end of the fifth comparator 1001a is connected with the test control chip 101 through the matrix alarm circuit 4. The third amplifier 1001c is used for amplifying a voltage difference between the ground circuits of the chip test circuit and the burn-in test board, and the fifth comparator 1001a is used for outputting a preset level when a voltage value at the first input end of the fifth comparator 1001a is greater than a voltage value at the second input end of the fifth comparator 1001a. The ground alarm link is used for detecting a voltage difference between the ground of the resource board card and the ground of the BIB board. If the voltage difference is too large, a voltage output by the power supply module 3 will be inaccurate, and the voltage output by the power supply module 3 will affect power-on of the chip under test. Since the voltage difference is usually between 100 mV and 200 mV, the voltage difference is small, and thus the voltage difference needs to be amplified by the third amplifier 1001c, and then compared with a preset voltage threshold value output by the ground alarm circuit through the fifth comparator 1001a and the digital-to-analog converter 9. When the voltage value of the voltage difference exceeds the preset voltage threshold value, the fifth comparator 1001a outputs the preset level, and triggers the test control chip 101 to perform abnormal alarm processing.

[0077] A sixth comparator 1001b (comparator in the over-temperature alarm link) is arranged in the over-temperature alarm link. A first input end of the sixth comparator 1001b is connected with an over-temperature protection circuit of the power supply module 3, a digital-to-analog converter 9 is connected with a second input end of the sixth comparator 1001b, and an output end of the sixth comparator 1001b is connected with the test control chip 101 through the matrix alarm circuit 4. The sixth comparator 1001b is used for outputting a preset level when a voltage value at the first input end of the sixth comparator 1001b is greater than a voltage value at the second input end of the sixth comparator 1001b. If the power supply module 3 is abnormal, a serious heating phenomenon may occur, and thus the chip test circuit may be damaged. Therefore, the over-temperature protection circuit can be arranged in the power supply module 3. When the temperature of the power supply module 3 rises, a voltage of the over-temperature protection circuit rises. When the voltage exceeds a preset voltage threshold value output by the over-temperature alarm circuit through the digital-to-analog converter 11, the sixth comparator 1001b outputs the preset level, and triggers the test control chip 101 to perform abnormal alarm processing.

[0078] In a possible implementation, as shown in FIG. 1, Figure 5As shown, the control module 1 further includes a processor 102 and a controller 103. The processor 102 is connected with the upper computer through a network, for receiving the alarm information sent by the test control chip 101 and sending the alarm information to the upper computer, and for receiving and analyzing the chip test instruction sent by the upper computer and forwarding the chip test instruction to the controller 103, the chip test instruction being used for instructing the power supply voltage corresponding to the chip to be tested. The controller 103 is connected with the front-stage power supply of each power supply module 3, for controlling the front-stage power supply to supply power to each power supply module 3 based on the chip test instruction. Illustratively, the controller 103 can adopt a microcontroller unit (MCU), a system on chip (SOC), a microprocessor unit (MPU) or the like, and the embodiment of the present disclosure is described by taking the MCU as an example. The MCU can be responsible for the power health management monitoring of the whole resource board card, and monitor whether the voltage of all secondary power supplies of the resource board card is normal when the resource board card is working. In addition, the MCU is also responsible for the power-on timing control of the secondary power supply of the resource board card and the front-stage power supply enable control of the power supply module 3. The MCU can supply power to one of the power supply modules 3 or all of the power supply modules 3 by controlling the front-stage power supply enable of the power supply module 3.

[0079] The first alarm module 2 and the second alarm module 10 in the chip test circuit provided by the embodiment of the present disclosure can realize multiple types of abnormality detection and alarm. Among them, the open circuit is usually caused by the fuse blowing, and an over charge safety device (OSD) is usually arranged in the circuit. When the power supply is overcharged, the voltage generated by the power supply can cause the OSD to trigger an internal short circuit, and a large instantaneous current is generated to blow the fuse, thereby cutting off the loop inside the power supply and realizing safety protection. For open circuit alarm, the related art mainly uses the ohm scale of a multimeter to measure the link impedance, judges whether there is an open circuit according to the impedance value, or enables the internal 1V voltage source in the FAULT register through the OLSx bit, and judges whether the load open circuit occurs according to the state of the OUTx bit in the OUT register. However, the first method has low efficiency and high cost. The factory uses the multimeter to confirm whether the power supply path is open or not by manpower, and can only be used when the resource board card is powered off. Moreover, the number of resource board cards is large, and it is difficult to quickly realize the open circuit detection of the power supply path of all resource board cards. The second method has a complex circuit structure, needs to be combined with multiple circuit elements, and has a slow response speed of abnormality alarm.

[0080] The chip test circuit provided by the embodiment of the present disclosure takes the test control chip 101 as a control core, takes the ADC as a voltage value measuring device, and realizes the open circuit alarm detection function in combination with the amplifier, the comparator and the matrix alarm circuit 4. The test control chip 101 is responsible for driving the power-on and power-off of each power supply module 3 and the power-off of the power supply module 3 corresponding to the target detection link for voltage anomaly, and can judge the abnormal channel and the abnormal type to generate alarm information.

[0081] Compared with the traditional open circuit detection circuit, the chip test circuit provided by the embodiment of the present disclosure has the following advantages:

[0082] 1. High efficiency and fast abnormal response speed

[0083] The chip test circuit provided by the embodiment of the present disclosure connects the output end of the second amplifier 201f to the input end of the fourth comparator 201d, and monitors the voltage difference between the first link 5 and the second link 6 through the fourth comparator. If the voltage difference is abnormal, the fourth comparator 201d will immediately output a preset level (for example, a low level). The preset level of the fourth comparator 201d is connected to the input end of the matrix alarm circuit 4, so the corresponding output in the matrix alarm circuit 4 also immediately becomes a preset level. The test control chip 101 scans the output of the matrix alarm circuit 4 at each port. Once the test control chip 101 detects that the level of a certain link judgment pin and a certain type judgment pin changes from a normal level to a preset level, the test control chip 101 will immediately take a power-off strategy to control the timing power-off of the corresponding power supply module 3 and the target detection link, and generate alarm information based on the determined power supply channel and abnormal alarm type. Because the test control chip 101 is a logic device that can realize software control parallel processing, if multiple target detection links have power supply anomalies, the test control chip 101 can simultaneously control the timing power-off of all abnormal target detection links and power supply modules 3, and light the alarm lamp.

[0084] 2. Low circuit complexity

[0085] The chip test circuit provided by the embodiment of the present disclosure is combined by using an amplifier, a comparator and a matrix alarm circuit 4, and the output end of the comparator is connected to the input end of the matrix alarm circuit 4. The test control chip 101 can quickly capture the target detection link that occurs abnormally by scanning the levels of the judgment pins of each link, and can quickly determine the abnormal alarm type by scanning the levels of the judgment pins of each type, and quickly control the corresponding power module 3 to sequentially power down. Compared with using multiple MCUs to realize the monitoring function, the chip test circuit provided by the embodiment of the present disclosure uses the test control chip 101 and the matrix alarm circuit 4 to replace the MCU to detect the alarm, which is simpler and more efficient, and reduces the complexity of the circuit design. Using multiple MCUs for monitoring not only requires communication between each MCU, but also needs to upload abnormal data to the processor 102 for response, and the software design process is very complex, and each MCU also needs to design a peripheral circuit, which makes the hardware design of the circuit more complex.

[0086] 3. Lower chip test cost

[0087] As the second point described above, the chip test circuit provided by the embodiment of the present disclosure uses the test control chip 101 and the matrix alarm circuit 4 to replace the MCU to realize the alarm voltage detection of the power supply channel, which greatly reduces the design cost of the resource board, and also reduces the risk of software misjudgment by using hardware and gates, increases the detection reliability, and the response speed of the hardware is faster than the scanning detection reaction speed of the software. Therefore, the chip test circuit provided by the embodiment of the present disclosure can better protect the chip under test.

[0088] 4. Alarm information can be saved completely and is convenient for analysis

[0089] The chip test circuit provided by the embodiment of the present disclosure adopts the architecture of test control chip 101+processor 102+controller 103, wherein the controller 103 is responsible for health management monitoring of all power supplies of the resource board card, and can detect whether the power supply voltage is abnormal by polling scanning. The test control chip 101 detects the target detection link and the abnormal type that occurs abnormal alarm by scanning the high and low levels of each port. When the target detection link occurs power supply abnormal alarm, the controller 103 can record the voltage values of all power supplies of the resource board card at present, the test control chip 101 records the alarm information, and sends the alarm information to the processor 102 for saving and reporting, which is convenient for subsequent further analysis and processing.

[0090] In a possible implementation manner, as shown in Figure 6 The first link 5 and the second link 6 are connected with at least one chip under test through the gold finger connector 12. In addition, other types of plug-in connectors, patch connectors, fixed connectors and the like can also be used to connect the resource board card and the BIB board.

[0091] Figure 7 A first link 5 is shown, in which a first relay switch 502 is arranged in the first link 5, the first relay switch 502 is connected with the gold finger connector 12, the test control chip 101 is used to control the opening and closing state of each switch channel in the first relay switch 502, and different switch channels of the first relay switch 502 are used to connect different chips to be tested. Illustratively, the first relay switch 502 can adopt a mechanical relay switch. A large number of chips to be tested are usually arranged in the BIB board, and one or more chips to be tested can be selected and powered by switching the first relay switch 502.

[0092] Figure 8 A second link 6 is shown. The second link 6 is arranged with a second relay switch 601 and an analog switch 602; the second relay switch 601 is connected with the gold finger connector 12, the processor 102 is used to control the opening and closing state of each switch channel in the second relay switch 601, and different switch channels of the second relay switch 601 are used to connect different chips to be tested; the analog switch 602 is connected with at least one power module 3, the test control chip 101 is used to control the opening and closing state of the analog switch 602 to select and feed back the voltage of the chip to be tested for detection, and to adjust the output voltage of the at least one power module 3 according to the measured detection feedback voltage value. Illustratively, the second relay switch 601 can adopt an optical coupling relay switch. The second link 6 can feed back the voltage of the chip to be tested to the power module 3, so that the power module 3 can adjust the output voltage to maintain the stability of the output voltage. Optionally, an op-amp link 603 and an instrument amplifier link 604 can be arranged in the second link 6 to amplify the remote sense voltage, so that the power module 3 can accurately read the voltage value.

[0093] The embodiments of the present disclosure further provide a chip test board card (such as a resource board card shown in the figure), in which the chip test circuit provided by each of the above embodiments is arranged. Figure 1 The embodiments of the present disclosure further provide a chip test board card (such as a resource board card shown in the figure), in which the chip test circuit provided by each of the above embodiments is arranged.

[0094] The above describes the basic principles of the present disclosure in combination with specific embodiments, but it should be pointed out that the advantages, advantages, effects and the like mentioned in the present disclosure are only examples and are not limited, and these advantages, advantages, effects and the like cannot be considered as the must-have of each embodiment of the present disclosure. In addition, the above specific details are only for the purpose of example and for the purpose of understanding, and are not limited to the above specific details, and the present disclosure does not limit the must-use of the above specific details to realize.

[0095] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. Parts that are the same, similar, or corresponding between the embodiments can be mutually referred to. The above describes the basic principles of the disclosure in combination with specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in the disclosure are only examples and are not limiting. The advantages, benefits, and effects cannot be considered as necessary for each embodiment of the disclosure. In addition, the specific details of the above disclosure are only for the purpose of example and understanding, and are not limiting. The above details do not limit the disclosure to the specific details.

[0096] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. Parts that are the same or similar between the embodiments can be mutually referred to.

[0097] The block diagrams of the devices, apparatuses, equipment, and systems involved in the disclosure are only illustrative examples and are not intended to require or imply the connection, arrangement, and configuration shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "include", "contain", "have", and the like are open-ended words that mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0098] The devices and equipment of the disclosure can be implemented in many ways. For example, the devices and equipment of the disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware.

[0099] It should also be noted that in the devices and equipment of the disclosure, each component or step can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of the disclosure.

[0100] The above description of the disclosed aspects is provided so that any person skilled in the art can make or use the disclosure. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Therefore, the disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0101] The foregoing description has been presented for the purposes of illustration and description. Furthermore, the description is not intended to limit the embodiments of the disclosure to the forms disclosed herein. Although the various example aspects and embodiments have been described herein with regard to particular aspects and embodiments, those skilled in the art will recognize that certain modifications, changes, substitutions, additions and sub-combinations can be made without departing from the spirit of the disclosure.

Claims

1. A chip test circuit, characterized by comprising: The test device comprises a control module, a first alarm module, a matrix alarm circuit and at least one power supply module, the control module comprises a test control chip, and the first alarm module comprises at least one first alarm link; The power supply module is connected with the power supply end of the pin of the corresponding to-be-tested chip through the first link and is connected with the detection end of the pin of the corresponding to-be-tested chip through the second link, and the power supply module is used for supplying power to the to-be-tested chip; The input end of the first alarm link is connected with a target detection link, the output end of the first alarm link is connected with the test control chip through the matrix alarm circuit, the first alarm link is used for comparing the voltage value of the target detection link with a preset voltage threshold, and when the relationship between the voltage value of the target detection link and the preset voltage threshold meets a preset alarm condition, the first alarm link sends a preset level to the matrix alarm circuit, and the target detection link comprises at least one of the first link and the second link; The test control chip is connected with the power supply module, is used for determining a target detection link with voltage abnormality through the matrix alarm circuit when the preset level is received, and controls the power supply module corresponding to the target detection link with voltage abnormality to be powered off and to generate alarm information, wherein when the preset level sent by at least two first alarm links is received, the test control chip is used for controlling the power supply modules corresponding to the target detection links connected with the at least two first alarm links to be powered off in parallel.

2. The circuit of claim 1, wherein, A comparator is arranged in the first alarm link, the input end of the comparator comprises a first input end and a second input end, the first input end is connected with at least one of the first link and the second link, and the second input end is connected with a digital-to-analog converter, and the digital-to-analog converter is used for outputting a voltage according to the preset voltage threshold; The output end of the comparator is connected with the matrix alarm circuit, and the comparator is used for outputting the preset level when the relationship between the voltage value of the first input end and the voltage value of the second input end meets the preset alarm condition.

3. The circuit of claim 1, wherein, A power sampling resistor is arranged in the first link, each first alarm link comprises at least one first alarm sublink, the first alarm sublink comprises at least one of an overcurrent alarm link, an overvoltage alarm link, an undervoltage alarm link and an open circuit alarm link, and a comparator is arranged in the first alarm sublink; The output end of the comparator of each first alarm sublink is connected with the test control chip through the matrix alarm circuit; In the matrix alarm circuit, each first alarm sublink corresponds to at least two diode branches, the at least two diode branches comprise alarm channel diode branches and alarm type diode branches, the alarm channel diode branches are used for connecting the output end of the comparator and the link judgment pin of the test control chip, different first alarm links correspond to different link judgment pins, the alarm type diode branches are used for connecting the output end of the comparator and the type judgment pin of the test control chip, and different alarm type first alarm sublinks correspond to different type judgment pins. The test control chip is used for determining a target detection link of the voltage abnormality based on receiving the preset level of the link judgment pin, and determining an alarm type based on receiving the preset level of the type judgment pin.

4. The circuit of claim 3, wherein, The over-current alarm link is provided with a first amplifier and a first comparator, two input ends of the first amplifier are connected with two ends of the power sampling resistor respectively, an output end of the first amplifier is connected with a first input end of the first comparator, and the first amplifier is used for amplifying the voltage of the power sampling resistor; A first input end of a second comparator in the over-voltage alarm link is connected with the second link; A first input end of a third comparator in the under-voltage alarm link is connected with the second link; The open-circuit alarm link is provided with a second amplifier and a fourth comparator, two input ends of the second amplifier are connected with the second link and the first link respectively, an output end of the second amplifier is connected with a first input end of the fourth comparator, and the second amplifier is used for amplifying the voltage difference between the second link and the first link.

5. The circuit of claim 2, wherein, The to-be-tested chip is arranged in an aging test board, and the circuit further comprises a second alarm module, the second alarm module comprises a second alarm link, and the second alarm link comprises at least one of a ground alarm link and an over-temperature alarm link; The ground alarm link is provided with a third amplifier and a fifth comparator, two input ends of the third amplifier are connected with a ground circuit of the chip test circuit and a ground circuit of the aging test board respectively, an output end of the third amplifier is connected with a first input end of the fifth comparator, the digital-analog converter is connected with a second input end of the fifth comparator, an output end of the fifth comparator is connected with the test control chip through the matrix alarm circuit, the third amplifier is used for amplifying a ground voltage difference of the chip test circuit and the aging test board, and the fifth comparator is used for outputting the preset level when a voltage value of the first input end of the fifth comparator is greater than a voltage value of the second input end of the fifth comparator. The over-temperature alarm link is provided with a sixth comparator, a first input end of the sixth comparator is connected with an over-temperature protection circuit of the power module, the digital-analog converter is connected with a second input end of the sixth comparator, an output end of the sixth comparator is connected with the test control chip through the matrix alarm circuit, and the sixth comparator is used for outputting the preset level when a voltage value of the first input end of the sixth comparator is greater than a voltage value of the second input end of the sixth comparator.

6. The circuit according to any one of claims 1 to 5, characterized in that The control module further comprises a processor and a controller; The processor is used for receiving the alarm information sent by the test control chip, and sending the alarm information to an upper computer; The processor is further used for receiving and analyzing a chip test instruction sent by the upper computer, and forwarding the chip test instruction to the controller, and the chip test instruction is used for indicating a corresponding power supply voltage of a to-be-tested chip. The control module further comprises a processor and a controller; The processor is used for receiving the alarm information sent by the test control chip, and sending the alarm information to an upper computer; The processor is further used for receiving and analyzing a chip test instruction sent by the upper computer, and forwarding the chip test instruction to the controller, and the chip test instruction is used for indicating a corresponding power supply voltage of a to-be-tested chip. The controller is connected with a front-stage power supply of the power module, and is configured to control the front-stage power supply to supply power to the power module based on the chip test instruction.

7. The circuit of claim 6, wherein, The first link and the second link are connected with at least one chip to be tested through a golden finger connector.

8. The circuit of claim 7, wherein, The first link is provided with a first relay switch connected with the golden finger connector, and the test control chip is configured to control the opening and closing states of each switch channel of the first relay switch, and different switch channels of the first relay switch are configured to connect different chips to be tested.

9. The circuit of claim 7, wherein, The second link is provided with a second relay switch and an analog switch. The second relay switch is connected with the golden finger connector, and the processor is configured to control the opening and closing states of each switch channel of the second relay switch, and different switch channels of the second relay switch are configured to connect different chips to be tested. The analog switch is connected with the at least one power module, and the test control chip is configured to control the opening and closing states of the analog switch to select a chip to be tested for feedback voltage measurement, and adjust the output voltage of the at least one power module according to the measured feedback voltage value.

10. A chip test board card, characterized by, The chip test board card is deployed with the chip test circuit according to any one of claims 1 to 9.

Images