Reset circuit

Abstract

The utility model belongs to the related technical field of BMS hardware key expansion circuit technology, and particularly relates to a reset circuit. A trigger circuit is arranged on a reset circuit and comprises a trigger module, a first trigger circuit and a second trigger circuit, the trigger module is connected with the first trigger circuit and the second trigger circuit, the trigger module is used for receiving an external trigger action and outputting a trigger signal, and a delay circuit and a first switch circuit are arranged for delayed on-off, the first trigger circuit is connected with the timing end of the controlled module so as to detect the rising edge of the trigger signal and achieve software reset. Hardware resetting is performed through the first trigger circuit, and software resetting of the second trigger circuit is set at the same time, so that a hardware resetting circuit is added on the basis of original software resetting of the circuit, and software jamming is avoided. And resetting can be realized only by unpacking.

Description

Technical Field

[0001] This technology belongs to the technical field of BMS hardware button expansion circuit technology, and in particular relates to a reset circuit. Background Technology

[0002] A Battery Management System (BMS) is a lithium battery management system used in backup batteries for communication base stations and home energy storage. During operation, the BMS may freeze or become stuck. Typically, a reset button is provided on the BMS to reset it.

[0003] In existing BMS reset button technology, the main approach is based on MCU software reset / sleep / wake-up. When the I / O port detects a signal and determines that a software reset / sleep / wake-up is needed, the program automatically runs the corresponding software to fulfill the requirement. However, if the program freezes, the BMS will be unable to perform a software reset. In this case, the battery pack must be removed and a power-off restart performed to restore the BMS to normal operation. This issue significantly increases the difficulty of BMS maintenance and operation. Utility Model Content

[0004] To address the aforementioned issues, this invention proposes a reset circuit that incorporates both hardware and software reset methods, enabling the BMS to have two distinct reset approaches. This avoids the need to disassemble and power off the battery pack to reset it when the software freezes, thus preventing increased maintenance and upkeep difficulties for the BMS.

[0005] The objective of this utility model is achieved through the following technical solution:

[0006] In a first aspect, this utility model proposes a reset circuit, comprising:

[0007] The trigger circuit includes a trigger module, a first trigger circuit, and a second trigger circuit. The trigger module is connected to the first trigger circuit and the second trigger circuit, and the trigger module is used to receive external trigger actions and output trigger signals.

[0008] The delay circuit is connected to the output of the second trigger circuit and is used to delay the output of the trigger signal from the trigger circuit.

[0009] And a first switching circuit, connected to the output of the delay circuit, is used to convert the trigger signal output by the delay circuit into a reset signal, and output the reset signal to the reset terminal of the controlled module to realize hardware reset;

[0010] The first trigger circuit is connected to the timing terminal of the controlled module to detect the rising edge of the trigger signal and perform a software reset.

[0011] A trigger circuit is incorporated into the reset circuit, comprising a trigger module, a first trigger circuit, and a second trigger circuit. The trigger module is connected to both the first and second trigger circuits and receives external trigger actions, outputting a trigger signal. A delay circuit and a first switching circuit are used for delayed on / off switching. The first trigger circuit is connected to the timing terminal of the controlled module to detect the rising edge of the trigger signal and implement a software reset. Hardware reset is achieved through the first trigger circuit, while software reset is implemented through the second trigger circuit. This adds a hardware reset circuit to the existing software reset, preventing software freezes. Unpacking is required to perform the reset.

[0012] In some implementations, the trigger module is provided with a second switch circuit and a third switch circuit. The second switch circuit is connected within the first trigger circuit to switch the first trigger circuit on and off; the third switch circuit is connected within the second trigger circuit to switch the second trigger circuit on and off.

[0013] By setting a second switch circuit and a third switch circuit in the trigger circuit, the reset circuit can control the on / off state of the first trigger circuit and the second trigger circuit respectively, so as to select software reset or hardware reset.

[0014] In some implementations, the trigger module is a trigger chip, which is equipped with a trigger button, and the triggering action is pressing the trigger button;

[0015] The trigger chip is equipped with a first pin and a second pin. When the trigger button is pressed, the first switching circuit is turned on through the first pin and the second pin, and turned off otherwise.

[0016] The trigger chip is also equipped with a third pin and a fourth pin. The second switching circuit is turned on when the trigger button is pressed, and turned off when the button is pressed.

[0017] By using a trigger module as a trigger chip, the external trigger action can be detected when the trigger button of the trigger chip is pressed, thereby realizing an external active reset.

[0018] In some implementations, the first trigger circuit is provided with a reset trigger terminal and a first power input terminal. The reset trigger terminal is connected to the timing terminal of the controlled module, and the first power input terminal is supplied with voltage from an external power source and is connected to the reset trigger terminal.

[0019] The second switching circuit is located between the first power input terminal and the reset trigger terminal. Alternatively, the first pin of the second switching circuit is connected to the first power input terminal, and the second pin is grounded, so as to realize the voltage change of the timing terminal of the controlled module.

[0020] The first trigger circuit is equipped with a reset trigger terminal. After receiving a signal from the software terminal, the reset circuit will perform a software reset through the first trigger circuit, and detect the rising edge of the signal of the trigger module and the trigger time of the trigger chip to determine the reset mode. The first switch circuit pulls down the input of the timing terminal. When the switch is released, the rising edge can be detected to determine the reset signal.

[0021] In some implementations, the first trigger circuit includes a first resistor, a second resistor, and a first capacitor;

[0022] One end of the first resistor is connected to the first power input terminal, and the other end of the first resistor is connected to the first pin, one end of the first capacitor, and one end of the second resistor. The other end of the second resistor is connected to the reset trigger terminal and the timing terminal of the controlled module. The other end of the first capacitor and the second pin are grounded.

[0023] In some implementations, the second trigger circuit is provided with a second power input terminal and a second power output terminal, the third switch circuit is provided between the second power input terminal and the second power output terminal, the third pin is connected to the second power input terminal, the fourth pin is connected to the second power output terminal, and the second power input terminal is connected to an external power supply.

[0024] By setting a second trigger circuit, the second switch circuit is turned on when the trigger chip is pressed, and the second trigger circuit outputs a high-level signal.

[0025] In some implementations, the second trigger circuit includes a third resistor and a fourth resistor. One end of the third resistor is connected to the second power input terminal, and the other end of the third resistor is connected to the third pin. One end of the fourth resistor is connected to the fourth pin, and the other end of the fourth resistor is the output terminal of the second trigger circuit.

[0026] In some implementations, the delay circuit includes a comparator circuit and a buffer circuit; the comparator circuit is provided with a first comparison terminal and a second comparison terminal; the first comparison terminal is connected to a reference voltage source.

[0027] The input terminal of the buffer circuit is connected to the output terminal of the second trigger circuit, the output terminal of the buffer circuit is connected to the input terminal of the comparator circuit, and the output terminal of the buffer circuit is connected to the second comparison terminal of the comparator circuit; the output terminal of the second trigger circuit is the output terminal of the comparator circuit.

[0028] By setting a delay circuit, the signal can be buffered and delayed by a buffer circuit. After a certain buffering time, it is input to the comparison circuit for comparison. After a certain time, the second comparison terminal input is greater than the first comparison terminal of the reference, thereby outputting a trigger signal through the output terminal of the output comparison circuit.

[0029] In some implementations, the comparator circuit includes a comparator, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a second capacitor, and a third capacitor; the buffer circuit includes a fourth capacitor and a fifth capacitor.

[0030] The fourth and fifth capacitors are located between the ground terminal and the negative terminal of the comparator; the fifth resistor and the second capacitor are connected between the positive terminal of the comparator and the ground terminal; the sixth resistor is connected between the reference voltage source and the positive terminal of the comparator; the seventh and eighth resistors are connected in series and in parallel between the reference voltage source and the output terminal of the comparator; one end of the third capacitor is connected between the seventh and eighth resistors, and the other end of the third capacitor is grounded.

[0031] By using a capacitor to buffer and delay the trigger signal, accidental triggering can be avoided, as well as reset failure caused by signal instability.

[0032] In some embodiments, the first switching circuit includes: a first MOSFET, a second MOSFET, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a fourth capacitor, and a diode;

[0033] The first MOSFET is a PMOS transistor, and the second MOSFET is an NMOS transistor. The gate of the first MOSFET is connected to the output of the comparator. The source of the first MOSFET is connected between the seventh and eighth resistors. The drain of the first MOSFET is connected to one end of the ninth resistor. The other end of the ninth resistor is connected to the gate of the second MOSFET. The source of the second MOSFET is grounded. The tenth resistor is connected between the gate and source of the second MOSFET. The drain of the second MOSFET is connected to one end of the twelfth resistor. The other end of the twelfth resistor is connected to the reset terminal of the controlled module. The drain of the second MOSFET is also connected to one end of the eleventh resistor. The other end of the eleventh resistor is connected to the third power input terminal. One end of the diode is connected to the drain of the second MOSFET. The positive terminal of the diode is connected to the drain of the second MOSFET. The negative terminal of the diode is connected to the third power input terminal. The sixth capacitor is connected between the drain of the second MOSFET and the ground terminal.

[0034] By designing a MOSFET switching circuit, after receiving the trigger signal from the delay circuit, the first switching circuit is turned on, which grounds the reset terminal of the controlled module, so that the reset terminal receives a reset signal.

[0035] The beneficial effects of the reset circuit of this utility model are:

[0036] A trigger circuit is incorporated into the reset circuit, comprising a trigger module, a first trigger circuit, and a second trigger circuit. The trigger module is connected to both the first and second trigger circuits and receives external trigger actions, outputting a trigger signal. A delay circuit and a first switching circuit are used for delayed on / off switching. The first trigger circuit is connected to the timing terminal of the controlled module to detect the rising edge of the trigger signal and implement a software reset. Hardware reset is achieved through the first trigger circuit, while software reset is implemented through the second trigger circuit. This adds a hardware reset circuit to the existing software reset, preventing software freezes. Unpacking is required to perform the reset. Attached Figure Description

[0037] Figure 1 This is a framework diagram of a reset circuit according to the present invention;

[0038] Figure 2 This invention provides a framework for a reset circuit. Figure 2 ;

[0039] Figure 3 This is a circuit diagram of a reset circuit according to the present invention.

[0040] Figure label:

[0041] R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; R12, twelfth resistor;

[0042] C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor;

[0043] D1, diode;

[0044] Q1, first MOSFET; Q2, second MOSFET;

[0045] U1, trigger chip; U2, comparator;

[0046] VCC1, first power input terminal; DELAY, reset trigger terminal; VCC2, reference voltage source; PC1, timing terminal of the controlled module; VCC3, third power input terminal; RESET, reset terminal of the controlled module;

[0047] MCU, controlled module; 21, trigger module; 211, second switch circuit; 212, third switch circuit; 22, first trigger circuit; 23, second trigger circuit; 3, first switch circuit; 4, delay circuit. Detailed Implementation

[0048] The preferred embodiments of this application will now be described in detail with reference to the accompanying drawings, so that the advantages and features of this application can be more easily understood by those skilled in the art, thereby providing a clearer definition of the scope of protection of this application.

[0049] Please refer to the diagrams, where the same component symbols represent the same components. The principles of this application are illustrated by way of example implementation in a suitable computing environment. The following description is based on the specific embodiments of this application exemplified, and should not be construed as limiting other specific embodiments not detailed herein.

[0050] As used herein, the term "module" can refer to a software or hardware object that executes on the computing system. The various components, modules, engines, and services described herein can be implementations on the computing system. The apparatuses and methods described herein can be implemented in software or hardware, both of which are within the scope of this application.

[0051] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0052] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0053] Example 1:

[0054] like Figure 1 As shown, this embodiment proposes a reset circuit, which includes:

[0055] The triggering circuit includes a triggering module 21, a first triggering circuit 22, and a second triggering circuit 23. The triggering module 21 is connected to the first triggering circuit 22 and the second triggering circuit 23, and the triggering module 21 is used to receive external triggering actions and output triggering signals.

[0056] The delay circuit 4 is connected to the output terminal of the second trigger circuit 23 and is used to delay the output of the trigger signal from the trigger circuit.

[0057] And the first switching circuit 3, which is connected to the output terminal of the delay circuit 4, is used to convert the trigger signal output by the delay circuit 4 into a reset signal, and output the reset signal to the reset terminal RESET of the controlled module MCU to realize hardware reset;

[0058] The first trigger circuit 22 is connected to the timing terminal PC1 of the controlled module MCU to detect the rising edge of the trigger signal and realize software reset.

[0059] Specifically, a trigger circuit is provided, which includes a trigger module 21 to receive external trigger actions and output trigger signals. The trigger module 21 can be a pressing component, such as a button, switch, etc., or a sensor module, such as an infrared sensor, temperature sensor, etc. It can also be a relay; after receiving an external trigger action, the relay turns off and outputs a trigger signal. A first trigger circuit 22 and a second trigger circuit 23 are provided to implement software reset and hardware reset, respectively. The reset method can be selected by signal selection, such as judging software reset and hardware reset by signal high / low level, by switch selection, or by meeting certain conditions in the circuit. For example, if multiple trigger actions and signals are detected, it can be determined that the software trigger has failed, and hardware triggering can be selected. Furthermore, during hardware triggering, a delay circuit 4 is provided to delay the trigger signal, avoiding abnormal resets caused by accidental hardware touches. The delay circuit 4 can use capacitor delay, chip delay, or delay-on / off methods. The reset terminal is usually in a low-level state. Therefore, a first switch circuit 3 can be set in the delay circuit 4. The first switch circuit 3 is used to pull the RESET signal of the controlled module MCU low, so as to turn the trigger circuit into a low-level reset signal. Furthermore, a pull-up power supply can be set at the RESET terminal of the controlled module MCU so that the RESET terminal of the controlled module MCU is high when it is in normal operation and not in the reset state.

[0060] More specifically, the controlled module MCU can be the MCU of the BMS, and the RESET terminal of the controlled module MCU is the reset terminal of the MCU.

[0061] A trigger circuit is incorporated into the reset circuit, comprising a trigger module 21, a first trigger circuit 22, and a second trigger circuit 23. The trigger module 21 is connected to both the first and second trigger circuits 22 and 23. The trigger module 21 receives external trigger actions and outputs a trigger signal. A delay circuit 4 and a first switch circuit 3 are used for delayed on / off switching. The first trigger circuit 22 is connected to the timing terminal PC1 of the controlled module MCU to detect the rising edge of the trigger signal and implement a software reset. Hardware reset is achieved through the first trigger circuit 22, while software reset is implemented through the second trigger circuit 23. This adds a hardware reset circuit to the existing software reset, preventing software freezes. Unpacking is required to perform the reset.

[0062] Example 2:

[0063] like Figures 2-3 As shown, this embodiment further optimizes and explains the circuit structure proposed in Example 1:

[0064] In some embodiments, the trigger module 21 is provided with a second switch circuit 211 and a third switch circuit 212. The second switch circuit 211 is connected within the first trigger circuit 22 to switch the first trigger circuit 22 on and off. The third switch circuit 212 is connected within the second trigger circuit 23 to switch the second trigger circuit 23 on and off.

[0065] Specifically, the trigger module 21 is equipped with a second switch circuit 211 and a third switch circuit 212 to respectively enable the first trigger circuit 22 to be switched on and off and the second trigger circuit 23 to be switched on and off. This allows the trigger module 21 to output the trigger signal normally by switching the second switch circuit 211 and the third switch circuit 212 after issuing the trigger signal.

[0066] Furthermore, the second switch circuit 211 and the third switch circuit 212 can be simultaneously controlled by the trigger module 21 to achieve simultaneous switching of the first trigger circuit 22 and the second trigger circuit 23. However, to distinguish between hardware reset and software reset, an additional trigger signal can be set in the first trigger circuit 22 so that when the additional trigger signal is triggered, the trigger signal can only flow normally to the timing terminal PC1 of the controlled module MCU after receiving the additional trigger signal. At the same time, the additional trigger signal can disable the RESET terminal of the controlled module MCU, avoiding the problem of reset failure caused by the simultaneous occurrence of two reset signals.

[0067] By setting a second switch circuit 211 and a third switch circuit 212 in the trigger circuit, the reset circuit can control the on / off state of the first trigger circuit 22 and the second trigger circuit 23 respectively, so as to select software reset or hardware reset.

[0068] In some embodiments, the trigger module 21 is a trigger chip U1, which is equipped with a trigger button, and the triggering action is pressing the trigger button.

[0069] The trigger chip U1 is equipped with a first pin and a second pin. When the trigger button is pressed, the first switch circuit 3 is turned on through the first pin and the second pin, and turned off otherwise.

[0070] The trigger chip U1 is also equipped with a third pin and a fourth pin. The second switch circuit 211 is turned on when the trigger button is pressed, and turned off when the trigger button is pressed.

[0071] Specifically, the trigger module 21 can be a trigger chip U1. The trigger chip U1 is equipped with a trigger button so that pressing it will close the first switch circuit 3 and the second switch circuit 211, thereby outputting trigger signals through the first trigger circuit 22 and the second trigger circuit 23. When the trigger chip U1 is pressed, it will turn on the first and second pins, as well as the third and fourth pins, to enable the normal operation of the first trigger circuit 22 and the second trigger circuit 23.

[0072] The trigger module 21 is used as the trigger chip U1 so that when the trigger button of the trigger chip U1 is pressed, the external trigger action can be detected, and an external active reset can be achieved.

[0073] In some embodiments, the first trigger circuit 22 is provided with a reset trigger terminal DELAY and a first power input terminal VCC1. The reset trigger terminal DELAY is connected to the timing terminal PC1 of the controlled module MCU, and the first power input terminal VCC1 is supplied with voltage from an external power source and is connected to the reset trigger terminal DELAY.

[0074] The second switch circuit 211 is set between the first power input terminal VCC1 and the reset trigger terminal DELAY. Alternatively, the first pin of the second switch circuit 211 is connected to the first power input terminal VCC1, and the second pin is grounded, so as to realize the voltage change of the timing terminal PC1 of the controlled module MCU.

[0075] Specifically, a reset trigger pin DELAY is provided. DELAY serves as an additional trigger signal for software reset, allowing the method of triggering the reset to be determined via this pin. Simultaneously, when DELAY is triggered, it activates the timing pin PC1 of the controlled module MCU, which is connected to the first trigger signal, enabling a software reset. Conversely, when DELAY is not triggered, the reset pin RESET of the controlled module MCU is activated, enabling a hardware reset. A first power input pin VCC1 is provided and connected to an external power supply, typically 3.3V. VCC1 keeps the controlled module MCU at a high level under normal conditions. After triggering, when the second switch circuit 211 is turned on, the potential of the timing pin PC1 of the controlled module MCU is pulled low, and timing begins. After the trigger module 21 is released, the timing terminal PC1 of the controlled module MCU returns to a high potential, thereby detecting the existence of a rising edge of the level signal and recording the rising edge and its duration. Based on the duration, the reset mode is selected, such as reset / sleep / wake-up function. More specifically, the reset function is 1 second, the sleep function is 2 seconds, and the wake-up function is 3 seconds.

[0076] The first trigger circuit 22 is equipped with a reset trigger terminal DELAY. After receiving a signal from the software terminal, the reset circuit will perform a software reset through the first trigger circuit 22, and detect the rising edge of the signal of the trigger module 21 and the trigger time of the trigger chip U1 to determine the reset mode. The first switch circuit 3 pulls down the input of the timing terminal. When it is released, the rising edge can be detected to determine the reset signal.

[0077] In some embodiments, the first trigger circuit 22 includes a first resistor R1, a second resistor R2, and a first capacitor C1;

[0078] One end of the first resistor R1 is connected to the first power input terminal VCC1, and the other end of the first resistor R1 is connected to the first pin, one end of the first capacitor C1, and one end of the second resistor R2. The other end of the second resistor R2 is connected to the reset trigger terminal DELAY and the timing terminal PC1 of the controlled module MCU. The other end of the first capacitor C1 and the second pin are grounded.

[0079] Specifically, the first resistor R1 is a 1K 0603 stainless steel resistor, and the second resistor R2 is a 10K 0603 stainless steel resistor. The first capacitor C1 is a 0.1uF 0603 stainless steel capacitor. The first resistor R1 can be used as a voltage divider resistor, or it can be combined with the first capacitor C1 to form a filter circuit to filter the signal. The second resistor R2 can be used as a pull-up resistor to divide the 3.3V voltage.

[0080] In some embodiments, the second trigger circuit 23 is provided with a second power input terminal and a second power output terminal, and the third switch circuit 212 is provided between the second power input terminal and the second power output terminal. The third pin is connected to the second power input terminal, the fourth pin is connected to the second power output terminal, and the second power input terminal is connected to an external power source.

[0081] Specifically, the second trigger circuit 23 outputs a high-level signal to the second power output terminal through the second power input terminal. The second trigger circuit 23 is generally connected to 3.3V to control the switching of subsequent switching circuits. The third switch circuit 212 blocks or connects the trigger signal from the second power input terminal to the second power output terminal, so that a high-level signal can be output from the second power input terminal to the second power output terminal only when the trigger module 21 is pressed.

[0082] The first power input terminal VCC1 and the second power input terminal can be the same, both being 3.3V, or they can be the same port for power input.

[0083] By setting the second trigger circuit 23, the second switch circuit 211 is turned on when the trigger chip U1 is pressed, and the second trigger circuit 23 outputs a high-level signal.

[0084] In some embodiments, the second trigger circuit 23 includes a third resistor R3 and a fourth resistor R4. One end of the third resistor R3 is connected to the second power input terminal, and the other end of the third resistor R3 is connected to the third pin. One end of the fourth resistor R4 is connected to the fourth pin, and the other end of the fourth resistor R4 is the output terminal of the second trigger circuit 23.

[0085] Specifically, the third resistor R3 can be a 220K resistor of 0603, the fourth resistor R4 can be a 1K resistor of 0603, and the third resistor R3 can be a voltage divider resistor.

[0086] In some embodiments, the delay circuit 4 includes a comparator circuit and a buffer circuit; the comparator circuit is provided with a first comparison terminal and a second comparison terminal; the first comparison terminal is connected to a reference voltage source VCC2;

[0087] The input terminal of the buffer circuit is connected to the output terminal of the second trigger circuit 23, the output terminal of the buffer circuit is connected to the input terminal of the comparator circuit, and the output terminal of the buffer circuit is connected to the second comparison terminal of the comparator circuit; the output terminal of the second trigger circuit 23 is the output terminal of the comparator circuit.

[0088] Specifically, the delay circuit 4 includes a comparator circuit and a buffer circuit. The comparator circuit has a first comparison terminal and a second comparison terminal. After being buffered for a certain period of time by the buffer circuit, the output is sent to the comparator circuit for comparison to avoid abnormal reset caused by accidental touch. The output of the second trigger circuit 23, after passing through the comparator circuit and meeting the output voltage requirement, outputs a high level at the output of the comparator circuit, thereby triggering the subsequent first switch circuit 3.

[0089] By setting the delay circuit 4, the signal can be buffered and delayed by the buffer circuit. After a certain buffering time, it is input to the comparison circuit for comparison. After a certain time, the second comparison terminal input is greater than the first comparison terminal of the reference, and thus the trigger signal is output through the output terminal of the output comparison circuit.

[0090] In some embodiments, the comparison circuit includes a comparator U2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, and a third capacitor C3; the buffer circuit includes a fourth capacitor C4 and a fifth capacitor C5.

[0091] The fourth capacitor C4 and the fifth capacitor C5 are placed between the ground terminal and the negative terminal of comparator U2; the fifth resistor R5 and the second capacitor C2 are connected between the positive terminal of comparator U2 and the ground terminal; the sixth resistor R6 is connected between the reference voltage source VCC2 and the positive terminal of comparator U2; the seventh resistor R7 and the eighth resistor R8 are connected in series and connected between the reference voltage source VCC2 and the output terminal of comparator U2; one end of the third capacitor C3 is connected between the seventh resistor R7 and the eighth resistor R8, and the other end of the third capacitor C3 is grounded.

[0092] More specifically, the fourth capacitor C4 and the fifth capacitor C5 are 10uF 0603 capacitors, the fifth resistor R5 is a 510K 0603 resistor, the sixth resistor R6 is a 100K 0603 resistor, the seventh resistor R7 is a 10K 0603 resistor, and the eighth resistor R8 is a 100K 0603 resistor. Comparator U2 is an LTC331YT5 comparator, the second capacitor C2 is a 0.1uF 0603 capacitor, and the third capacitor C3 is a 0.1uF 0603 capacitor. The fourth capacitor C4 and the fifth capacitor C5 can both be delay capacitors to delay the input of comparator U2. The voltage can only be continuously output to comparator U2 after the fourth capacitor C4 and the fifth capacitor C5 have fully charged. The other capacitors, such as the second capacitor C2 and the third capacitor C3, are conventional filter capacitors. The fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are also voltage divider filter resistors.

[0093] By using a capacitor to buffer and delay the trigger signal, accidental triggering can be avoided, as well as reset failure caused by signal instability.

[0094] In some embodiments, the first switching circuit 3 includes: a first MOSFET Q1, a second MOSFET Q2, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth capacitor, and a diode D1.

[0095] The first MOSFET Q1 is a PMOS transistor, and the second MOSFET Q2 is an NMOS transistor. The gate of the first MOSFET Q1 is connected to the output of comparator U2. The source of the first MOSFET Q1 is connected between the seventh resistor R7 and the eighth resistor R8. The drain of the first MOSFET Q1 is connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the gate of the second MOSFET Q2. The source of the second MOSFET Q2 is grounded. The tenth resistor R10 is connected between the gate and source of the second MOSFET Q2. The drain of the second MOSFET Q2 is connected to... Connect one end of the twelfth resistor R12, and connect the other end of the twelfth resistor R12 to the reset terminal RESET of the controlled module MCU. The drain of the second MOSFET Q2 is also connected to one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 is connected to the third power input terminal VCC3. One end of the diode D1 is connected to the drain of the second MOSFET Q2, the positive terminal of the diode D1 is connected to the drain of the second MOSFET Q2, and the negative terminal of the diode D1 is connected to the third power input terminal VCC3. The sixth capacitor is connected between the drain of the second MOSFET Q2 and the ground terminal.

[0096] Specifically, the first MOSFET Q1 can be a MEBSS84, the second MOSFET Q2 can be an ME2N7002E, the ninth resistor R9 can be a 1K resistor from a 0603 capacitor, the tenth resistor R10 can be a 1M resistor from a 0603 capacitor, the eleventh resistor R11 can be a 10K resistor from a 0603 capacitor, the twelfth resistor R12 can be a 1K resistor from a 0603 capacitor, the diode D1 can be a 1SS355, and the sixth capacitor can be a 0.1uF capacitor from a 0603 capacitor. The ninth resistor R9, the eighth resistor R8, the tenth resistor R10, the eleventh resistor R11, and the twelfth resistor R12 are all voltage divider filter resistors. The fourth capacitor C4 is a filter capacitor.

[0097] By designing a MOSFET switching circuit, after receiving the trigger signal from the delay circuit 4, the first switching circuit 3 is turned on, which grounds the RESET terminal of the controlled module MCU, so that the reset terminal receives a reset signal.

[0098] Example 3:

[0099] This embodiment, based on the reset circuit proposed in Embodiments 1 and 2, proposes a specific implementation method in BMS, specifically including: a minimum system of MCU with BMS, the MCU being STM32F103VCT6B, the first trigger circuit 22 of the reset circuit being connected to any of the PC1~PC3 interfaces of the MCU to realize software reset, and the first switch circuit 3 being connected to the NRST port to realize hardware reset.

[0100] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A reset circuit, characterized by comprising: The application relates to a trigger circuit, which comprises a trigger module (21), a first trigger circuit (22) and a second trigger circuit (23), the trigger module (21) is connected with the first trigger circuit (22) and the second trigger circuit (23), and the trigger module (21) is used for receiving an external trigger action and outputting a trigger signal; a delay circuit (4) is connected with an output end of the second trigger circuit (23) and is used for delaying the trigger signal output by the trigger circuit; and a first switch circuit (3) is connected with an output end of the delay circuit (4) and is used for converting the trigger signal output by the delay circuit (4) into a reset signal and outputting the reset signal to a reset end (RESET) of a controlled module (MCU) to realize hardware reset; wherein the first trigger circuit (22) is connected with a timing end (PC1) of the controlled module (MCU) to detect the rising edge of the trigger signal and realize software reset. The trigger module (21) is provided with a second switch circuit (211) and a third switch circuit (212), the second switch circuit (211) is connected in the first trigger circuit (22) to switch the first trigger circuit (22) on and off, and the third switch circuit (212) is connected in the second trigger circuit (23) to switch the second trigger circuit (23) on and off. The trigger module (21) is a trigger chip (U1), the trigger chip (U1) is provided with a trigger button, and the trigger action is pressing the trigger button; The trigger chip (U1) is provided with a first pin and a second pin, the first switch circuit (3) is turned on through the first pin and the second pin when the trigger button is pressed, and vice versa; The trigger chip (U1) is further provided with a third pin and a fourth pin, the second switch circuit (211) is turned on through the third pin and the fourth pin when the trigger button is pressed, and vice versa.

2. The reset circuit of claim 1, wherein, The first trigger circuit (22) is provided with a reset trigger end (DELAY) and a first power input end (VCC1), the reset trigger end (DELAY) is connected with the timing end (PC1) of the controlled module (MCU), and the first power input end (VCC1) is inputted with an external power voltage and connected with the reset trigger end (DELAY); 3. The reset circuit of claim 2, wherein, The second switch circuit (211) is arranged between the first power input end (VCC1) and the reset trigger end (DELAY), or the first pin of the second switch circuit (211) is connected on the first power input end (VCC1), and the second pin is grounded to realize voltage change of the timing end (PC1) of the controlled module (MCU). The first trigger circuit (22) comprises a first resistor (R1), a second resistor (R2) and a first capacitor (C1). ​ 4. The reset circuit of claim 3, wherein, ​ ​ 5. The reset circuit of claim 4, wherein, ​ The first resistance (R1) is connected with the first power input end (VCC1) at one end, and is connected with the first pin, the first capacitor (C1) at one end and the second resistance (R2) at one end at the other end, and the other end of the second resistance (R2) is connected with the reset trigger end (DELAY), the timing end (PC1) of the controlled module (MCU), the other end of the first capacitor (C1) and the second pin are grounded.

6. The reset circuit of claim 3, wherein, The second trigger circuit (23) is provided with a second power input end and a second power output end, the third switch circuit (212) is arranged between the second power input end and the second power output end, the third pin is connected with the second power input end, the fourth pin is connected with the second power output end, and the second power input end is connected with an external power supply.

7. The reset circuit of claim 6, wherein, The second trigger circuit (23) comprises a third resistance (R3) and a fourth resistance (R4), one end of the third resistance (R3) is connected with the second power input end, the other end of the third resistance (R3) is connected with the third pin, one end of the fourth resistance (R4) is connected with the fourth pin, and the other end of the fourth resistance (R4) is the output end of the second trigger circuit (23).

8. The reset circuit of claim 1, wherein, The delay circuit (4) comprises a comparison circuit and a buffer circuit, the comparison circuit is provided with a first comparison end and a second comparison end, and the first comparison end is connected with a reference voltage source (VCC2); The input end of the buffer circuit is connected with the output end of the second trigger circuit (23), the output end of the buffer circuit is connected with the input end of the comparison circuit, the output end of the buffer circuit is connected with the second comparison end of the comparison circuit, and the output end of the second trigger circuit (23) is the output end of the comparison circuit.

9. The reset circuit of claim 8, wherein, The comparison circuit comprises a comparator (U2), a fifth resistance (R5), a sixth resistance (R6), a seventh resistance (R7), an eighth resistance (R8), a second capacitor (C2) and a third capacitor (C3), and the buffer circuit comprises a fourth capacitor (C4) and a fifth capacitor. The fourth capacitor (C4), the fifth capacitor and the comparator (U2) are arranged between the ground end and the negative end of the comparator (U2), the fifth resistance (R5) and the second capacitor (C2) are connected between the positive end and the ground end of the comparator (U2), the sixth resistance (R6) is connected between the reference voltage source (VCC2) and the positive end of the comparator (U2), the seventh resistance (R7) and the eighth resistance (R8) are connected in series and connected between the reference voltage source (VCC2) and the output end of the comparator (U2), and one end of the third capacitor (C3) is connected between the seventh resistance (R7) and the eighth resistance (R8), and the other end of the third capacitor (C3) is grounded.

10. The reset circuit of claim 9, wherein, The first switch circuit (3) comprises a first MOS tube (Q1), a second MOS tube (Q2), a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11), a twelfth resistor (R12), a sixth capacitor and a diode (D1); The first MOS tube (Q1) is a PMOS tube, the second MOS tube (Q2) is an NMOS tube, the gate of the first MOS tube (Q1) is connected with the output end of the comparator (U2), the source of the first MOS tube (Q1) is connected between the seventh resistor (R7) and the eighth resistor (R8), the drain of the first MOS tube (Q1) is connected with one end of the ninth resistor (R9), the other end of the ninth resistor (R9) is connected with the gate of the second MOS tube (Q2), the source of the second MOS tube (Q2) is grounded, the tenth resistor (R10) is connected between the gate and the source of the second MOS tube (Q2), the drain of the second MOS tube (Q2) is connected with one end of the twelfth resistor (R12), the other end of the twelfth resistor (R12) is connected with the reset end (RESET) of the controlled module (MCU), the drain of the second MOS tube (Q2) is also connected with one end of the eleventh resistor (R11), the other end of the eleventh resistor (R11) is connected with the third power input end (VCC3), one end of the diode (D1) is connected with the drain of the second MOS tube (Q2), the positive end of the diode (D1) is connected with the drain of the second MOS tube (Q2), and the negative end of the diode (D1) is connected with the third power input end (VCC3), and the sixth capacitor is connected between the drain of the second MOS tube (Q2) and the ground end.

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