Digital sampler circuit

Abstract

According to the digital sampler circuit provided by the embodiment of the invention, the modulation circuit and the correlated double sampling circuit are arranged in the digital sampler circuit, and the modulation circuit is used for switching and connecting the output end and the grounding end of the signal source based on the first pulse signal; the method comprises the following steps of: switching a received level signal between an effective level and a zero level of a signal source, respectively latching the effective level and the zero level by using a correlated double-sampling technology, and outputting a difference value between the effective level and the zero level, so that the effect of deducting error electromotive force from the effective level is realized, and the accuracy of the error electromotive force is improved. The influence of error electromotive force caused by noise signals on the effective level of a signal source is reduced, and the signal-to-noise ratio of the digital sampler circuit is improved, so that the accuracy of a chip test result is improved.

Description

Technical Field

[0001] This disclosure relates to automated testing techniques, and in particular to a digital sampler circuit. Background Technology

[0002] During the testing of chips such as Liquid Crystal Display (LCD) chips and Organic Light-Emitting Diode Display (OLED) chips, the testing machine needs to simultaneously acquire medium-voltage analog test signals from a large number of pins, which requires a digital sampler (Digitizer) function.

[0003] However, during signal sampling, the temperature difference between the tester and the chip under test, the leakage current, the leakage current due to factors such as cable impedance, and the DC bias (offset) of the pre-conditioning circuit will all be superimposed on the output signal of the chip under test as error electromotive force. Moreover, this error electromotive force changes with time, temperature, and other factors. Currently, the digitizer circuit of the tester does not have the function of eliminating the above errors, resulting in inaccurate signal sampling results. Utility Model Content

[0004] This disclosure provides a digital sampler circuit that can improve the signal-to-noise ratio of the digital sampler circuit, thereby improving the accuracy of chip test results.

[0005] One aspect of this disclosure provides a digital sampler circuit, including a modulation circuit and a correlated double sampling circuit;

[0006] At least two input terminals of the modulation circuit are respectively connected to the output terminal of the signal source and the ground terminal of the signal source. The modulation circuit is used to switch the connection relationship between the output terminal of the modulation circuit and the at least two input terminals based on the first pulse signal, so as to alternately receive the effective level and zero level of the signal source.

[0007] The input terminal of the correlation dual sampling circuit is connected to the output terminal of the modulation circuit. The correlation dual sampling circuit is used to sample and latch the zero-point level based on the second pulse signal, and to sample and latch the effective level based on the third pulse signal. The output signal of the correlation dual sampling circuit is the difference between the effective level and the zero-point level.

[0008] Optionally, the associated dual sampling circuit includes a clamping circuit and a sample-and-hold circuit;

[0009] The input terminal of the clamping circuit is connected to the output terminal of the modulation circuit. The clamping circuit is used to sample and latch the zero-point level output by the modulation circuit when the second pulse signal is received, and to transmit the level output by the modulation circuit when the second pulse signal is not received.

[0010] The input terminal of the sample-and-hold circuit is connected to the output terminal of the clamping circuit. The sample-and-hold circuit is used to sample and latch the effective level output by the clamping circuit when the third pulse signal is received.

[0011] Optionally, within one pulse period of the first pulse signal, the clamping circuit receives the second pulse signal once, the sample-and-hold circuit receives the third pulse signal once, and the generation time of the third pulse signal is after the generation time of the first pulse signal, the end time of the third pulse signal is before the end time of the first pulse signal, the generation time of the second pulse signal is after the end time of the first pulse signal, and the end time of the second pulse signal is before the generation time of the next first pulse signal.

[0012] Optionally, the clamping circuit includes a first sampling switch and a first buffer. One end of the first sampling switch is grounded, and the other end of the first sampling switch is connected to a first capacitor in the associated dual sampling circuit. The input terminal of the first buffer is connected to the first capacitor, and the output terminal of the first buffer is connected to the sample-and-hold circuit. The first sampling switch is used to close when the second pulse signal is received and to open when the second pulse signal ends. The first buffer is used to cut off the current when the first sampling switch is closed so that the first capacitor samples and holds the output level of the signal source, and to transmit the output level of the signal source to the sample-and-hold circuit after the first sampling switch is opened.

[0013] The sample-and-hold circuit includes a second sampling switch, a second buffer, and a second capacitor. One end of the second sampling switch is connected to the output terminal of the clamping circuit, and the other end of the second sampling switch is connected to the second buffer and the second capacitor. The second sampling switch is used to close when the third pulse signal is received and to open when the third pulse signal ends. The second buffer is used to cut off the current when the second sampling switch is closed so that the second capacitor samples and holds the output level of the signal source, and to output the difference between the sampling level of the clamping circuit and the sampling level of the first buffer after the second sampling switch is opened.

[0014] Optionally, a third buffer is provided between the signal generator of the first pulse signal and the modulation circuit. The third buffer is used to generate a first driving current when the first pulse signal is received to drive the modulation circuit to switch the connection relationship between the output terminal of the modulation circuit and the at least two input terminals, and to stop generating the first driving current when the first pulse signal ends, so that the modulation circuit switches the connection relationship between the output terminal of the modulation circuit and the at least two input terminals again.

[0015] A fourth buffer is provided between the signal generator of the second pulse signal and the correlated double sampling circuit. The fourth buffer is used to generate a second driving current when the second pulse signal is received to drive the correlated double sampling circuit to sample and latch the zero-point level, and to stop generating the second driving current when the second pulse signal ends, so that the correlated double sampling circuit stops sampling the zero-point level.

[0016] A fifth buffer is provided between the signal generator of the third pulse signal and the correlated double sampling circuit. The fifth buffer is used to generate a third driving current when the third pulse signal is received to drive the correlated double sampling circuit to sample and latch the effective level, and to stop generating the third driving current when the third pulse signal ends, so that the correlated double sampling circuit stops sampling the effective level.

[0017] Optionally, the modulation circuit is provided with a single-pole double-throw switch, and the at least two input terminals of the modulation circuit include the first stationary contact and the second stationary contact of the single-pole double-throw switch.

[0018] The first stationary contact is connected to the output terminal of the signal source, and the second stationary contact is connected to the ground terminal of the signal source. The moving contact of the single-pole double-throw switch is connected to the first stationary contact when it receives the first pulse signal, and is connected to the second stationary contact when the first pulse signal ends.

[0019] Optionally, the modulation circuit includes an amplifier, the input of which is connected to the moving contact of the single-pole double-throw switch, and the output of which is connected to the input of the associated double sampling circuit. The amplifier is used to adjust the amplitude and buffer the received level signal.

[0020] Optionally, the circuit at the signal source end is located in the first isothermal block, and the modulation circuit and the correlated double sampling are located in the second isothermal block.

[0021] Optionally, the output of the correlated dual sampling circuit is connected to the input of a low-pass filter circuit, which is used to smooth the received level signal.

[0022] Optionally, the output of the related dual sampling circuit is connected to the input of the analog-to-digital converter circuit, which is used to encode the received analog signal into a digital signal.

[0023] Based on the embodiments of this disclosure, by setting a modulation circuit and a correlated double sampling circuit in the digital sampler circuit, the modulation circuit switches the output terminal and ground terminal of the signal source based on the first pulse signal, so that the received level signal switches between the effective level and the zero level of the signal source. The correlated double sampling technique is used to latch the effective level and the zero level respectively, and the difference between the effective level and the zero level is output. This achieves the effect of subtracting the error electromotive force from the effective level, reducing the influence of the error electromotive force caused by the noise signal on the effective level of the signal source, improving the signal-to-noise ratio of the digital sampler circuit, and thus improving the accuracy of the chip test results.

[0024] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0025] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0026] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0027] Figure 1 A schematic diagram of the structure of a digital sampler circuit provided in an exemplary embodiment of this disclosure;

[0028] Figure 2 A schematic diagram of the structure of a digital sampler circuit provided for another exemplary embodiment of this disclosure;

[0029] Figure 3 A waveform diagram of a pulse signal provided for an exemplary embodiment of this disclosure;

[0030] Figure 4 A schematic diagram of the structure of a related dual sampling circuit provided in an exemplary embodiment of this disclosure;

[0031] Figure 5 A schematic diagram of the structure of a digital sampler circuit provided for another exemplary embodiment of this disclosure;

[0032] Figure 6 A schematic diagram of the structure of a modulation circuit provided in an exemplary embodiment of this disclosure;

[0033] Figure 7 A schematic diagram of the structure of a digital sampler circuit provided for another exemplary embodiment of this disclosure;

[0034] Figure 8 A schematic diagram of the structure of a digital sampler circuit provided for another exemplary embodiment of this disclosure.

[0035] The attached figures are labeled as follows:

[0036] Signal source-1; Modulation circuit-2; Correlation double sampling circuit-3; First pulse signal generator-4; Second pulse signal generator-5; Third pulse signal generator-6; First isothermal block-7; Second isothermal block-8; Low-pass filter circuit-9; Analog-to-digital converter circuit-10;

[0037] Single-pole double-throw switch-21; Amplifier-22; Clamping circuit-31; Sample and hold circuit-32; First capacitor-33; Third buffer-41; Fourth buffer-51; Fifth buffer-61;

[0038] First stationary contact - 211; Second stationary contact - 212; Moving contact - 213; First sampling switch - 311; First buffer - 312; Second sampling switch - 321; Second buffer - 322; Second capacitor - 323. Detailed Implementation

[0039] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0040] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0041] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0042] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0043] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0044] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0045] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0046] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0047] Technologies and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies and equipment should be considered part of the specification.

[0048] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0049] Figure 1 This is a structural block diagram of a digital sampler circuit provided in an exemplary embodiment of this disclosure. Figure 1 As shown, the digital sampler circuit includes a modulation circuit 2 and a correlated double sampling circuit 3.

[0050] At least two input terminals of the modulation circuit 2 are connected to the output terminal of the signal source 1 and the ground terminal of the signal source 1, respectively. The modulation circuit 2 is used to switch the connection relationship between the output terminal of the modulation circuit 2 and the at least two input terminals based on the first pulse signal, so as to alternately receive the effective level and zero level of the signal source 1.

[0051] Optionally, the modulation circuit 2 can be connected to a pulse signal generator to receive a pulse signal with a preset duty cycle (hereinafter referred to as the first pulse signal) sent by the pulse signal generator. For example, the preset duty cycle can be 50%. When the pulse signal is received, the output terminal of the modulation circuit 2 is connected to the output terminal of the signal source 1. During the period when no pulse signal is received, the output terminal of the modulation circuit 2 is connected to the ground terminal of the signal source 1, so that the duration for which the modulation circuit 2 receives the effective level and the zero-point level of the signal source 1 are the same, so that the subsequent correlation dual sampling circuit 3 can collect the effective level and the zero-point level respectively.

[0052] The input terminal of the correlation dual sampling circuit 3 is connected to the output terminal of the modulation circuit 2. The correlation dual sampling circuit 3 is used to sample and latch the zero-point level based on the second pulse signal, and to sample and latch the effective level based on the third pulse signal. The output signal of the correlation dual sampling circuit 3 is the difference between the effective level and the zero-point level.

[0053] Optionally, the correlated dual sampling circuit 3 can be connected to a pulse signal generator to receive the second and third pulse signals sent by the pulse signal generator. The second and third pulse signals are generated alternately; specifically, the third pulse signal is generated during the generation of the first pulse signal, while the second pulse signal is generated between two adjacent first pulse signals. This ensures that the correlated dual sampling circuit 3 can separately acquire the effective level and zero-point level of the signal source 1. Since noise always exists in the environment of the signal source 1, meaning that both the effective level and the zero-point level are subject to noise interference, the difference between the output effective level and the zero-point level can be used to subtract the error electromotive force caused by noise from the effective level.

[0054] Based on the embodiments of this disclosure, by setting a modulation circuit and a correlated double sampling circuit in the digital sampler circuit, the modulation circuit switches the output terminal and ground terminal of the signal source based on the first pulse signal, so that the received level signal switches between the effective level and the zero level of the signal source. The correlated double sampling technique is used to latch the effective level and the zero level respectively, and the difference between the effective level and the zero level is output. This achieves the effect of subtracting the error electromotive force from the effective level, reducing the influence of the error electromotive force caused by the noise signal on the effective level of the signal source, improving the signal-to-noise ratio of the digital sampler circuit, and thus improving the accuracy of the chip test results.

[0055] In one possible implementation, such as Figure 2 As shown, the related dual sampling circuit 3 includes a clamping circuit 31 and a sample-and-hold circuit 32, which are responsible for sampling and latching the zero-point level and the effective level, respectively.

[0056] The input terminal of the clamping circuit 31 is connected to the output terminal of the modulation circuit 2. The clamping circuit 31 is used to sample and latch the zero-point level output by the modulation circuit 2 when the second pulse signal is received, and to transmit the level output by the modulation circuit when the second pulse signal is not received. By pre-setting parameters such as the period, pulse width, and start time of the first and second pulse signals, the pulse generator sends the second pulse signal to the clamping circuit 31 between two adjacent first pulse signals (i.e., during the period when the modulation circuit 2 does not receive the first pulse signal). At this time, the modulation circuit 2 transmits the zero-point level of the signal source 1, thereby enabling the clamping circuit 31 to sample and hold the zero-point level. When the second pulse signal ends, the clamping circuit 31 stops sampling and holding the input signal and transmits the level signal output by the modulation circuit 2 to the sample-and-hold circuit 32.

[0057] The input of the sample-and-hold circuit 32 is connected to the output of the clamping circuit 31. The sample-and-hold circuit 32 samples and latches the effective level output by the clamping circuit 31 upon receiving the third pulse signal. By pre-setting parameters such as the period, pulse width, and start time of the first and third pulse signals, the pulse generator sends the third pulse signal to the sample-and-hold circuit 32 during the occurrence period of the first pulse signal. At this time, the modulation circuit 2 transmits the effective level of the signal source 1, allowing the sample-and-hold circuit 32 to sample and hold the effective level. After the third pulse signal ends, the sample-and-hold circuit 32 outputs the difference between the sampled level of the sample-and-hold circuit 32 and the sampled level of the clamping circuit 31.

[0058] In one possible implementation, such as Figure 3 As shown, the modulation circuit 2 receives the effective level signal from the signal source 1 under the control of the first pulse signal. The output level signal of the modulation circuit 2 is in phase and frequency with the first pulse signal. Within one pulse period of the first pulse signal (the duration between the start time of one first pulse signal and the start time of the next first pulse signal), the clamping circuit 31 receives a second pulse signal once, and the sample-and-hold circuit 32 receives a third pulse signal once. The generation time of the third pulse signal is after the generation time of the first pulse signal, and the end time of the third pulse signal is before the end time of the first pulse signal. The generation time of the second pulse signal is after the end time of the first pulse signal, and the end time of the second pulse signal is before the generation time of the next first pulse signal. Optionally, considering that the level signal needs a certain buffer time to be transmitted from the signal source 1 to the tester, the pulse width of the second and third pulse signals can be set to be greater than the preset pulse width, based on the above conditions, to ensure that the relevant dual sampling circuit 2 can acquire the values ​​of the zero-point level and the effective level.

[0059] In one possible implementation, such as Figure 4As shown, the clamping circuit 31 includes a first sampling switch 311 and a first buffer 312. One end of the first sampling switch 311 is grounded, and the other end is connected to the first capacitor 33 in the associated dual sampling circuit 3. The input terminal of the first buffer 312 is connected to the first capacitor 33, and the output terminal of the first buffer 312 is connected to the sample-and-hold circuit 32. The first sampling switch 311 is used to close when a second pulse signal is received and to open when the second pulse signal ends. The first buffer 312 is used to cut off the current when the first sampling switch 311 is closed so that the first capacitor 33 samples and holds the output level of the signal source, and to transmit the output level of the signal source 1 to the sample-and-hold circuit 32 after the first sampling switch 311 is opened. In addition, the first capacitor 33 can also provide impedance conversion of the level signal from the signal source 1 terminal to the associated dual sampling circuit 3 terminal, preventing the signal source 1 from being affected by the current or voltage that may be applied by the associated dual sampling circuit 3.

[0060] By controlling parameters such as the period, pulse width, and start time of the first pulse signal and the second pulse signal, during the zero-point level of the output signal source 1 of the modulation circuit 2, the first sampling switch 311 is closed by the second pulse signal. At this time, the first buffer 312 can impede the current, so that the first capacitor 33 is clamped to the signal ground. The charging of the first capacitor 33 realizes the latching of the zero-point level. When the first sampling switch 311 is opened, the level signal output by the modulation circuit 2 can be input to the sample-and-hold circuit 32 through the clamping circuit 31.

[0061] like Figure 4 As shown, the sample-and-hold circuit 32 includes a second sampling switch 321, a second buffer 322, and a second capacitor 323. One end of the second sampling switch 321 is connected to the output terminal of the clamping circuit 31, and the other end is connected to the second buffer 322 and the second capacitor 323. The second sampling switch 321 is used to close when a third pulse signal is received and to open when the third pulse signal ends. The second buffer 322 is used to cut off the current when the second sampling switch 321 is closed so that the second capacitor 323 samples and holds the output level of the signal source 1, and to output the difference between the sampling level of the clamping circuit 31 and the sampling level of the first buffer 322 after the second sampling switch 321 is opened.

[0062] By controlling parameters such as the period, pulse width, and start time of the first and third pulse signals, during the effective level of the output signal source 1 of the modulation circuit 2, the second sampling switch 321 is closed by the third pulse signal. At this time, the first sampling switch 311 is open, and the effective level of the signal source 1 is input to the sample-and-hold circuit 32. The second buffer 322 can impede the current, so that the second capacitor 323 is charged to achieve sampling and holding of the effective level. When the second sampling switch 321 is open, the current output by the signal source 1 no longer flows into the sample-and-hold circuit 32, and the sample-and-hold circuit 32 outputs the difference between the sampling level of the clamping circuit 31 and the sampling level of the first buffer 322.

[0063] In one possible implementation, such as Figure 5 As shown, a third buffer 41 can be provided between the signal generator of the first pulse signal (hereinafter referred to as the first pulse signal generator 4) and the modulation circuit 2. Specifically, a third buffer 41 can be provided between the first pulse signal generator 4 and the switch in the modulation circuit 2. The third buffer 41 is used to generate a first driving current when the first pulse signal is received, so as to drive the modulation circuit 2 to switch the connection relationship between the output terminal of the modulation circuit 2 and at least two input terminals, so that the output terminal of the modulation circuit 2 is connected to the output terminal of the signal source 1, and to stop generating the first driving current when the first pulse signal ends, so that the modulation circuit 2 switches the connection relationship between the output terminal of the modulation circuit and at least two input terminals again, so that the output terminal of the modulation circuit 2 is connected to the ground terminal of the signal source 1.

[0064] A fourth buffer 51 can be provided between the signal generator of the second pulse signal (hereinafter referred to as the second pulse signal generator 5) and the correlated double sampling circuit 3. Specifically, a fourth buffer 51 can be provided between the second pulse signal generator 5 and the first sampling switch 311. The fourth buffer 51 is used to generate a second driving current when the second pulse signal is received to drive the correlated double sampling circuit 3 to sample and latch the zero-point level, and to stop generating the second driving current when the second pulse signal ends, so that the correlated double sampling circuit 3 stops sampling the zero-point level.

[0065] A fifth buffer 61 can be provided between the signal generator of the third pulse signal (hereinafter referred to as the third pulse signal generator 6) and the related dual sampling circuit 3. Specifically, a fifth buffer 61 can be provided between the third pulse signal generator 6 and the second sampling switch 321. The fifth buffer 61 is used to generate a third driving current when the third pulse signal is received to drive the related dual sampling circuit 3 to sample and latch the effective level, and to stop generating the third driving current when the third pulse signal ends, so that the related dual sampling circuit 3 stops sampling the effective level.

[0066] The sampling switch in this embodiment can be any type of single-pole single-throw switch, and the modulation circuit 2 can be any type of single-pole multi-throw switch. However, some types of switches require strong signals for control. If such switches are directly connected to the pulse signal generator, the pulse signal generator needs to generate a strong pulse signal, which can easily interfere with other devices in the digital sampler circuit. Therefore, by setting a buffer between the pulse signal generator and the switch, the pulse signal generated by the pulse signal generator triggers the corresponding buffer to generate a drive current to drive the corresponding switch to switch its state, which can reduce interference with other devices.

[0067] In one possible implementation, such as Figure 6 As shown, the modulation circuit 2 is equipped with a single-pole double-throw switch 21. At least two input terminals of the modulation circuit 2 include a first stationary contact 211 and a second stationary contact 212 of the single-pole double-throw switch 21. The first stationary contact 211 is connected to the output terminal of the signal source 1, and the second stationary contact 212 is connected to the ground terminal of the signal source 1. The moving contact 213 of the single-pole double-throw switch 21 connects to the first stationary contact 211 when it receives a first pulse signal, and connects to the second stationary contact 212 when the first pulse signal ends.

[0068] In one possible implementation, such as Figure 6 As shown, an amplifier 22 can also be included in the modulation circuit. The input terminal of the amplifier 22 is connected to the moving contact 213 of the single-pole double-throw switch 21, and the output terminal of the amplifier 22 is connected to the input terminal of the related dual sampling circuit 3. The amplifier 22 is used to adjust the amplitude and buffer the received level signal. The amplifier 22 can be, for example, a differential amplifier, a three-op-amp instrumentation amplifier, or other types of amplifiers. This embodiment does not limit the type of amplifier 22.

[0069] In one possible implementation, such as Figure 7 As shown, the circuit at the signal source 1 end is located in the first isothermal block 7, and the test machine end circuit, including the modulation circuit 2 and the related dual sampling circuit 3, is located in the second isothermal block 8. By using the first isothermal block 7 and the second isothermal block 8, the temperature difference between each node at the signal source 1 end and each node at the test machine end digital sampling circuit is kept within a preset range. This allows the thermoelectric potential superimposed on the effective level and the zero-point level to be approximately equal, and the difference between the effective level and the zero-point level can be equivalent to subtracting the error electromotive force from the effective level.

[0070] In one possible implementation, such as Figure 8As shown, the output of the correlated dual sampling circuit 3 is connected to the input of the low-pass filter circuit 9, which smooths the received level signal. The low-pass filter circuit 9 can filter out high-frequency noise signals in the level signal. In particular, the noise generated by the frequent switching of the switches in the modulation circuit 2 and the correlated dual sampling circuit 3 can cause glitches in the output level signal. Therefore, the low-pass filter circuit 9 can smooth the sampled level, thereby further improving the signal-to-noise ratio of the channel and thus improving the accuracy of the chip test results.

[0071] In one possible implementation, such as Figure 8 As shown, the output of the related dual sampling circuit 3 can be connected to the input of the analog-to-digital converter circuit 10 through the low-pass filter circuit 9. The analog-to-digital converter circuit 10 is used to encode the received analog signal into a digital signal.

[0072] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0073] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or corresponding parts between embodiments can be referred to interchangeably. The basic principles of this disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of the various embodiments of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the specific details required for its implementation.

[0074] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0075] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0076] The apparatus and device of this disclosure may be implemented in many ways. For example, the apparatus and device of this disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware.

[0077] It should also be noted that in the apparatus and equipment disclosed herein, the components or steps can be disassembled and / or recombined. Such disassembly and / or recombination should be considered as equivalent solutions to this disclosure.

[0078] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0079] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, adjustments, additions, and sub-combinations therein.

Claims

1. A digital sampler circuit, characterized in that, Includes modulation circuitry and correlated double sampling circuitry; At least two input terminals of the modulation circuit are respectively connected to the output terminal of the signal source and the ground terminal of the signal source. The modulation circuit is used to switch the connection relationship between the output terminal of the modulation circuit and the at least two input terminals based on the first pulse signal, so as to alternately receive the effective level and zero level of the signal source. The input terminal of the correlation dual sampling circuit is connected to the output terminal of the modulation circuit. The correlation dual sampling circuit is used to sample and latch the zero-point level based on the second pulse signal, and to sample and latch the effective level based on the third pulse signal. The output signal of the correlation dual sampling circuit is the difference between the effective level and the zero-point level.

2. The digital sampler circuit according to claim 1, characterized in that, The relevant dual sampling circuit includes a clamping circuit and a sample-and-hold circuit; The input terminal of the clamping circuit is connected to the output terminal of the modulation circuit. The clamping circuit is used to sample and latch the zero-point level output by the modulation circuit when the second pulse signal is received, and to transmit the level output by the modulation circuit when the second pulse signal is not received. The input terminal of the sample-and-hold circuit is connected to the output terminal of the clamping circuit. The sample-and-hold circuit is used to sample and latch the effective level output by the clamping circuit when the third pulse signal is received.

3. The digital sampler circuit according to claim 2, characterized in that, Within one pulse period of the first pulse signal, the clamping circuit receives the second pulse signal once, and the sample-and-hold circuit receives the third pulse signal once. The generation time of the third pulse signal is after the generation time of the first pulse signal, and the end time of the third pulse signal is before the end time of the first pulse signal. The generation time of the second pulse signal is after the end time of the first pulse signal, and the end time of the second pulse signal is before the generation time of the next first pulse signal.

4. The digital sampler circuit according to claim 2, characterized in that, The clamping circuit includes a first sampling switch and a first buffer. One end of the first sampling switch is grounded, and the other end is connected to a first capacitor in the associated dual sampling circuit. The input terminal of the first buffer is connected to the first capacitor, and the output terminal of the first buffer is connected to the sample-and-hold circuit. The first sampling switch is used to close when the second pulse signal is received and to open when the second pulse signal ends. The first buffer is used to cut off the current when the first sampling switch is closed so that the first capacitor samples and holds the output level of the signal source, and to transmit the output level of the signal source to the sample-and-hold circuit after the first sampling switch is opened. The sample-and-hold circuit includes a second sampling switch, a second buffer, and a second capacitor. One end of the second sampling switch is connected to the output terminal of the clamping circuit, and the other end of the second sampling switch is connected to the second buffer and the second capacitor. The second sampling switch is used to close when the third pulse signal is received and to open when the third pulse signal ends. The second buffer is used to cut off the current when the second sampling switch is closed so that the second capacitor samples and holds the output level of the signal source, and to output the difference between the sampling level of the clamping circuit and the sampling level of the first buffer after the second sampling switch is opened.

5. The digital sampler circuit according to any one of claims 1 to 4, characterized in that, A third buffer is provided between the signal generator of the first pulse signal and the modulation circuit. The third buffer is used to generate a first driving current when the first pulse signal is received, so as to drive the modulation circuit to switch the connection relationship between the output terminal of the modulation circuit and the at least two input terminals, and to stop generating the first driving current when the first pulse signal ends, so that the modulation circuit switches the connection relationship between the output terminal of the modulation circuit and the at least two input terminals again. A fourth buffer is provided between the signal generator of the second pulse signal and the correlated double sampling circuit. The fourth buffer is used to generate a second driving current when the second pulse signal is received to drive the correlated double sampling circuit to sample and latch the zero-point level, and to stop generating the second driving current when the second pulse signal ends, so that the correlated double sampling circuit stops sampling the zero-point level. A fifth buffer is provided between the signal generator of the third pulse signal and the correlated double sampling circuit. The fifth buffer is used to generate a third driving current when the third pulse signal is received to drive the correlated double sampling circuit to sample and latch the effective level, and to stop generating the third driving current when the third pulse signal ends, so that the correlated double sampling circuit stops sampling the effective level.

6. The digital sampler circuit according to any one of claims 1 to 4, characterized in that, The modulation circuit is provided with a single-pole double-throw switch, and the at least two input terminals of the modulation circuit include the first stationary contact and the second stationary contact of the single-pole double-throw switch. The first stationary contact is connected to the output terminal of the signal source, and the second stationary contact is connected to the ground terminal of the signal source. The moving contact of the single-pole double-throw switch is connected to the first stationary contact when it receives the first pulse signal, and is connected to the second stationary contact when the first pulse signal ends.

7. The digital sampler circuit according to claim 6, characterized in that, The modulation circuit includes an amplifier. The input of the amplifier is connected to the moving contact of the single-pole double-throw switch, and the output of the amplifier is connected to the input of the related double sampling circuit. The amplifier is used to adjust the amplitude and buffer the received level signal.

8. The digital sampler circuit according to any one of claims 1 to 4, characterized in that, The circuit at the signal source end is located in the first isothermal block, and the modulation circuit and the related dual sampling circuit are located in the second isothermal block.

9. The digital sampler circuit according to any one of claims 1 to 4, characterized in that, The output of the related dual sampling circuit is connected to the input of the low-pass filter circuit, which is used to smooth the received level signal.

10. The digital sampler circuit according to any one of claims 1 to 4, characterized in that, The output of the related dual sampling circuit is connected to the input of the analog-to-digital converter circuit, which encodes the received analog signal into a digital signal.

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