Semiconductor device

Abstract

Embodiments of the disclosure provide a semiconductor device. The semiconductor device includes a circuit and a first bitcell array. The circuit is coupled to a first power rail and a second power rail. The first bitcell array includes a first subarray having a plurality of first bitcells coupled between the first power rail and the second power rail. In response to a first operating voltage on the first power rail and a second operating voltage on the second power rail, the first bitcells are configured as a decoupling capacitor between the first power rail and the second power rail.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a semiconductor device that provides a decoupling capacitor. Background Technology

[0002] Circuits similar to those used in high-bandwidth memory and high-speed computing power transmission networks require large decoupling capacitors to reduce power supply spiking and ground bounce. With the increasing density and shrinking size of recently designed integrated circuits, the performance and efficiency required for decoupling capacitors have also increased accordingly. For example, higher capacitance per unit area, fewer front-end devices, lower leakage current, and less back-end metal are needed. Utility Model Content

[0003] In some embodiments, a semiconductor device is provided, including a circuit and a first element cell array. The circuit is coupled to a first power rail and a second power rail. The first element cell array includes a first subarray. The first subarray has a plurality of first element cells coupled between the first power rail and the second power rail. In response to a first operating voltage on the first power rail and a second operating voltage on the second power rail, these first element cells are configured as decoupling capacitors between the first power rail and the second power rail of the circuit.

[0004] In some embodiments, a semiconductor device is provided, including circuitry and a first element cell array. The circuitry operates using a first supply voltage and a second supply voltage on a first power rail and a second power rail, respectively. The first element cell array includes a plurality of first element cells arranged in a plurality of rows and a plurality of columns. Each row is coupled to one of a plurality of local bit connections and a plurality of local substrate connections. The first bit connections of the first element cell array are coupled between the first element cells and the first power rail. The first substrate connections of the first element cell array are coupled between the first element cells and the second power rail. The local bit connections are coupled to the first bit connections, and the local substrate connections are coupled to the first substrate connections. Each of the first element cells includes a capacitor. The first element cells are configured as decoupling capacitors for a circuit between the first power rail and the second power rail.

[0005] In some embodiments, a semiconductor device is provided, including a circuit and a first element cell array. The circuit is coupled to a first power rail and a second power rail. The first element cell array includes a first subarray and a second subarray. The first subarray has a plurality of first element cells coupled between the first power rail and the second power rail. In response to a first operating voltage on the first power rail and a second operating voltage on the second power rail, these first element cells are configured as decoupling capacitors between the first and second power rails of the circuit. The second subarray is configured as a memory array for storing data. Attached Figure Description

[0006] When with attachment Figure 1 When reading this document, the best understanding of the embodiments disclosed herein is based on the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for ease of discussion, the dimensions of the various features can be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0008] Figure 2 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figure 1 The semiconductor device shown;

[0009] Figure 3 According to some embodiments of this disclosure Figures 1 to 2 A schematic diagram of a bit cell array in a semiconductor device shown;

[0010] Figure 4 According to some embodiments of this disclosure Figures 1 to 2 A schematic diagram of a bit cell array in a semiconductor device shown;

[0011] Figure 5 and Figure 6 According to some embodiments of this disclosure Figure 4 A schematic diagram of the subarrays in the bit cell array shown;

[0012] Figure 7 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figure 1 The semiconductor device shown Figure 2 The semiconductor device shown;

[0013] Figure 8 According to some embodiments of this disclosure Figure 7 A schematic diagram of a cross-sectional view of the semiconductor device shown;

[0014] Figure 9 According to some embodiments of this disclosure Figures 7 to 8 A schematic diagram of a portion of the semiconductor device shown;

[0015] Figure 10 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figure 7 The semiconductor device shown;

[0016] Figure 11 According to some embodiments of this disclosure Figure 10A schematic diagram of a cross-sectional view of the semiconductor device shown;

[0017] Figure 12 According to some embodiments of this disclosure Figure 10 A schematic diagram of a portion of the semiconductor device shown;

[0018] Figure 13 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figure 7 The semiconductor device shown;

[0019] Figure 14 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figure 10 The semiconductor device shown;

[0020] Figure 15 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figures 7 to 14 The semiconductor device shown;

[0021] Figures 16A to 16B This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figures 1 to 15 The semiconductor device shown;

[0022] Figure 17A and Figure 17B This is an exemplary timing diagram of the voltage signal of a semiconductor device during test operation according to some embodiments of this disclosure;

[0023] Figure 18 This is a schematic diagram of a bit cell according to some embodiments of the present disclosure, which corresponds to Figures 1 to 15 The bit unit in the semiconductor device shown;

[0024] Figure 19 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figures 1 to 15 , Figures 16A to 16B and Figures 17A to 17B The semiconductor device shown;

[0025] Figure 20A and Figure 20B This is an exemplary timing diagram of the voltage signal of a semiconductor device during test operation according to some embodiments of this disclosure;

[0026] Figure 21 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 and Figures 20A to 20B The semiconductor device shown;

[0027] Figure 22A and Figure 22B According to some embodiments of this disclosure Figure 21 A schematic diagram of a portion of the semiconductor device shown;

[0028] Figure 23 This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure, which corresponds to Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 , Figures 20A to 20B , Figure 21 and Figures 22A to 22B The semiconductor device shown;

[0029] Figure 24 For operation according to some embodiments Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 , Figures 20A to 20B , Figure 21 , Figures 22A to 22B and Figure 23 A flowchart of a method for a semiconductor device is shown.

[0030] [Symbol Explanation]

[0031] 100: Semiconductor device

[0032] 101: Capacitor

[0033] 102: Transistor

[0034] 110: Bit cell array

[0035] 110a: Bit cell array

[0036] 110b: Bit cell array

[0037] 120: Circuit

[0038] 130: Control circuit

[0039] 140: Character Wiring Driver Circuit

[0040] 150: Power control circuit

[0041] 200: Semiconductor devices

[0042] 300: Semiconductor device

[0043] 301-303: Connections

[0044] 400: Semiconductor device

[0045] 401-403: Connections

[0046] 500: Semiconductor device

[0047] 600: Semiconductor device

[0048] 700: Semiconductor device

[0049] 800: Semiconductor device

[0050] 900: Semiconductor device

[0051] 1000: Semiconductor device

[0052] 1001: Floor

[0053] 1100: Semiconductor device

[0054] 1200: Method

[0055] 1201~1204: Operation

[0056] AA' : line

[0057] BB' : line

[0058] BC: Bit unit

[0059] BC': Bit unit

[0060] BL: Bit Wiring

[0061] BL1~BLn: Bit wiring

[0062] BLi: Bit Wiring

[0063] BLi1: Bit Wiring

[0064] BLM: Bit Wiring

[0065] BLM1: Bit Wiring

[0066] BLMi: Bit Wiring

[0067] CL: Block capacitor

[0068] CP: Comparator

[0069] CS10: Control signal

[0070] CSi: Signal

[0071] L1: Layer

[0072] L2: Layer

[0073] LBL: Local Bit Wiring

[0074] LPL: Local board wiring

[0075] MCSi: Signal

[0076] MPSi: Switch

[0077] MUX: Multiplexer

[0078] PL: Baseboard wiring

[0079] PL1~PLn: Board wiring

[0080] PLi: Substrate Wiring

[0081] PLi1: Substrate wiring

[0082] PLi3: Bit Wiring

[0083] PSi: Switch

[0084] R1: Electric rail

[0085] R2: Electric rail

[0086] S1: Top side

[0087] S2: Bottom side

[0088] SB: Subarray

[0089] SBi: Subarray

[0090] SBi1: Subarray

[0091] SBi2: Subarray

[0092] SBi3: Subarray

[0093] SBM: Subarray

[0094] SH: signal

[0095] Si: Switch

[0096] TR: Transistor

[0097] VBLi: Signal

[0098] VDD: Supply voltage

[0099] VDDIO: Supply voltage

[0100] VEi: Signal

[0101] VH: Voltage

[0102] VL: Voltage

[0103] VNEG: Negative voltage

[0104] VPLi: Signal

[0105] VR: Voltage

[0106] VR1: Signal

[0107] VSS: Reference Voltage

[0108] VWL: Voltage

[0109] WL: Character Wiring

[0110] WL1~WLk: Character wiring

[0111] WLM: Character Wiring

[0112] WLM1: Character Wiring

[0113] WLMi: Character Wiring Detailed Implementation

[0114] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify embodiments of this disclosure. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0115] For ease of description, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” “upper,” and the like, are used herein to describe the relationship of one element or feature to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used herein will be interpreted accordingly.

[0116] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which they are used. The use of examples in this specification, including instances of any term discussed herein, is illustrative only and is in no way intended to limit the scope or meaning of the embodiments disclosed herein or any exemplary terminology. Similarly, the embodiments disclosed herein are not limited to the various embodiments given in this specification.

[0117] Although the terms “first,” “second,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0118] First refer to Figure 1 . Figure 1 This is a schematic diagram of a semiconductor device 100 according to some embodiments of the present disclosure. For illustration, the semiconductor device 100 includes a bit cell array 110, circuitry 120, control circuitry 130, and power rails R1 and R2. The bit cell array 110 includes a plurality of bit connections BL (including bit connections BL1 to BLn), a plurality of substrate connections PL (including substrate connections PL1 to PLn), and a plurality of word connections WL (including word connections WL1 to WLk). In some embodiments, the bit cell array 110 is coupled to the power rails R1 and R2 via the bit connections BL and the substrate connections PL, respectively. The circuitry 120 is coupled to the power rails R1 and R2. According to some embodiments of the present disclosure, the circuitry 120 operates using a supply (operating) voltage provided by the power rails R1 and R2. In some embodiments, the circuitry 120 includes a charge pump, a digital low drop-out (LDO) regulator, or any circuitry that requires decoupling capacitors during operation. In some embodiments, the bit cell array 110 provides decoupling capacitors for the circuitry 120. In some embodiments, control circuitry 130 is coupled to word line WL and power rails R1 and R2. Control circuitry 130 controls the voltage on word line WL and power rails R1 and R2. In some embodiments, control circuitry 130 includes word line driver circuitry 140 for controlling the voltage on word line WL. In some embodiments, control circuitry 130 includes power control circuitry 150 for controlling the voltage on power rails R1 and R2.

[0119] In some embodiments, the bit cell array 110 is a memory array. In some embodiments, the bit cell array 110 is a back-end (back-end process) memory array. In some embodiments, the bit cell array 110 is a dynamic random-access memory (DRAM) array. In some embodiments, the bit cell array 110 is a back-end DRAM array.

[0120] like Figure 1 As shown, in some embodiments, circuitry 120 is disposed in layer L1, and bit cell array 110 is disposed in layer L2. According to various embodiments of this disclosure, layers L1 and L2 are different from each other and separated from each other in the Z direction. For example, in some embodiments, layer L1 includes a metal layer different from the metal layer included in layer L2. In some embodiments, layer L1 corresponds to a back-end layer, and layer L2 corresponds to a front-end (front-end process) layer.

[0121] In some embodiments, the control circuitry 130 is disposed in layer L1. In some embodiments, the bit cell array 110 and the circuitry 120 are located in the same wafer, and the control circuitry 130 is excluded from or partially excluded from the wafer.

[0122] Provided for illustrative purposes Figure 1 The configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, the bit cell array 110 is located below the circuit 120 along the Z direction.

[0123] For reference Figure 2 . Figure 2 For some embodiments according to this disclosure, corresponding to Figure 1 A schematic diagram of semiconductor device 200 of semiconductor device 100 shown. Relative to Figure 1 The embodiments are provided for ease of understanding. Figure 2 Similar elements are denoted by the same reference numerals. For the sake of brevity, specific operations of similar elements already discussed in detail in the preceding paragraphs have been omitted herein. In some embodiments, semiconductor device 200 is relative to, for example... Figure 1 The semiconductor device 100 is configured.

[0124] To illustrate, such as Figure 2 As shown, the bit cell array 110 and circuit 120 are configured in the same layer in some embodiments. For example, the bit cell array 110 and circuit 120 are configured in layer L1. In some embodiments, the bit cell array 110 and circuit 120 are configured in a front-end layer. In some embodiments, the bit cell array 110 and circuit 120 are configured in a back-end layer.

[0125] Provided for illustrative purposes Figure 2 The configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, power rails R1 and / or R2 are above / below layer L1 along direction Z.

[0126] For reference Figure 3 . Figure 3 According to some embodiments of this disclosure Figures 1 to 2 A schematic diagram of the bit cell array 110 in the semiconductor devices 100 to 200 shown.

[0127] To illustrate, Figure 3 The bit cell array 110 further includes a plurality of bit cells BC configured in rows and columns. Each bit cell BC is coupled to one of the bit lines BL (e.g., bit line BLi), one of the word lines WL (e.g., word line WLi), and one of the substrate lines PL (e.g., substrate line PLi). In some embodiments, bit cells BC in a row are coupled to the same word line WL, and bit cells BC in a column are coupled to the same bit line BL.

[0128] The bit cell array 110 operates as a decoupling capacitor by providing a decoupling capacitor to the circuit 120 through a bit connection BL coupled to the power rail R1 and a substrate connection PL coupled to the power rail R2.

[0129] In some embodiments, bit unit BC includes a DRAM unit. In some embodiments, bit unit BC is a back-end DRAM unit. Figure 3 As shown, the bit cell BC includes a capacitor 101 and a transistor 102. The capacitor 101 is coupled between a substrate connection (e.g., substrate connection PLi) and the source / drain terminals of the transistor 102. The drain / source terminals of the transistor 102 are coupled to a bit connection (e.g., bit connection BLi). The control terminal (gate terminal) of the transistor 102 is coupled to a word connection (e.g., word connection WLi). In some embodiments, the transistor 102 is a thin-film transistor. In some embodiments, the transistor 102 is an n-type transistor. In some embodiments, the transistor 102 is a p-type transistor.

[0130] Provided for illustrative purposes Figure 3 The configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, the bit cell array 110 includes more than... Figure 3 The bit cell BC shown has more / fewer bit cells BC.

[0131] For reference Figure 4 . Figure 4 According to some embodiments of this disclosure Figures 1 to 2A schematic diagram of the bit cell array 110 in the semiconductor devices 100 to 200 shown.

[0132] In some embodiments, Figure 4 The bit cell array 110 is relative to, for example Figure 3 The bit cell array 110 is configured. Figure 4 The bit cell array 110 and Figure 3 The difference between the element arrays 110 is that Figure 3 The bit cell array 110 includes one or more subarrays SB containing multiple bit cells BC. Bit cells BC in the same subarray SB are coupled to the same bit connection BL (e.g., bit connection BLi), the same word connection WL (e.g., word connection WLi), and the same substrate connection PL (e.g., substrate connection PLi). In some embodiments, the same bit connection BL of the subarray SB is coupled to power rail R1, and the same substrate connection PL of the subarray SB is coupled to power rail R2; and the subarray SB provides decoupling capacitance between power rails R1 and R2 for circuit 120.

[0133] like Figure 4 As shown, the capacitor 101 of each bit cell BC in the subarray SB is coupled between the same substrate connection (e.g., substrate connection PLi) and the source / drain terminals of the corresponding transistor 102. The drain / source terminals of the transistor 102 of each bit cell BC in the subarray SB are coupled to the same bit connection (e.g., bit connection BLi). The control terminal (gate terminal) of the transistor 102 of each bit cell BC in the subarray SB is coupled to a unified word connection (e.g., word connection WLi).

[0134] In some embodiments, the bit cells BC in the subarray SB are arranged in columns and rows. The capacitors 101 of the bit cells BC in the same row are coupled to the same local substrate wiring LPL. The drain / source terminals of the transistors 102 of the bit cells BC in the same row are coupled to the same local bit wiring LBL. The control terminals (gate terminals) of the transistors 102 of the bit cells BC in the same column are coupled to the same local word wiring.

[0135] In some embodiments, a local substrate connection LPL is coupled to the same substrate connection PL of a subarray SB. In some embodiments, a local bit connection LBL is coupled to the same bit connection BL of a subarray SB. In some embodiments, a local word connection LWL is coupled to the same word connection W of a subarray SB. In some embodiments, the same substrate connection PL of a subarray SB extends along a first direction (e.g., direction X), and the local substrate connection LPL of the subarray SB extends along a second direction perpendicular to the first direction (e.g., direction Y). Similarly, in some embodiments, the same bit connection BL of a subarray SB extends along a first direction (e.g., direction X), and the local bit connection LBL of the subarray SB extends along a second direction perpendicular to the first direction (e.g., direction Y). In some embodiments, the local word connection LWL of a subarray SB extends along a first direction (e.g., direction X), and the same word connection WL of the subarray SB extends along a second direction perpendicular to the first direction (e.g., direction Y). (Given for illustrative purposes) Figure 4 The configuration. Various implementations are all within the scope of this disclosure. For example, in some embodiments, the subarray SB includes a larger... Figure 3 The bit cells BC shown have more / fewer bit cells BC. In some embodiments, the bit cell array 110 includes multiple subarrays SB with different numbers of bit cells BC.

[0136] For reference Figure 5 and Figure 6 . Figure 5 and Figure 6 According to some embodiments of this disclosure Figure 4 A schematic diagram of the subarray SB in the bit cell array 110 shown.

[0137] Figure 5 and Figure 6 exhibit Figure 4 The equivalent circuit of the circuit shown is illustrated. For simplicity, Figure 5 and Figure 6 The block capacitor CL in the middle is Figure 4 The equivalent capacitor of all capacitors 101 in the subarray SB. Figure 5 and Figure 6 The transistor TR in the subarray SB is the equivalent transistor of all transistors 102 in the subarray SB.

[0138] exist Figure 5 In the embodiment, power rails R1 and R2 ( Figure 5(Not shown) Voltages VL and VH are transmitted respectively. Accordingly, a substrate connection (e.g., substrate connection PLi) coupled to the subarray SB is given a voltage VH. A bit connection (e.g., bit connection BLi) coupled to the subarray SB is given a voltage VL. A word connection (e.g., word connection WLi) coupled to the subarray SB is given a voltage VWL. In some embodiments, voltage VH is higher than voltage VL. Voltage VWL is the word connection voltage used to select bit cell BC (i.e., turn on transistor 102 in bit cell BC). In some embodiments, voltage VH corresponds to the supply voltage VDD (e.g., 1 volt) or supply voltage VDDIO of semiconductor device 100, and voltage VL corresponds to the reference voltage VSS of semiconductor device 100. In some embodiments, the reference voltage VSS is ground voltage (0 volts). In another embodiment, voltage VH is the reference voltage VSS, and voltage VL is a negative voltage VNEG. For example, according to some embodiments, voltage VH is 0 volts, voltage VL is about -0.5 volts, and voltage VWL is 0 or about 1 volt.

[0139] Instead of Figure 5 In the embodiments, power rails R1 and R2 transmit voltages VL and VH respectively. Figure 6 In the embodiment, power rails R1 and R2 ( Figure 6 (Not shown in the text) respectively transmit voltages VH and VL. Accordingly, in Figure 6 In one embodiment, a voltage VL is applied to a substrate wiring (e.g., substrate wiring PLi) coupled to a subarray SB, and a voltage VH is applied to a bit wiring (e.g., bit wiring BLi) coupled to a subarray SB.

[0140] For reference Figure 7 . Figure 7 For some embodiments according to this disclosure, corresponding to Figure 1 The semiconductor device 100 shown and Figure 2 A schematic diagram of semiconductor device 300 of semiconductor device 200 shown. Relative to Figures 1 to 6 The embodiments are provided for ease of understanding. Figure 7 Similar elements in the drawings are indicated by the same reference numerals. In some embodiments, semiconductor device 300 is relative to, for example, Figure 1 Semiconductor device 100 or Figure 2 Semiconductor device 200 is configured.

[0141] The difference between semiconductor device 300 and semiconductor devices 100 to 200 is that semiconductor device 300 includes two stacked bit cell arrays 110a to 110b. Bit cell arrays 110a to 110b are configured relative to, for example, bit cell array 110. According to some embodiments, each of the bit cell arrays 110a to 110b has a top side S1 and a bottom side S2. In some embodiments, the top sides S1 of the two stacked bit cell arrays 110a to 110b are arranged facing the same direction (e.g., upward along the z-direction). Figure 7 As shown, bit cell array 110a is positioned below bit cell array 110b. Furthermore, power rail R2 is above bit cell array 110b, and power rail R1 is below bit cell array 110a.

[0142] For illustration, bit cell array 110a includes subarray SB1i relative to subarray SB configuration ( Figure 7 (Not shown in the image). Subarray SBi is coupled to bit wiring BLi and substrate wiring PLi. Bit wiring BLi is coupled to power rail R1, which is coupled to circuit 120.

[0143] Similarly, another element array 110b includes a subarray SBi1 configured relative to subarray SB. Figure 7 (Not shown in the image). Subarray SBi1 is coupled to bit wiring BLi1 and substrate wiring PLi1. Substrate wiring PLi1 is coupled to power rail R2, which is coupled to circuit 120. Word wiring WLi is coupled to both subarray SBi and SBi1.

[0144] For reference Figure 7 and Figure 8 . Figure 8 According to some embodiments of this disclosure Figure 7 The schematic diagram shows a cross-sectional view of the semiconductor device 300 along line AA'.

[0145] like Figure 8 As shown, the semiconductor device 300 further includes connections 301 to 303. Bit wiring BLi1 is coupled to substrate wiring PLi via connection 301 (e.g., a metal wire and a via). Bit wiring BLi is coupled to power rail R1 via connection 302. Substrate wiring PLi1 is coupled to power rail R2 via connection 303.

[0146] For reference Figure 9 . Figure 9 According to some embodiments of this disclosure Figures 7 to 8 A schematic diagram of a portion of the semiconductor device 300 shown.

[0147] like Figure 9As shown, in some embodiments, the bit wiring (e.g., bit wiring BLi1) of one of the two adjacent subarrays SB is coupled to the substrate wiring (e.g., substrate wiring PLi) of the other subarray (e.g., subarray SBi1).

[0148] For illustration, the bulk capacitor CL in subarray SBi is coupled to the substrate wiring PLi, and further coupled to the transistor TR of subarray SBi1 via bit wiring BLi1. The transistor TR in subarray SBi is coupled between the bulk capacitor CL and the bit wiring BLi.

[0149] Similarly, the block capacitor CL in subarray SBi1 is coupled to the substrate wiring PLi1. The drain / source terminals of the transistor TR in subarray SBi1 are coupled to the bit wiring BLi1. The control terminals of subarray SBi1 and the transistor TR in SBi are coupled to the word wiring WLi.

[0150] Provided for illustrative purposes Figures 7 to 9 The configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, bit cell array 110a is above bit cell array 110b.

[0151] For reference Figure 10 . Figure 10 For some embodiments according to this disclosure, corresponding to Figure 7 A schematic diagram of semiconductor device 400 of semiconductor device 300 shown. Relative to Figures 1 to 9 The embodiments are provided for ease of understanding. Figure 10 Similar elements in the drawings are indicated by the same reference numerals. In some embodiments, semiconductor device 400 is relative to, for example, Figure 7 The semiconductor device 300 is configured.

[0152] The difference between semiconductor device 300 and semiconductor device 400 lies in that one of the two stacked bit cell arrays 110 is flipped. For example, bit cell array 110b is flipped, and the top side S1 of bit cell array 110a and the bottom side of bit cell array 110b are arranged facing the same direction (e.g., upward along the z-direction). In other words, the top sides S1 of bit cell arrays 110a to 110b are arranged face-to-face. Figure 10 As shown, bit cell arrays 110a and 110b share a common substrate wiring (e.g., substrate wiring PLi coupled to bit cell arrays 110a and 110b).

[0153] Additionally, subarray SBi in bit cell array 110a is coupled to bit wiring BLi, substrate wiring PLi, and word wiring WLi. Bit wiring BLi is coupled to power rail R1, which is coupled to circuit 120. Similarly, subarray SBi1 is coupled to bit wiring BLi1, substrate wiring PL, and word wiring WLi. Bit wiring BLi1 is coupled to power rail R2, which is coupled to circuit 120.

[0154] For reference Figure 10 and Figure 11 . Figure 11 According to some embodiments of this disclosure Figure 10 The diagram shows a schematic cross-sectional view of the semiconductor device 400 along line BB'.

[0155] like Figure 11 As shown, the semiconductor device 400 further includes connections 401-403 (e.g., metal lines and / or vias). Bit connection BLi is coupled to power rail R1 via connection 402. Bit connection BLi1 is coupled to power rail R2 via connection 403. Bit connection BLi1 is coupled to substrate connection PLi via connection 301. In some embodiments, substrate connections PLi1 and PLi are coupled to each other via connection 401. In some embodiments, local substrate connections PLP of subarrays SBi and SBi1 are directly coupled to a common substrate connection PLi.

[0156] For reference Figure 12 . Figure 12 According to some embodiments of this disclosure Figure 10 A schematic diagram of a portion of the semiconductor device 400 shown.

[0157] For illustration, the block capacitor CL in subarray SBi is coupled to the substrate wiring PLi. The drain / source terminals of transistor TR in subarray SBi are coupled to the bit wiring BLi. The control terminals of transistor TR in subarrays SBi and SB are coupled to the word wiring WLi.

[0158] Similarly, the block capacitor CL in subarray SBi1 is coupled to the substrate wiring PLi. The drain / source terminals of transistor TR in subarray SBi1 are coupled to the bit wiring BLi1. The control terminals of transistor TR in subarrays SBi1 and SB are coupled to the word wiring.

[0159] Provided for illustrative purposes Figures 10 to 12 The configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, bit cell array 110a is above bit cell array 110b.

[0160] According to some embodiments of this disclosure, the stacked bit cell array provides a larger voltage allowable difference between power rails R1 and R2. For explanation, in some embodiments, as... Figures 7 to 12 The voltage permissible difference between power rails R1 and R2 provided by the two stacked bit cell arrays shown is twice the voltage permissible difference between power rails R1 and R2 provided by a single bit cell array.

[0161] For reference Figure 13 . Figure 13 For some embodiments according to this disclosure, corresponding to Figure 7 A schematic diagram of semiconductor device 500 of semiconductor device 300 shown. Relative to Figures 1 to 9 The embodiments are provided for ease of understanding. Figure 13 Similar elements in the drawings are indicated by the same reference numerals. In some embodiments, semiconductor device 500 is relative to... Figure 7 The semiconductor device 300 is configured. It should be noted that, for simplicity, Figure 13 Some parts of the semiconductor device 500 were not shown in the image.

[0162] The difference between semiconductor device 300 and semiconductor device 500 is that semiconductor device 500 includes more than two stacked bit cell arrays 110. Bit cell array 110 is referenced above. Figures 7 to 9 The same methods described are stacked and connected to each other. For example... Figure 13 As shown, the subarrays SB of the stacked bit cell array 110 are connected to each other via adjacent bit connections BL and substrate connections PL. For example, the bit connection BLi3 of the subarray SBi3 of the subarray SB, which is one of the stacked bit cell arrays 110a, is coupled to the substrate connection PLi2 of the subarray SB2 of the subarray SB of the adjacent bit cell array 110 below / above the subarray SBi3.

[0163] In some embodiments, the bit wiring BL (e.g., bit wiring BLi) of the first bit cell array 110 in the stacked bit cell array 110 of the semiconductor device 500 is coupled to the power rail R1. The substrate wiring PL (e.g., substrate wiring PLi3) of the last bit cell array 110 in the stacked bit cell array 110 of the semiconductor device 500 is coupled to the power rail R2.

[0164] For reference Figure 14 . Figure 14 For some embodiments according to this disclosure, corresponding to Figure 10 A schematic diagram of semiconductor device 600 of semiconductor device 400 shown. Relative to Figures 1 to 12 The embodiments are provided for ease of understanding. Figure 14Similar elements in the drawings are indicated by the same reference numerals. In some embodiments, semiconductor device 600 is relative to... Figure 10 The semiconductor device 400 is configured. It should be noted that, for simplicity, Figure 14 Some parts of the semiconductor device 600 are not shown in the image.

[0165] The difference between semiconductor device 400 and semiconductor device 600 is that semiconductor device 600 includes more than two stacked bit cell arrays 110. Bit cell array 110 is referenced above. Figures 10 to 12 The same methods described are stacked and connected to each other. For example... Figure 14 As shown, even-numbered bit cell arrays 110 in the stacked bit cell arrays 110 of the semiconductor device 600 are flipped. In various embodiments, an even number of bit cell arrays 110 in the stacked bit cell arrays 110 of the semiconductor device 600 are flipped. Adjacent subarrays SB of the stacked bit cell arrays 110 have a common substrate connection PL or a common bit connection BL. For example, subarray SB12 is a subarray SB of one of the stacked bit cell arrays 110; subarray SB3 is a subarray SB of an adjacent bit cell array 110 stacked below / above subarray SB12; and subarrays SB12 and SB3 are coupled to the common bit connection BL12, as shown. Figure 14 As shown in the image.

[0166] In some embodiments, the bit wiring BL (e.g., bit wiring BLi) or substrate wiring PL (not a common bit wiring BL or a common substrate wiring PL) of the first bit cell array 110 in the stacked bit cell array 110 of the semiconductor device 600 is coupled to power rail R1. The substrate wiring PL (e.g., substrate wiring PLi3) or bit wiring BL (not a common bit wiring BL or a common substrate wiring PL) of the last bit cell array 110 in the stacked bit cell array 110 of the semiconductor device 600 is coupled to power rail R2.

[0167] For reference Figure 15 . Figure 15 For some embodiments according to this disclosure, corresponding to Figures 7 to 14 A schematic diagram of semiconductor device 700 of semiconductor devices 300 to 600 shown. Relative to Figures 1 to 14 The embodiments are provided for ease of understanding. Figure 15 Similar elements in the drawings are indicated by the same reference numerals. In some embodiments, semiconductor device 700 is relative to, for example, Figures 13 to 14 The semiconductor devices are configured to be 500 to 600. It should be noted that, for simplicity, Figure 15 Some parts of the semiconductor device 700 were not shown in the image.

[0168] The difference between semiconductor device 700 and semiconductor devices 500 to 600 lies in that the bit cell array 110 of semiconductor device 700 is stacked in a manner that combines semiconductor devices 500 and 600. For example, as Figure 15 As shown, subarrays SB, SBi1, SBi2 and SBi3 are subarrays SB of the stacked bit cell array 110 of semiconductor device 700; subarrays SBi and SBi1 are stacked in the same manner as semiconductor device 500 described above; and subarrays SBi2 and SBi3 are stacked in the same manner as semiconductor device 600 described above.

[0169] In some embodiments, the bit wiring BL (e.g., bit wiring BL1) or substrate wiring PL (not a common bit wiring BL or a common substrate wiring PL) of the first bit cell array 110 in the stacked bit cell array 110 of the semiconductor device 700 is coupled to power rail R1. The substrate wiring PL (e.g., substrate wiring PLi3) or bit wiring BL (not a common bit wiring BL or a common substrate wiring PL) of the last bit cell array 110 in the stacked bit cell array 110 of the semiconductor device 700 is coupled to power rail R2.

[0170] According to some embodiments, the voltage permissible difference between power rails R1 and R2 provided by semiconductor devices 500 to 700 is proportional to the number of stacked bit cell arrays 110.

[0171] Provided for illustrative purposes Figures 13 to 15 Configurations. Various implementations are within the scope of this disclosure. For example, in some embodiments, each bit cell array 110 has multiple subarrays SB that are coupled to subarrays SB of adjacent bit cell arrays 110 stacked above / below.

[0172] For reference Figures 16A to 16B . Figures 16A to 16B For some embodiments according to this disclosure, corresponding to Figures 1 to 15 A schematic diagram of semiconductor device 800 of semiconductor devices 100 to 700 shown. Relative to Figures 1 to 15 The embodiments are provided for ease of understanding. Figures 16A to 16B Similar elements in the drawings are indicated by the same reference numerals. In some embodiments, semiconductor device 800 is relative to, for example, Figures 1 to 15 The semiconductor device is configured as one of 100 to 700. It should be noted that, for simplicity, Figures 16A to 16B Some parts of the semiconductor device 800 were not shown in the image.

[0173] Compared to semiconductor devices 100 to 700, semiconductor device 800 is further configured to perform test and repair operations. In some embodiments, during a test operation, control circuitry 130 filters defective subarrays SB (e.g., weak bit cells BC with leakage current or short-circuit connections between substrate wiring and bit wiring BL). In some embodiments, during a repair operation, control circuitry 130 disables subarrays SB. Details of the test and repair operations will be referenced in the following paragraphs. Figures 17A to 17B Describe it.

[0174] like Figure 16A As shown, the difference between semiconductor device 800 and semiconductor devices 100 to 700 is that semiconductor device 800 further includes a switch PSi coupled between the power rail R1 and the bit wiring BLi of the subarray SBi. Additionally, semiconductor device 800 further includes a comparator CP and a multiplexer MUX. The multiplexer MUX includes multiple switches. Each of the switches is coupled between a first input terminal (e.g., a positive input) of the comparator CP and the subarray SB of semiconductor device 800. For example, the switch MPSi of the multiplexer MUX is coupled between the first input terminal of the comparator CP and the subarray SBi.

[0175] Additionally, switch MPSi is turned on according to signal MCSi to couple bit connection BLi to the first input of comparator CP. The second input of comparator CP (e.g., the negative input) is coupled to voltage VR. Comparator CP generates signal SH at its output. Switch PSi is turned on according to signal CSi to couple bit connection BLi to power rail R1.

[0176] like Figure 16B As shown, switch Si can be a transistor. In one embodiment, switch PS is an n-type transistor. In another embodiment, switch PSi is a p-type transistor.

[0177] To illustrate, subarray SBi or stacked subarray SB (similar to...) Figures 7 to 15 The subarrays SBi, SBi1, etc. shown are coupled between the power rail R2 and the drain / source terminals of the switch PSi. The source / drain terminals of the switch PSi are coupled to the power rail R1. The control terminal (gate terminal) of the switch PSi is coupled to the switch CSi.

[0178] For simplicity, such as Figure 16B As shown, all capacitors 101 in the subarray SBi or stacked subarray SB are represented as block capacitors CL, and all transistors 102 in the subarray SBi or stacked subarray SB are represented as transistors TR.

[0179] Provided for illustrative purposes Figures 16A to 16BThe configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, the semiconductor device 800 includes a plurality of switches similarly coupled between a power rail R1 and a subarray SB (or a stacked subarray). In some embodiments, the switches (e.g., switches PSi) are coupled between a power rail R2 and a subarray SB (or a stacked subarray) rather than between a power rail R1 and a subarray SB (or a stacked subarray).

[0180] For reference Figures 16A to 16B and Figures 17A to 17B . Figure 17A and Figure 17B This is an exemplary timing diagram of the voltage signal of a semiconductor device 800 during test operation according to some embodiments of this disclosure.

[0181] In some embodiments, control circuitry 130 controls signals on board wiring PL, bit wiring BL, word wiring WL, switches, and multiplexer MUX to perform test operations to check the connections of board wiring PL and bit wiring BL for each subarray SB or stacked subarray. For ease of explanation, the following paragraphs describe only examples of test operations for a single subarray SB. It should be noted that test operations for multiple subarrays SB and stacked subarrays SB can be performed in a similar manner.

[0182] For clarity, the voltage signals on the substrate wiring PLi, power rail R1, bit wiring BLi, and character wiring WLi are labeled as signals VPLi, VR1, VBLi, and VEi, respectively. In some embodiments, the control circuit 130 of the semiconductor device 800 ( Figures 16A to 16B (Not shown) Control signals VPLi, VR1, CSi, VBLi, VEi, and MSCi are used to perform a test operation to check the connection of substrate wiring PLi and bit wiring BLi. Specifically, control circuit 130 performs a test operation to determine whether substrate wiring PLi and bit wiring BLi are short-circuited (or include weak bit cells BC with current leakage). In some embodiments, when substrate wiring PLi and bit wiring BLi are determined to be not short-circuited (or subarray SBi does not include weak bit cells BC), control circuit 130 determines that subarray SBi passes the test operation. Conversely, when substrate wiring PLi and bit wiring BLi are determined to be short-circuited (or subarray SBi includes weak bit cells BC), control circuit 130 determines that semiconductor device 800 fails the test operation.

[0183] Figure 17A This demonstrates the voltage signal of the semiconductor device 800 when the substrate wiring PLi and the bit wiring BLi are not short-circuited (or the subarray SBi does not include the weak bit cell BC). Figure 17BThis demonstrates the voltage signal of the semiconductor device 800 when the substrate wiring PLi and the bit wiring BLi are short-circuited (or the subarray SBi includes weak bit cells BC).

[0184] like Figures 17A to 17B As shown, during the test operation, a first voltage (e.g., the voltage VL described above) is applied to the power rail R1. The signal VR1 has the first voltage at time t1.

[0185] During the test operation, at time t1, switch PSi is turned on according to signal CSi. Figures 17A to 17B In some embodiments, the switch PSi is an n-type transistor, and the signal CSi is pulled high to... Figures 17A to 17B The switch PSi shown in the image is the on / off switch.

[0186] In response to the switch PSi being turned on, the first voltage from the power rail R1 is applied to the bit connection BLi. Figures 17A to 17B Of the two, signal VBLi has a first voltage at time t1.

[0187] During the test operation, the switch MPSi in the multiplexer MUX is initially turned off. In some embodiments, the signal MCSi is inverted compared to the signal CSi. In some embodiments, the switch MPSi responds to the on / off state of the switch PSi. In some embodiments, the switch PSi is an n-type transistor, such as... Figures 17A to 17B As shown, the signal MCSi is pulled low at time t1 to disconnect the switch MPSi.

[0188] During the test operation, the subarray SBi was initially not enabled. In other words, transistor 102 coupled to the character line WLi was turned off at time t1. In some embodiments, transistor 102 is an n-type transistor, such as... Figures 17A to 17B As shown, the signal VEi on the character line WLi is pulled low to disconnect transistor 102.

[0189] At time t2, switch PSi is off and switch MPSi is on. In some embodiments, such as Figures 17A to 17B As shown in the figure, at time t2, signal CSi is pulled low and signal MCSi is pulled high.

[0190] At time t2, a second voltage (e.g., voltage VH) is applied to the substrate wiring PLi from the power rail R2. The signal VPLi has the second voltage at time t2.

[0191] At time t2, subarray SBi is enabled to operate as a decoupling capacitor. In other words, transistor 102 coupled to word line WLi is turned on at time t2. In some embodiments, transistor 102 is an n-type transistor, and signal VEi on word line WLi is pulled high (e.g., with voltage VWL) to turn on transistor 102, as... Figures 17A to 17B As shown in the image.

[0192] like Figure 17A As shown, when the substrate wiring PLi and the bit wiring BLi are not short-circuited (or the subarray SBi does not include the weak bit cell BC), the signal VBLi maintains a first voltage VL at time t2. In response to the switch MPSi being turned on, the comparator CP compares the voltage of the signal VBLi with the voltage VR at time t2. In some embodiments, the voltage VR is between the first voltage and the second voltage (e.g., when the first voltage and the second voltage are voltages VL and VH respectively, VH > VR > VL). In some embodiments, the voltage VR = VH + VL / 2.

[0193] The comparator CP generates a signal SH at time t2 based on a comparison between the voltage of signal VBLi and voltage VR. In some embodiments, when the voltage of signal VBLi is lower than voltage VR, the comparator CP pulls the signal SH low. The control circuit 130 determines, based on the signal SH pulled low after time t2, that the substrate wiring PLi and the bit wiring BLi are not short-circuited (or SBi does not include the weak bit cell BC).

[0194] like Figure 17B As shown, when the substrate wiring PLi and the bit wiring BLi are short-circuited (or the subarray SBi includes weak bit cells BC), at time t2, the voltage from the substrate wiring PLi is transmitted to the bit wiring BLi. The signal VBLi has a second voltage at time t2. In response to the switch MPSi being turned on, the comparator CP compares the voltage of the signal VBLi with the voltage VR at time t2. The comparator CP generates a signal SH at time t2 based on the comparison between the voltage of the signal VBLi and the voltage VR. In some embodiments, when the voltage of the signal VBLi is higher than the voltage VR, the comparator CP pulls the signal SH high. The control circuit 130 determines that the substrate wiring PLi and the bit wiring BLi are short-circuited (or SBi includes weak bit cells BC) based on the signal SH that is pulled high after time t2.

[0195] Table 1 below shows the signals of a semiconductor device 800 according to some embodiments. In Table 1, "1" represents pull-high, "0" represents pull-low, and "X" represents unknown. The second row indicates signals during normal operation (providing decoupling capacitance to circuit 120). The third row shows signals during test operation after time t2 when the substrate wiring PLi and bit wiring BLi are not short-circuited (or the subarray SBi does not include weak bit cell BC). The fourth row shows signals during test operation after time t2 when the substrate wiring PLi and bit wiring BLi are short-circuited (or the subarray SBi includes weak bit cell BC). The fifth row shows signals during test operation after time t2 when the subarray SBi is not selected (deactivated). The sixth row shows signals during repair operation.

[0196]

[0197] Table 1

[0198] As shown in Table 1, during the repair operation, subarray SBi is disabled. Specifically, the repair operation is performed to disable subarray SBi when substrate wiring PLi and bit wiring BLi are determined to be short-circuited (or subarray SBi includes weak bit cells BC). In some embodiments, during the repair operation, control circuit 130 pulls signal VEi low to disable subarray SBi. For example, when subarray SB operates to provide decoupling capacitance to circuit 120, control circuit 130 performs the repair operation to disable the defective subarray SB among all subarrays SB.

[0199] Provided for illustrative purposes Figures 16A to 16B and Figures 17A to 17B The configuration is as follows. Various implementations are within the scope of this disclosure. For example, in some embodiments, bit connection BLi is subjected to a voltage VH at time t1, and substrate connection PLi is subjected to a voltage VH at time t2. In some embodiments, the transistors / switches of the semiconductor device 800 (e.g., transistor 102, switch PSi, etc.) are p-type. It should be noted that, in order to perform similar operations, the control signals of p-type transistors / switches are out of phase with the control signals of n-type transistors / switches.

[0200] For reference Figure 18 . Figure 18 For some embodiments according to this disclosure, corresponding to Figures 1 to 15 A schematic diagram of bit unit BC' of bit unit BC in the semiconductor devices 100 to 800 shown. Relative to Figures 1 to 15 The embodiments are provided for ease of understanding. Figure 18 Similar elements in the drawings are indicated by the same reference numerals. In some embodiments, semiconductor device 800 is relative to, for example, Figures 1 to 15 The bit units BC in the semiconductor devices 100 to 800 shown are configured.

[0201] The difference between bit cell BC' and bit cell BC lies in the short-circuiting of the source and drain terminals of transistor 102. In one embodiment, the source and drain terminals of transistor 102 in bit cell BC' are short-circuited through process modification. For example, the mask in the manufacturing process of the bit cell is modified to extend the source or drain region so that the source and drain terminals are in contact with each other. In some embodiments, Figures 1 to 15 The bit cell BC in the semiconductor devices 100 to 800 shown may be replaced by bit cell BC'. In some embodiments, the word connection WL coupled to bit cell BC' is floating.

[0202] For reference Figure 19 . Figure 19 For some embodiments according to this disclosure, corresponding to Figures 1 to 15 , Figures 16A to 16B and Figures 17A to 17B A schematic diagram of semiconductor device 900 of the semiconductor devices 100 to 800 shown. (Relative to...) Figures 1 to 15 , Figures 16A to 16B and Figures 17A to 17B The embodiments are provided for ease of understanding. Figure 19 Similar elements in the drawings are indicated by the same reference numerals. In some embodiments, semiconductor device 900 is relative to, for example, Figures 16A to 16B and Figures 17A to 17B The semiconductor device is configured as 800. It should be noted that, for simplicity, Figure 19 Some parts of the semiconductor device 900 were not shown in the image.

[0203] like Figure 19 As shown, the difference between semiconductor device 900 and semiconductor device 800 is that semiconductor device 900 has a subarray SB that has bit cells BC' instead of bit cells BC.

[0204] For reference Figure 19 and Figures 20A to 20B . Figure 20A and Figure 20B This is an exemplary timing diagram of the voltage signal of a semiconductor device 900 during test operation according to some embodiments of this disclosure. Figure 20A This demonstrates the voltage signal of the semiconductor device 900 when the substrate wiring PLi and the bit wiring BLi are not short-circuited (or the subarray SBi does not include the weak bit cell BC), and Figure 20B The voltage signal of the semiconductor device 900 is displayed when the substrate wiring PLi and the bit wiring BLi are short-circuited (or the subarray SBi includes weak bit cells BC).

[0205] The test operation of semiconductor device 900 is configured relative to the test operation of semiconductor device 800 described above. The difference between the test operation of semiconductor device 800 and the voltage signal of semiconductor device 900 is that the character wiring WL is not used to control semiconductor device 900 for test operation.

[0206] Table 2 below shows the signals of a semiconductor device 900 according to some embodiments. In Table 2, "1" represents pull-high, "0" represents pull-low, and "X" represents unknown. The second row indicates signals during normal operation (providing decoupling capacitance to circuit 120). The third row shows signals during test operation after time t2 when the substrate wiring PLi and bit wiring BLi are not short-circuited (or the subarray SBi does not include weak bit cell BC). The fourth row shows signals during test operation after time t2 when the substrate wiring PLi and bit wiring BLi are short-circuited (or the subarray SBi includes weak bit cell BC). The fifth row shows signals during test operation after time t2 when the subarray SBi is not selected (deactivated). The sixth row shows signals during repair operation.

[0207]

[0208] Table 2

[0209] As shown in Table 2, during the repair operation of semiconductor device 900, subarray SBi is disabled. Specifically, the repair operation is performed to disable subarray SBi when substrate wiring PLi and bit wiring BLi are determined to be short-circuited (or subarray SBi includes weak bit cells BC). In some embodiments, during the repair operation, control circuit 130 disconnects (pulls down signal CSi when switch PSi is an n-type transistor) switch PSi to disable subarray SBi. For example, when subarray SB operates to provide decoupling capacitance to circuit 120, control circuit 130 performs a repair operation to disable defective subarray SB among all subarrays SB.

[0210] In some embodiments, control circuitry 130 controls signals (e.g., voltages on bit wiring BL, substrate wiring PL, and word wiring WL) destined for semiconductor devices 100 to 900 to change subarray SB from self-decoupling mode (providing decoupling capacitors to circuitry 130) to memory mode. In memory mode, subarray SB functions as a memory array (e.g., DRAM) for storing data.

[0211] For reference Figure 21 . Figure 21 For some embodiments according to this disclosure, corresponding to Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 and Figures 20A to 20BA schematic diagram of semiconductor device 1000, showing semiconductor devices 100 to 900. Relative to... Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 and Figures 20A to 20B The embodiments are provided for ease of understanding. Figure 21 Similar elements are denoted by the same reference numerals. In some embodiments, semiconductor device 1000 is configured relative to, for example, semiconductor devices 100 to 900. It should be noted that, for simplicity, Figure 21 Some parts of the semiconductor device 1000 are not shown in the image.

[0212] like Figure 21 As shown, the difference between semiconductor device 1000 and semiconductor devices 100 to 900 is that the bit cell array 110 of semiconductor device 1000 further includes switches (e.g., switches Si) formed in layers 1001 between each stacked subarray SB (e.g., subarrays SBi and SBi1). In some embodiments, when one of the subarrays SB in the stacked subarrays SB is changed to memory mode by the control circuit 130, the switches between the stacked subarrays are turned off. For example, when subarrays SBi and / or SBi1 are in memory mode, the control circuit 130 turns off the switches Si by the control signal CS10.

[0213] For reference Figure 22A and Figure 22B . Figure 22A and Figure 22B According to some embodiments of this disclosure Figure 21 A schematic diagram of a portion of the semiconductor device 1000 shown. Figure 22A As shown, in some embodiments, switch Si is coupled between the substrate wiring PL (e.g., PLi) of subarray SB (e.g., SBi) and the bit wiring (e.g., BLi1) of the adjacent stacked subarray (e.g., SBi1). Figure 22B As shown, in some embodiments, switch Si is coupled between the substrate wiring PL (e.g., PLi) of subarray SB (e.g., SBi) and the block capacitor CL of the adjacent stacked flip subarray (e.g., SBi1).

[0214] In some embodiments, the bit cell array 110 includes several subarrays that are different from the subarray SB. These subarrays that are different from the subarray SB serve as memory arrays, while the subarray SB is used to provide decoupling capacitors.

[0215] For reference Figure 23 . Figure 23 For some embodiments according to this disclosure, corresponding to Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 , Figures 20A to 20B , Figure 21 and Figures 22A to 22B A schematic diagram of semiconductor device 1100 of the semiconductor devices 100 to 1000 shown. Relative to... Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 , Figures 20A to 20B , Figure 21 and Figures 22A to 22B The embodiments are provided for ease of understanding. Figure 23 Similar elements are denoted by the same reference numerals. In some embodiments, semiconductor device 1100 is configured relative to, for example, semiconductor devices 100 to 1000. It should be noted that, for simplicity, Figure 23 Some parts of the semiconductor device 1100 are not shown in the image.

[0216] like Figure 23 As shown, the difference between semiconductor device 1100 and semiconductor devices 100 to 1000 is that the bit cell array 110 of semiconductor device 1100 further includes at least one subarray SBM serving as a memory array. For illustration, the subarray SBM includes multiple bit lines BLM (e.g., bit lines BLM1 to BLM1i) and multiple word lines WLM (e.g., word lines WLM1 to WLM1i). Figure 23 As shown, the control circuit 130 is coupled to the subarray SBM via bit wiring (BLM) and word wiring (WLM). In some embodiments, the control circuit 130 writes data to the subarray SBM or reads data from the subarray SBM via bit wiring (BLM) and word wiring (WLM).

[0217] In some embodiments, semiconductor devices 100 to 1100 include compute-in-memory (CIM) circuitry. In some embodiments, the array 110 of individual cells in semiconductor devices 100 to 1100 includes a memory array of CIM circuitry. In some embodiments, each subarray SB of semiconductor devices 100 to 1100 is configured as a decoupling capacitor for CIM circuitry. In some embodiments, the subarray SBM of semiconductor device 1100 is configured as a memory array of CIM circuitry.

[0218] For reference Figure 24 . Figure 24 For operation according to some embodiments Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 , Figures 20A to 20B , Figure 21 , Figures 22A to 22B and Figure 23 The flowchart illustrates method 1200 for semiconductor devices 100, 200...1000 or 1100. It should be understood that for additional embodiments of method 1200, [further details may be needed]. Figure 24 Additional operations are provided before, during, and after the illustrated process, and some of the operations described below may replace or eliminate them. The order of operations / processes may be interchangeable. Similar reference numerals are used to denote similar elements throughout the various views and illustrative embodiments. Method 1200 includes the following references corresponding to... Figures 1 to 15 , Figures 16A to 16B , Figures 17A to 17B , Figures 18 to 19 , Figures 20A to 20B , Figure 21 , Figures 22A to 22B and Figure 23 The operations 1201 to 1204 described in the semiconductor devices 100, 200...1000 or 1100.

[0219] In the test operation of semiconductor devices 100, 200...1000 or 1100, operations 1201 to 1204 are performed to determine whether there are defects in the subarray SB or the stacked subarray SB.

[0220] In operation 1201, a first voltage (e.g., voltage VL) is applied to the power rail R1, and a switch (e.g., switch PSi) is turned on to charge or discharge the bit wiring (e.g., bit wiring BLi) of the subarray SB according to the first voltage. The subarray SB operates as a decoupling capacitor of circuit 120 and includes bit cells BC coupled between the bit wiring of the subarray SB and the substrate wiring (e.g., substrate wiring PLi).

[0221] In operation 1202, the switch is disconnected to disconnect the bit wiring from the power rail.

[0222] In operation 1203, a second voltage (e.g., voltage VH) is applied to the substrate wiring via power rail R2. When the subarray SB includes defective bit cells (e.g., weak bit cells BC with current leakage or bit cells BC that are short-circuited in the event of capacitor 101 failure), the voltage on the bit wiring is pulled up or down according to the second voltage on the substrate wiring.

[0223] In operation 1204, comparator CP compares the voltage on the bit wiring with a reference voltage VR to determine whether one of the bit cells BC of subarray SB is defective. In some embodiments, the reference voltage is between a first voltage and a second voltage.

[0224] In one embodiment, the first voltage is lower than the second voltage, and the subarray is determined to be defective based on the bit wiring voltage being greater than the third voltage. In another embodiment, the first voltage is greater than the second voltage, and the subarray is determined to be defective based on the bit wiring voltage being less than the third voltage.

[0225] In some embodiments, during a repair operation, in order to prevent the subarray SB from operating as a decoupling capacitor of circuit 120, based on the determination in operation 1204 that one of the bit cells BC of the subarray SB is defective, the transistors 102 in each of the bit cells BC of the subarray SB are turned off to disconnect the capacitors 101 in each of the bit cells BC of the subarray SB from the bit wiring.

[0226] In some embodiments, during normal operation, transistors 102 in each of the bit cells BC of the subarray SB are turned on, and a switch coupled between the bit wiring and the power rail R1 is turned on to couple a capacitor to the power rail R1, so that the subarray SB can operate as a decoupling capacitor for the circuit 120.

[0227] In some embodiments, during a repair operation, based on the determination that one of the plurality of bit cells is defective, a switch coupled between the bit wiring and the power rail R1 is opened so that the subarray SB cannot operate as a decoupling capacitor of the circuit 120.

[0228] As described above, this disclosure provides a semiconductor device and method for providing decoupling capacitors. The provided semiconductor device uses the same array of bit cells in a memory array (e.g., back-end DRAM bit cells) without incurring additional manufacturing costs for decoupling capacitor applications. The provided method includes a test operation to screen defective subarrays and a repair operation to skip defective bit cells. Furthermore, the stacking scheme of the provided semiconductor device allows for higher voltage operation. Compared to some methods, the semiconductor device and method disclosed herein provide a larger capacitance per unit area and lower current leakage.

[0229] In some embodiments, a semiconductor device is provided. The semiconductor device includes a circuit and a first element cell array. The circuit is coupled to a first power rail and a second power rail. The first element cell array includes a first subarray having a plurality of first element cells coupled between the first power rail and the second power rail. When the circuit operates in response to a first operating voltage on the first power rail and a second operating voltage on the second power rail, the first element cells are configured as decoupling capacitors between the first power rail and the second power rail of the circuit.

[0230] In some embodiments, the bit cell array is a back-end dynamic random access memory array.

[0231] In some embodiments, the circuit is configured in the front-end process layer and the bit cell array is configured in the back-end process layer.

[0232] In some embodiments, the semiconductor device further includes a second bit cell array stacked on the first bit cell array and includes a second subarray having second bit cells coupled between a second power rail and a plurality of first bit cells. The plurality of first bit cells and the plurality of second bit cells are configured as a circuit between the first power rail and the second power rail via decoupling capacitors.

[0233] In some embodiments, the semiconductor device further includes a metal connection in a layer located between the first subarray and the second subarray, wherein the metal connection is coupled to a substrate wiring of the first subarray and a substrate wiring and a bit wiring of the second subarray.

[0234] In some embodiments, the metal connection includes a first through hole and a second through hole that are separated from each other in the horizontal direction.

[0235] In some embodiments, the semiconductor device further includes: a bit wiring coupled between a first power rail and a first subarray; and a substrate wiring coupled between a second power rail and the first subarray. Each bit cell in the plurality of first bit cells includes: a transistor having a first end coupled to the bit wiring; and a capacitor coupled between the substrate wiring and a second end of the transistor.

[0236] In some embodiments, the semiconductor device further includes: a comparator; and a switch coupled between a bit connection and a first power rail. During a test operation, the switch is turned on to charge the bit connection to a first operating voltage, and then turned off to disconnect the bit connection from the first power rail. When the switch is off, the comparator compares the voltage on the bit connection with a reference voltage to determine whether the first subarray has weak bit cells.

[0237] In some embodiments, the semiconductor device further includes a word line, wherein the control terminals of the transistors of each of the plurality of first bit cells are coupled to the word line. During a repair operation, based on a determination that the first subarray has weak bit cells, the transistors of each of the plurality of first bit cells are disconnected in response to a control signal on the word line.

[0238] In some embodiments, during the repair operation, based on the determination that the first subarray has weak bit cells, the switch is turned off so that the plurality of first bit cells cannot operate as decoupling capacitors.

[0239] In some embodiments, the first element array further includes a second subarray configured as a memory array for storing data.

[0240] In some embodiments, a semiconductor device is provided. The semiconductor device includes circuitry and a first element cell array. The circuitry operates using a first voltage and a second voltage on a first power rail and a second power rail, respectively. The first element cell array includes a plurality of first element cells arranged in a plurality of rows and a plurality of columns. Each of the plurality of rows is coupled to one of local bit connections and one of local substrate connections. The first element connection of the first element cell array is coupled between the first element cell and the first power rail. The first substrate connection of the first element cell array is coupled between the first element cell and the second power rail. Local bit connections are coupled to the first element connections, and local substrate connections are coupled to the first substrate connections. Each of the plurality of first element cells includes a capacitor. The first element cell is configured as a decoupling capacitor for a circuit between the first power rail and the second power rail.

[0241] In some embodiments, the semiconductor device further includes: a second bit cell array stacked on a first bit cell array and comprising a plurality of second bit cells, wherein a second substrate wiring of the second bit cell array is coupled between the plurality of second bit cells and a second power rail, and a second bit wiring of the second bit cell array is coupled to a first bit wiring, wherein the first bit cell array and the second bit cell array are connected via decoupling capacitors configured as a circuit between the first power rail and the second power rail.

[0242] In some embodiments, the semiconductor device further includes: a second bit cell array stacked on a first bit cell array and comprising a plurality of second bit cells, wherein the second bit cell array is flipped compared to the first bit cell array, second bit wiring of the second bit cell array is coupled between the plurality of bit cells and a second power rail, and a first substrate wiring is a common substrate wiring of the first bit cell array and the second bit cell array, wherein the first bit cell array and the second bit cell array are configured as decoupling capacitors for a circuit between the first power rail and the second power rail.

[0243] In some embodiments, the semiconductor device further includes: a plurality of second bit cell arrays stacked on a first bit cell array, wherein the first bit cell array and the plurality of second bit cell arrays are coupled between a first power rail and a second power rail and are connected via a decoupling capacitor configured as a circuit.

[0244] In some embodiments, the first voltage has a negative voltage level, and the second voltage has a ground voltage level.

[0245] In some embodiments, a method for operating a semiconductor device is provided. The method includes: applying a first voltage to a power rail and turning on a switch to charge bit wiring of a subarray, the subarray operating as a decoupling capacitor for a circuit and including a plurality of bit cells coupled between the bit wiring of the subarray and substrate wiring; turning off the switch to disconnect the bit wiring from the power rail; applying a second voltage to the substrate wiring; and comparing the voltage on the bit wiring with a third voltage to determine whether one of the plurality of bit cells is defective.

[0246] In some embodiments, comparing the voltage of the bit connection with a third voltage includes determining that the subarray is defective based on the fact that the voltage of the bit connection is greater than the third voltage.

[0247] In some embodiments, the method further includes: during a repair operation, based on the determination that one of the plurality of bit cells is defective, disconnecting the transistors in each bit cell of the plurality of bit cells to disconnect the capacitors in each bit cell of the plurality of bit cells from the bit wiring.

[0248] In some embodiments, the method further includes, in normal operation, turning on the transistors in each of the plurality of bit cells and turning on a switch to couple the capacitor to the power rail, so that the subarray can operate as a decoupling capacitor for the circuit.

[0249] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of the embodiments disclosed herein. Those skilled in the art should understand that the embodiments disclosed herein can be used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the embodiments disclosed herein.

Claims

1. A semiconductor device, characterized in that, Include: A circuit, coupled to a first power rail and a second power rail; and A first-order element array, comprising a first subarray, the first subarray having a plurality of first-order elements coupled between the first power rail and the second power rail. The plurality of first element units are configured as a decoupling capacitor between the first and second power rails of the circuit, in response to a first operating voltage on the first power rail and a second operating voltage on the second power rail.

2. The semiconductor device as claimed in claim 1, characterized in that, The first element cell array is a back-end dynamic random access memory array.

3. The semiconductor device as claimed in claim 1, characterized in that, The circuit is configured in a front-end process layer, and the first element array is configured in a back-end process layer.

4. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A second bit cell array, stacked on the first bit cell array and including a second subarray, the second subarray having a plurality of second bit cells coupled between the second power rail and the plurality of first bit cells, wherein the plurality of first bit cells and the plurality of second bit cells are configured as a decoupling capacitor between the first power rail and the second power rail of the circuit; as well as A metal connection is located in a layer between the first subarray and the second subarray, wherein the metal connection is coupled to one of a substrate connection of the first subarray and a substrate connection and a bit connection of the second subarray. The metal connection includes a first through hole and a second through hole that are separated from each other in a horizontal direction.

5. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A single-element connection is coupled between the first power rail and the second power rail; A substrate wiring is connected between the second power rail and the first sub-array. The individual elements in the plurality of first-bit elements include: A transistor having a first terminal coupled to the bit wiring; and A capacitor is coupled between the substrate wiring and a second terminal of the transistor.

6. The semiconductor device as claimed in claim 5, characterized in that, Further includes: A comparator; and A switch is coupled between the bit connection and the first power rail. In one test operation, the switch is configured to turn on to charge the bit connection to the first operating voltage, and then turn off to disconnect the bit connection from the first power rail. When the switch is open, the comparator compares a voltage on the bit connection with a reference voltage to determine whether the first subarray has a weak bit cell.

7. A semiconductor device, characterized in that, Include: A circuit for operation using a first supply voltage on a first power rail and a second supply voltage on a second power rail, respectively; and A first bit cell array includes a plurality of first bit cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of rows is coupled to one of a plurality of local bit wirings and one of a plurality of local substrate wirings. One of the first element connections of the first element array is coupled between the plurality of first element units and the first power rail. A first substrate wiring of the first element unit array is coupled between the plurality of first element units and the second power rail. The plurality of local bit wirings are coupled to the first bit wiring, and the plurality of local substrate wirings are coupled to the first substrate wiring. Each of the plurality of first element units includes a capacitor, and The plurality of first element units are configured as a decoupling capacitor for the circuit between the first power rail and the second power rail.

8. The semiconductor device as claimed in claim 7, characterized in that, Further includes: A second bit cell array, which is stacked on the first bit cell array and contains a plurality of second bit cells. A second substrate wiring of the second bit cell array is coupled between the plurality of second bit cells and the second power rail, and A second bit connection of the second bit cell array is coupled to the first bit connection. The first bit array and the second bit array are configured as the decoupling capacitors of the circuit between the first power rail and the second power rail.

9. The semiconductor device as claimed in claim 7, characterized in that, Further includes: A second bit cell array, which is stacked on the first bit cell array and contains a plurality of second bit cells. The second bit array is flipped compared to the first bit array. A second bit wiring of the second bit cell array is coupled between the plurality of second bit cells and the second power rail, and The first substrate wiring is a common substrate wiring for the first bit cell array and the second bit cell array. The first bit array and the second bit array are configured as the decoupling capacitors of the circuit between the first power rail and the second power rail.

10. A semiconductor device, characterized in that, Include: A circuit, coupled to a first power rail and a second power rail; and An array of first-order unit cells, comprising: A first subarray having a plurality of first element cells coupled between the first power rail and the second power rail. The plurality of first element units are configured as a decoupling capacitor between the first power rail and the second power rail in response to a first operating voltage on the first power rail and a second operating voltage on the second power rail. as well as A second subarray is configured as a memory array for storing data.

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