semiconductor structure

Abstract

This disclosure pertains to a semiconductor structure of an on-substrate gate all-around field-effect transistor (GAAFET). This semiconductor structure includes an isolation layer beneath the source / drain epitaxial structures of the GAAFET. The isolation layer comprises silicon oxide and is formed using a flowable chemical vapor deposition process. The isolation layer is disposed on the side of the bottommost internal spacer structure of the GAAFET and protrudes into the substrate. The isolation layer suppresses leakage current across the substrate between the opposing source / drain epitaxial structures. The isolation layer also suppresses leakage current across the bottommost internal spacer structure between the gate structure and the source / drain epitaxial structures of the GAAFET.

Description

Technical Field

[0001] This disclosure pertains to a semiconductor structure. Background Technology

[0002] Compared to other types of field-effect transistors (FETs) where the gate structure covers the sidewalls and top surface of the semiconductor fin structure, gate-all-around (GAA) FETs, such as nanosheet or nanowire GAA FETs, offer improved gate control over the channel region. Due to their all-around geometry, GAA FETs can achieve larger effective channel widths and higher drive currents. Utility Model Content

[0003] In some embodiments, this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a nanostructure element, a gate structure, an internal spacer structure, source / drain regions, and an isolation layer. The nanostructure element is on the substrate. The gate structure surrounds the nanostructure element. The internal spacer structure is adjacent to the gate structure and located below the nanostructure element. The source / drain regions are in contact with the sides of the nanostructure element. The isolation layer is located below the source / drain regions and is in contact with the sides of the internal spacer structure.

[0004] In some embodiments, this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a plurality of nanosheet layers, a gate structure, a plurality of internal spacers, a source / drain structure, and an isolation layer. The nanosheet layers are on the substrate. The gate structure surrounds the nanosheet layers. The internal spacers are in contact with the gate structure. The source / drain structure is in contact with the nanosheet layers. The isolation layer is located below the source / drain structure and is in contact with the side of the bottommost internal spacer.

[0005] In some embodiments, this disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, nanostructured elements, a gate structure, a plurality of internal spacers, source / drain epitaxial structures, and an isolation layer. The nanostructured elements are on the substrate. The gate structure surrounds the nanostructured elements. The internal spacers are adjacent to the gate structure. The source / drain epitaxial structures are isolated from the gate structure by these internal spacers. The isolation layer is located below the source / drain epitaxial structures and contacts the side of the bottommost internal spacer. Attached Figure Description

[0006] Can be attached Figure 1The best way to understand the various aspects of this disclosure is through the following detailed description. It should be noted that, in accordance with common industry practice, the features may not be drawn to scale. In fact, for ease of explanation and discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 It is an isometric view of a semiconductor device including nanostructured transistors according to some embodiments;

[0008] Figure 2 This is a cross-sectional view of a semiconductor device including nanostructured transistors according to some embodiments;

[0009] Figures 3A to 3C This is an enlarged cross-sectional view of a region in a semiconductor device including nanostructured transistors according to some embodiments.

[0010] Figure 4 This is a flowchart of a method for forming an isolation structure of source / drain epitaxial structure in a nanostructured transistor according to some embodiments;

[0011] Figure 5 and Figure 6 This is an isometric view of an intermediate structure during the fabrication process of an isolation structure for the source / drain epitaxial structure in a nanostructured transistor, according to some embodiments.

[0012] Figures 7 to 17 This is a cross-sectional view of an intermediate structure during the fabrication process of an isolation structure for forming a source / drain epitaxial structure in a nanostructured transistor, according to some embodiments.

[0013] The illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, reference numerals generally denote identical, functionally similar, and / or structurally similar elements.

[0014] [Symbol Explanation]

[0015] 100: Semiconductor devices

[0016] 102: Substrate

[0017] 105: Gate All-Surround Field-Effect Transistor

[0018] 110: Fin Structure

[0019] 115: Gate Structure

[0020] 115a: Interface dielectric layer

[0021] 115b: Gate dielectric layer

[0022] 115c: Gate electrode

[0023] 115cb: The bottommost gate electrode

[0024] 120: Nanosheets

[0025] 120b: The bottommost nanosheet layer

[0026] 120bs: Side view

[0027] 125: Source / Drain epitaxial structure

[0028] 130: Internal spacer structure

[0029] 130b: The inner spacer structure at the bottom

[0030] 130bs: Side view

[0031] 130bt: Top surface

[0032] 135: Gate interstitial material

[0033] 138: Shallow trench isolation area

[0034] 145: Isolation layer

[0035] 145s: bottom surface

[0036] 145t: Top surface

[0037] 163: Source / Drain Contact

[0038] 165: Interlayer dielectric layer

[0039] 170: Leakage current path

[0040] 250: Epitaxial region

[0041] 250b: The bottom epitaxial region

[0042] 253: Epitaxial region

[0043] 255: Epitaxial region

[0044] 300: Part

[0045] 400: Method

[0046] 405: Operation

[0047] 410: Operation

[0048] 415: Operation

[0049] 420: Operation

[0050] 425: Operation

[0051] 430: Operation

[0052] 435: Operation

[0053] 520: Stacking

[0054] 520a: First nanosheet

[0055] 520b: Second nanosheet

[0056] 620: Fin Structure

[0057] 620a: First nanosheet

[0058] 620b: Second nanosheet

[0059] 700: Sacrificial gate structure

[0060] 700a: Sacrificial gate electrode

[0061] 705: Covering layer

[0062] 820a: First nanosheet

[0063] 840: Opening

[0064] 920a: First nanosheet

[0065] 945: Depressed structure

[0066] 1030: Dielectric layer

[0067] AB: Cutting line

[0068] BB: Line

[0069] D1: Depth

[0070] D2: Altitude

[0071] L1: Distance

[0072] L2: Distance

[0073] Lc: Length

[0074] T3: Vertical distance

[0075] T4: Vertical distance

[0076] x: direction

[0077] y: direction

[0078] z: Direction Detailed Implementation

[0079] The following disclosure provides many different implementations or examples for achieving different features of the provided object. To simplify this disclosure, specific examples of elements and configurations are described below. Of course, these are merely examples and are not intended to limit the disclosure. For example, in the following description, implementations of forming a first feature on a second feature may include where the first and second features are formed in direct contact, or implementations in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact.

[0080] Furthermore, for ease of description, this document uses spatial relative terms such as "down," "below," "below," "above," "above," etc., to describe the relationship between one element or feature in the figure and another element or feature in the figure. Spatial relative terms are intended to include different orientations of the device during use or operation, other than those described in the figure. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0081] In some embodiments, the terms "about" and "substantially" may indicate that the value varies by less than 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to limit the scope of this disclosure. It should be understood that the terms "about" and "substantially" can be a certain percentage value as interpreted by those skilled in the art based on the teachings of this disclosure.

[0082] It should be noted that references to "an embodiment," "an implementation," "an exemplary embodiment," "exemplary," etc., in the specification indicate that the embodiment may include specific features, structures, or properties, but not every embodiment necessarily includes specific features, structures, or properties. Furthermore, these terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or property is described in conjunction with an embodiment, whether explicitly described or not, it can be associated with other embodiments by those generally skilled in the art, regardless of whether it is explicitly described.

[0083] It should be understood that the terms or words used in this article are for descriptive purposes, not for limiting purposes. Therefore, the terms or words used in this article should be interpreted by those skilled in the art based on the teachings of this article.

[0084] By way of example, and not limitation, a nanostructured transistor, such as a gate-all-around nanosheet or nanowire field-effect transistor (collectively referred to as a "gate-all-around field-effect transistor") having nanosheet (NS) or nanowire (NW) channel regions, can be formed as follows: A fin structure having alternating layers of silicon-germanium (SiGe) and silicon (Si) nanosheets or nanowires is formed on a substrate (e.g., on a semiconductor substrate). A sacrificial gate structure is then formed at the middle portion of the fin structure to cover the top and sidewall surfaces of the fin structure, such that the edge portions of the fin structure are not covered by the sacrificial gate structure. The edge portions of the fin structure not covered by the sacrificial gate structure are removed. Subsequently, the edge portions of the silicon-germanium nanosheet or nanowire layers are recessed relative to the edge portions of the silicon nanosheet or nanowire layers, and the spaces formed by the etched portions of the silicon-germanium nanosheet or nanowire layers are filled by depositing a dielectric material, thereby forming an internal spacer structure. Then, a source / drain (S / D) epitaxial structure is formed adjacent to (or in contact with) the edge portion of the fin structure, such that the source / drain epitaxial structure contacts the silicon nanosheets or nanowire layers and is isolated (or separated) from the silicon-germanium nanosheets or nanowire layers by an internal spacer structure. The source / drain may refer to the source or drain individually or collectively, depending on the context. In the following operations, the sacrificial gate structure is removed to expose the top and sidewall surfaces of the fin structure. The silicon-germanium nanosheets or nanowire layers are selectively removed from the fin structure. In the selective removal process, the silicon nanosheets or nanowire layers and the internal spacer structure are not removed. Subsequently, a metal gate structure is formed surrounding the silicon nanosheets or nanowire layers. Similar to before the selective removal of the silicon-germanium nanosheets or nanowire layers, the metal gate structure is isolated (or separated) from the source / drain epitaxial structure by an internal spacer structure.

[0085] The structure of a gate-all-around field-effect transistor (GAW) can be patterned using any suitable method. For example, the structure can be patterned using one or more lithography processes, including dual-patterning or multi-patterning processes. Dual-patterning or multi-patterning processes combine lithography and self-alignment processes to create patterns with smaller pitches than those achievable using a single, direct lithography process. For example, in some embodiments, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAW structure.

[0086] As semiconductor devices continue to shrink, the critical dimensions of the gate-all-around (GAO) field-effect transistor (FET) formed by the above-described process—such as the length / width of the silicon nanosheet or nanowire layer serving as the channel—are becoming increasingly smaller. These channels can be formed by removing a portion of the silicon-germanium nanosheet or nanowire layer, thereby creating openings with a high aspect ratio in the fin structure. Due to the high aspect ratio, challenging problems arise during opening formation. Specifically, in the silicon-germanium nanosheet or nanowire layer, the bottommost layer may have a less uniform shape (e.g., uneven thickness and / or length) compared to the corresponding layer above it. When the silicon-germanium nanosheet or nanowire layer is subsequently replaced by the gate structure, the bottommost gate structure may correspondingly have a less uniform shape. Therefore, the channel region under the bottommost gate structure in the substrate may have less effective gate control, resulting in leaky current channels between the opposing source / drain epitaxial structures of the GAO. Furthermore, the less uniform shape of the bottom silicon-germanium nanosheet or nanowire layer may also affect the geometry of the adjacent bottom inner spacer, thus causing leakage current between the source / drain epitaxial structure and the bottom gate structure.

[0087] The embodiments described herein are designed to overcome the aforementioned challenges. In some embodiments, the gate-all-around field-effect transistor (GAFET) may include an isolation layer beneath the source / drain epitaxial structure of the GAFET. The isolation layer may include silicon oxide and may be formed by a flowable chemical vapor deposition (FCVD) process. The isolation layer may be disposed on the side of the bottommost inner spacer structure of the GAFET and protrude into the substrate. The isolation layer may suppress leakage current across the substrate between opposing source / drain epitaxial structures. The isolation layer may also suppress leakage current across the bottommost inner spacer structure between the gate structure and the source / drain epitaxial structure of the GAFET. Furthermore, the isolation layer may increase the gate capacitance between the gate structure and the source / drain epitaxial structure of the GAFET.

[0088] According to some implementation methods, refer to Figure 1 and Figure 2 A semiconductor device 100 having a plurality of gate-all-around field-effect transistors 105 formed on a substrate 102. Figure 1 An isometric view of a semiconductor device 100 according to some embodiments is shown. The semiconductor device 100 may be included in a microprocessor, memory cell, or other integrated circuit (IC). Figure 2 A semiconductor device 100 according to some embodiments is shown along... Figure 1 A cross-sectional view of line BB (e.g., a plane formed along the x and z directions).

[0089] Reference Figure 1 The substrate 102 may be a semiconductor material, such as silicon. In some embodiments, the substrate 102 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 may include (i) an elemental semiconductor, such as silicon (Si) or germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide phosphide (GaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. Furthermore, the substrate 102 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, the crystal orientation of the substrate 102 may be (100), (110), or (111).

[0090] although Figure 1 and Figure 2 A fin structure 110 with two gate-all-around field-effect transistors 105 is shown, but any number of gate-all-around field-effect transistors 105 may be arranged along the fin structure 110. In some embodiments, the gate-all-around field-effect transistors 105 may include a plurality of fin structures 110 extending along a first horizontal direction (e.g., in direction x) and a gate structure 115 crossing these fin structures 110 along a second horizontal direction (e.g., in direction y). In some embodiments, the crystal orientation of the fin structure 110 may be the same as the crystal orientation of the substrate 102.

[0091] Reference Figure 1 and Figure 2One or more nanosheet (NS) layers 120 may be disposed on the fin structure 110. Each nanosheet layer 120 may be enclosed by a gate structure 115 to serve as a channel for a gate-all-around field-effect transistor 105. For example, the top, side, and bottom surfaces of each nanosheet layer 120 may be enclosed by and physically contacted with the gate structure 115. The fin structure 110 and the nanosheet layer 120 may be made of a material similar to (e.g., having a lattice mismatch rate of about 5%) the substrate 102. In some embodiments, the crystal orientation of the nanosheet layer 120 may be the same as that of the fin structure 110. In some embodiments, each of the fin structure 110 and the nanosheet layer 120 may be made of silicon or silicon-germanium. Each of the fin structure 110 and the nanosheet layer 120 may be undoped, doped with a p-type dopant, doped with an n-type dopant, or doped with an intrinsic dopant. In some embodiments, the fin structure 110 and the nanosheet layer 120 may be commonly doped with a p-type dopant or an n-type dopant. Although Figure 1 The diagram shows that each gate-all-around field-effect transistor 105 includes four nanosheet layers 120, and Figure 2 The diagram shows that each gate-all-around field-effect transistor 105 includes three nanosheet layers 120, but each gate-all-around field-effect transistor 105 may include any number of nanosheet layers 120. For example, each gate-all-around field-effect transistor 105 may include one, two, five, or six nanosheet layers 120.

[0092] Reference Figure 1 and Figure 2 The gate structure 115 may be a multilayer structure encapsulating each nanosheet layer 120 to modulate the gate-all-around field-effect transistor 105. The gate structure 115 may have a length Lc representing the channel length of the gate-all-around field-effect transistor 105. The length Lc may have any suitable horizontal (e.g., in direction x) dimension, for example from about 3 nm to about 200 nm. In some embodiments, the height of the gate structure 115 along the vertical direction (e.g., in direction z) above the fin structure 110 may be between about 12 nm and about 14 nm. In some embodiments, the height of the gate structure 115 above the fin structure 110 may be greater than about 14 nm. Exemplarily but not limitingly, each gate structure 115 may include a stack of dielectrics formed by an interface dielectric layer 115a and a gate dielectric layer 115b. Furthermore, each gate structure 115 includes a capping layer, one or more work function metal layers, and a metal filler (not shown for simplicity). Figure 1The gate electrode 115c (shown separately) is a gate electrode. The gate dielectric layer 115b may comprise any suitable dielectric material and have any suitable thickness to provide channel adjustment for the gate all-around field-effect transistor 105. In some embodiments, the gate dielectric layer 115b may be made of silicon oxide or a high-k dielectric material (e.g., hafnium oxide or aluminum oxide). In some embodiments, the gate dielectric layer 115b may have a thickness of about 1 nm to about 5 nm. Other materials and thicknesses of the gate dielectric layer 115b as disclosed herein are also within the scope and spirit of this disclosure. The gate electrode 115c may be used as the gate terminal of the gate all-around field-effect transistor 105. The gate electrode 115c may comprise any suitable conductive material, and these conductive materials provide a suitable work function to adjust the gate all-around field-effect transistor 105. In some embodiments, the gate electrode 115c may be made of titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, or nickel. Based on the disclosure herein, other materials of the gate electrode 115c also fall within the scope and spirit of this disclosure.

[0093] Reference Figure 1 and Figure 2 The source / drain epitaxial structure 125 may be disposed on opposite sides of each nanosheet 120 (e.g., along direction x) to serve as the source and drain terminals of the gate-all-around field-effect transistor 105. The source / drain epitaxial structure 125 may be disposed on the fin structure 110. In some embodiments, the source / drain epitaxial structure 125 may be disposed above an isolation layer 145 on the fin structure 110, such that the source / drain epitaxial structure 125 is electrically isolated from the fin structure 110. The source / drain epitaxial structure 125 may be made of an epitaxially grown semiconductor material similar to (e.g., with a lattice mismatch rate within about 5%) the nanosheet 120. In some embodiments, the source / drain epitaxial structure 125 may be made of Si, Ge, SiGe, InGaAs, or GaAs. The source / drain epitaxial structure 125 may be doped with p-type dopant, n-type dopant, or intrinsic dopant. In some embodiments, the doping type of the source / drain epitaxial structure 125 may differ from that of the nanosheet 120. In some embodiments, the n-type dopant in the source / drain epitaxial structure 125 may include P, As, Sb, and / or combinations thereof. In some embodiments, the crystal orientation of the source / drain epitaxial structure 125 may be the same as that of the nanosheet 120.

[0094] Each source / drain epitaxial structure 125 may include epitaxial region 250, epitaxial region 253, and epitaxial region 255, such as Figure 2As shown. Epitaxial regions 250, 253, and 255 can be formed at different stages of the epitaxial process. Each epitaxial region 250 can be epitaxially grown from the side of the nanosheet 120, extending in a horizontal direction (e.g., along direction x), and spaced apart from each other. Each epitaxial region 250 may have a perpendicular interface with the nanosheet 120 and a tilted or curved surface opposite the perpendicular interface. Epitaxial region 253 may be epitaxially grown from the tilted or curved surface of epitaxial region 250. Each source / drain epitaxial structure 125 may include two epitaxial regions 253 disposed on both sides of the source / drain epitaxial structure 125. Each epitaxial region 253 may be a continuous epitaxial layer connecting all epitaxial regions 250, wherein the epitaxial regions 250 are vertically disposed on one of the two sides of the source / drain epitaxial structure 125. Epitaxial regions 255 can be epitaxially grown from the sides of epitaxial regions 253 and can extend in a vertical direction (e.g., along direction z). Each epitaxial region 255 can connect to two epitaxial regions 253 within each source / drain epitaxial structure 125. In some embodiments, the distance L1 between two source / drain epitaxial structures 125 on opposite sides of the gate-all-around field-effect transistor 105 can be between about 5 nm and about 250 nm. In some embodiments, the doping concentrations of epitaxial regions 250, 253, and 255 can be different. For example, the doping concentration of epitaxial region 255 can be greater than that of epitaxial region 253, and the doping concentration of epitaxial region 253 can be greater than that of epitaxial region 250. In some embodiments, the relatively low doping concentration of epitaxial region 250 can prevent dopant from unnecessarily diffusing into nanosheet 120, as this could impair the conductivity of nanosheet 120. In some implementations, the relatively high doping concentration of the epitaxial region 255 can reduce the contact resistance between the source / drain contact 163 and the source / drain epitaxial structure 125.

[0095] Reference Figure 1 and Figure 2The semiconductor device 100 may include an internal spacer structure 130 adjacent to (or in contact with) the side of the gate structure 115. The internal spacer structure 130 may space the gate structure 115 away from the source / drain epitaxial structure 125. For example, the internal spacer structure 130 may be formed on opposite sides of the gate structure 115 along the channel direction (e.g., along direction x) of the gate-around-the-field-effect transistor 105 to space the gate structure 115 away from the source / drain epitaxial structure 125. In some embodiments, the internal spacer structure 130 may be formed between two vertically (e.g., in direction z) adjacent nanosheet layers 120. In some embodiments, the internal spacer structure 130 may be formed between the fin structure 110 and the nanosheet layer 120. In some embodiments, the internal spacer structure 130 may include a silicon-based dielectric, such as silicon nitride (SiN), silicon carbonitride oxynitride (SiOCN), silicon carbonitride (SiCN), or silicon oxynitride (SiON). In some embodiments, the internal spacer structure 130 may include a low-k material, such as a porous material and a carbon-rich silicon oxide-based dielectric.

[0096] Reference Figure 1 and Figure 2 The semiconductor device 100 may include an isolation layer 145 disposed on the fin structure 110 and below the source / drain epitaxial structure 125. In processes including etching openings with high aspect ratios, when forming the source / drain epitaxial structure 125, the bottommost gate structure of the gate structure 115 may form a less uniform shape, resulting in poor control over the conductivity of the fin structure 110 below the bottommost gate structure. Therefore, a leakage current path 170 may be formed in the region of the fin structure 110 between the source / drain epitaxial structures 125 below the bottommost gate electrode 115cb. The presence of the isolation layer 145 below the source / drain epitaxial structure 125 effectively blocks the leakage current path 170. The isolation layer 145 present below the source / drain epitaxial structure 125 also blocks leakage current and increases the gate capacitance between the source / drain epitaxial structure 125 and the bottommost gate electrode 115cb. In some embodiments, the isolation layer 145 may contact the epitaxial region 253 and the epitaxial region 255. In some embodiments, depending on the position of the top surface 145t of the isolation layer 145, the isolation layer 145 may contact or isolate the epitaxial region 250. In some embodiments, the top surface 145t may be planar. In some embodiments, the top surface 145t may be curved, such as concave or convex. In some embodiments, the isolation layer 145 may include an oxide material, such as silicon oxide. In some embodiments, the isolation layer 145 may be formed in a flowable chemical vapor deposition (FCVD) process. In some embodiments, the isolation layer 145 may protrude into the fin structure 110. In some embodiments, such as Figure 2As shown, the depth D1 of the isolation layer 145 protruding into the fin structure 110 can be between about 40 nm and about 60 nm. For example, the depth D1 can be between about 50 nm and about 55 nm. In some embodiments, the bottom surface 145s of the isolation layer 145 in contact with the fin structure 110 may be curved. In some embodiments, the isolation layer 145 may extend above the fin structure 110. In some embodiments, such as Figure 2 As shown, the height D2 of the isolation layer 145 extending above the fin structure 110 can be between about 0 nm and about 20 nm. For example, the height D2 can be about 5 nm to about 10 nm. The isolation layer 145 can be disposed on the side of the bottommost inner spacer structure 130b, such as... Figure 2 As shown. In some embodiments, the distance L2 between the two isolation layers 145 under the two source / drain epitaxial structures 125 of the gate-all-around field-effect transistor 105 can be between about 55 nm and about 250 nm. The distance L2 can also correspond to the horizontal distance between the two outer sides of the two bottommost inner spacer structures 130b of the gate-all-around field-effect transistor 105. Similarly, the distance L1 corresponds to the horizontal distance between the two outer sides of the two opposing inner spacer structures 130 on the bottommost inner spacer structure 130b. In some embodiments, the distance L1 can be greater than the length Lc. In some embodiments, the distance L2 can be greater than the distance L1 due to the above-described etching process that creates openings with a high aspect ratio. In some embodiments, the ratio of distance L1 to distance L2 can be between about 0.8 and about 1.

[0097] Reference Figure 1 and Figure 2 The semiconductor device 100 may further include a gate spacer 135 formed between the gate structure 115 and the source / drain epitaxial structure 125 to provide structural support during the formation of the gate structure 115. Furthermore, the gate spacer 135 may be located at the source / drain contact (in... Figure 1 The gate spacer 135 provides electrical isolation and protection for the gate structure 115 during its formation process (not shown in the diagram). The gate spacer 135 can be made of any suitable dielectric material. In some embodiments, the gate spacer 135 can be made of silicon oxide, silicon nitride, or a low-k material with a dielectric constant less than about 3.9. In some embodiments, the gate spacer 135 can have any suitable thickness, for example, from about 5 nm to about 15 nm. Other materials and thicknesses of the gate spacer 135 are also within the scope and spirit of this disclosure based on the present disclosure.

[0098] Reference Figure 1 and Figure 2The semiconductor device 100 may further include a shallow trench isolation (STI) region 138 configured to provide electrical isolation between the fin structures 110. Furthermore, the shallow trench isolation region 138 may also provide electrical isolation between the gate-all-around field-effect transistor 105 and adjacent active and passive components integrated or deposited on the substrate 102. The shallow trench isolation region 138 may include one or more layers of dielectric material, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the shallow trench isolation region 138 may contact the isolation layer 145, such as... Figure 1 As shown. In some embodiments, the shallow trench isolation region 138 and the isolation layer 145 may comprise the same dielectric material. In some embodiments, the shallow trench isolation region 138 and the isolation layer 145 may comprise different dielectric materials. In some embodiments, the interface between the shallow trench isolation region 138 and the fin structure 110 and the interface between the shallow trench isolation region 138 and the isolation layer 145 may be coplanar. Based on the disclosure herein, other dielectric materials used for the shallow trench isolation region 138 are also within the scope and spirit of this disclosure.

[0099] Reference Figure 1 and Figure 2 The semiconductor device 100 may further include an interlayer dielectric (ILD) layer 165 to provide electrical isolation to surrounding or covered structural elements, such as providing electrical isolation to the gate structure 115 and the source / drain epitaxial structure 125. In some embodiments, a gate spacer 135 may be formed between the gate structure 115 and the interlayer dielectric layer 165. The interlayer dielectric layer 165 may include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, and silicon carbonitride. The interlayer dielectric layer 165 may have any suitable thickness, for example from about 50 nm to about 200 nm, to provide electrical insulation. Other insulating materials and thicknesses used for the interlayer dielectric layer 165 as disclosed herein are also within the scope and spirit of this disclosure.

[0100] Reference Figure 1 and Figure 2The semiconductor device 100 may further include a source / drain contact 163 that contacts the source / drain epitaxial structure 125. The source / drain contact 163 may be disposed on the source / drain epitaxial structure 125 and surrounded by an interlayer dielectric layer 165. In some embodiments, the height of the source / drain contact 163 may be between about 27 nm and about 33 nm. The source / drain contact 163 may comprise any suitable conductive material that provides low contact resistance with the source / drain epitaxial structure 125. In some embodiments, the source / drain contact 163 may be made of polysilicon, titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, or nickel. Other materials for the source / drain contact 163 as disclosed herein are also within the scope and spirit of this disclosure.

[0101] Figures 3A to 3C Show Figure 2 Enlarged portion 300 in the cross-sectional view. Figures 3A to 3C Embodiments of isolation layers 145 with different heights D2 are shown. Unless otherwise stated, Figure 1 and Figure 2 The discussion of elements with the same symbol is applicable to Figures 3A to 3C In the discussion.

[0102] Reference Figure 3A The isolation layer 145 may have a top surface 145t that is coplanar with the top surface 130bt of the bottommost internal spacer structure 130b. In some embodiments, by having the top surface 145t and the top surface 130bt coplanar, the isolation layer 145 may cover the entire side surface 130bs of the bottommost internal spacer structure 130b, thereby isolating the source / drain epitaxial structure 125 from the bottommost internal spacer structure 130b and suppressing leakage current between the source / drain epitaxial structure 125 and the bottommost gate electrode 115cb. In some embodiments, by having the top surface 145t and the top surface 130bt coplanar, the isolation layer 145 does not cover the side surface 120bs of the bottommost nanosheet layer 120b, thereby not reducing the contact area and contact conductivity between the source / drain epitaxial structure 125 and the bottommost nanosheet layer 120b. When the top surface 145t reaches the same vertical position as the top surface 130bt, the top surface 145t can be made coplanar with the top surface 130bt by terminating the flowable chemical vapor deposition process in the process of forming the isolation layer 145. In some embodiments, by making the top surface 145t coplanar with the top surface 130bt, the top surface 145t can contact the bottom endpoint of the bottommost epitaxial region 250b.

[0103] Reference Figure 3BIn some embodiments, the isolation layer 145 may have a top surface 145t lower than the top surface 130bt of the bottommost inner spacer structure 130b. For example, the vertical distance T3 from the top surface 130bt to the top surface 145t may be non-zero. In some embodiments, when the vertical distance T3 is non-zero, the requirement for precise control of the vertical position of the top surface 145t during the formation of the isolation layer 145 can be reduced. In some embodiments, the ratio of the vertical distance T3 to the height D2 may be between approximately 0 and approximately 0.5. In some embodiments, if the ratio of the vertical distance T3 to the height D2 is greater than approximately 0.5, the contact area between the side surface 130bs of the bottommost inner spacer structure 130b and the source / drain epitaxial structure 125 may be too large, resulting in leakage current between the source / drain epitaxial structure 125 and the bottommost gate electrode 115cb that may not be effectively suppressed. During the formation of the isolation layer 145, the top surface 145t can be formed below the top surface 130bt by terminating the flowable chemical vapor deposition process before the top surface 145t reaches the vertical position of the top surface 130bt. In some embodiments, the top surface 145t can be separated from the bottommost epitaxial region 250b by being lower than the top surface 130bt.

[0104] Reference Figure 3C In some embodiments, the insulating layer 145 may have a top surface 145t higher than the top surface 130bt of the bottommost inner spacer structure 130b. For example, the vertical distance T4 from the top surface 145t to the top surface 130bt may be non-zero, allowing the insulating layer 145 to contact the side surface 120bs of the bottommost nanosheet layer 120b. In some embodiments, when the vertical distance T4 is non-zero, the requirement for precise control of the vertical position of the top surface 145t during the formation of the insulating layer 145 can be reduced. In some embodiments, the ratio of the vertical distance T4 to the height D2 may be between approximately 0 and approximately 0.2. In some embodiments, if the ratio of the vertical distance T4 to the height D2 is greater than approximately 0.2, the contact area between the bottommost nanosheet layer 120b and the source / drain epitaxial structure 125 may be too small, potentially impairing the contact conductivity between the source / drain epitaxial structure 125 and the bottommost nanosheet layer 120b. During the formation of the isolation layer 145, after the top surface 145t reaches the vertical position of the top surface 130bt, the top surface 145t can be formed above the top surface 130bt by terminating the flowable chemical vapor deposition process. In some embodiments, by having the top surface 145t higher than the top surface 130bt, the top surface 145t can contact the bottom surface of the bottommost epitaxial region 250b.

[0105] although Figures 3A to 3CThe three embodiments of the isolation layer 145 shown are different, but those skilled in the art will understand that different features of these embodiments may be included in one embodiment. For example, the gate-all-around field-effect transistor 105 may include a first source / drain epitaxial structure 125 located on a first isolation layer 145 and a second source / drain epitaxial structure 125 located on a second isolation layer 145, wherein (i) the first top surface 145t of the first isolation layer 145 is coplanar with the first top surface 130bt of the first bottom inner spacer structure 130b of the first adjacent first isolation layer 145, and (ii) the second top surface 145t of the second isolation layer 145 is higher or lower than the second top surface 130bt of the second bottom inner spacer structure 130b of the second adjacent second isolation layer 145. In some embodiments, the first and second isolation layers 145 of the gate-all-around field-effect transistor 105 may have, for example, Figures 3A to 3C Any combination of the embodiments shown.

[0106] According to some implementation methods Figure 4 Showing the formation Figures 1 to 3C The flowchart illustrates a method 400 for manufacturing the gate-all-around field-effect transistor 105 shown. This disclosure is not limited to the description of these operations, and other operations may be performed. Other manufacturing operations may be performed between various operations of method 400 and may be omitted for clarity. Furthermore, not all operations provided herein need to be performed. Additionally, some operations may be performed simultaneously or in conjunction with… Figure 4 The different sequences of execution are shown. In some implementations, one or more other operations may be performed to supplement or replace the currently described operations. For ease of illustration, refer to... Figures 5 to 17 The structure described is shown in method 400. Unless otherwise stated, Figures 1 to 3C The discussion of elements with the same symbol is applicable to Figures 5 to 17 The discussion.

[0107] Reference Figure 4 Method 400 begins with operation 405, a process of forming alternating stacks of first nanosheets and second nanosheets on a substrate (e.g., substrate 102). Figure 5 This is an isometric view of the substrate 102 after operation 405, showing a stack 520 formed by alternating first nanosheets 520a and second nanosheets 520b. In some embodiments, the first nanosheets 520a and second nanosheets 520b are formed on the exposed top surface of the substrate 102. In some embodiments, the first nanosheet 520a is a sacrificial nanosheet to be subsequently removed, and the second nanosheet 520b corresponds to... Figure 1The nanosheet layer 120 is shown. In some embodiments, the material of the first nanosheet layer 520a in the stack 520 is selected such that the first nanosheet layer 520a can be selectively removed by etching from the stack 520, but the second nanosheet layer 520b is not removed. For example, the first nanosheet layer 520a may be a silicon-germanium nanosheet layer, and the second nanosheet layer 520b may be a silicon nanosheet layer.

[0108] The first nanosheet 520a and the second nanosheet 520b can be grown using any suitable method. For example, the first nanosheet 520a and the second nanosheet 520b can be grown by chemical vapor deposition, using precursor gases such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), germanane (GeH4), digermanane (Ge2H6), other suitable gases, or combinations thereof. In some embodiments, the first nanosheet 520a may include germanium at a concentration between about 20% and about 30%, but the nanosheet 120 is substantially germanium-free, for example, having a germanium concentration of less than about 1%. In some embodiments, the second nanosheet 520b corresponds to... Figure 1 The nanosheet layer 120 forms the channel region of the gate-all-around field-effect transistor 105 and can be lightly doped or intrinsic (e.g., undoped). If lightly doped, the doping amount of the second nanosheet layer 520b is less than about 10. 13 atoms / cm 3 The first nanosheet 520a and the second nanosheet 520b can be deposited sequentially without vacuum interruption (e.g., in situ) to avoid the formation of any intermediate layers. In some embodiments, the first nanosheet 520a can be doped in subsequent etching operations compared to the second nanosheet 520b to increase the etching selectivity for the first nanosheet 520a.

[0109] In some embodiments, the thickness of the first nanosheet 520a controls the spacing between each second nanosheet 520b in the stack 520. For example, the thicknesses of the first nanosheet 520a and the second nanosheet 520b can range from about 3 nm to about 15 nm. Since the first nanosheet 520a and the second nanosheet 520b are grown individually, the thickness of each nanosheet can be adjusted independently based on deposition time, etc. In some embodiments, more or fewer first nanosheets 520a and second nanosheets 520b can be formed in the stack 520. In some embodiments, the total number of nanosheets can be 2n, where n is the number of first nanosheets 520a or the number of second nanosheets 520b in the stack 520. In some embodiments, n can be 1, 2, 3, 4, 5, 6, or any integer greater than 6.

[0110] Reference Figure 4 Method 400 continues to operation 410, a process for patterning stack 520 to form a fin structure. In some embodiments, stack 520 is patterned to form a fin structure having a width along the y-direction and a length along the x-direction. The fin structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fin structure, including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes combine lithography and self-alignment processes, thereby creating patterns with smaller spacing than that achievable using a single and direct lithography process. For example, in some embodiments, a sacrificial layer is formed on stack 520 and patterned by a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are used as a mask structure to pattern the fin structure.

[0111] Exemplary and not restrictive, Figure 6 This is an isometric view of the fin structure 620 formed by stacking 520 through the patterning process described in operation 410. In some embodiments, the fin structure 620 can be formed by etching the first nanosheet 520a and the second nanosheet 520b into the first nanosheet 620a and the second nanosheet 620b. In some embodiments, the patterning process does not terminate at the top surface of the substrate 102, but continues to etch the top of the substrate 102 to form the fin structure 110 from the substrate 102 below the fin structure 620. Since the fin structure 620 and the fin structure 110 are formed using the same patterning process, the fin structure 620 and the fin structure 110 are substantially aligned with each other. For example, the sidewall surfaces of the fin structure 620 in the plane formed by directions x and z and in the plane formed by directions y and z are substantially aligned with the corresponding sidewall surfaces of the fin structure 110, such as... Figure 6 As shown.

[0112] Additional fin structures, such as fin structure 620, may be formed on substrate 102 in the same or different regions. For simplicity, Figure 6 These additional fin structures are not illustrated. By way of example and not limitation, each fin structure 620 has a width along the y-direction and ranges from about 15 nm to about 150 nm.

[0113] In some embodiments, the first nanosheet layer 620a and the second nanosheet layer 620b are referred to as "nanosheets" when their widths along the y-direction are substantially different from their heights along the z-direction. For example, when their widths are greater than / less than their heights. In some embodiments, the first nanosheet layer 620a and the second nanosheet layer 620b may also be referred to as "nanowires" when their widths along the y-direction are substantially equal to their heights along the z-direction. In some embodiments, the first nanosheet layer 620a and the second nanosheet layer 620b are deposited as nanosheets and subsequently patterned to form nanowires with substantially equal heights and widths. By way of example and not limitation, the first nanosheet layer 620a and the second nanosheet layer 620b are described herein as nanosheet (NS) layers. Nanowires (NW) are also within the spirit and scope of this disclosure as disclosed herein. Furthermore, for illustrative purposes and without limiting the scope of this disclosure, the first nanosheet 620a and the second nanosheet 620b in method 400 are described herein as nanosheets of silicon-germanium and silicon, respectively.

[0114] In some embodiments, after forming the fin structure 620, a shallow trench isolation region 138 may be formed on an etched or recessed portion of the substrate 102 to cover the sidewall surface of the fin structure 110. In some embodiments, the shallow trench isolation region 138 may electrically isolate the fin structure 110 and include one or more silicon oxide-based dielectrics. Exemplarily, and not limitingly, the shallow trench isolation region 138 may be formed as follows: A material of the isolation structure (e.g., a silicon oxide-based dielectric) is deposited covertly on the fin structure 620 and the substrate 102. The material of the thus deposited isolation structure may be planarized (e.g., by a chemical mechanical polishing (CMP) process) such that the top surface of the material of the isolation structure is substantially coplanar with the top surface of the fin structure 620. The planarized material of the isolation structure is then etched back so that the resulting shallow trench isolation region 138 has a height substantially similar to that of the fin structure 110, such as... Figure 6 As shown. In some embodiments, the fin structure 620 protrudes from the shallow trench isolation region 138, such that the shallow trench isolation region 138 does not cover the sidewall portion of the fin structure 620, as shown. Figure 6 As shown. This was intentional and can promote, for example... Figure 1 The formation of the gate-all-around field-effect transistor 105 shown.

[0115] Method 400 continues to operation 415, a process of removing a portion of the fin structure to form an opening in the fin structure, including (i) forming such as Figure 7 The sacrificial gate structure 700 is shown, and (ii) the portion of the fin structure 620 exposed by the sacrificial gate structure 700 is removed, as shown. Figure 8As shown.

[0116] In some embodiments, the sacrificial gate structure 700 is formed having a length along the direction y (e.g., perpendicular to). Figure 6 The isometric view shows the fin structure 620, which has a width along the direction x. Exemplary and not limiting, Figure 7 yes Figure 6 Cross-sectional view along cutting line AB. Figure 7 This shows a sacrificial gate structure 700 formed on a portion of the fin structure 620. Because... Figure 7 This is a cross-sectional view, not an isometric view; a portion of the sacrificial gate structure 700 covering the sidewall portion of the fin structure 620 is not shown. Furthermore, in Figure 7 In the cross-sectional view, only the following are shown. Figure 6 One of the fin structures 620. In some embodiments, portions of the sacrificial gate structure 700 are formed between the fin structures 620 and on the shallow trench isolation region 138, such as Figure 6 As shown.

[0117] In some embodiments, the sacrificial gate structure 700 may cover the top and sidewall portions of the fin structure 620. Subsequently, in a gate replacement process, the sacrificial gate structure 700 is... Figure 1 The gate structure 115 shown is replaced. The sacrificial gate structure 700 may include a sacrificial gate dielectric (not shown for simplicity). Figure 7 The sacrificial gate electrode 700a is formed on the diagram. The sacrificial gate structure 700 may also include a capping layer 705 formed on the top surface of the sacrificial gate structure 700. In some embodiments, the capping layer 705 protects the sacrificial gate electrode 700a from subsequent etching operations. During this manufacturing stage, a gate spacer 135 may be formed on the side surface of the sacrificial gate structure 700. As described above, the gate spacer 135 is not removed during the gate replacement process, and the gate spacer 135 helps to... Figure 1 The formation of the gate structure 115 shown.

[0118] By way of example, and not limitation, the sacrificial gate structure 700 can be formed by depositing and patterning the sacrificial gate electrode 700a on the fin structure 620. In some embodiments, the sacrificial gate structure 700 is formed on multiple fin structures 620. Figure 7 As shown, a portion of the fin structure 620 is not covered by the sacrificial gate structure 700. This is because the width of the sacrificial gate structure 700 is narrower than the length of the fin structure 620 along the x-direction. In some embodiments, the sacrificial gate structure 700 is used as a mask structure in subsequent etching operations to define, as... Figure 1The gate fully surrounds the channel region of the field-effect transistor 105 shown. Therefore, the lateral dimensions (e.g., width and length) of the sacrificial gate structure 700 and the gate structure 115 are substantially similar.

[0119] Reference Figure 8 The removal process can remove portions of the fin structure 620 not covered by the sacrificed gate structure 700. In some embodiments, the removal process involves a dry etching process, a wet etching process, or a combination thereof. The removal process is selective for the first nanosheet 620a and the second nanosheet 620b to form the first nanosheet 820a and nanosheet 120, respectively. The removal process can further remove portions of the fin structure 110. In some embodiments, the dry etching process includes an etchant containing oxygen-containing gas, fluorine-containing gas (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6)); chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), and / or boron trichloride (BCl3)); bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)); iodine-containing gas; other suitable etching gases and / or plasma; or combinations thereof. Wet etching chemicals may include diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia; solutions containing hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH); or combinations thereof.

[0120] In some embodiments, the etchant used in the above etching process does not substantially etch the sacrificial gate structure 700 protected by the capping layer 705 and the gate spacer 135, and as shown above. Figure 6 The shallow trench isolation region 138 is shown. This is because the capping layer 705, the gate spacer 135, and the shallow trench isolation region 138 comprise materials with low etch selectivity, such as silicon nitride-based materials (e.g., silicon nitride, silicon carbonitride, and silicon carbonitride oxide) or silicon oxide-based materials. In some embodiments, Figure 6 The shallow trench isolation region 138 shown is used as an etch stop layer in the above-described etching process.

[0121] Due to operation 415, an opening 840 is formed in each fin structure 620, such as Figure 8As shown. Opening 840 divides each fin structure 620 into a separated portion covered by the sacrificial gate structure 700. In some embodiments, the removal process in operation 415 may further include removing portions of fin structure 110 not covered by the remaining portions of fin structure 620, and the curved surface forming opening 840 on fin structure 110. Removing portions of fin structure 110 may include etching portions of fin structure 110 using a manner similar to etching portions of fin structure 620 not covered by the sacrificial gate structure 700.

[0122] Reference Figure 4 Method 400 continues to operation 420, a process for forming an internal spacer. The process for forming the internal spacer may include (i) selectively etching edge portions of the first nanosheet 820a to form, for example... Figure 9 As shown in the recessed structure 945, (ii) a dielectric material is deposited to fill the recessed structure 945, such as Figure 10 As shown, and (iii) removing the dielectric material outside the recessed structure 945, such as Figure 11 As shown. According to some implementation methods, Figure 9 Show Figure 8 The exposed edge of the first nanosheet 820a is laterally etched (e.g., recessed) along the x-direction to form the structure of the first nanosheet 920a. According to some embodiments, the exposed edge of the first nanosheet 820a is recessed (e.g., partially etched) along the x-direction for a range of approximately 3 nm to approximately 10 nm to form a structure such as... Figure 9 The recessed structure shown is 945.

[0123] In some embodiments, selective etching of the first nanosheet layer 820a can be achieved using a dry etching process selective for silicon and germanium. For example, halogen-based chemicals exhibit high etching selectivity for germanium but low etching selectivity for silicon. Therefore, halogen gas etching of germanium-containing layers (e.g., the first nanosheet layer 820a) is faster than etching layers that are substantially germanium-free, such as nanosheet layer 120. In some embodiments, halogen-based chemicals include fluorine-based and / or chlorine-based gases. Alternatively, wet etching chemicals with high selectivity for silicon and germanium can be used. Exemplarily, and not limitingly, wet etching chemicals may include a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), or a mixture of ammonium hydroxide and hydrogen peroxide and water (APM). The etching process described above is timed to remove the desired amount of silicon and germanium.

[0124] In some embodiments, the first nanosheet 820a with a higher germanium atom concentration exhibits a higher etching rate than the nanosheet 120 with a lower or zero germanium atom concentration. Therefore, the etching rate of the above-described etching process can be adjusted by changing the germanium atom concentration (e.g., germanium content) in the first nanosheet 820a. As described above, the germanium content in the first nanosheet 820a can be between about 20% and about 30%. A silicon-germanium nanosheet with about 20% germanium can be etched more slowly than a silicon-germanium nanosheet with about 30% germanium. Therefore, the germanium concentration can be adjusted accordingly to achieve the desired etching rate and selectivity between the first nanosheet 820a and the nanosheet 120.

[0125] Reference Figures 9 to 11 The internal spacer structure 130 may be formed in the recessed structure 945. In some embodiments, forming the internal spacer structure 130 may include (i) in Figure 9 A dielectric layer 1030 with a thickness between approximately 2 nm and approximately 7 nm is deposited over the entire structure, such as... Figure 10 As shown, and (ii) removing the portion of dielectric layer 1030 outside the recessed structure 945 to leave the internal spacer structure 130 in the recessed structure 945 for filling, as Figure 11 As shown.

[0126] Reference Figure 4 Method 400 continues to operation 425, the process of forming an isolation layer in the opening. For example... Figure 12 As shown, the isolation layer 145 can be deposited on the bottom surface of the opening 840 to fill the space left by the removal of a portion of the fin structure 110. In some embodiments, the isolation layer 145 can be deposited until the top surface 145t of the isolation layer 145 is above the fin structure 110. For example, the isolation layer 145 can be deposited until the top surface 145t is located at a vertical position that is substantially similar to or substantially the same as the top surface 130bt of the bottommost inner spacer structure 130b, such as... Figures 3A to 3C The implementation method is shown below.

[0127] In some embodiments, the isolation layer 145 can be formed by forming a silicon oxide layer. In some embodiments, the isolation layer 145 can be formed by performing a flowable chemical vapor deposition (FCVD) process. In a flowable chemical vapor deposition process, a flowable dielectric material is deposited instead of silicon oxide. As the name suggests, the flowable dielectric material can "flow" during the deposition process to fill gaps or spaces (e.g., openings 840) with high aspect ratios. In a flowable chemical vapor deposition process, various chemicals can be added to the silicon-containing precursor to make the deposited film flowable. In some embodiments, nitrogen-hydrogen bonds can be added. Flowable dielectric precursors (particularly flowable silicon oxide precursors) include silicates, siloxanes, methyl silsesquioxane (MSQ), hydrogensilsesquioxane (HSQ), MSQ / HSQ, perhydrosilazane (TCPS), perhydro-polysilazane (PSZ), tetraethyl orthosilicate (TEOS), or silylamine (e.g., trisilylamine (TSA)). These flowable silicon oxide materials are formed in multiple processing steps. After depositing the flowable film, it is cured and then annealed to remove unwanted elements, thereby forming silicon oxide at the bottom of the gaps or spaces. As the unwanted elements are removed, the flowable film becomes denser and shrinks. In some embodiments, multiple annealing operations are performed. The flowable film is then cured and annealed.

[0128] Reference Figure 4 Method 400 continues to operation 430, a process for forming source / drain epitaxial structures on the isolation layer and in the opening. For example, as... Figures 13 to 15 As shown, the source / drain epitaxial structure 125 can be formed by sequentially growing epitaxial regions 250, 253 and 255 in the opening 840.

[0129] In some implementations, such as Figure 13 As shown, the epitaxial region 250 can be epitaxially grown using a process similar to chemical vapor deposition used in operation 405 to form a shape as shown in the diagram. Figure 5The first nanosheet 520a and the second nanosheet 520b are shown. In some embodiments, the epitaxial region 250 may be epitaxially grown along a horizontal direction (e.g., along direction x) on the side of the nanosheet 120. In some embodiments, the epitaxial region 250 may be grown using a plasma-enhanced chemical vapor deposition (PECVD) process. In some embodiments, a precursor gas (e.g., SiH4, SiH2Cl2, SiHCl3, and / or combinations thereof) may be used to grow a semiconductor material (e.g., silicon) having the same or similar crystal structure as the nanosheet 120. In some embodiments, an etching gas (e.g., hydrogen chloride (HCl)) may be used to selectively remove semiconductor material with an amorphous structure formed on the dielectric surface (e.g., on the side surfaces of the inner spacer structure 130 and the gate spacer 135, or on the top surface 145t of the isolation layer 145). Removing the semiconductor material with an amorphous structure ensures that the crystal structure of the epitaxial region 250 is crystalline. In some embodiments, a precursor gas for the dopant, such as phosphine (PH3), arsine (AsH3), antimony (SbH3), and / or combinations thereof, may be used to dope the epitaxial region 250 in a chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process.

[0130] In some implementations, such as Figure 14 As shown, epitaxial region 253 may be formed on the exposed side of epitaxial region 250. Unless otherwise stated, the description of the process for forming epitaxial region 250 applies to the process for forming epitaxial region 253. In some embodiments, epitaxial region 253 may be epitaxially grown on the side of epitaxial region 250 along horizontal and vertical directions (e.g., along directions x and z). In some embodiments, epitaxial region 253 may be formed in contact with the top surface 145t of isolation layer 145. In some embodiments, epitaxial region 253 may be doped to have a dopant concentration greater than that of epitaxial region 250. In some embodiments, the time and / or growth rate of epitaxial region 253 growth may be controlled to ensure that epitaxial regions 253 grown from epitaxial regions 250 on each side of opening 840 can extend sufficiently and connect together in the vertical direction (e.g., along direction z).

[0131] In some implementations, such as Figure 15As shown, epitaxial region 255 may be formed on the exposed side of epitaxial region 253. Unless otherwise stated, the description of the process for forming epitaxial region 250 and / or epitaxial region 253 applies to the process for forming epitaxial region 255. In some embodiments, epitaxial region 255 may be doped to have a dopant concentration greater than that of epitaxial region 253. In some embodiments, the growth time and / or growth rate of epitaxial region 255 may be controlled to ensure that epitaxial regions 255 grown from epitaxial regions 253 on opposite sides of opening 840 can extend sufficiently and connect together in the horizontal direction (e.g., along direction x).

[0132] Reference Figure 4 Method 400 continues to operation 435, a process for forming a metal gate structure. The process for forming the metal gate structure may include (i) removing the sacrificial gate structure 700 and the first nanosheet 920a, such as... Figure 16 As shown, and (ii) forming a metal gate structure 115 to surround the nanosheet layer 120, as Figure 17 As shown.

[0133] In some embodiments, removing the sacrificial gate structure 700 may include removing the capping layer 705 to expose the sacrificial gate electrode 700a, followed by removing the sacrificial gate electrode 700a to expose the fin structure 620 between the source / drain epitaxial structures 125. In some embodiments, removing the first nanosheet layer 920a may include selectively etching the first nanosheet layer 920a without removing the nanosheet layer 120, such as... Figure 16 As shown.

[0134] In some embodiments, forming the metal gate structure 115 may include (i) forming an interface dielectric layer 115a on the exposed surface of the nanosheet layer 120, (ii) forming a gate dielectric layer 115b on the interface dielectric layer 115a, and (iii) forming a gate electrode 115c on the gate dielectric layer 115b, such as Figure 17 As shown above, the metal gate structure 115 is electrically isolated from the source / drain epitaxial structure 125 by the inner spacer structure 130 and the gate spacer 135. In some embodiments, after forming the metal gate structure 115, an interlayer dielectric layer 165 may be formed to fill the space above the source / drain epitaxial structure 125, and a source / drain contact 163 may be formed through the interlayer dielectric layer 165 and contact the source / drain epitaxial structure 125.

[0135] This document describes an embodiment of a gate-all-around field-effect transistor (GAAFET) structure and a method for forming this structure. This structure includes an isolation layer beneath the source / drain epitaxial structures of the GAAFET. The isolation layer comprises silicon oxide and is formed by a flowable chemical vapor deposition process. The isolation layer is disposed on the side of the bottommost internal spacer structure of the GAAFET and protrudes into the substrate. The isolation layer suppresses leakage current across the substrate between the opposing source / drain epitaxial structures. The isolation layer also suppresses leakage current across the bottommost internal spacer structure between the gate structure and the source / drain epitaxial structures in the GAAFET.

[0136] In some embodiments, the semiconductor structure includes a substrate, a nanostructure element, a gate structure, an internal spacer structure, source / drain regions, and an isolation layer. The nanostructure element is on the substrate. The gate structure surrounds the nanostructure element. The internal spacer structure is adjacent to the gate structure and located below the nanostructure element. The source / drain regions are in contact with the sides of the nanostructure element. The isolation layer is located below the source / drain regions and is in contact with the sides of the internal spacer structure. In some embodiments, the top surface of the isolation layer is coplanar with the interface between the internal spacer structure and the nanostructure element. In some embodiments, the top surface of the isolation layer is located above the bottom surface of the internal spacer structure. In some embodiments, the isolation layer includes silicon oxide. In some embodiments, the bottom surface of the source / drain region is coplanar with the bottom surface of the nanostructure element. In some embodiments, the source / drain region includes: a first epitaxial layer on the side of the nanostructure element; and a second epitaxial layer on the convex surface of the first epitaxial layer. In some embodiments, the first and second epitaxial layers are in contact with the isolation layer.

[0137] In some embodiments, the semiconductor structure includes a substrate, multiple nanosheet layers, a gate structure, multiple internal spacers, an isolation layer, and a source / drain structure. The nanosheet layers are on the substrate. The gate structure surrounds the nanosheet layers. The internal spacers contact the gate structure. The isolation layer is on the side of the bottommost internal spacer. The source / drain structure is on the isolation layer and contacts the nanosheet layers. In some embodiments, the semiconductor structure includes a substrate, multiple nanosheet layers, a gate structure, multiple internal spacers, a source / drain structure, and an isolation layer. The nanosheet layers are on the substrate. The gate structure surrounds the nanosheet layers. The internal spacers contact the gate structure. The source / drain structure contacts the nanosheet layers. The isolation layer is located below the source / drain structure and contacts the side of the bottommost internal spacer. In some embodiments, the top surface of the isolation layer is coplanar with the top surface of the bottommost internal spacer. In some embodiments, the isolation layer protrudes into the substrate. In some embodiments, the interface between the isolation layer and the substrate is curved. In some embodiments, the source / drain structure is separated from the bottom inner spacer. In some embodiments, the semiconductor structure further includes: another isolation layer on the side of another bottom inner spacer; and another source / drain structure on another isolation layer, wherein the nanosheet layer is located between the source / drain structure and the other source / drain structure, and wherein the distance between the isolation layer and the other isolation layer is greater than the distance between the source / drain structure and the other source / drain structure.

[0138] In some embodiments, the semiconductor structure includes a substrate, nanostructured elements, a gate structure, a plurality of internal spacers, source / drain epitaxial structures, and an isolation layer. The nanostructured elements are on the substrate. The gate structure surrounds the nanostructured elements. The internal spacers are adjacent to the gate structure. The source / drain epitaxial structures are isolated from the gate structure by these internal spacers. The isolation layer is located below the source / drain epitaxial structures and contacts the side of the bottommost internal spacer.

[0139] In some embodiments, a method of forming a semiconductor structure includes the following operations: forming a plurality of channel layers and a plurality of sacrificial layers alternately stacked on a substrate; forming openings through the stack and into the substrate; removing a portion of each of the sacrificial layers exposed in the openings to form a plurality of recess structures; forming a plurality of internal spacers in the recess structures; forming an isolation layer on the bottom surface of the openings and on the side surface of the bottommost internal spacer; forming an epitaxial region on the isolation layer. In some embodiments, forming the isolation layer includes performing flowable chemical vapor deposition to deposit oxide material on the bottom surface of the openings without depositing oxide material on the plurality of side surfaces of the channel layers. In some embodiments, forming the isolation layer includes depositing oxide material until the top surface of the isolation layer is coplanar with the top surface of the bottommost internal spacer. In some embodiments, forming the epitaxial region includes forming a plurality of epitaxial layers on the plurality of exposed side surfaces of the channel layers. In some embodiments, forming the epitaxial region further includes: forming a first continuous epitaxial layer connecting half of the epitaxial layers on a first side of the opening; and forming a second continuous epitaxial layer connecting the other half of the epitaxial layers on a second side of the opening. In some embodiments, forming the epitaxial region further includes forming a vertical epitaxial layer connecting the first continuous epitaxial layer and the second continuous epitaxial layer. In some embodiments, the method further includes replacing the sacrificial layer with a gate structure surrounding the channel layer.

[0140] It should be understood that the "Implementation Methods" section, not the "Summary" section, is intended to be used to interpret the appended claims. The summary section of this disclosure may list one or more embodiments of this disclosure, but not all possible embodiments, and therefore is not intended to limit the appended claims in any way.

[0141] The foregoing disclosure outlines the features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various modifications, substitutions, and alterations to this document without departing from its spirit and scope.

Claims

1. A semiconductor structure, characterized by, include: A nanostructured element is placed on a substrate; A gate structure surrounds the nanostructure element; An internal spacer structure is adjacent to the gate structure and located below the nanostructure element; A source / drain region is in contact with one side of the nanostructured device; as well as An isolation layer is located below the source / drain region and contacts one side of the internal spacer structure.

2. The semiconductor structure of claim 1, wherein, The top surface of the isolation layer is coplanar with the interface between the internal interstitial structure and the nanostructure element.

3. The semiconductor structure of claim 1, wherein, The top surface of the isolation layer is located above the bottom surface of the internal spacer structure.

4. The semiconductor structure of any one of claims 1 to 3, wherein, The source / drain region includes: A first epitaxial layer is present on this side of the nanostructure element; and A second epitaxial layer is placed on a convex surface of the first epitaxial layer.

5. The semiconductor structure of claim 4, wherein, The first epitaxial layer and the second epitaxial layer are in contact with the isolation layer.

6. A semiconductor structure, characterized by include: Multiple nanosheets are stacked on a single substrate; A gate structure surrounds the plurality of nanosheet layers; Multiple internal spacers are in contact with the gate structure; A source / drain structure is in contact with the multiple nanosheets; as well as An isolation layer is located below the source / drain structure and contacts one side of the bottommost inner spacer of the plurality of inner spacers.

7. The semiconductor structure of claim 6, wherein, The isolation layer protrudes into the substrate.

8. The semiconductor structure of claim 6, wherein, The interface between the isolation layer and the substrate is curved.

9. The semiconductor structure of any one of claims 6 to 8, wherein, Also includes: Another isolation layer is located on one side of the bottom inner spacer among the plurality of inner spacers; as well as Another source / drain structure is on the other isolation layer, wherein the plurality of nanosheet layers are located between the source / drain structure and the other source / drain structure, and wherein a distance between the isolation layer and the other isolation layer is greater than a distance between the source / drain structure and the other source / drain structure.

10. A semiconductor structure, characterized by include: A nanostructured element is placed on a substrate; A gate structure surrounds the nanostructure element; Multiple internal spacers are adjacent to the gate structure; The source / drain epitaxial structure is isolated from the gate structure by the plurality of internal spacers; as well as An isolation layer is located below the source / drain epitaxial structure and contacts one side of the bottommost inner spacer of the plurality of inner spacers.

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