Reference circuit, chip, and electronic device

Abstract

The embodiment of the application provides a reference circuit, a chip and an electronic device, the reference circuit comprises a first voltage generating module, a second voltage generating module, a third voltage generating module, a voltage summing module and an output module, the first negative temperature coefficient voltage is generated through the first voltage generating module, the second voltage generating module generates a positive temperature coefficient voltage, the third voltage generating module generates a high-order temperature compensation voltage based on the first negative temperature coefficient voltage and the first voltage, the voltage summing module generates a first output voltage based on the first negative temperature coefficient voltage, the positive temperature coefficient voltage and the high-order temperature compensation voltage, and the output module outputs the first output voltage as a reference voltage after performing a mismatch processing, the output module is added on the basis of the voltage summing module, the first output voltage can be outputted as the reference voltage after the mismatch processing of the output module, and therefore the stability of the reference voltage is improved due to the improvement or elimination of the mismatch.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a reference circuit, chip, and electronic device. Background Technology

[0002] The reference voltage provided by the bandgap reference circuit can be widely used in analog integrated circuits, such as converters and power management chips.

[0003] However, the aforementioned reference voltage may exhibit poor stability for various reasons. Utility Model Content

[0004] In view of the above problems, embodiments of this application provide a reference circuit, chip, and electronic device to solve the above technical problems.

[0005] In a first aspect, embodiments of this application provide a reference circuit, which includes a first voltage generation module, a second voltage generation module, a third voltage generation module, a voltage summing module, and an output module. The first voltage generation module is used to generate a first negative temperature coefficient voltage; the second voltage generation module is used to generate a first voltage and a second voltage, and generate a positive temperature coefficient voltage based on the first voltage and the second voltage; the third voltage generation module is used to generate a higher-order temperature compensation voltage based on the first negative temperature coefficient voltage and the first voltage; the voltage summing module is used to generate a first output voltage based on the first negative temperature coefficient voltage, the positive temperature coefficient voltage, and the higher-order temperature compensation voltage; and the output module is used to output the first output voltage as a reference voltage after offset processing.

[0006] Secondly, embodiments of this application also provide a chip that includes the aforementioned reference circuit.

[0007] Thirdly, embodiments of this application also provide an electronic device, which includes the aforementioned reference circuit or chip.

[0008] The reference circuit, chip, and electronic device provided in this application embodiment generate a first negative temperature coefficient voltage through a first voltage generation module, a second voltage generation module generates a positive temperature coefficient voltage, a third voltage generation module generates a higher-order temperature compensation voltage based on the first negative temperature coefficient voltage and the first voltage, and a voltage summing module generates a first output voltage based on the first negative temperature coefficient voltage, the positive temperature coefficient voltage, and the higher-order temperature compensation voltage. After offset processing, the output module outputs the first output voltage as the reference voltage. By adding an output module based on the voltage summing module, the first output voltage can be output as the reference voltage after offset processing of the output module. Since the offset is improved or eliminated, the stability of the reference voltage is improved.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic block diagram of the reference circuit provided in an embodiment of this application is shown.

[0012] Figure 2 The block diagram of the voltage summation module is shown.

[0013] Figure 3 The circuit diagram of the first switching unit is shown.

[0014] Figure 4 The circuit schematic of the first voltage generation module is shown.

[0015] Figure 5 The circuit schematic of the second voltage generation module is shown.

[0016] Figure 6 The circuit diagram of the second switching unit is shown.

[0017] Figure 7 The circuit schematic of the third voltage generation module is shown.

[0018] Figure 8 The circuit diagram of the third switching unit is shown.

[0019] Figure 9 The circuit schematic of the output module is shown.

[0020] Figure 10 A schematic diagram illustrating an application scenario of the reference circuit provided in an embodiment of this application is shown.

[0021] Figure 11 A timing diagram of the reference circuit provided in an embodiment of this application is shown.

[0022] Figure 12 A schematic diagram of the chip structure provided in an embodiment of this application is shown.

[0023] Figure 13 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0024] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0025] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0026] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0027] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0028] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0029] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0030] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0031] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0032] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0033] Traditional bandgap reference circuits typically only provide first-order temperature compensation before directly supplying power to the load, without addressing second-order or higher-order temperature drift. This reduces the accuracy of the reference voltage. Furthermore, directly supplying power to the load from the reference circuit results in insufficient driving capability.

[0034] In view of this, the embodiments of this application introduce a first-order temperature compensation and a higher-order temperature compensation architecture to offset the first-order and higher-order temperature drift of the reference circuit, thereby improving the accuracy of the reference voltage. Simultaneously, by outputting the reference voltage through the output module, the offset voltage is eliminated while improving the driving capability of the reference voltage.

[0035] This application provides a reference circuit, such as... Figure 1As shown, the reference circuit 100 includes a first voltage generation module 10, a second voltage generation module 20, a third voltage generation module 30, a voltage summing module 40, and an output module 50. The first voltage generation module 10 generates a first negative temperature coefficient voltage. The second voltage generation module 20 generates a first voltage and a second voltage, and generates a positive temperature coefficient voltage based on the first voltage and the second voltage. The third voltage generation module 30 generates a higher-order temperature compensation voltage based on the first negative temperature coefficient voltage and the first voltage. The voltage summing module 40 generates a first output voltage based on the first negative temperature coefficient voltage, the positive temperature coefficient voltage, and the higher-order temperature compensation voltage. The output module 50 performs offset processing and outputs the first output voltage as the reference voltage VREF.

[0036] It is understood that the reference circuit 100 provided in this application embodiment generates a first negative temperature coefficient voltage through a first voltage generation module 10. This first negative temperature coefficient voltage includes a first-order temperature coefficient voltage and a higher-order temperature coefficient voltage. A second voltage generation module 20 generates a positive temperature coefficient voltage, a third voltage generation module 30 generates a higher-order temperature compensation voltage based on the first negative temperature coefficient voltage and the first voltage, and a voltage summing module 40 generates a first output voltage based on the first negative temperature coefficient voltage, the positive temperature coefficient voltage, and the higher-order temperature compensation voltage. After offset processing, the output module 50 outputs the first output voltage as the reference voltage VREF. By adding an output module 50 to the voltage summing module 40, the first output voltage can be output as the reference voltage VREF after offset processing in the output module 50. Since the offset is improved or eliminated, the stability of the reference voltage VREF is improved.

[0037] In some embodiments, such as Figure 2 As shown, the voltage summing module 40 includes a first operational amplifier OP1, a first capacitor C1, and a first switching unit 41. The first end of the first capacitor C1 is connected to the first input terminal of the first operational amplifier OP1, and the second end of the first capacitor C1, the second input terminal of the first operational amplifier OP1, and the output terminal of the first operational amplifier OP1 are all connected to the first switching unit 41.

[0038] It should be noted that the second terminal of the first capacitor C1 is alternately connected to the second input terminal and the output terminal of the first operational amplifier OP1 under the control of the first switching unit 41, and the first terminal and the second terminal of the first capacitor C1 are alternately connected to the output terminal of the first operational amplifier OP1 under the control of the first switching unit 41.

[0039] The first input terminal and the second input terminal of the first operational amplifier OP1 are respectively the inverting input terminal and the non-inverting input terminal.

[0040] In some embodiments, such as Figure 3As shown, the first switching unit 41 includes a first switch S1, a second switch S2, and a third switch S3. The first terminal of the first switch S1 is connected to the non-inverting input terminal of the first operational amplifier OP1, and the second terminal of the first switch S1 is connected to the second terminal of the first capacitor C1. The first terminal of the second switch S2 is connected to the output terminal of the first operational amplifier OP1, and the second terminal of the second switch S2 is connected to the first terminal of the first capacitor C1. The first terminal of the third switch S3 is connected to the output terminal of the first operational amplifier OP1, and the second terminal of the third switch S3 is connected to the first terminal of the first capacitor C1.

[0041] It should be noted that Vos1 is the offset voltage of the first operational amplifier OP1. The control terminals of the first switch S1 and the third switch S3 are both connected to the first clock signal Clk1 to control the synchronous switching of the first switch S1 and the third switch S3. The control terminal of the second switch S2 is connected to the second clock signal Clk1_, which is inverted compared to the first clock signal Clk1, to control the alternating switching of the second switch S2 with any one of the first switch S1 and the third switch S3. The first terminal of the first switch S1 is used to receive the first negative temperature coefficient voltage.

[0042] In the first phase, the first clock signal Clk1 is high, the first switch S1 and the third switch S3 are both on, the second switch S2 is off, the voltage at the non-inverting input of the first operational amplifier OP1 is Vos1, and the voltage at the inverting input is also pulled to Vos1 due to the virtual short characteristic. The first negative temperature coefficient voltage is applied to the second terminal of the first capacitor C1 through the first switch S1. At this time, the voltage across the first capacitor C1 is the first negative temperature coefficient voltage minus Vos1.

[0043] In the second phase, the first clock signal Clk1 is low, the first switch S1 and the third switch S3 are both open, and the second switch S2 is on. The voltage at the non-inverting input of the first operational amplifier OP1 is Vos1, and the voltage at the inverting input is also pulled to Vos1 due to the virtual short characteristic. At this time, the voltage across the first capacitor C1 is the first output voltage minus Vos1. According to the law of conservation of charge, the charge stored in the first capacitor C1 in the first phase is equal to the charge transferred in the second phase. Vos1 is dynamically eliminated during the charge transfer process. Therefore, the first output voltage is equal to the first negative temperature coefficient voltage, thereby eliminating the offset voltage of the first operational amplifier OP1.

[0044] In some embodiments, such as Figure 4As shown, the first voltage generating module 10 includes a first current source A1 and a first transistor Q1. The first terminal of the first current source A1 is connected to the power supply terminal VDD, the first terminal of the first transistor Q1 is connected to the second terminal of the first current source A1 and the first terminal of the first switch S1, and the second terminal of the first transistor Q1 is connected to the control terminal of the first transistor Q1 and the ground terminal GND.

[0045] It should be noted that the first terminal, control terminal, and second terminal of the first transistor Q1 are, respectively, the emitter, base, and collector. Since both the collector and base of the first transistor Q1 are grounded, the first negative temperature coefficient voltage output from the emitter of the first transistor Q1 is the voltage difference (Vbe) between the base and emitter of the first transistor Q1.

[0046] The first transistor Q1 is a bipolar junction transistor (BJT). The base-emitter voltage (VBE) of a bipolar junction transistor exhibits a non-linear relationship with temperature, and its mathematical expression can be expanded using a Taylor series as follows:

[0047] VBE(T)=a0+a1T+a2T^2+...+anT^n

[0048] Where a0 represents the VBE value at room temperature (e.g., 25℃). a1 represents the first-order temperature coefficient (negative, approximately -2mV / ℃), which dominates the linear temperature drift. a2...an represent higher-order temperature coefficients (e.g., quadratic and nth-order terms), used to describe nonlinear temperature drift. T represents the temperature. Therefore, the first negative temperature coefficient voltage includes both the first-order and higher-order temperature coefficient voltages.

[0049] In some embodiments, such as Figure 5 As shown, the second voltage generating module 20 includes a second capacitor C2, a second transistor Q2, a third transistor Q3, a second current source A2, and a second switching unit 21. The first terminal of the second current source A2 is connected to the power supply terminal VDD. The first terminal of the second capacitor C2 is connected to the first terminal of the first capacitor C1. The second terminal of the second transistor Q2 is connected to the control terminal of the second transistor Q2 and the ground terminal GND. The second terminal of the third transistor Q3 is connected to the control terminal of the third transistor Q3 and the ground terminal GND. The second terminal of the second current source A2, the second terminal of the second capacitor C2, the first terminal of the second transistor Q2, and the first terminal of the third transistor Q3 are all connected to the second switching unit 21.

[0050] It should be noted that the first terminal, control terminal, and second terminal of the second transistor Q2 are, in order, the emitter, base, and collector. Similarly, the first terminal, control terminal, and second terminal of the third transistor Q3 are, in order, the emitter, base, and collector. The first terminal of the second transistor Q2 is used to generate the first voltage. The first terminal of the third transistor Q3 is used to generate the second voltage.

[0051] The second terminal of the second current source A2 is alternately connected to the first terminal of the second transistor Q2 and the first terminal of the third transistor Q3 under the control of the second switching unit 21. The second terminal of the second capacitor C2 is alternately connected to the first terminal of the second transistor Q2 and the first terminal of the third transistor Q3 under the control of the second switching unit 21.

[0052] Since the current provided by the second current source A2 is a positive temperature coefficient current, and the width-to-length ratio of the second transistor Q2 is different from that of the third transistor Q3, the voltage difference between the emitter and base of the second transistor Q2 is different from that between the emitter and base of the third transistor Q3. Thus, when the voltage difference between the emitter and base of a single transistor is a negative temperature coefficient voltage, the positive temperature coefficient voltage can be obtained by subtracting the voltage difference between the emitter and base of the two transistors.

[0053] The positive temperature coefficient voltage generated by the same positive temperature coefficient current source mainly includes the first-order temperature coefficient voltage, so it can cancel out the first-order temperature coefficient voltage in the first negative temperature coefficient voltage.

[0054] In some embodiments, such as Figure 6 As shown, the second switching unit 21 includes a fourth switch S4, a fifth switch S5, a sixth switch S6, and a seventh switch S7. The first terminal of the fourth switch S4 is connected to the first terminal of the second transistor Q2, and the second terminal of the fourth switch S4 is connected to the second terminal of the second capacitor C2. The first terminal of the fifth switch S5 is connected to the first terminal of the third transistor Q3, and the second terminal of the fifth switch S5 is connected to the second terminal of both the second capacitor C2 and the fourth switch S4. The first terminal of the sixth switch S6 is connected to the second terminal of the second current source A2, and the second terminal of the sixth switch S6 is connected to the first terminal of the third transistor Q3. The first terminal of the seventh switch S7 is connected to the first terminal of the sixth switch S6 and the second terminal of the second current source A2, and the second terminal of the seventh switch S7 is connected to the first terminal of the second transistor Q2.

[0055] It should be noted that the control terminal of the fourth switch S4 is connected to the third clock signal Clk2_, and the control terminal of the fifth switch S5 is connected to the fourth clock signal Clk2, with the fourth clock signal Clk2 being inverted from the third clock signal Clk2_. The control terminal of the sixth switch S6 is connected to the fourth clock signal Clk2, and the control terminal of the seventh switch S7 is connected to the third clock signal Clk2_. This allows the fourth switch S4 and the sixth switch S6 to switch synchronously, as well as the fifth switch S5 and the seventh switch S7 to switch synchronously; simultaneously, it also allows any one of the fourth switch S4 and the sixth switch S6 to alternate with any one of the fifth switch S5 and the seventh switch S7.

[0056] Where Iref is the reference current provided by the second current source A2. The reference current provided by the second current source A2 can be, for example, equal to the reference current provided by the first current source A1. The voltage across the first terminal of the second capacitor C2 is a positive temperature coefficient voltage.

[0057] In some embodiments, such as Figure 7 As shown, the third voltage generation module 30 includes a first resistor R1, a second operational amplifier OP2, a first field-effect transistor M1, a second field-effect transistor M2, a fourth transistor Q4, a third capacitor C3, and a third switching unit 31. The first terminal of the first resistor R1 is connected to ground GND. The first input terminal of the second operational amplifier OP2 is connected to the second terminal of the first resistor R1, and the second input terminal of the second operational amplifier OP2 is connected to the first terminal of the first transistor Q1. The first terminal of the first field-effect transistor M1 is connected to the power supply VDD, and the second terminal of the first field-effect transistor M1 is connected to the first input terminal of the second operational amplifier OP2 and the second terminal of the first resistor R1. The control terminal of the first field-effect transistor M1 is connected to the output terminal of the second operational amplifier OP2. The first terminal of the second field-effect transistor M2 is connected to the power supply VDD, and the control terminal of the second field-effect transistor M2 is connected to the control terminal of the first field-effect transistor M1 and the output terminal of the second operational amplifier OP2. The first terminal of the fourth transistor Q4 is connected to the second terminal of the second field-effect transistor M2, and the second terminal of the fourth transistor Q4 is connected to its control terminal and ground GND. The first terminal of the third capacitor C3 is connected to the first terminal of the first capacitor C1. The third switching unit 31 is connected to the second terminal of the third capacitor C3, the first terminal of the fourth transistor Q4, the first terminal of the second transistor Q2, and the second terminal of the seventh switch S7.

[0058] It should be noted that the first and second input terminals of the second operational amplifier OP2 are, in sequence, the non-inverting input terminal and the inverting input terminal. The first, control, and second terminals of the fourth transistor Q4 are, in sequence, the emitter, the base, and the collector. The third switching unit 31 is used to control the second terminal of the third capacitor C3 to be alternately connected to the first terminal of the fourth transistor Q4 and the first terminal of the second transistor Q2.

[0059] It is understandable that the inverting input of the second operational amplifier OP2 is connected to the emitter of the first transistor Q1. The voltage at the emitter of the first transistor Q1 is a negative temperature coefficient current. Therefore, according to the virtual short characteristic of the op-amp, the current at the non-inverting input of the second operational amplifier OP2 is a negative temperature coefficient current. Thus, the current through the first resistor R1 and the first field-effect transistor M1 is a negative temperature coefficient current. The current flowing through the fourth transistor Q4 via the mirror image of the second field-effect transistor M2 is a negative temperature coefficient current, and the current flowing through the second transistor Q2 is a positive temperature coefficient current. Therefore, when the third switching unit 31 controls the second terminal of the third capacitor C3 to be alternately connected to the first terminal of the fourth transistor Q4 and the first terminal of the second transistor Q2, the charge at the second terminal of the third capacitor C3 includes the charge generated by the voltage difference between the VBE of the fourth transistor Q4 and the VBE of the second transistor Q2. The charge voltage generated by the negative and positive temperature coefficient currents mainly includes higher-order temperature coefficient voltages, which can offset the influence of higher-order temperature voltages generated by higher-order temperature coefficients in the first negative temperature coefficient voltage, thereby making the first output voltage unaffected by temperature.

[0060] In some embodiments, such as Figure 8 As shown, the third switch unit 31 includes an eighth switch S8 and a ninth switch S9. The first end of the eighth switch S8 is connected to the first terminal of the second transistor Q2, and the first end of the ninth switch S9 is connected to the first terminal of the fourth transistor Q4. The second ends of the eighth switch S8 and the ninth switch S9 are both connected to the second end of the third capacitor C3.

[0061] It should be noted that the control terminal of the eighth switch S8 is connected to the fourth clock signal Clk2. The control terminal of the ninth switch S9 is connected to the third clock signal Clk2_. This controls the second terminal of the third capacitor C3 to be alternately connected to the first terminal of the second transistor Q2 and the first terminal of the fourth transistor Q4.

[0062] Optionally, such as Figure 8 As shown, the third voltage generation module 30 may further include a sixth capacitor C6, the first end of the sixth capacitor C6 is connected to the second end of the first resistor R1, and the second end of the sixth capacitor C6 is connected to the second operational amplifier OP2.

[0063] In some embodiments, such as Figure 9As shown, the output module 50 includes a tenth switch S10, a fourth capacitor C4, an eleventh switch S11, a fifth capacitor C5, a third operational amplifier OP3, a twelfth switch S12, and a thirteenth switch S13. The first terminal of the tenth switch S10 is connected to the output terminal of the voltage summing module 40. The second terminal of the tenth switch S10 is connected to the first terminal of the fourth capacitor C4, the first input terminal of the third operational amplifier OP3, and the first terminal of the eleventh switch S11. The second terminal of the fourth capacitor C4 is connected to the ground terminal GND. The second terminal of the eleventh switch S11 is connected to the first terminal of the fifth capacitor C5 and the first terminal of the twelfth switch S12. The second terminal of the fifth capacitor C5 is connected to the second input terminal of the third operational amplifier OP3 and the first terminal of the thirteenth switch S13. The output terminal of the third operational amplifier OP3 is connected to the second terminals of the twelfth switch S12 and the thirteenth switch S13, and is used to output the reference voltage VREF.

[0064] It should be noted that the first and second input terminals of the third operational amplifier OP3 are, respectively, the non-inverting input and the inverting input. Vos2 is the offset voltage of the third operational amplifier OP3. The control terminals of the tenth switch S10, the eleventh switch S11, and the thirteenth switch S13 are all connected to the fifth clock signal Clk3. The control terminal of the twelfth switch S12 is connected to the sixth clock signal Clk3_. The sixth clock signal Clk3_ is inverted compared to the fifth clock signal Clk3, and can control the synchronous switching of the tenth switch S10, the eleventh switch S11, and the thirteenth switch S13, and control the alternating switching of the twelfth switch S12 with any one of the tenth switch S10, the eleventh switch S11, and the thirteenth switch S13.

[0065] Understandably, the output module 50 uses switched capacitors to dynamically eliminate the influence of the input offset voltage (Vos2) of the third operational amplifier OP3 on the reference voltage VREF. The specific process is as follows:

[0066] During the calibration phase, the fifth clock signal Clk3 is high, the tenth switch S10, the eleventh switch S11, and the thirteenth switch S13 are all turned on, and the twelfth switch S12 is turned off. The charge of the first output voltage (from the voltage summing module 40) is stored at the first terminal of the fourth capacitor C4 and the first terminal of the fifth capacitor C5. The offset voltage Vos2 of the third operational amplifier OP3 is pre-stored at the first terminal of the fifth capacitor C5. During the output phase, the fifth clock signal Clk3 is low, the tenth switch S10, the eleventh switch S11, and the thirteenth switch S13 are all turned off, and the twelfth switch S12 is turned on. At this time, the first terminal of the fifth capacitor C5 is connected to the output terminal of the third operational amplifier OP3, and the first output voltage at the first terminal of the fifth capacitor C5 is output. The effect of Vos2 is reversed by the charge pre-stored in the fifth capacitor C5, thus obtaining a pure reference voltage VREF.

[0067] like Figure 10 As shown, the reference circuit 100 can provide a reference voltage VREF for the analog-to-digital converter 110. The reference circuit 100 can generate the reference voltage VREF based on the first clock signal Clk1, the fourth clock signal Clk2, and the fifth clock signal Clk3. The analog-to-digital converter 110 performs alternating sampling and integration phases based on the reference voltage VREF. The transition edges of the first clock signal Clk1 and the fourth clock signal Clk2 are both located in the sampling phase and / or the integration phase, and the effective level of the fifth clock signal Clk3 is located in the first half of the sampling or integration phase.

[0068] It is understood that the reference circuit 100 provided in this application generates a reference voltage VREF based on the first clock signal Clk1, the fourth clock signal Clk2, and the fifth clock signal Clk3. The analog-to-digital converter 110 performs alternating sampling and integration phases based on the reference voltage VREF. The transition edges of the first clock signal Clk1 and the fourth clock signal Clk2 are both located in the sampling phase and / or the integration phase, and the effective level of the fifth clock signal Clk3 is located in the first half of the sampling or integration phase. This allows the analog-to-digital converter 110 sufficient time to mitigate the errors caused by the transition edges, thereby improving the performance degradation of the analog-to-digital converter 110 caused by these errors.

[0069] It should be noted that the analog-to-digital converter 110 can be a discrete analog-to-digital converter, such as a Σ-Δ analog-to-digital converter (Sigma-Delta ADC, SDADC), a successive approximation analog-to-digital converter (SAR ADC), a pipeline analog-to-digital converter (Pipeline ADC), or a flash analog-to-digital converter (Flash ADC), etc.

[0070] The effective level can be exemplarily a high level that enables the corresponding switch to be in the on state. The effective level of the fifth clock signal Clk3 is used to calibrate the offset of the output module 50. This ensures that when the sixth clock signal Clk3_, which is inverse of the fifth clock signal Clk3, is at the effective level, the output does not contain the reference voltage VREF that includes the offset voltage, thereby allowing the analog-to-digital converter 110 to use a more accurate reference voltage VREF.

[0071] Figure 11 A timing diagram of the reference circuit 100 provided in an embodiment of this application is shown. Here, PHS represents the sampling phase, with a high level indicating the sampling stage and a low level indicating idle. PHI represents the integration phase, with a high level indicating the integration stage and a low level indicating idle. Vout_op1 represents the first output voltage output by the first operational amplifier OP1, and Vos_buf represents the voltage difference between Vout_op1 and the reference voltage VREF. The time period indicated by os_c represents the reference voltage VREF used by the analog-to-digital converter 110, which does not include the offset voltage of the first output voltage source Vos1. The time period indicated by no_os_c represents the reference voltage VREF used by the analog-to-digital converter 110, which includes the offset voltage of the first output voltage source Vos1. The sum of the time periods indicated by os_c and no_os_c is one cycle of PHS or PHI.

[0072] like Figure 11 As shown, each operating cycle of the reference circuit 100 may include a first stage, a second stage, and a third stage in sequence.

[0073] In the first stage, the first clock signal Clk1 is at a high level, and the fourth clock signal Clk2 and the fifth clock signal Clk3 are both at a low level, so as to control the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the ninth switch S9 and the twelfth switch S12 to be in the on state, and control the second switch S2, the fourth switch S4, the sixth switch S6, the eighth switch S8, the tenth switch S10, the eleventh switch S11 and the thirteenth switch S13 to be in the off state.

[0074] In the second stage, the fourth clock signal Clk2 is at a high level, and the first clock signal Clk1 and the fifth clock signal Clk3 are both at a low level, so as to control the second switch S2, the fourth switch S4, the sixth switch S6, the eighth switch S8 and the twelfth switch S12 to be in the on state, and control the first switch S1, the third switch S3, the fifth switch S5, the seventh switch S7, the ninth switch S9, the tenth switch S10, the eleventh switch S11 and the thirteenth switch S13 to be in the off state.

[0075] In the third stage, the fifth clock signal Clk3 is at a high level, and the first clock signal Clk1 and the fourth clock signal Clk2 are both at a low level, so as to control the second switch S2, the fifth switch S5, the seventh switch S7, the ninth switch S9, the tenth switch S10, the eleventh switch S11 and the thirteenth switch S13 to be in the on state, and control the first switch S1, the third switch S3, the fourth switch S4, the sixth switch S6, the eighth switch S8 and the twelfth switch S12 to be in the off state.

[0076] It should be noted that, for example, a high level is an active level, controlling the corresponding switch to be in the ON state. A low level is an inactive level, controlling the corresponding switch to be in the OFF state.

[0077] In summary, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 can all be bipolar junction transistors (BJTs). A negative temperature coefficient current flowing through the BJT can generate a higher-order temperature drift term. Setting the voltage between the base and emitter of the transistor, Vbe, as VT1, this application utilizes the positive temperature coefficient characteristic of the difference between the Vbe of the third transistor Q3 and the Vbe of the first transistor Q1 to generate a first-order positive temperature coefficient voltage VT2 using the second voltage generation module 20. A negative temperature coefficient current is generated by the negative temperature coefficient characteristic of the first transistor Q1 and flows through the fourth transistor Q4, generating a higher-order temperature compensation voltage VT3.

[0078] In the first stage, the offset of the first operational amplifier OP1 is stored in the first capacitor C1, while the offset of the third operational amplifier OP3 is stored in the fifth capacitor C5. In the second stage, the voltage across the second capacitor C2 and the third capacitor C3 is summed using the first capacitor C1. The lower-level board voltages of the second capacitor C2 and the third capacitor C3 are switched by the third transistor Q3, the fourth transistor Q4, and the second transistor Q2, respectively. This ultimately generates an offset-canceled reference voltage VREF.

[0079] Specifically, when the first clock signal Clk1 is high, the first operational amplifier OP1 is calibrated. When the fourth clock signal Clk2 is high, the first output voltage of the first operational amplifier OP1, Vout_op1, is as follows:

[0080]

[0081] When the fifth clock signal Clk3 is high, the calibration offset is determined. When the fifth clock signal Clk3 is low (i.e., when the sixth clock signal Clk3 is high), the reference voltage VREF is expressed as follows:

[0082]

[0083] Let: V_Q1=VT1, (V_Q2-V_Q3)=VT2, (V_Q2-V_Q4)=VT3, then:

[0084]

[0085] It should be noted that V_Q1 represents the Vbe of the first transistor Q1, V_Q2 represents the Vbe of the second transistor Q2, V_Q3 represents the Vbe of the third transistor Q3, V_Q4 represents the Vbe of the fourth transistor Q4, C1 represents the capacitance of the first capacitor C1, C2 represents the capacitance of the second capacitor C2, C3 represents the capacitance of the third capacitor C3, Vos1 represents the offset voltage of the first operational amplifier OP1, and Vos2 represents the offset voltage of the third operational amplifier OP3.

[0086] This application embodiment also provides a chip 200, such as Figure 12 As shown, the chip 200 includes the aforementioned reference circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0087] It is understood that since the chip 200 provided in this application embodiment includes the aforementioned reference circuit 100, it can also generate a first negative temperature coefficient voltage through the first voltage generation module 10, generate a positive temperature coefficient voltage through the second voltage generation module 20, generate a higher-order temperature compensation voltage based on the first negative temperature coefficient voltage and the first voltage through the third voltage generation module 30, generate a first output voltage based on the first negative temperature coefficient voltage, the positive temperature coefficient voltage and the higher-order temperature compensation voltage through the voltage summing module 40, and output the first output voltage as the reference voltage VREF after offset processing by the output module 50. By adding the output module 50 on the basis of the voltage summing module 40, the first output voltage can be output as the reference voltage VREF after offset processing by the output module 50. Since the offset is improved or eliminated, the stability of the reference voltage VREF is improved.

[0088] This application also provides an electronic device 300, such as... Figure 13As shown, the electronic device 300 includes a device body and the aforementioned reference circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a power meter, a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a power bank, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, true wireless earbuds, a car infotainment screen, a car, a smart wearable device, a mobile terminal, and smart home devices. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0089] It is understood that since the electronic device 300 provided in this application embodiment includes the aforementioned reference circuit 100 or chip 200, it can also generate a first negative temperature coefficient voltage through the first voltage generation module 10, generate a positive temperature coefficient voltage through the second voltage generation module 20, generate a higher-order temperature compensation voltage based on the first negative temperature coefficient voltage and the first voltage through the third voltage generation module 30, generate a first output voltage based on the first negative temperature coefficient voltage, the positive temperature coefficient voltage and the higher-order temperature compensation voltage through the voltage summing module 40, and output the first output voltage as the reference voltage VREF after the output module 50 performs offset processing. By adding the output module 50 on the basis of the voltage summing module 40, the first output voltage can be output as the reference voltage VREF after the output module 50 performs offset processing. Since the offset is improved or eliminated, the stability of the reference voltage VREF is improved.

[0090] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A reference circuit, characterized in that, The reference circuit includes: The first voltage generation module is used to generate the first negative temperature coefficient voltage; The second voltage generation module is used to generate a first voltage and a second voltage, and to generate a positive temperature coefficient voltage based on the first voltage and the second voltage. The third voltage generation module is used to generate a higher-order temperature compensation voltage based on the first negative temperature coefficient voltage and the first voltage. A voltage summing module is used to generate a first output voltage based on the first negative temperature coefficient voltage, the positive temperature coefficient voltage, and the higher-order temperature compensation voltage; The output module is used to output the first output voltage as a reference voltage after offset processing.

2. The reference circuit as described in claim 1, characterized in that, The voltage summing module includes a first operational amplifier, a first capacitor, and a first switching unit; The first end of the first capacitor is connected to the first input terminal of the first operational amplifier, and the second end is alternately connected to the second input terminal and the output terminal of the first operational amplifier under the control of the first switching unit. The first end and the second end of the first capacitor are also alternately connected to the output terminal of the first operational amplifier under the control of the first switching unit.

3. The reference circuit as described in claim 2, characterized in that, The first switching unit includes a first switch, a second switch, and a third switch; The first switch is connected between the second terminal of the first capacitor and the second input terminal of the first operational amplifier; The second switch is connected between the second terminal of the first capacitor and the output terminal of the first operational amplifier; The third switch is connected between the first terminal of the first capacitor and the output terminal of the first operational amplifier.

4. The reference circuit as described in claim 2, characterized in that, The first voltage generation module includes a first current source and a first transistor; The first terminal of the first transistor is connected to the first current source and the non-inverting input terminal of the first operational amplifier, and the second terminal of the first transistor is connected to the control terminal and the ground terminal of the first transistor.

5. The reference circuit as described in claim 4, characterized in that, The second voltage generation module includes a second current source, a second switching unit, a second capacitor, a second transistor, and a third transistor; The second current source is alternately connected to the first terminal of the second transistor and the first terminal of the third transistor under the control of the second switching unit; The second terminal of the second transistor is connected to the control terminal and the ground terminal of the second transistor, and the second terminal of the third transistor is connected to the control terminal and the ground terminal of the third transistor; The first terminal of the second capacitor is connected to the first terminal of the first capacitor, and the second terminal is alternately connected to the first terminal of the second transistor and the first terminal of the third transistor under the control of the second switching unit.

6. The reference circuit as described in claim 5, characterized in that, The second switching unit includes a fourth switch, a fifth switch, a sixth switch, and a seventh switch; The fourth switch is connected between the first terminal of the second transistor and the second terminal of the second capacitor; The fifth switch is connected between the first terminal of the third transistor and the second terminal of the second capacitor; The sixth switch is connected between the second current source and the first electrode of the third transistor; The seventh switch is connected between the second current source and the first electrode of the second transistor.

7. The reference circuit as described in claim 5, characterized in that, The third voltage generation module includes a first resistor, a second operational amplifier, a first field-effect transistor, a second field-effect transistor, a fourth transistor, a third switching unit, and a third capacitor; The first end of the first resistor is connected to the ground terminal; The first input terminal of the second operational amplifier is connected to the second terminal of the first resistor, and the second input terminal of the second operational amplifier is connected to the first terminal of the first transistor. The first terminal of the first field-effect transistor is connected to the power supply terminal, the second terminal of the first field-effect transistor is connected to the first input terminal of the second operational amplifier and the second terminal of the first resistor, and the control terminal of the first field-effect transistor is connected to the output terminal of the second operational amplifier. The first terminal of the second field-effect transistor is connected to the power supply terminal, and the control terminal of the second field-effect transistor is connected to the control terminal of the first field-effect transistor and the output terminal of the second operational amplifier. The first terminal of the fourth transistor is connected to the second terminal of the second field-effect transistor, and the second terminal of the fourth transistor is connected to the control terminal and the ground terminal of the fourth transistor. The first terminal of the third capacitor is connected to the first terminal of the first capacitor, and the second terminal of the third capacitor is alternately connected to the first terminal of the fourth transistor and the first terminal of the second transistor under the control of the third switching unit.

8. The reference circuit as described in claim 7, characterized in that, The third switching unit includes an eighth switch and a ninth switch; The eighth switch is connected between the second terminal of the third capacitor and the first terminal of the second transistor; The ninth switch is connected between the second terminal of the third capacitor and the first terminal of the fourth transistor.

9. The reference circuit as described in any one of claims 1 to 8, characterized in that, The output module includes a third operational amplifier, a fourth capacitor, a fifth capacitor, a tenth switch, an eleventh switch, a twelfth switch, and a thirteenth switch; The tenth switch is connected between the output terminal of the voltage summing module and the first input terminal of the third operational amplifier; The fourth capacitor is connected between the first input terminal and the ground terminal of the third operational amplifier. The eleventh switch is connected between the first input terminal of the third operational amplifier and the first terminal of the fifth capacitor; The second terminal of the fifth capacitor is connected to the second input terminal of the third operational amplifier; The output of the third operational amplifier is used to output the reference voltage; The twelfth switch is connected between the first terminal of the fifth capacitor and the output terminal of the third operational amplifier. The thirteenth switch is connected between the output terminal of the third operational amplifier and the second input terminal of the third operational amplifier; The twelfth switch alternates with any one of the tenth, eleventh, and thirteenth switches.

10. A chip, characterized in that, The chip includes a reference circuit as described in any one of claims 1 to 9.

11. An electronic device, characterized in that, The electronic device includes a device body and a chip as described in claim 10 disposed on the device body.

Images