An ESD protection circuit

Abstract

The utility model discloses an ESD protection circuit, including first branch, second branch and third branch, first branch includes first bleed transistor and second bleed transistor in series, second branch and first bleed transistor are parallel, second branch includes first electric capacity and first resistance, and first electric capacity and first resistance electric connection to the grid of first bleed transistor, third branch and first branch are parallel, third branch includes the voltage drop unit and filter unit in series, and the voltage drop unit and filter unit electric connection to the grid of second bleed transistor, the ESD protection circuit of the utility model can respond to ESD event on one hand, filter out the influence of radio frequency interference signal on the other hand, reduce the small leakage caused thereby.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency chip technology, and in particular to an ESD protection circuit. Background Technology

[0002] External ports of radio frequency (RF) products are divided into RF ports and DC ports. RF ports handle the input and output of high-power signals, while DC ports serve as power supply ports and status control ports. The power supply port connects to the power source, while the status control port controls the operating state of switches based on different status signals. Because semiconductor devices have poor voltage withstand capabilities, RF chips and other semiconductor RF devices require electrostatic discharge (ESD) protection devices for their external ports. Different types of ports in RF devices employ different ESD protection methods; typical ESD protection devices for DC ports are GGNMOS or GCNMOS.

[0003] like Figure 1 As shown, in the protection method of GGNMOS, the discharge transistor NM1 is an NMOS device. The discharge transistor NM1 can carry large currents and is typically large in size, hence it is also called Big MOS. Taking the power supply port as an example, when an ESD event occurs at the VDD port, the VDD port voltage rises rapidly, and the parasitic transistor in the substrate of the discharge transistor NM1 turns on, quickly discharging the electrostatic charge at the VDD port, thus protecting the VDD port. During normal operation, the voltage difference between the gate and source of the discharge transistor NM1 is zero, and the discharge transistor NM1 remains off, not affecting normal product operation. The advantage of GGNMOS circuits is their simple structure, but their disadvantage is the high ESD protection turn-on voltage, which limits the application range of GGNMOS.

[0004] like Figure 2As shown, in the GCNMOS protection method, the discharge transistor NM1 is an NMOS device, and its gate is connected to the first capacitor C1 and the first resistor R1. Taking the power supply port as an example, when an ESD event occurs at the DC port, the VDD port voltage rises rapidly. Utilizing the characteristic that the voltage across the first capacitor C1 cannot change abruptly, the voltage at point A of the gate of the discharge transistor NM1 rises rapidly, causing the discharge transistor NM1 to turn on. It then rapidly discharges the electrostatic charge at the VDD port through the NMOS channel, thereby protecting the VDD port. When the product is operating normally, the first resistor R1 discharges the gate charge of the discharge transistor NM1, keeping the gate voltage zero, and the discharge transistor NM1 remains off, not affecting the normal operation of the product. The advantage of GCNMOS circuits is their low ESD protection turn-on voltage. However, as the size of RF switches becomes smaller, the isolation between the RF port and the DC port becomes worse. High-power signals flowing through the RF port can leak to the DC port, forming interference signals. The gate potential of the discharge transistor NM1 fluctuates due to the interference signals, causing the discharge transistor NM1 to turn on periodically, resulting in a large leakage current and increasing the power consumption of the product in high-power mode. This limits the application of GCNMOS in small-size, high-power RF switches.

[0005] On the other hand, Big MOS devices are typically nominally 2.5V devices in RF processes, while the VDD voltage can reach 5V. To ensure that Big MOS operates within its voltage rating range, the two MOS devices need to be connected in series, and the operating potential of the series node needs to be maintained within a range close to 2.5V. Therefore, designing a new ESD protection circuit that can leverage the fast response advantage of GCNMOS circuits, avoid the periodic on-time switching problem of the bleeder tube caused by RF signal interference, and maintain the source-drain voltage VDS of the Big MOS near its nominal value of 2.5V is a problem that urgently needs to be solved. Utility Model Content

[0006] In view of this, the purpose of this utility model is to design a new ESD protection circuit that maintains the VDS voltage of Big MOS at around 2.5V under the working voltage of VDD of 5V during normal operation, while simultaneously achieving fast response and anti-RF interference performance. It can quickly discharge the charge of ESD events and reduce leakage current when the circuit is interfered with by RF signals.

[0007] Based on the above objectives, this utility model provides an ESD protection circuit, including a first branch, a second branch and a third branch, wherein the ESD protection circuit is disposed between the circuit VDD terminal and the circuit VSS terminal.

[0008] The first branch includes a first discharge transistor and a second discharge transistor connected in series; the drain of the second discharge transistor is electrically connected to the VDD terminal of the circuit, the source of the second discharge transistor is electrically connected to the drain of the first discharge transistor, and the source of the first discharge transistor is electrically connected to the VSS terminal of the circuit.

[0009] The second branch is connected in parallel with the first discharge transistor; the second branch includes a first capacitor and a first resistor; the two ends of the first capacitor are electrically connected to the drain and gate of the first discharge transistor, respectively; the two ends of the first resistor are electrically connected to the gate and source of the first discharge transistor, respectively.

[0010] The third branch is connected in parallel with the first branch; the third branch includes a voltage drop unit and a filter unit connected in series; the two ends of the voltage drop unit are electrically connected to the VDD terminal of the circuit and the gate of the second bleeder transistor, respectively; one end of the filter unit is electrically connected to the gate of the second bleeder transistor, and the other end of the filter unit is electrically connected to the VSS terminal of the circuit; the voltage drop unit is used to maintain the voltage drop of the gate of the second bleeder transistor relative to the VDD terminal of the circuit; the filter unit is used to rapidly attenuate the high-frequency radio frequency signal through filtering.

[0011] Preferably, the voltage drop unit comprises a plurality of diodes connected in series.

[0012] Preferably, the diode is a silicon diode, and the number of diodes is set to four.

[0013] Preferably, the filtering unit includes a second capacitor and a second resistor connected in parallel; both the second capacitor and the second resistor are connected across the gate of the second discharge transistor and the VSS terminal of the circuit.

[0014] Preferably, both the first discharge transistor and the second discharge transistor are N-type Big MOS devices.

[0015] In summary, this utility model has the following beneficial effects:

[0016] (1) The ESD protection circuit of this utility model can respond quickly to ESD events on the one hand, and filter out the influence of radio frequency interference signals on the other hand, reducing the small leakage current caused by it.

[0017] (2) When the present invention is working normally with VDD of 5V, it can maintain the voltage across the discharge transistor at 2.5V, which is suitable for conventional Big MOS with a withstand voltage of 2.5V. The diode occupies a small chip area, reducing the overall circuit area. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 The circuit diagram is shown for a GGNMOS circuit in the prior art.

[0020] Figure 2 The circuit diagram is shown for a GCNMOS circuit in the prior art.

[0021] Figure 3 This is a circuit diagram of the ESD protection circuit according to an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0023] Figure 3The circuit diagram of the ESD protection circuit of this embodiment is shown, including a first branch, a second branch, and a third branch. The first branch includes a second discharge transistor NM2 and a first discharge transistor NM1 connected in series. Both the second discharge transistor NM2 and the first discharge transistor NM1 are N-type Big MOS devices capable of carrying large currents. The drain of the second discharge transistor NM2 is electrically connected to the VDD terminal of the circuit, the source of the second discharge transistor NM2 is electrically connected to the drain of the first discharge transistor NM1, and the source of the first discharge transistor NM1 is electrically connected to the VSS terminal of the circuit. The second branch is connected in parallel with the first discharge transistor NM1. The second branch includes a first capacitor C1 and a first resistor R1 connected in series. The series node of the first capacitor C1 and the first resistor R1 is electrically connected to the gate of the first discharge transistor NM1. Specifically, the two ends of the first capacitor C1 are electrically connected to the drain and the gate of the first discharge transistor NM1, respectively, and the two ends of the first resistor are electrically connected to the gate and the source of the first discharge transistor, respectively. The third branch is connected in parallel with the first branch. The third branch includes a series-connected voltage drop unit and a filter unit, with the series connection point of the voltage drop unit and filter unit electrically connected to the gate of the second bleeder transistor NM2. Specifically, the two ends of the voltage drop unit are electrically connected to the circuit's VDD terminal and the gate of the second bleeder transistor NM2, respectively. One end of the filter unit is electrically connected to the gate of the second bleeder transistor NM2, and the other end is electrically connected to the circuit's VSS terminal. The voltage drop unit includes four diodes D1-D4 connected in series. Diodes D1-D4 are silicon diodes. Using series-connected diodes as components of the voltage drop unit can significantly save chip area. The number of four diodes is a specific structural design to achieve a voltage drop of approximately 2.5V. In other applications, the number of diodes can be greater than or less than four to increase or decrease the voltage drop. The filter unit includes a second capacitor C2 and a second resistor R2 connected in parallel. Both the second capacitor C2 and the second resistor R2 are connected across the gate of the second bleeder transistor NM2 and the circuit's VSS terminal.

[0024] When the circuit is operating normally, circuit node A corresponds to the gate of the second bleeder transistor NM2, and circuit node B corresponds to the series connection of the second bleeder transistor NM2 and the first bleeder transistor NM1. Since the forward voltage drop of a single silicon diode is approximately 0.6-0.7V, the four diodes connected in series generate a voltage drop of approximately 2.5V. Therefore, when the RF device is operating normally, the gate potential of the second bleeder transistor NM2 is VDD voltage (5V) minus 2.5V, which is approximately 2.5V. The potential of circuit node B follows that of circuit node A under the influence of bleeder transistor NM2, and is therefore also around 2.5V, ensuring that the VDS voltages of both the second bleeder transistor NM2 and the first bleeder transistor NM1 are near 2.5V.

[0025] When high-frequency radio frequency signal interference occurs at the VDD or VSS terminals, the RC parallel circuit of the filter unit can rapidly attenuate the interfering radio frequency signal at circuit node A, restore the potential of circuit node A to a stable state, keep the second discharge transistor NM2 in the off state, and reduce the small leakage current of the ESD protection circuit when encountering radio frequency signal interference.

[0026] When an ESD event occurs, the voltage at the VDD terminal rises rapidly, causing the voltage at circuit node A to rise. This turns on the second discharge transistor NM2, which in turn causes the voltage at circuit node B to rise. The first discharge transistor NM1, the first capacitor C1, and the first resistor R1 form a GCNMOS circuit, which can also quickly respond to the voltage rise at circuit node B by turning on the first discharge transistor NM1, thereby opening the current discharge path and allowing the ESD current to be quickly discharged from the first branch.

[0027] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An ESD protection circuit, wherein the ESD protection circuit is disposed between the VDD terminal and the VSS terminal of the circuit, characterized in that, Including the first branch road, the second branch road, and the third branch road; The first branch includes a first discharge transistor and a second discharge transistor connected in series; the drain of the second discharge transistor is electrically connected to the VDD terminal of the circuit, the source of the second discharge transistor is electrically connected to the drain of the first discharge transistor, and the source of the first discharge transistor is electrically connected to the VSS terminal of the circuit. The second branch is connected in parallel with the first discharge transistor; the second branch includes a first capacitor and a first resistor; the two ends of the first capacitor are electrically connected to the drain and gate of the first discharge transistor, respectively; the two ends of the first resistor are electrically connected to the gate and source of the first discharge transistor, respectively. The third branch is connected in parallel with the first branch; the third branch includes a voltage drop unit and a filter unit connected in series; the two ends of the voltage drop unit are electrically connected to the VDD terminal of the circuit and the gate of the second bleeder transistor, respectively; one end of the filter unit is electrically connected to the gate of the second bleeder transistor, and the other end of the filter unit is electrically connected to the VSS terminal of the circuit; the voltage drop unit is used to maintain the voltage drop of the gate of the second bleeder transistor relative to the VDD terminal of the circuit; the filter unit is used to rapidly attenuate the high-frequency radio frequency signal through filtering.

2. The ESD protection circuit according to claim 1, characterized in that, The voltage drop unit includes multiple diodes connected in series.

3. The ESD protection circuit according to claim 2, characterized in that, The diodes are silicon diodes, and the number of diodes is set to four.

4. The ESD protection circuit according to claim 1, characterized in that, The filtering unit includes a second capacitor and a second resistor connected in parallel; both the second capacitor and the second resistor are connected across the gate of the second discharge transistor and the VSS terminal of the circuit.

5. The ESD protection circuit according to claim 1, characterized in that, Both the first and second discharge transistors are N-type Big MOS devices.

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