Circularly symmetric distributed double-sided heat dissipation high-power IPM packaging structure

Abstract

The utility model relates to IPM packaging technical field especially a kind of double-sided heat dissipation high-power IPM packaging structure of circular symmetry distribution, including upper copper ceramic substrate and lower copper ceramic substrate, the upper copper ceramic substrate is connected with lower copper ceramic substrate by IPM module, the material quality of upper copper ceramic substrate ceramic layer and lower copper ceramic substrate ceramic layer is all aluminium nitride ceramic or aluminium oxide ceramic, the upper copper layer of upper copper ceramic substrate is connected with upper radiator by upper heat-conducting silicone grease layer, the lower copper layer of lower copper ceramic substrate is connected with lower radiator by lower heat-conducting silicone grease layer.The utility model's double-sided heat dissipation high-power IPM packaging structure of circular symmetry distribution, by upper and lower two copper ceramic substrates, buffer layer, copper column realize the electrical connection of each part in module, so that module overall packaging structure is simplified, and realizes double-sided heat dissipation, can substantially improve module heat dissipation performance, to enhance the service life of module.

Description

Technical Field

[0001] This utility model relates to the field of IPM packaging technology, and in particular to a circularly symmetrically distributed, double-sided heat dissipation high-power IPM packaging structure. Background Technology

[0002] Intelligent Power Modules (IPMs) are highly integrated power electronic devices that combine power switches, drive circuits, and protection functions. They offer the following advantages: High Integration: Built-in IGBT / MOSFETs, drive circuits, and protection functions simplify design, reduce external components, and save space. High Efficiency and Energy Saving: Optimized switching characteristics reduce conduction and switching losses, improving system efficiency and making them suitable for high-frequency applications. Reliable Protection: Integrated overcurrent, short-circuit, over-temperature, and undervoltage protection functions provide fast response and enhance system safety. Excellent Heat Dissipation: Utilizing advanced packaging technology (such as DBC substrates), they offer excellent thermal conductivity, facilitating heat dissipation design and increasing power density. IPMs are widely used in frequency converters, servo drives, new energy sources, and home appliances, balancing high performance and high reliability, making them an ideal choice for modern power electronic systems.

[0003] With the increasing demand for higher voltage and current in high-power systems, the voltage levels of chips integrated within IPMs are constantly rising, and SiC MOSFET chips can also be selected as the main chips. However, in the case of three-phase parallel connection within an IPM module, the dispersion of parasitic parameters in the circuit leads to uneven electrical and thermal stress on the chips in each of the three phases. This causes some chips in the module to fail prematurely due to excessive stress, severely reducing the overall lifespan of the module. In addition, the use of high-power SiC chips places higher demands on the module's heat dissipation capabilities. Ordinary single-sided heat dissipation packaging will result in excessively high overall junction temperatures, which is very detrimental to the module. Summary of the Invention

[0004] The technical problem to be solved by this utility model is to provide a circularly symmetrically distributed, double-sided heat dissipation high-power IPM package structure to solve the above problem.

[0005] The technical solution of this utility model to solve the above-mentioned technical problems is: a circularly symmetrically distributed double-sided heat dissipation high-power IPM packaging structure, including an upper copper-ceramic substrate and a lower copper-ceramic substrate, wherein the upper copper-ceramic substrate is connected to the lower copper-ceramic substrate through an IPM module.

[0006] As a preferred technical solution of this utility model, the copper-clad ceramic substrate includes a copper layer on the copper-clad ceramic substrate, a ceramic layer on the copper-clad ceramic substrate is connected to the inner side of the copper layer on the copper-clad ceramic substrate, and a first phase copper layer, a second phase copper layer, a third phase copper layer, and an inner ring copper layer on the copper-clad ceramic substrate are respectively connected to the inner side of the ceramic layer on the copper-clad ceramic substrate. The copper-clad ceramic substrate includes a lower copper layer, a ceramic layer connected to the inner side of the lower copper layer, and a first phase copper layer, a second phase copper layer, a third phase copper layer, and an outer ring copper layer connected to the inner side of the ceramic layer.

[0007] As a preferred technical solution of this utility model, the IPM module includes a first phase IPM unit, a second phase IPM unit and a third phase IPM unit. The first phase IPM unit, the second phase IPM unit and the third phase IPM unit are respectively connected to the upper copper-clad ceramic substrate and the lower copper-clad ceramic substrate on both sides. The first phase IPM unit, the second phase IPM unit and the third phase IPM unit are symmetrically distributed in a circle in the internal space of the module.

[0008] As a preferred technical solution of this utility model, the bottom side of the first phase IPM unit is connected to the first phase copper layer of the lower copper-ceramic substrate and the outer ring copper layer of the lower copper-ceramic substrate, respectively, and the top of the first phase IPM unit is connected to the inner ring copper layer of the upper copper-ceramic substrate and the first phase copper layer of the upper copper-ceramic substrate, respectively. The bottom side of the second phase IPM unit is connected to the second phase copper layer of the lower copper-ceramic substrate and the outer ring copper layer of the lower copper-ceramic substrate, respectively. The top of the second phase IPM unit is connected to the inner ring copper layer of the upper copper-ceramic substrate and the second phase copper layer of the upper copper-ceramic substrate, respectively. The bottom side of the third phase IPM unit is connected to the third phase copper layer of the lower copper-clad ceramic substrate and the outer ring copper layer of the lower copper-clad ceramic substrate, respectively. The top of the third phase IPM unit is connected to the inner ring copper layer of the upper copper-clad ceramic substrate and the third phase copper layer of the upper copper-clad ceramic substrate, respectively.

[0009] As a preferred technical solution of this utility model, the first phase IPM unit includes a first inner bridge arm unit and a first outer bridge arm unit. The first outer bridge arm unit includes a first high-voltage SiC MOSFET chip and a first fast recovery diode chip. The drain of the lower surface of the first high-voltage SiC MOSFET chip is connected to the outer ring copper layer of the lower copper-ceramic substrate through a first phase first solder layer. The source of the upper surface of the first high-voltage SiC MOSFET chip is connected to the first phase first buffer layer through a first phase second solder layer. The first phase first buffer layer is connected to the first phase copper layer of the upper copper-ceramic substrate through a first phase third solder layer. The cathode on the lower surface of the first fast recovery diode chip is connected to the outer ring copper layer of the lower copper-ceramic substrate through the first phase fourth solder layer, and the anode on the upper surface of the first fast recovery diode chip is connected to the first phase second buffer layer through the first phase fifth solder layer, and the first phase second buffer layer is connected to the first phase copper layer of the upper copper-ceramic substrate through the first phase sixth solder layer. The first inner bridge arm unit includes a second high-voltage SiC MOSFET chip and a second fast recovery diode chip. The drain of the lower surface of the second high-voltage SiC MOSFET chip is connected to the first phase copper layer of the lower copper-ceramic substrate through the first phase seventh solder layer. The source of the upper surface of the second high-voltage SiC MOSFET chip is connected to the first phase third buffer layer through the first phase eighth solder layer. The first phase third buffer layer is connected to the inner ring copper layer of the upper copper-ceramic substrate through the first phase ninth solder layer. The cathode on the lower surface of the second fast recovery diode chip is connected to the first phase copper layer of the lower copper ceramic substrate through the tenth solder layer of the first phase. The anode on the upper surface of the second fast recovery diode chip is connected to the fourth buffer layer of the first phase through the eleventh solder layer of the first phase. The fourth buffer layer of the first phase is connected to the inner ring copper layer of the upper copper ceramic substrate through the twelfth solder layer of the first phase. The outer ring copper layer of the lower copper-clad ceramic substrate is connected to the first phase copper pillar through the lower solder layer of the first phase copper pillar, and the first phase copper pillar is connected to the inner ring copper layer of the upper copper-clad ceramic substrate through the upper solder layer of the first phase copper pillar.

[0010] As a preferred technical solution of this utility model, the second phase IPM unit includes a second inner bridge arm unit and a second outer bridge arm unit. The second outer bridge arm unit includes a third high-voltage SiC MOSFET chip and a third fast recovery diode chip. The drain of the lower surface of the third high-voltage SiC MOSFET chip is connected to the outer ring copper layer of the lower copper-ceramic substrate through the second phase first solder layer. The source of the upper surface of the third high-voltage SiC MOSFET chip is connected to the second phase first buffer layer through the second phase second solder layer. The second phase first buffer layer is connected to the second phase copper layer of the upper copper-ceramic substrate through the second phase third solder layer. The cathode on the lower surface of the third fast recovery diode chip is connected to the outer ring copper layer of the lower copper-clad ceramic substrate through the second phase fourth solder layer, and the anode on the upper surface of the third fast recovery diode chip is connected to the second phase second buffer layer through the second phase fifth solder layer, and the second phase second buffer layer is connected to the second phase copper layer of the upper copper-clad ceramic substrate through the second phase sixth solder layer. The second inner bridge arm unit includes a fourth high-voltage SiC MOSFET chip and a fourth fast recovery diode chip. The drain of the lower surface of the fourth high-voltage SiC MOSFET chip is connected to the second phase copper layer of the lower copper-ceramic substrate through the seventh solder layer of the second phase. The source of the upper surface of the fourth high-voltage SiC MOSFET chip is connected to the third buffer layer of the second phase through the eighth solder layer of the second phase. The third buffer layer of the second phase is connected to the inner ring copper layer of the upper copper-ceramic substrate through the ninth solder layer of the second phase. The cathode on the lower surface of the fourth fast recovery diode chip is connected to the second phase copper layer of the lower copper-ceramic substrate through the tenth solder layer of the second phase. The anode on the upper surface of the fourth fast recovery diode chip is connected to the fourth buffer layer of the second phase through the eleventh solder layer of the second phase. The fourth buffer layer of the second phase is connected to the inner ring copper layer of the upper copper-ceramic substrate through the twelfth solder layer of the second phase. The outer ring copper layer of the lower copper-ceramic substrate is connected to the second phase copper pillar through the lower solder layer of the second phase copper pillar, and the second phase copper pillar is connected to the inner ring copper layer of the upper copper-ceramic substrate through the upper solder layer of the second phase copper pillar.

[0011] As a preferred technical solution of this utility model, the third phase IPM unit includes a third inner bridge arm unit and a third outer bridge arm unit; The third outer bridge arm unit includes a fifth high-voltage SiC MOSFET chip and a fifth fast recovery diode chip. The drain of the lower surface of the fifth high-voltage SiC MOSFET chip is connected to the outer ring copper layer of the lower copper-ceramic substrate through the third phase first solder layer. The source of the upper surface of the fifth high-voltage SiC MOSFET chip is connected to the third phase first buffer layer through the third phase second solder layer. The third phase first buffer layer is connected to the third phase copper layer of the upper copper-ceramic substrate through the third phase third solder layer. The cathode on the lower surface of the fifth fast recovery diode chip is connected to the outer ring copper layer of the lower copper-ceramic substrate through the third phase fourth solder layer. The anode on the upper surface of the fifth fast recovery diode chip is connected to the third phase second buffer layer through the third phase fifth solder layer. The third phase second buffer layer is connected to the third phase copper layer of the upper copper-ceramic substrate through the third phase sixth solder layer. The third inner bridge arm unit includes a sixth high-voltage SiC MOSFET chip and a sixth fast recovery diode chip. The drain of the lower surface of the sixth high-voltage SiC MOSFET chip is connected to the third phase copper layer of the lower copper-ceramic substrate through the third phase seventh solder layer. The source of the sixth high-voltage SiC MOSFET chip is connected to the third phase third buffer layer through the third phase eighth solder layer. The third phase third buffer layer is connected to the inner ring copper layer of the upper copper-ceramic substrate through the third phase ninth solder layer. The cathode on the lower surface of the sixth fast recovery diode chip is connected to the third phase copper layer of the lower copper ceramic substrate through the tenth solder layer of the third phase, and the anode on the upper surface of the sixth fast recovery diode chip is connected to the fourth buffer layer of the third phase through the eleventh solder layer of the third phase, and the fourth buffer layer of the third phase is connected to the inner ring copper layer of the upper copper ceramic substrate through the twelfth solder layer of the third phase. The outer ring copper layer of the lower copper-clad ceramic substrate is connected to the third phase copper pillar through the lower solder layer of the third phase copper pillar, and the third phase copper pillar is connected to the inner ring copper layer of the upper copper-clad ceramic substrate through the upper solder layer of the third phase copper pillar.

[0012] As a preferred embodiment of this utility model, both the upper copper ceramic substrate ceramic layer and the lower copper ceramic substrate ceramic layer are made of aluminum nitride ceramic or alumina ceramic.

[0013] In a preferred embodiment of this invention, the upper copper layer of the upper copper-ceramic substrate is connected to the upper heat sink via an upper thermally conductive silicone grease layer, and the lower copper layer of the lower copper-ceramic substrate is connected to the lower heat sink via a lower thermally conductive silicone grease layer.

[0014] Because of this structure, the circularly symmetrically distributed, double-sided heat-dissipating high-power IPM package structure proposed in this invention features SiC MOSFET chips and fast recovery diode chips symmetrically distributed around the center of the copper-clad ceramic substrate. The parasitic parameters of each phase IPM unit are essentially the same, resulting in a more uniform current distribution. Electrical connections between the various parts of the module are achieved through the upper and lower copper-clad ceramic substrates, a buffer layer, and copper pillars, simplifying the overall package structure and enabling double-sided heat dissipation. This significantly improves the module's heat dissipation performance, thereby extending its lifespan. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of the IPM packaging structure described in this utility model.

[0016] Figure 2 This is a schematic diagram of the IPM packaging structure described in this utility model.

[0017] Figure 3 This is a cross-sectional schematic diagram of the IPM packaging structure described in this utility model.

[0018] Figure 4 This is a schematic diagram of the first phase IPM unit of the IPM packaging structure described in this utility model.

[0019] Figure 5 This is a schematic diagram of the second-phase IPM unit and the third-phase IPM unit of the IPM packaging structure described in this utility model.

[0020] Figure 6 This is a top view of the copper-ceramic substrate under the IPM packaging structure described in this utility model.

[0021] Figure 7 This is a bottom view of the copper-clad ceramic substrate of the IPM packaging structure described in this utility model.

[0022] In the diagram: 1 is the first high-voltage SiC MOSFET chip, 2 is the first fast recovery diode chip, 3 is the second high-voltage SiC MOSFET chip, 4 is the second fast recovery diode chip, 5 is the third high-voltage SiC MOSFET chip, 6 is the third fast recovery diode chip, 7 is the fourth high-voltage SiC MOSFET chip, 8 is the fourth fast recovery diode chip, 9 is the fifth high-voltage SiC MOSFET chip, 10 is the fifth fast recovery diode chip, and 11 is the sixth high-voltage SiC MOSFET chip. MOSFET chip, 12 is the sixth fast recovery diode chip, 13 is the first solder layer of the first phase, 14 is the second solder layer of the first phase, 15 is the third solder layer of the first phase, 16 is the fourth solder layer of the first phase, 17 is the fifth solder layer of the first phase, 18 is the sixth solder layer of the first phase, 19 is the seventh solder layer of the first phase, 20 is the eighth solder layer of the first phase, 21 is the ninth solder layer of the first phase, 22 is the tenth solder layer of the first phase, 23 is the eleventh solder layer of the first phase, 24 is the twelfth solder layer of the first phase, 25 is the lower solder layer of the first phase copper pillar, 26 is the upper solder layer of the first phase copper pillar, 27 is the first buffer of the first phase. Layer 28 is the second buffer layer of the first phase, layer 29 is the third buffer layer of the first phase, layer 30 is the fourth buffer layer of the first phase, layer 31 is the copper pillar of the first phase, layer 32 is the first solder layer of the second phase, layer 33 is the second solder layer of the second phase, layer 34 is the third solder layer of the second phase, layer 35 is the fourth solder layer of the second phase, layer 36 is the fifth solder layer of the second phase, layer 37 is the sixth solder layer of the second phase, layer 38 is the seventh solder layer of the second phase, layer 39 is the eighth solder layer of the second phase, layer 40 is the ninth solder layer of the second phase, layer 41 is the tenth solder layer of the second phase, layer 42 is the eleventh solder layer of the second phase, layer 43 is the twelfth solder layer of the second phase, and layer 44 is the lower solder layer of the copper pillar of the second phase. 45 is the solder layer on the second-phase copper pillar; 46 is the first buffer layer of the second phase; 47 is the second buffer layer of the second phase; 48 is the third buffer layer of the second phase; 49 is the fourth buffer layer of the second phase; 50 is the second-phase copper pillar; 51 is the first solder layer of the third phase; 52 is the second solder layer of the third phase; 53 is the third solder layer of the third phase; 54 is the fourth solder layer of the third phase; 55 is the fifth solder layer of the third phase; 56 is the sixth solder layer of the third phase; 57 is the seventh solder layer of the third phase; 58 is the eighth solder layer of the third phase; 59 is the ninth solder layer of the third phase; 60 is the tenth solder layer of the third phase; 61 is the eleventh solder layer of the third phase; 62... 63 is the third phase 12 solder layer, 64 is the third phase copper pillar lower solder layer, 65 is the third phase copper pillar upper solder layer, 66 is the third phase first buffer layer, 67 is the third phase second buffer layer, 68 is the third phase fourth buffer layer, 69 is the third phase copper pillar, 70 is the lower heat sink, 71 is the upper heat sink, 72 is the lower thermal conductive grease layer, 73 is the upper thermal conductive grease layer, 74 is the lower copper layer of the lower copper-clad ceramic substrate, 75 is the ceramic layer of the lower copper-clad ceramic substrate, 76 is the first phase copper layer of the lower copper-clad ceramic substrate, 77 is the second phase copper layer of the lower copper-clad ceramic substrate, and 78 is the third phase copper layer of the lower copper-clad ceramic substrate.79 is the outer ring copper layer of the lower copper-ceramic substrate; 80 is the upper copper layer of the upper copper-ceramic substrate; 81 is the ceramic layer of the upper copper-ceramic substrate; 82 is the first phase copper layer of the upper copper-ceramic substrate; 83 is the second phase copper layer of the upper copper-ceramic substrate; 84 is the third phase copper layer of the upper copper-ceramic substrate; 85 is the inner ring copper layer of the upper copper-ceramic substrate; 86 is the first phase IPM unit; 87 is the second phase IPM unit; and 88 is the third phase IPM unit. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0024] like Figures 1-6 As shown, the present invention discloses a circularly symmetrically distributed double-sided heat dissipation high-power IPM package structure, including an upper copper ceramic substrate and a lower copper ceramic substrate, wherein the upper copper ceramic substrate is connected to the lower copper ceramic substrate through an IPM module.

[0025] Furthermore, the copper-clad ceramic substrate includes a copper layer 80 on the copper-clad ceramic substrate, a ceramic layer 81 on the copper-clad ceramic substrate is connected to the inner side of the copper layer 80, and a first phase copper layer 82, a second phase copper layer 83, a third phase copper layer 84, and an inner ring copper layer 85 on the copper-clad ceramic substrate are respectively connected to the inner side of the ceramic layer 81. The copper-clad ceramic substrate includes a lower copper layer 74, a ceramic layer 75 connected to the inner side of the lower copper layer 74, and a first phase copper layer 76, a second phase copper layer 77, a third phase copper layer 78, and an outer ring copper layer 79 connected to the inner side of the ceramic layer 75.

[0026] Furthermore, the IPM module includes a first-phase IPM unit 86, a second-phase IPM unit 87, and a third-phase IPM unit 88. The two sides of the first-phase IPM unit 86, the second-phase IPM unit 87, and the third-phase IPM unit 88 are respectively connected to the upper copper-clad ceramic substrate and the lower copper-clad ceramic substrate. The first-phase IPM unit 86, the second-phase IPM unit 87, and the third-phase IPM unit 88 are arranged in a circular symmetrical distribution in the internal space of the module.

[0027] Furthermore, the bottom side of the first phase IPM unit 86 is connected to the first phase copper layer 76 of the lower copper-ceramic substrate and the outer ring copper layer 79 of the lower copper-ceramic substrate, respectively, and the top of the first phase IPM unit 86 is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate and the first phase copper layer 82 of the upper copper-ceramic substrate, respectively. The bottom side of the second phase IPM unit 87 is connected to the second phase copper layer 77 of the lower copper-ceramic substrate and the outer ring copper layer 79 of the lower copper-ceramic substrate, respectively. The top of the second phase IPM unit 87 is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate and the second phase copper layer 83 of the upper copper-ceramic substrate, respectively. The bottom side of the third phase IPM unit 88 is connected to the third phase copper layer 78 of the lower copper-ceramic substrate and the outer ring copper layer 79 of the lower copper-ceramic substrate, respectively. The top of the third phase IPM unit 88 is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate and the third phase copper layer 84 of the upper copper-ceramic substrate, respectively.

[0028] Furthermore, the first phase IPM unit 86 includes a first inner bridge arm unit and a first outer bridge arm unit. The first outer bridge arm unit includes a first high-voltage SiC MOSFET chip 1 and a first fast recovery diode chip 2. The drain of the lower surface of the first high-voltage SiC MOSFET chip 1 is connected to the outer ring copper layer 79 of the lower copper-ceramic substrate through the first phase first solder layer 13. The source of the upper surface of the first high-voltage SiC MOSFET chip 1 is connected to the first phase first buffer layer 27 through the first phase second solder layer 14. The first phase first buffer layer 27 is connected to the first phase copper layer 82 of the upper copper-ceramic substrate through the first phase third solder layer 15. The cathode on the lower surface of the first fast recovery diode chip 2 is connected to the outer ring copper layer 79 of the lower copper-ceramic substrate through the first phase fourth solder layer 16, and the anode on the upper surface of the first fast recovery diode chip 2 is connected to the first phase second buffer layer 28 through the first phase fifth solder layer 17, and the first phase second buffer layer 28 is connected to the first phase copper layer 82 of the upper copper-ceramic substrate through the first phase sixth solder layer 18. The first inner bridge arm unit includes a second high-voltage SiC MOSFET chip 3 and a second fast recovery diode chip 4. The drain of the lower surface of the second high-voltage SiC MOSFET chip 3 is connected to the first phase copper layer 76 of the lower copper-ceramic substrate through the first phase seventh solder layer 19. The source of the upper surface of the second high-voltage SiC MOSFET chip 3 is connected to the first phase third buffer layer 29 through the first phase eighth solder layer 20. The first phase third buffer layer 29 is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate through the first phase ninth solder layer 21. The cathode on the lower surface of the second fast recovery diode chip 4 is connected to the first phase copper layer 76 of the lower copper-ceramic substrate through the tenth solder layer 22 of the first phase. The anode on the upper surface of the second fast recovery diode chip 4 is connected to the fourth buffer layer 30 of the first phase through the eleventh solder layer 23 of the first phase. The fourth buffer layer 30 of the first phase is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate through the twelfth solder layer 24 of the first phase. The outer ring copper layer 79 of the lower copper ceramic substrate is connected to the first phase copper pillar 31 through the lower solder layer 25 of the first phase copper pillar, and the first phase copper pillar 31 is connected to the inner ring copper layer 85 of the upper copper ceramic substrate through the upper solder layer 26 of the first phase copper pillar.

[0029] Furthermore, the second phase IPM unit 87 of this utility model includes a second inner bridge arm unit and a second outer bridge arm unit; The second outer bridge arm unit includes a third high-voltage SiC MOSFET chip 5 and a third fast recovery diode chip 6. The drain of the lower surface of the third high-voltage SiC MOSFET chip 5 is connected to the outer ring copper layer 79 of the lower copper-ceramic substrate through the second phase first solder layer 32. The source of the upper surface of the third high-voltage SiC MOSFET chip 5 is connected to the second phase first buffer layer 46 through the second phase second solder layer 33. The second phase first buffer layer 46 is connected to the second phase copper layer 83 of the upper copper-ceramic substrate through the second phase third solder layer (34). The cathode on the lower surface of the third fast recovery diode chip 6 is connected to the outer ring copper layer 79 of the lower copper-clad ceramic substrate through the second phase fourth solder layer 35. The anode on the upper surface of the third fast recovery diode chip 6 is connected to the second phase second buffer layer 47 through the second phase fifth solder layer 36. The second phase second buffer layer 47 is connected to the second phase copper layer 83 of the upper copper-clad ceramic substrate through the second phase sixth solder layer 37. The second inner bridge arm unit includes a fourth high-voltage SiC MOSFET chip 7 and a fourth fast recovery diode chip 8. The drain of the lower surface of the fourth high-voltage SiC MOSFET chip 7 is connected to the second phase copper layer 77 of the lower copper-ceramic substrate through the second phase seventh solder layer 38. The source of the upper surface of the fourth high-voltage SiC MOSFET chip 7 is connected to the second phase third buffer layer 48 through the second phase eighth solder layer 39. The second phase third buffer layer 48 is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate through the second phase ninth solder layer 40. The cathode on the lower surface of the fourth fast recovery diode chip 8 is connected to the second phase copper layer 77 of the lower copper-ceramic substrate through the tenth solder layer 41 of the second phase. The anode on the upper surface of the fourth fast recovery diode chip 8 is connected to the fourth buffer layer 49 of the second phase through the eleventh solder layer 42 of the second phase. The fourth buffer layer 49 of the second phase is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate through the twelfth solder layer 43 of the second phase. The outer ring copper layer 79 of the lower copper ceramic substrate is connected to the second phase copper pillar 50 through the lower solder layer 44 of the second phase copper pillar, and the second phase copper pillar 50 is connected to the inner ring copper layer 85 of the upper copper ceramic substrate through the upper solder layer 45 of the second phase copper pillar.

[0030] Furthermore, the third phase IPM unit 88 of this utility model includes a third inner bridge arm unit and a third outer bridge arm unit. The third outer bridge arm unit includes a fifth high-voltage SiC MOSFET chip 9 and a fifth fast recovery diode chip 10. The drain of the lower surface of the fifth high-voltage SiC MOSFET chip 9 is connected to the outer ring copper layer 79 of the lower copper-ceramic substrate through the third phase first solder layer 51. The source of the upper surface of the fifth high-voltage SiC MOSFET chip 9 is connected to the third phase first buffer layer 65 through the third phase second solder layer 52. The third phase first buffer layer 65 is connected to the third phase copper layer 84 of the upper copper-ceramic substrate through the third phase third solder layer 53. The cathode on the lower surface of the fifth fast recovery diode chip 10 is connected to the outer ring copper layer 79 of the lower copper-clad ceramic substrate through the third phase fourth solder layer 54. The anode on the upper surface of the fifth fast recovery diode chip 10 is connected to the third phase second buffer layer 66 through the third phase fifth solder layer 55. The third phase second buffer layer 66 is connected to the third phase copper layer 84 of the upper copper-clad ceramic substrate through the third phase sixth solder layer 56. The third inner bridge arm unit includes a sixth high-voltage SiC MOSFET chip 11 and a sixth fast recovery diode chip 12. The drain of the lower surface of the sixth high-voltage SiC MOSFET chip 11 is connected to the third phase copper layer 78 of the lower copper-ceramic substrate through the third phase seventh solder layer 57. The source of the sixth high-voltage SiC MOSFET chip 11 is connected to the third phase third buffer layer 67 through the third phase eighth solder layer 58. The third phase third buffer layer 67 is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate through the third phase ninth solder layer 59. The cathode on the lower surface of the sixth fast recovery diode chip 12 is connected to the third phase copper layer 78 of the lower copper-ceramic substrate through the third phase tenth solder layer 60. The anode on the upper surface of the sixth fast recovery diode chip 12 is connected to the third phase fourth buffer layer 68 through the third phase eleventh solder layer 61. The third phase fourth buffer layer 68 is connected to the inner ring copper layer 85 of the upper copper-ceramic substrate through the third phase twelfth solder layer 62. The outer ring copper layer 79 of the lower copper ceramic substrate is connected to the third phase copper pillar 69 through the lower solder layer 63 of the third phase copper pillar, and the third phase copper pillar 69 is connected to the inner ring copper layer 85 of the upper copper ceramic substrate through the upper solder layer 64 of the third phase copper pillar.

[0031] Furthermore, in this invention, both the upper copper ceramic substrate ceramic layer 81 and the lower copper ceramic substrate ceramic layer 75 are made of aluminum nitride ceramic or aluminum oxide ceramic.

[0032] Furthermore, in this invention, the upper copper layer 80 of the upper copper-ceramic substrate is connected to the upper heat sink 71 through the upper thermally conductive silicone grease layer 73, and the lower copper layer 74 of the lower copper-ceramic substrate is connected to the lower heat sink 70 through the lower thermally conductive silicone grease layer 72.

[0033] The description and application of this utility model herein are illustrative and not intended to limit the scope of the utility model to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and practical substitutions and equivalent components of the embodiments are well known to those skilled in the art. It will be apparent to those skilled in the art that this utility model can be implemented in other forms, structures, arrangements, proportions, and with other elements, materials, and components without departing from the spirit or essential characteristics of the utility model. Other variations and modifications can be made to the embodiments disclosed herein without departing from the spirit or essential characteristics of the utility model.

Claims

1. A circularly symmetrically distributed, double-sided heat-dissipating high-power IPM package structure, characterized in that: It includes an upper copper-clad ceramic substrate and a lower copper-clad ceramic substrate. The upper copper-clad ceramic substrate is connected to the lower copper-clad ceramic substrate through an IPM module. The upper copper-clad ceramic substrate includes an upper copper layer (80), an upper copper-clad ceramic layer (81) connected to the inner side of the upper copper layer (80), and an upper copper-clad ceramic layer (82), a upper copper-clad ceramic layer (83), a upper copper-clad ceramic layer (84), and an inner ring copper layer (85) of the upper copper-clad ceramic substrate respectively connected to the inner side of the upper copper-clad ceramic layer (81). The copper-clad ceramic substrate includes a lower copper layer (74), a lower copper-clad ceramic layer (75) connected to the inner side of the lower copper layer (74), and a first phase copper layer (76), a second phase copper layer (77), a third phase copper layer (78), and an outer ring copper layer (79) connected to the inner side of the lower copper-clad ceramic layer (75).

2. The circularly symmetrically distributed, double-sided heat dissipation high-power IPM package structure according to claim 1, characterized in that: The IPM module includes a first phase IPM unit (86), a second phase IPM unit (87), and a third phase IPM unit (88). The first phase IPM unit (86), the second phase IPM unit (87), and the third phase IPM unit (88) are connected to the upper copper-clad ceramic substrate and the lower copper-clad ceramic substrate on their respective sides. The first phase IPM unit (86), the second phase IPM unit (87), and the third phase IPM unit (88) are arranged in a circular symmetrical distribution in the internal space of the module.

3. The circularly symmetrically distributed, double-sided heat dissipation high-power IPM package structure according to claim 2, characterized in that: The bottom side of the first phase IPM unit (86) is connected to the first phase copper layer (76) of the lower copper ceramic substrate and the outer ring copper layer (79) of the lower copper ceramic substrate, respectively. The top of the first phase IPM unit (86) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate and the first phase copper layer (82) of the upper copper ceramic substrate, respectively. The bottom side of the second phase IPM unit (87) is connected to the second phase copper layer (77) of the lower copper ceramic substrate and the outer ring copper layer (79) of the lower copper ceramic substrate, respectively. The top of the second phase IPM unit (87) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate and the second phase copper layer (83) of the upper copper ceramic substrate, respectively. The bottom side of the third phase IPM unit (88) is connected to the third phase copper layer (78) of the lower copper ceramic substrate and the outer ring copper layer (79) of the lower copper ceramic substrate, respectively. The top of the third phase IPM unit (88) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate and the third phase copper layer (84) of the upper copper ceramic substrate, respectively.

4. The circularly symmetrically distributed, double-sided heat dissipation high-power IPM package structure according to claim 3, characterized in that: The first phase IPM unit (86) includes a first inner bridge arm unit and a first outer bridge arm unit; The first outer bridge arm unit includes a first high-voltage SiC MOSFET chip (1) and a first fast recovery diode chip (2). The drain of the lower surface of the first high-voltage SiC MOSFET chip (1) is connected to the outer ring copper layer (79) of the lower copper ceramic substrate through the first phase first solder layer (13). The source of the upper surface of the first high-voltage SiC MOSFET chip (1) is connected to the first phase first buffer layer (27) through the first phase second solder layer (14). The first phase first buffer layer (27) is connected to the first phase copper layer (82) of the upper copper ceramic substrate through the first phase third solder layer (15). The cathode on the lower surface of the first fast recovery diode chip (2) is connected to the outer ring copper layer (79) of the lower copper ceramic substrate through the first phase fourth solder layer (16), and the anode on the upper surface of the first fast recovery diode chip (2) is connected to the first phase second buffer layer (28) through the first phase fifth solder layer (17), and the first phase second buffer layer (28) is connected to the first phase copper layer (82) of the upper copper ceramic substrate through the first phase sixth solder layer (18). The first inner bridge arm unit includes a second high-voltage SiC MOSFET chip (3) and a second fast recovery diode chip (4). The drain of the lower surface of the second high-voltage SiC MOSFET chip (3) is connected to the first phase copper layer (76) of the lower copper ceramic substrate through the first phase seventh solder layer (19). The source of the upper surface of the second high-voltage SiC MOSFET chip (3) is connected to the first phase third buffer layer (29) through the first phase eighth solder layer (20). The first phase third buffer layer (29) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate through the first phase ninth solder layer (21). The cathode on the lower surface of the second fast recovery diode chip (4) is connected to the first phase copper layer (76) of the lower copper ceramic substrate through the first phase tenth solder layer (22), and the anode on the upper surface of the second fast recovery diode chip (4) is connected to the first phase fourth buffer layer (30) through the first phase eleventh solder layer (23), and the first phase fourth buffer layer (30) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate through the first phase twelfth solder layer (24). The outer ring copper layer (79) of the lower copper ceramic substrate is connected to the first phase copper pillar (31) through the lower solder layer (25) of the first phase copper pillar, and the first phase copper pillar (31) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate through the upper solder layer (26) of the first phase copper pillar.

5. The circularly symmetrically distributed, double-sided heat dissipation high-power IPM package structure according to claim 3, characterized in that: The second phase IPM unit (87) includes a second inner bridge arm unit and a second outer bridge arm unit; The second outer bridge arm unit includes a third high-voltage SiC MOSFET chip (5) and a third fast recovery diode chip (6). The drain of the lower surface of the third high-voltage SiC MOSFET chip (5) is connected to the outer ring copper layer (79) of the lower copper-ceramic substrate through the second phase first solder layer (32). The source of the upper surface of the third high-voltage SiC MOSFET chip (5) is connected to the second phase first buffer layer (46) through the second phase second solder layer (33). The second phase first buffer layer (46) is connected to the second phase copper layer (83) of the upper copper-ceramic substrate through the second phase third solder layer (34). The cathode on the lower surface of the third fast recovery diode chip (6) is connected to the outer ring copper layer (79) of the lower copper-clad ceramic substrate through the second phase fourth solder layer (35), and the anode on the upper surface of the third fast recovery diode chip (6) is connected to the second phase second buffer layer (47) through the second phase fifth solder layer (36), and the second phase second buffer layer (47) is connected to the second phase copper layer (83) of the upper copper-clad ceramic substrate through the second phase sixth solder layer (37). The second inner bridge arm unit includes a fourth high-voltage SiC MOSFET chip (7) and a fourth fast recovery diode chip (8). The drain of the lower surface of the fourth high-voltage SiC MOSFET chip (7) is connected to the second phase copper layer (77) of the lower copper-ceramic substrate through the second phase seventh solder layer (38). The source of the upper surface of the fourth high-voltage SiC MOSFET chip (7) is connected to the second phase third buffer layer (48) through the second phase eighth solder layer (39). The second phase third buffer layer (48) is connected to the inner ring copper layer (85) of the upper copper-ceramic substrate through the second phase ninth solder layer (40). The cathode on the lower surface of the fourth fast recovery diode chip (8) is connected to the second phase copper layer (77) of the lower copper ceramic substrate through the tenth solder layer (41) of the second phase. The anode on the upper surface of the fourth fast recovery diode chip (8) is connected to the fourth buffer layer (49) of the second phase through the eleventh solder layer (42) of the second phase. The fourth buffer layer (49) of the second phase is connected to the inner ring copper layer (85) of the upper copper ceramic substrate through the twelfth solder layer (43) of the second phase. The outer ring copper layer (79) of the lower copper ceramic substrate is connected to the second phase copper pillar (50) through the lower solder layer (44) of the second phase copper pillar, and the second phase copper pillar (50) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate through the upper solder layer (45) of the second phase copper pillar.

6. The circularly symmetrically distributed, double-sided heat dissipation high-power IPM package structure according to claim 3, characterized in that: The third phase IPM unit (88) includes a third inner bridge arm unit and a third outer bridge arm unit; The third outer bridge arm unit includes a fifth high-voltage SiC MOSFET chip (9) and a fifth fast recovery diode chip (10). The drain of the lower surface of the fifth high-voltage SiC MOSFET chip (9) is connected to the outer ring copper layer (79) of the lower copper-ceramic substrate through the third phase first solder layer (51). The source of the upper surface of the fifth high-voltage SiC MOSFET chip (9) is connected to the third phase first buffer layer (65) through the third phase second solder layer (52). The third phase first buffer layer (65) is connected to the third phase copper layer (84) of the upper copper-ceramic substrate through the third phase third solder layer (53). The cathode on the lower surface of the fifth fast recovery diode chip (10) is connected to the outer ring copper layer (79) of the lower copper ceramic substrate through the third phase fourth solder layer (54), and the anode on the upper surface of the fifth fast recovery diode chip (10) is connected to the third phase second buffer layer (66) through the third phase fifth solder layer (55), and the third phase second buffer layer (66) is connected to the third phase copper layer (84) of the upper copper ceramic substrate through the third phase sixth solder layer (56). The third inner bridge arm unit includes a sixth high-voltage SiC MOSFET chip (11) and a sixth fast recovery diode chip (12). The drain of the lower surface of the sixth high-voltage SiC MOSFET chip (11) is connected to the third phase copper layer (78) of the lower copper ceramic substrate through the third phase seventh solder layer (57). The source of the upper surface of the sixth high-voltage SiC MOSFET chip (11) is connected to the third phase third buffer layer (67) through the third phase eighth solder layer (58). The third phase third buffer layer (67) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate through the third phase ninth solder layer (59). The cathode on the lower surface of the sixth fast recovery diode chip (12) is connected to the third phase copper layer (78) of the lower copper ceramic substrate through the tenth solder layer (60) of the third phase. The anode on the upper surface of the sixth fast recovery diode chip (12) is connected to the fourth buffer layer (68) of the third phase through the eleventh solder layer (61) of the third phase. The fourth buffer layer (68) of the third phase is connected to the inner ring copper layer (85) of the upper copper ceramic substrate through the twelfth solder layer (62) of the third phase. The outer ring copper layer (79) of the lower copper ceramic substrate is connected to the third phase copper pillar (69) through the lower solder layer (63) of the third phase copper pillar, and the third phase copper pillar (69) is connected to the inner ring copper layer (85) of the upper copper ceramic substrate through the upper solder layer (64) of the third phase copper pillar.

7. The circularly symmetrically distributed, double-sided heat dissipation high-power IPM package structure according to claim 1, characterized in that: The upper copper ceramic substrate ceramic layer (81) and the lower copper ceramic substrate ceramic layer (75) are both made of aluminum nitride ceramic or alumina ceramic.

8. The circularly symmetrically distributed, double-sided heat dissipation high-power IPM package structure according to claim 1, characterized in that: The upper copper layer (80) of the upper copper-clad ceramic substrate is connected to the upper heat sink (71) through the upper thermally conductive silicone grease layer (73), and the lower copper layer (74) of the lower copper-clad ceramic substrate is connected to the lower heat sink (70) through the lower thermally conductive silicone grease layer (72).

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