Semiconductor device

Abstract

Semiconductor device comprising the following: a substrate (102) on which a gate structure (212) is formed, which has a trench (404) with opposing side faces (414) and a bottom surface (416) defined on the substrate (102), wherein the gate structure includes the following: a gate dielectric layer (216) arranged along the opposite side faces (414) and the bottom face (416); a growth control material (412) arranged on upper sections of the opposite side surfaces (414) of the gate structure (212), wherein the lateral thickness of the growth control material (412) decreases continuously from the upper surface downwards; and a gate electrode filling material (418) arranged on the growth control material (412), on lower sections of the side surfaces (414) and on the bottom surface (416) of the gate structure (212), wherein the lower sections of the side surfaces (414) and the bottom surface (416) of the gate structure (212) are free of the growth control material (412).

Description

BACKGROUND

[0001] The semiconductor industry has evolved into nanometer-scale processing nodes in its pursuit of higher device density, increased performance, and lower costs. Despite groundbreaking advances in materials and fabrication, scaling up planar devices, such as the conventional MOSFET, has proven challenging. For example, deposition techniques, etching techniques, and other processes that circulate liquids, gases, or plasma across device structures generally work well when the structural elements are widely spaced and readily accessible to surrounding reactants. However, narrow trenches and high-aspect-ratio cavities restrict circulation and reduce the number of reactants available within the trench. This can lead to uneven deposition or etching within the trench.

[0002] To further develop the technology, circuit designers are currently searching for novel structures to increase performance. One area of ​​research is the development of three-dimensional designs, such as a fin-like field-effect transistor (FinFET). A FinFET can be visualized as a typical planar device that has been extruded from a substrate and into the gate. A typical FinFET is fabricated with a thin "rib" (or rib structure) extending upward from the substrate. The FET's channel is formed within this vertical rib, and a gate is formed over the channel region of the rib (for example, wrapped around it). Wrapping the gate around the rib increases the contact area between the channel region and the gate, allowing the gate to control the channel from multiple sides.This can be exploited synergistically in various ways, and in some applications, FinFETs enable reduced short-channel effects, reduced leakage currents, and higher current flow. Or, put another way, they can be faster, smaller, and more efficient than planar devices.

[0003] However, FinFETs and other non-planar devices have even more complex geometries and can have more high-aspect-ratio trenches that need to be filled. Accordingly, while conventional device fabrication techniques were adequate in some respects, they were less satisfactory in others. To meet the ever-increasing design requirements, further advances in device fabrication and other areas are needed. This disclosure provides improvements relating to the fabrication of planar devices as well as FinFETs and other non-planar devices. The closest prior art in this respect is represented, for example, by US 2012 / 0 256 238 A1, WO 2013 / 095 433 A1, US 2010 / 0 255 669 A1, and US 2014 / 0 103 404 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale and are used for illustrative purposes only. The dimensions of the various structural elements may be enlarged or reduced as necessary for the clarity of the discussion. Furthermore, various elements and features are shown in the figures, not all of which are labeled with a reference number for the sake of clarity. It is understood, however, that symmetrical structural elements and items are arranged similarly. Fig. Figure 1 is a cross-sectional view of a semiconductor device according to embodiments of the present disclosure. Fig. Figure 2A is a perspective view of a non-planar semiconductor device according to embodiments of the present disclosure. Fig. 2B is a cross-sectional view of the non-planar semiconductor device, wherein the cross-section was taken through a channel region, according to embodiments of the present disclosure. Fig. 2C is a cross-sectional view of the non-planar semiconductor device, wherein the cross-section was taken through a source / drain region, according to embodiments of the present disclosure. Fig. Figure 3 is a flowchart of a method for manufacturing a gate electrode according to embodiments of the present disclosure. The Fig. Figures 4-11 are cross-sectional views of a section of a non-planar component that is subjected to the method for manufacturing a gate electrode according to embodiments of the present disclosure. The Fig. Figures 12-19 are cross-sectional views of a section of a planar component that is subjected to the method for manufacturing a gate electrode according to embodiments of the present disclosure. Fig. Figure 20 is a flowchart of a method for forming a contact or through-contact according to embodiments of the present disclosure. The Fig. Figures 21-26B are cross-sectional views of a section of a planar component that is subjected to the method of forming a contact according to embodiments of the present disclosure. The Fig. 27A and Fig. Figure 27B shows cross-sectional views of a source / drain region of a non-planar component that is subjected to the method of making a contact according to embodiments of the present disclosure. The Fig. 28A and Fig. Figure 28B shows cross-sectional views of a channel region of a non-planar component that is subjected to the method of making a contact according to embodiments of the present disclosure. The Fig. 29A and Fig. Figure 29B shows cross-sectional views of a semiconductor device undergoing the process of creating a through-contact according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] The present disclosure relates generally to the manufacture of IC components, and in particular to the formation of conductive structural elements such as gates, contacts and vias of components.

[0006] It is understood that the following disclosure provides many different embodiments or examples for implementing various features of different embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.Furthermore, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features, so that the first and second features may not be in direct contact.

[0007] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of an element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. For example, if the component in the figures is inverted, elements described as "below" or "underneath" other elements or structural elements would then be oriented "above" them. That is, the exemplary term "below" can encompass an orientation both above and below.The device can also be oriented differently (rotated 90 degrees or oriented differently), and the spatially relative descriptors used in the present text can be interpreted accordingly.

[0008] A process for fabricating conductive structural elements is described, enabling improved gap filling in high-aspect-ratio trenches. The technique reduces (and even eliminates) constrictions, voids, and discontinuities that can occur with other deposition techniques and is useful for forming gates, contacts, vias, and other device structures. (For context, see below.) Fig. 1 and the Fig. 2A-2C planar and non-planar semiconductor devices, and some of their structural elements, can be formed by the processes of the present disclosure. Of course, these structural elements are merely examples, and the technique can be used to form any suitable structural element in any type of device.

[0009] Let's turn first to... Fig. 1, which illustrates a cross-sectional view of a semiconductor device 100 according to embodiments of the present disclosure. Fig. Figure 1 has been simplified for clarity and to better illustrate the concept of this disclosure. The semiconductor device 100 is typical of a planar MOSFET and is exemplary for both n-type metal-oxide-semiconductor transistor devices (referred to as NMOS devices) and p-type metal-oxide-semiconductor transistor devices (referred to as PMOS devices). The device 100 is formed on a substrate 102, such as a bulk silicon substrate. Alternatively, the substrate 102 may comprise an elemental (consisting of a single element) semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon-germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; and / or combinations thereof.Possible substrates 102 include a silicon-on-insulator (SOI) substrate. SOI substrates are produced by separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. In other examples, the substrate 102 may contain a multilayer semiconductor structure.

[0010] Substrate 102 can contain various doped regions (for example, p-type or n-type wells), such as the illustrated source / drain regions 104. Depending on the design requirements, the doped regions can be doped with p-type dopants, such as phosphorus or arsenic, and / or with n-type dopants, such as boron or BF₂. The doped regions can be formed directly on the substrate, in a p-well structure, an n-well structure, a double-well structure, or by means of a raised structure. Doped regions can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.In some embodiments, the doped regions contain halo or pocket regions that can reduce short-channel effects (for example, puncture effects) and can be formed by tilt-angle ion implantation or another suitable technique.

[0011] The semiconductor device 100 can include a gate structure 106 arranged on the substrate between the source / drain regions 104. The flow of carriers (electrons for an n-channel device and holes for a p-channel device) through a channel region between the source / drain regions 104 is controlled by a voltage applied to the gate structure 106. Suitable gate structures 106 include both polysilicon and metal gates. In an embodiment using a gate-first process, the gate structure 106 is a functional gate. Conversely, in an embodiment using a gate-last process, the gate structure 106 can be a functional gate or a sacrificial or dummy gate. In the exemplary gate-last process, a section of a sacrificial gate structure is removed and replaced by a functional gate material, such as a metal, to form a functional gate structure 106.The gate structure 106 can contain multiple layers, and in the illustrated embodiment, the gate structure 106 includes an interfacial layer (IL) 108, a dielectric layer 110, a cover layer 112, and a gate electrode 114. In some embodiments, sidewall spacers 116 are formed on one or more side faces of the gate structure.

[0012] To describe these features in more detail, the interface 108 is arranged on the substrate 102 and can contain an interface material such as silicon oxide, silicon nitride, silicon oxynitride, other semiconductor oxides, other suitable interface materials, and / or combinations thereof. The interface 108 can be formed to any suitable thickness using any suitable process, such as thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), physical vapor deposition (PVD), spin deposition, and / or other suitable deposition processes.

[0013] The gate dielectric layer 110 is arranged on the interface 108 and can comprise one or more dielectric materials, commonly characterized by their dielectric constant relative to silicon dioxide. That is, the gate dielectric layer 110 can contain a high K-value dielectric material, such as HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO₂-Al₂O₃) alloy, other suitable high K-value dielectric materials, and / or combinations thereof. Alternatively, or in addition, the gate dielectric layer 110 can contain other dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous carbon, tetraethyl orthosilicate (TEOS), other suitable dielectric materials, and / or combinations thereof.The gate dielectric layer 110 can be formed to any suitable thickness using any suitable process, such as ALD, CVD, HDP-CVD, PVD, spin coating and / or other suitable deposition processes.

[0014] The exemplary gate structure 106 can include a cover layer 112 arranged on the gate dielectric layer 110. The cover layer 112 can contain silicon oxide, silicon nitride, silicon oxynitride, other semiconductor oxides, other semiconductor nitrides, other suitable materials and / or combinations thereof.

[0015] A gate electrode 114 is arranged above the gate dielectric layer 110 and the cover layer 112, if present. Notwithstanding naming conventions, such as MOSFET, the semiconductor device 100 also includes embodiments with polysilicon-containing gate electrodes 114 as well as metal-containing electrodes 114. The gate electrode 114 can have a multilayer structure comprising one or more of the following: an adhesion layer, a wetting layer, a lining layer, and a metallic filler layer. Accordingly, the gate electrode 114 can contain any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0016] In some embodiments employing a gate-last process, the gate electrode 114 includes a sacrificial or dummy section containing polysilicon, a dielectric, a masking material, and / or other suitable materials. In such embodiments, the sacrificial section can be wholly or partially removed by a suitable wet and / or dry etching process and replaced by another gate electrode, such as a metal-containing gate electrode 114. As described in more detail below, the deposition technique of the present disclosure is suitable for use in forming a metallic gate in a recess created by removing a sacrificial gate section, even where the high aspect ratio (depth-to-width ratio) of the recess may pose difficulties for conventional deposition processes.

[0017] In some embodiments, gate spacers 116 or sidewall spacers are formed on each side of the gate structure 106 (at the sidewalls of the gate structure 106). The gate spacers 116 can be used to align the source / drain regions 104 and can provide a rigid surface to prevent trench collapse during a gate replacement process. The gate spacers 116 can comprise any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor carbide, a semiconductor oxynitride, other suitable materials, and / or combinations thereof.

[0018] To integrate the semiconductor device 100 into a circuit, an interconnect structure can be formed on the device 100. In the illustrated embodiment, the interconnect structure comprises a number of conductive traces 118 inserted between layers of an inter-level dielectric (ILD) 120. The ILD 120 can comprise any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, TEOS oxide, phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicon dioxide glass (FSG), carbon-doped silicon dioxide, or Black Diamond. ®Xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (bis-benzocyclobutene), SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable materials, and / or combinations thereof. The ILD 120 layers act as an insulator, supporting and insulating the conductive traces 118. Through-contacts 122 extend through the ILD 120 layers to connect conductive traces 118 at various horizontal positions, and contacts 124 extend through the ILD 120 layers to connect to source / drain regions 104, gate structures 106, and other structural elements on or near the substrate 102. As will be shown, the technique of the present disclosure is suitable for forming contacts 124 and through-holes 122. Of course, the contacts 124, through-holes 122 and the gate electrode 114 mentioned above are merely some examples of structural elements of components that can be formed by this technique.

[0019] While Fig. 1. Exemplary structural elements of planar building elements that can be formed using the technique discussed here are highlighted. Fig. 2A-2C are exemplary structural elements of a non-planar component that can be formed using the technique discussed here. Fig. Figure 2A is a perspective view of a non-planar semiconductor device 200 according to embodiments of the present disclosure. Fig. 2B is a cross-sectional view of a section of the semiconductor device 200, wherein the cross-section passes through a channel region (along plane 202), according to embodiments of the present disclosure. Fig. Figure 2C is a cross-sectional view of a section of the semiconductor device 200, wherein the cross-section was taken through a source / drain region (along plane 204), according to embodiments of the present disclosure. Fig. 2A-2C have been simplified for the sake of clarity and to better illustrate the concept of the present revelation.

[0020] We turn to the Fig. 2A-2C. The semiconductor device 200 comprises a substrate 102 or a wafer with one or more raised rib structures 206 formed on it. The rib structures 206 are representative of all raised structural elements, and although the illustrated embodiments include FinFET rib structures 206, other embodiments include other raised active and passive elements formed on the substrate 102. The illustrated rib structures 206 each comprise a pair of opposing source / drain regions 208, which may contain different doped semiconductor materials, and a channel region 210 located between the source / drain regions 208. The flow of carriers through the channel region 210 is controlled by a voltage applied to a gate structure 212 located adjacent to and surrounding the channel region 210.One of the gate structures 212 is shown translucent to better illustrate the underlying channel region 210. In the illustrated embodiment, the channel region 210 rises above the plane of the substrate 102 on which it is formed, and accordingly, the rib structure 206 can be described as a “non-planar” device. The raised channel region 210 provides a larger surface area near the gate structure 212 than in comparable planar devices. This enhances the electromagnetic field interactions between the gate structure 212 and the channel region 210, thereby reducing leakage currents and short-channel effects that occur in smaller devices. In this way, in many embodiments, FinFETs and other non-planar devices perform better on a smaller footprint than their planar counterparts.

[0021] The elements of the semiconductor device 200 will now be described in more detail. The substrate 102 can essentially be compared to the substrate 102 of Fig. 1 resembles and can contain any suitable semiconductor and / or non-semiconductor material. For example, substrate 102 can contain one or more layers of an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon-germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; a non-semiconductor material, such as soda-lime glass, silica glass, fused silica, calcium fluoride (CaF2); other suitable materials; and / or combinations thereof.

[0022] The rib structures 206 are formed on the substrate 102 by removing surrounding sections of the substrate 102, leaving the rib structures 206 exposed, and / or by depositing material to grow the rib structures 206 on the substrate 102. After a gate structure 212 has been formed to protect the channel regions 210 of the rib structures, additional semiconductor material can be added to the source / drain regions 208 of the rib structure 206. In many embodiments, the additional material is deposited by one or more epitaxial or epitaxial (epi) processes, thereby growing Si structural elements, SiGe structural elements, and / or other suitable structural elements in a crystalline state on the rib structure 206.Suitable epitaxy processes include CVD deposition techniques (for example, vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The material of the source / drain regions 208 can be doped in situ during the epitaxy process by incorporating dopant species containing p-type dopants, such as boron or BF₂; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the source / drain regions 208 are not doped in situ, an implantation process (i.e., a boundary layer implantation process) is performed to dope the regions 208.

[0023] The gate structure 212 is formed on one or more of the rib structures 206 and can include an interface layer 214, a gate dielectric layer 216, a cover layer 218, and a gate electrode 220, which is arranged on and around the channel region 210 of the rib structures 206. Each of these elements can be substantially similar in composition to its planar device counterparts. For example, the interface layer 214 can contain an oxide, HfSiO₂, a nitride, an oxynitride, and / or another suitable material and can be deposited by any suitable process, such as thermal oxidation, ALD, CVD, ozone oxidation, etc.The gate dielectric layer 216 can contain any suitable dielectric, such as a high K-value dielectric material, including: LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃ (STO), BaTiO₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO₃ (BST), Al₂O₃, Si₃N₄, oxynitrides (SiON), and / or other suitable materials. The cover layer 218 can comprise silicon oxide, silicon nitride, silicon oxynitride, other semiconductor oxides, other semiconductor nitrides, other suitable materials, and / or combinations thereof.

[0024] The gate electrode 220 is arranged on the gate dielectric layer 216 and on the cover layer 218, if present, and in various examples comprises polysilicon, metals, metal alloys, metal compounds, and / or non-metallic conductors. Suitable metals include W, Al, Cu, Ti, Ag, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, and / or other suitable materials. In some embodiments, different gate materials are used for nMOS and pMOS devices. The gate electrode 220 can have a multilayer structure comprising one or more of the following: an adhesion layer, a wetting layer, a lining layer, and a metallic filler layer. As with the planar device, the technique of the present disclosure can be used to form the gate electrode 220 as part of a gate replacement process or other gate formation technique.

[0025] The gate structure 212 can also include one or more sidewall spacer layers 222, two of which are shown. Suitable materials for the sidewall spacer layers 222 include dielectrics such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, and / or other dielectrics. In some examples, the sidewall spacer layers 222 contain alternating layers of different dielectrics, such as a first semiconductor oxide spacer layer and a second semiconductor nitride spacer layer. Any one of a number of techniques can be used to form the sidewall spacer layers 222, such as CVD, PVD, ALD, and / or other suitable deposition techniques.

[0026] Similar to the exemplary planar component, an interconnect structure is arranged on the substrate 102 and on the gate structure 212, which contains a number of conductor tracks 118 arranged between layers of an interlayer dielectric (ILD) 120. For clarity, the interconnect structure is not shown in Fig. 2A illustrates this so that other structural elements do not fade into the background. As in the planar example of Fig. 1 The technique of the present disclosure is suitable for producing contacts 124 and through-contacts 122 within the interconnect structure of the non-planar component 200.

[0027] An application that uses the technique discussed here to form a gate electrode is referred to as the Fig. 3-11 described. Fig. Figure 3 is a flowchart of the process 300 for forming a gate electrode according to embodiments of the present disclosure. It is understood that additional steps may be provided before, during, and after the process 300, and that some of the described steps may be replaced or omitted in other embodiments of the process 300. Fig. Figures 4-11 are cross-sectional views of a section of a non-planar device 200 that is subjected to the method 300 for forming the gate electrode, according to embodiments of the present disclosure. Examples applying the method 300 to a planar device are described with reference to later figures.

[0028] We turn to Block 302 of Fig. 3 as well as Fig. 4 to, where a substrate 102 is received, which contains a semiconductor device 200. The substrate 102 and the semiconductor device 200 can each be substantially like those of the Fig. 2A-2C are similar, and for the sake of brevity, similar elements are not described again. In the embodiment of Fig. 4 The semiconductor device 200 contains a section of a gate structure 212 essentially similar to that of Fig. 2A. The gate structure includes a sacrificial gate electrode 402, which may contain polysilicon, a dielectric, a masking material, and / or another suitable material. We turn to block 304 of Fig. 3 as well as Fig. 5 to where the sacrificial gate electrode 402 is removed, leaving a trench 404 defined by the sidewall spacing layers 222. Partly due to the geometry of the trench 404, the formation of layers within the trench 404 can prove challenging. For example, the trench 404 may have a high aspect ratio and / or narrow internal cavities where the deposition reaction participants do not circulate well.

[0029] A gate dielectric layer 216 of the gate structure 212 can be formed either before or after the removal of the sacrificial gate electrode 402. In the example of block 306 of Fig. 3 and Fig. 6. The gate dielectric layer 216 is formed within the trench 404 after the sacrificial gate electrode 402 has been removed. In the illustrated embodiment, the gate dielectric layer 216 is formed on the interface layer 214 in the trench 404 and also extends along the vertical surfaces of the sidewall spacer layers 222 such that the sections of the gate dielectric layer 216 on the vertical surfaces extend over the sections of the gate dielectric layer 216 on the interface layer 214. This creates a U-shaped structure. In some embodiments, a highly conformal deposition technique, such as CVD or ALD, is used to deposit the gate dielectric layer 216 in the U-shaped configuration, although non-conformal deposition techniques can also be used.In these and other embodiments, suitable deposition processes include CVD, high-density plasma CVD (HDP-CVD), ALD, PVD, spin deposition, and / or other suitable deposition processes. The gate dielectric layer 216 can have a similar composition to that in the [references]. Fig. 1-2C.

[0030] An exit working layer 406 of the gate structure 212 can also be formed either before or after the removal of the sacrificial gate electrode 402. In the example of block 308 of Fig. 3 and Fig. 6. The exit work layer 406 is formed on the gate dielectric layer 216 within the trench 404 after the sacrificial gate electrode 402 has been removed. The exit work layer 406 can be used to tune the threshold voltage of the resulting semiconductor device and, for this purpose, can contain a material specific to the type of device 200 being fabricated (for example, n-type exit work material for an n-type device, p-type exit work material for a p-type device). Exemplary p-type exit work metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type exit work materials, and / or combinations thereof. Examples of n-type exit metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type exit metals and / or combinations thereof.The exit working layer 406 can contain multiple layers and can be deposited to any suitable thickness by CVD, PVD, and / or other suitable processes. In the illustrated embodiment, the exit working layer 406 extends along the vertical surfaces of the gate dielectric layer 216 to form a U-shaped structure.

[0031] We turn to Block 310 of Fig. 3 as well as Fig. 7. A wetting layer 408 can be deposited on the gate dielectric layer 216 and / or the exit work layer 406. The wetting layer 408 strengthens the bonding between the layers and can promote uniform deposition of subsequent layers. In various examples, the wetting layer 408 contains Ti, Ta, Ni, Co, other metals, and / or combinations thereof. The wetting layer 408 can be formed within the trench 404 using any suitable deposition technique, such as ALD, CVD, and / or sputtering, and can be formed to any suitable thickness.

[0032] We turn to Block 310 of Fig. 3 as well as Fig. 8. A barrier layer 410 can be deposited on the wetting layer 408. The barrier layer 410 can be structured to prevent subsequent deposition processes from degrading other layers of the device 200. For example, some metals tend to diffuse into silicon-containing layers during deposition and even after fabrication is complete. Accordingly, the barrier layer 410 can contain TiN, TaN, and / or other suitable metals, metal oxides, and / or metal nitrides. Similar to the wetting layer 408, the barrier layer 410 can be deposited within the trench 404 using any suitable process, such as ALD, CVD, and / or sputtering, and can be deposited to any suitable thickness. In some embodiments, a single deposition step deposits a metal common to both the wetting layer 408 and the barrier layer 410.The metal of barrier layer 410 can then be subjected to oxidation, nitridation or other processes to form an oxide, nitride and / or other metal compound in barrier layer 410.

[0033] Although a filler material can be deposited directly on the barrier layer 410, it has been found that as the aspect ratio of the trench 404 increases, even conformal deposition processes tend to deposit material near the top of the trench 404 more rapidly. This can lead to the uppermost section of the trench 404 closing while voids remain in the lower section. This tendency to form voids becomes particularly acute when the trench aspect ratios approach or exceed 10:1 (depth:width), although it can also be observed at much smaller aspect ratios. Accordingly, in some embodiments, a growth control layer 412 is formed on the opposite trench side faces 414, but not necessarily on the trench bottom 416. This is shown in block 314 of Fig. 3 and in the Fig. 9A and Fig. Figure 9B shows that the growth control layer 412 influences the deposition rate of the technique used for subsequent deposition of the backfill material. In an exemplary embodiment, the growth control layer 412 reduces the deposition rate on the trench side faces 414 relative to the rate on the trench bottom 416 such that an otherwise conformal deposition technique fills the bottom of the trench 404 faster than the upper section. Or, in other words, the growth control layer 412 causes an ALD, CVD, sputtering, and / or other conformal deposition process to fill the trench 404 from the bottom upwards.

[0034] The growth control layer 412 can contain any suitable metal, metal oxide, metal carbide, metal nitride, and / or combinations thereof, and its composition may differ, for example, from that of the barrier layer 410. In various embodiments, the growth control layer 412 contains WC, WN, AlC, AlN, and / or other suitable materials. In some embodiments, one or more metal components of the growth control layer 412 are selected to match the metal components of the subsequently deposited filler material 418. In some such embodiments, WC or WN is selected for the growth control layer 412 based on a W-containing filler material 418. In other such embodiments, AlC or AlN is selected for the growth control layer 412 based on an Al-containing filler material 418.

[0035] The growth control layer 412 can be deposited to any desired thickness (measured perpendicular to the side surfaces 414), although for materials with lower conductivity the growth control layer 412 can be quite thin (for example, between about 0.1 nm (1 Å) and a maximum of about 2 nm (20 Å)). The growth control layer 412 extends at least along the upper portions of the side surfaces 414 and can extend all the way to the bottom surface 416, as shown in Fig. Figure 9B shows that, due to the growth control layer 412, the bottom surface 416 of the trench 404 has a different composition than the trench sidewalls, which are defined by the growth control layer 412. This difference can be used to coordinate subsequent deposition processes.

[0036] Any suitable conformal or non-conformal deposition technique can be used to form the growth-control layer 412. In various embodiments, ALD, CVD, sputtering, and / or other suitable techniques are used to form the growth-control layer 412 on the side faces 414. In one such embodiment, a metallic component of the growth-control layer 412 is deposited by ALD, and subsequent plasma treatment is performed using a nitrogen-containing and / or carbon-containing gas to form a metal nitride and / or metal carbide. Although some of these deposition techniques are conformal in most applications, in such embodiments the geometry of the trench 404 may prevent the reaction participants from reaching the bottom of the trench 404.This means that these techniques can deposit material on the side surfaces 414 more quickly than on the bottom surface 416, thus turning the difficulty of filling the trench bottom 416 into an advantage. The deposition can be followed by an anisotropic etching process to remove all deposited material from the bottom surface 416 of the trench 404. For example, in one embodiment, the growth control layer 412 is deposited by sputtering, followed by an anisotropic dry etching that targets deposited material on the bottom surface 416.

[0037] We turn to Block 316 of Fig. 3 as well as the Fig. 10 and Fig. 11. A filling material 418 of the gate electrode 220 can be deposited within the trench 404 on the growth control layer 412. Fig. 10 corresponds to the embodiments of Fig. 9A, where the growth control layer 412 does not extend to the soil surface 416, while Fig. 11 the embodiments of Fig. Figure 9B corresponds to the growth control layer 412 extending to the bottom surface 416. The filler material 418 can contain any suitable conductor, such as W, Al, Cu, Ti, Ag, Ru, Mo, other suitable metals, and alloys thereof. The filler material 418 can be formed using any suitable technique, such as ALD, CVD, and / or sputtering. Partly due to the growth control layer 412, the filler material 418 can be deposited more rapidly on the bottom surface 416 of the trench 404 than it is deposited on the side surfaces 414. In one specific application, a metal carbide growth control layer 412 reduces the deposition rate on the side surfaces 414 by a factor of 10. Experiments and analyses have shown that filling high-aspect-ratio trenches 404 in this manner significantly reduces the occurrence of vacancies and other defects in the filler material 418.

[0038] We turn to Block 318 of Fig. 3. A planarization technique such as chemical-mechanical planarization or polishing (CMP) can be performed on the semiconductor device 200 to remove excess material extending beyond trench 404. As shown in block 320 of Fig. Once 3 can be seen, the component 200 can be further processed.

[0039] Method 300 can also be used to form a gate electrode in a planar device, as described in the Fig. 3 and the Fig. 12-19 is described. Fig. Figures 12-19 are cross-sectional views of a section of a planar component 100 which is subjected to the method 300 of forming a gate electrode according to embodiments of the present disclosure.

[0040] We turn to Block 302 of Fig. 3 as well as Fig. 12 to, where a substrate 102 is received, which contains a semiconductor device 100. The substrate 102 and the semiconductor device 100 can each be substantially the same as those of Fig. 1 resembles, and for the sake of brevity, similar elements are not described again. In the embodiment of Fig. 12 The semiconductor device 100 contains a section of a gate structure 116 essentially similar to that of Fig. 1, which contains a sacrificial gate electrode 402. The sacrificial gate electrode 402 may contain polysilicon, a dielectric, a masking material, and / or other suitable materials. We refer to Block 304 of Fig. 3 as well as Fig. 13. The sacrificial gate electrode 402 is removed, leaving a trench 404 defined by the sidewall spacers 116. Partly due to the geometry of the trench 404, layer formation within it can be challenging. For example, the trench 404 may have a high aspect ratio and / or narrow internal cavities where the deposition reaction participants do not circulate well.

[0041] A gate dielectric layer 110 can be formed either before or after the removal of the sacrificial gate electrode 402. Accordingly, in block 306 of Fig. 3 and Fig. 14 The gate dielectric layer 110 is formed within the trench 404 after the sacrificial gate electrode 402 has been removed. In the illustrated embodiment, the gate dielectric layer 110 is formed on the interface 108 in the trench 404 and also extends along the vertical surfaces of the sidewall spacers 116 to form a U-shaped layer. Suitable deposition processes include CVD, high-density plasma CVD (HDPCVD), ALD, PVD, spin deposition, and / or other suitable deposition processes, and the gate dielectric layer 110 can have a composition similar to that of the Fig. resemble 1-2C.

[0042] An exit working layer 406 can also be formed either before or after the removal of the sacrificial gate electrode 402. In the example of block 308 of Fig. 3 and Fig. 14. The exit working layer 406 is formed on the gate dielectric layer 110 within the trench 404 after the sacrificial gate electrode 402 has been removed. The exit working layer 406 can contain a material that is tailored to the specific type of device 100 being formed and can vary in its composition from the exit working layer 406 of Fig. 4. In the illustrated embodiment, the exit working layer 406 extends along the vertical surfaces of the gate dielectric layer 110 to form a U-shape. The exit working layer 406 can contain multiple layers and can be deposited to any suitable thickness by CVD, PVD, and / or other suitable processes.

[0043] We turn to Block 310 of Fig. 3 as well as Fig. 15. A wetting layer 408 can be deposited on the gate dielectric layer 110 and / or the exit working layer 406. The wetting layer 408 can contain Ti, Ta, Ni, Co, other metals and / or combinations thereof and can be formed by any suitable technique, such as ALD, CVD or sputtering. The wetting layer 408 can be formed within the trench 404 using a suitable deposition technique, such as ALD, CVD and / or sputtering, and can be formed to any suitable thickness.

[0044] We turn to Block 312 of Fig. 3 as well as Fig. 16. A barrier layer 410 can be deposited on the wetting layer 408. The barrier layer 410 can contain TiN, TaN, and / or other suitable metals, metal oxides, and / or metal nitrides and can be deposited by any suitable technique, such as ALD, CVD, and / or sputtering. In some embodiments, a single deposition step deposits a metal common to both the wetting layer 408 and the barrier layer 410. The metal of the barrier layer 410 can then be subjected to oxidation, nitridation, or other processes to form an oxide, nitride, and / or other metal compound in the barrier layer 410.

[0045] We turn to Block 314 of Fig. 3 and the Fig. 17A and Fig. 17B. A growth control layer 412 is formed on the trench side faces 414, but not necessarily on the trench bottom 416. The growth control layer 412 influences the deposition rate of the technique used to subsequently deposit the fill material. Accordingly, the growth control layer 412 may contain any suitable metal, metal oxide, metal carbide, metal nitride, and / or combinations thereof. For example, the growth control layer 412 may contain WC, WN, AlC, AlN, and / or other suitable materials. In some embodiments, one or more metal components of the growth control layer 412 are selected to match metal components of the subsequently deposited fill material 418.

[0046] The growth control layer 412 can be deposited to any desired thickness (measured perpendicular to the side surfaces 414), and for materials with lower conductivity, the growth control layer 412 can be quite thin (for example, between about 0.1 nm (1 Å) and a maximum of about 2 nm (20 Å)). The growth control layer 412 extends at least along the upper portions of the side surfaces 414 and can extend all the way to the bottom surface 416, as shown in Fig. Figure 17B shows that, due to the growth control layer 412, the bottom surface 416 of the trench 404 has a different composition than the trench sidewalls, which are defined by the growth control layer 412. This difference can be used to coordinate subsequent deposition processes.

[0047] Any suitable conformal or non-conformal deposition technique can be used to form the growth-control layer 412. In various embodiments, ALD, CVD, sputtering, and / or other suitable techniques are used to form the growth-control layer 412 on the side surfaces 414. In one such embodiment, a metal component of the growth-control layer 412 is deposited by ALD, and subsequent plasma treatment is performed using a nitrogen-containing and / or carbon-containing gas to form a metal nitride and / or metal carbide. In some applications, conformal deposition techniques rely on the geometry of the trench 404 to prevent reaction participants from reaching the bottom 416 of the trench 404. The deposition may be followed by an anisotropic etching process to remove all deposited material from the bottom surface 416 of the trench 404.For example, in one embodiment the growth control layer 412 is deposited by sputtering, followed by an anisotropic dry etching that targets deposited material on the bottom surface 416.

[0048] We turn to Block 316 of Fig. 3 as well as the Fig. 18 and Fig. 19. A filling material 418 of the gate electrode 116 can be deposited within the trench 404 on the growth control layer 412. Fig. 18 corresponds to the embodiments of Fig. 17A, where the growth control layer 412 does not extend to the soil surface 416, while Fig. 19 the embodiments of Fig. Figure 17B corresponds to the growth control layer 412 extending to the bottom surface 416. The filler material 418 can contain any suitable conductor, such as W, Al, Cu, Ti, Ag, Ru, Mo, other suitable metals, and alloys thereof. The filler material 418 can be formed using any suitable technique, such as ALD, CVD, and / or sputtering. Partly due to the growth control layer 412, the filler material 418 can be deposited more rapidly on the bottom surface 416 of the trench 404 than on the side surfaces 414. It has been found that filling high-aspect-ratio trenches 404 in this manner significantly reduces the occurrence of voids and other defects in the filler material 418.

[0049] We turn to Block 318 of Fig. 3. A planarization technique, such as chemical-mechanical planarization or polishing (CMP), can be performed on the semiconductor device 100 to remove excess material extending beyond trench 404. As shown in Block 320 of Fig. Once 3 is visible, the component 100 can be made available for further processing.

[0050] As described above, the techniques of this disclosure can also be used to establish contacts and through-contacts. Examples of this are given with reference to the Fig. Described in sections 20-29B. Fig. Figure 20 is a flowchart of Method 2000 for forming a contact or through-contact according to embodiments of the present disclosure. It is understood that additional steps may be provided before, during, and after Method 2000, and that some of the described steps may be substituted or omitted for other embodiments of Method 2000. Fig. Figures 21-26 are cross-sectional views of a section of a component 100 that is subjected to the method 2000 for forming a contact or through-contact, according to embodiments of the present disclosure. Fig. 27A and Fig. Figure 27B are cross-sectional views of a source / drain region of a non-planar component 200 that has been subjected to the method 2000 according to embodiments of the present disclosure. Fig. 28A and Fig. Figure 28B are cross-sectional views of a channel region of a non-planar component 200 that has been subjected to the method 2000 according to embodiments of the present disclosure. Fig. 29A and Fig. Figure 29B are cross-sectional views of a semiconductor device 2900 that has been subjected to the method according to embodiments of the present disclosure.

[0051] We turn to Block 2002 from Fig. 20 as well Fig. 21 to, where a substrate 102 is received, which contains a semiconductor device 100. The substrate 102 and the semiconductor device 100 can each be substantially the same as those of Fig. 1 resemble, and for the sake of brevity, similar elements thereof are not described again. In the illustrated embodiment, the semiconductor device 100 comprises one or more layers of an ILD 120 arranged on the source / drain regions 104 and on the gate structure 116. We turn to Block 2004 of Fig. 20 to and stay at Fig. 21. A structured layer 2102, such as a photoresist layer, is formed and structured on the ILD 120 to expose contact or through-contact regions. In the embodiment of Fig. 21 The exposed contact or through-contact regions correspond to contact regions. The structured layer 2102 can be structured by direct writing, photolithography, and / or other suitable processes, and in an exemplary embodiment, selected regions of the structured layer 2102 are exposed to photolithographic radiation, causing a photoactive chemical in the structured layer 2102 to undergo a chemical reaction. A development process is carried out, which relies on the result of the chemical reaction to selectively remove exposed or unexposed regions of the structured layer 2102.

[0052] We turn to Block 2006 from Fig. 20 as well Fig. 22. The one or more ILD layers 120 are etched using the structured layer 2102 to selectively etch the contact or through-contact recesses, such as the contact recesses 2202 of Fig. 22. The etching of the ILD layer 120 may include any suitable etching technique, such as wet etching, dry etching, reactive ion etching (RIE), etc., and may use any suitable chemical etching composition or combination thereof. In an exemplary embodiment, the etching of block 2006 includes a first etching operation that uses a directional or anisotropic etching technique to form a vertical recess, and a second etching operation that uses a non-directional or isotropic etching technique to widen the recess. The remaining structured layer 2102 may be removed after the one or more ILD layers 120 have been etched.

[0053] We turn to Block 2008 from Fig. 20 as well Fig. 23. An adhesion layer 2302 is formed on the ILD and within the etched sections of the structured layer 2102. As the name suggests, the adhesion layer 2302 can be used to improve the quality of the interface between the existing materials, including the ILD layers 120, the source / drain regions 104, and the gate structure 116, and subsequently deposited materials, such as a contact filler or vias. Accordingly, the adhesion layer 2302 can contain one or more layers of conductive materials, such as metals (e.g., Ti, Ta, W, Al, Ni, Cu, Co, etc.) and metal nitrides, which can be deposited by ALD, CVD, EP CVD, PEALD, PVD, and / or other suitable deposition processes. In the present embodiment, the adhesion layer 2302 contains several deposited layers of Ti and TiN.In other embodiments, one or more additional layers are added, such as barrier layers.

[0054] Although the contacts 124 can be formed by depositing a filler material directly onto the adhesion layer 2302, it has been found that if the aspect ratio of the contact or through-contact recess becomes larger, voids and discontinuities can occur that resemble those described in the context of metal-gate filling techniques. Accordingly, as described in Block 2010 by Fig. 20 and in the Fig. 24A and Fig. Figure 24B shows that in some embodiments a growth control layer 2402 is formed on the side surfaces 2404 of the recess, but not necessarily on the bottom surface 2406. The growth control layer 2402 only needs to cover the uppermost section of the side surfaces 2404, as shown in Fig. 24A shown, or can extend to floor area 2406, as shown in Fig. 24B shown. The growth control layer 2402 affects the deposition rate of the technique used to subsequently deposit the filler material and may reduce the deposition rate on the recessed side surfaces 2404, so that an otherwise compliant deposition technique fills the bottom of the recess faster than the top section.

[0055] The growth control layer 2402 can contain any suitable metal, metal oxide, metal carbide, metal nitride, and / or combinations thereof, and may, for example, differ in its composition from the adhesion layer 2303. In various embodiments, the growth control layer 2402 contains WC, WN, AlC, AlN, and / or other suitable materials. In some embodiments, one or more metal components of the growth control layer 2402 are selected to match metal components of the subsequently deposited filler material. In some such embodiments, WC or WN is selected for the growth control layer 2402 based on a W-containing filler material. In other such embodiments, AlC or AlN is selected for the growth control layer 2402 based on an Al-containing filler material.

[0056] The growth control layer 2402 can be deposited to any desired thickness (measured perpendicular to the side surfaces 2404), although for materials with lower conductivity, the growth control layer 2402 can be quite thin (for example, between about 0.1 nm (1 Å) and a maximum of about 2 nm (20 Å)). As a result of the growth control layer 2402, the bottom surface 2406 of the recess has a different composition than the recessed side walls defined by the growth control layer 2402. This difference can be used to fine-tune subsequent deposition processes.

[0057] Any suitable conformal or non-conformal deposition process can be used to form the growth control layer 2402. In various embodiments, ALD, CVD, sputtering, and / or other suitable techniques are used to form the growth control layer 2402 on the side surfaces 2404. In one such embodiment, a metal component of the growth control layer 2402 is deposited by ALD, and subsequent plasma treatment is performed using a nitrogen-containing and / or carbon-containing gas to form a metal nitride and / or metal carbide. The deposition may be followed by an anisotropic etching process to remove all deposited material from the bottom surface 2406 of the recess 2202. For example, in one embodiment, the growth control layer 2402 is deposited by sputtering, followed by anisotropic dry etching targeting the deposited material on the bottom surface 2406.

[0058] We turn to Block 2012 from Fig. 20 as well Fig. 25. A contact or through-contact filler material 2502 can be deposited within the recess onto the growth control layer 2402. The filler material 2502 can contain any suitable conductor, such as metals (e.g., W, Al, Ta, Ti, Ni, Cu, etc.), metal oxides, metal nitrides, and / or combinations thereof. The contact filler material can be deposited by any suitable technique, such as PVD (e.g., sputtering), CVD, EP CVD, ALD, PEALD, and / or combinations thereof. Partly due to the growth control layer 2402, the filler material 2502 can be deposited more rapidly on the bottom surface 2406 of the recess 2402 than on the side surfaces 2404. Experiments and analyses have shown that filling high-aspect-ratio recesses in this manner significantly reduces the occurrence of voids and other defects in the filler material 2502.

[0059] We turn to Block 2014 from Fig. 20 and the Fig. 26A and Fig. 26B. A planarization technique, such as chemical-mechanical planarization or polishing (CMP), can be performed on the semiconductor device 100 to remove excess material extending beyond the recesses. Fig. 26A corresponds to the embodiments of Fig. 24A, where the growth control layer 2402 does not extend to the soil surface 2406, while Fig. 26B the embodiments of Fig. 24B corresponds to where the growth control layer 2402 extends to the soil surface 2406. As in block 2016 of Fig. Once 20 can be seen, the component 100 can be made available for further processing.

[0060] Further examples of contacts and through-contacts that can be formed using the 2000 procedure are shown in the Fig. 27A-29B shown. Let's turn to and first the Fig. 27A and Fig. 27B, where exemplary contacts 124 to source / drain regions 208 of a non-planar component 200, formed by the techniques discussed here, are revealed. In many aspects, the non-planar component 200 is essentially the Fig. 2A-2C are similar, and in the interest of brevity, a repetition of similar structures can be omitted.

[0061] In the illustrated embodiment, the contacts 124 extend into the ILD 120 in the vertical direction and span one or more source / drain regions 208 in the horizontal direction. Accordingly, an adhesion layer 2302 of the contacts 124 is formed, essentially similar to that of Fig. 23, on at least one surface of at least one source / drain region 208 using a technique such as that of Block 2008 of Fig. 20 arranged. The adhesion layer 2302 can also be arranged on the substrate 102 between the source / drain regions 208.

[0062] Contact 124 also contains a growth control layer 2402, which is controlled by a process such as that of block 2010. Fig. 20 is formed. The growth control layer 2402 is arranged on the side surfaces 2404 of the trench, but not necessarily on the substrate 102 up to the bottom surface 2406. Depending on the application, the growth control layer 2402 can be arranged on the source / drain regions 208, as shown in Fig. 27A shown, or can be omitted in these regions, as in Fig. 27B shown. A filler material 2502, such as the filler material 2502 from Fig. 25 is placed on the growth control layer 2402 to complete contact 124.

[0063] We turn to the Fig. 28A and Fig. 28B, where exemplary contacts 124 to a gate structure 212 of a non-planar device 200, formed by the techniques discussed here, are disclosed. In many aspects, the non-planar device 200 is essentially similar to that of the Fig. 2A-2C, and for the sake of brevity, a repetition of similar structures can be omitted. The contacts 124 contain an adhesion layer 2302 essentially similar to that of Fig. 23. The adhesion layer 2302 is placed within a recess located in the ILD 120 above the gate structure 212 using a technique such as that described in Block 2008. Fig. 20 are being trained.

[0064] The contact 124 also contains a growth control layer 2402, which is controlled by a process such as that of block 2010. Fig. 20 is formed. The growth control layer 2402 is placed on the side surfaces 2404 of the trench, but not necessarily on the trench bottom, so that the different composition of the resulting side walls can be used to tune subsequent deposition processes. Depending on the application, the growth control layer 2402 extends at least along the upper sections of the side surfaces 2404, as shown in Fig. 28A, and can extend all the way to the bottom surfaces (for example, the adhesion layer 2302 on the gate structure 212), as shown in Fig. 28B shown. A filler material 2502, such as the filler material 2502 from Fig. 25 is placed on the growth control layer 2402 to complete contact 124.

[0065] And finally, as in the Fig. 29A and Fig. Figure 29B shows that the method 2000 can be used to form through contacts 122. Fig. 29A and Fig. Figures 29B are cross-sectional diagrams of an interconnect structure of a semiconductor device 2900, such as a planar or non-planar semiconductor device, according to embodiments of the present disclosure. Similar to the contacts 124, the through-contacts 122 can have an adhesion layer 2302 substantially similar to that of Fig. 23. The adhesion layer 2302 is contained within a recess arranged in the ILD 120 by means of a technique such as that of Block 2008. Fig. 20 formed. The adhesion layer 2302 can touch an underlying conductor track 118.

[0066] The through-contacts 122 contain a growth control layer 2402, which is created by a process such as that of block 2010. Fig. 20 is formed. The growth control layer 2402 is arranged on the side surfaces 2404 of the recess, but not necessarily on the bottom surface 2406, so that the other composition of the resulting side walls can be used to adjust subsequent deposition processes. Depending on the application, the growth control layer 2402 extends at least along the upper sections of the side surfaces 2404, as shown in Fig. 29A, and can extend all the way to the adhesion layer 2302 on the gate structure 212, as shown in Fig. 29B shown. A filler material 2502, such as the filler material 2502 from Fig. 25 is arranged on the growth control layer 2402 to complete the through contact 122 and - in some embodiments - to form conductor tracks 118.

[0067] Accordingly, a technique for forming conductive structural elements is provided, and the structures produced by the technique are disclosed. In some embodiments, the method includes receiving a substrate with a gate structure. The gate structure contains a sacrificial section, which is removed to define a trench within the gate structure. The trench has opposing side faces and a bottom face defined thereon. A material layer is selectively formed on the opposing side faces such that the bottom face is free of the material layer. A gate electrode filler material is deposited on the material layer and on the bottom face within the trench.In some such embodiments, the formation of the material layer includes the deposition of a metal using atomic layer deposition (ALD) and the plasma treatment of the metal using a carbon-containing gas. In some such embodiments, the formation of the material layer includes a deposition process and an etching process configured to remove deposited material from the base surface.

[0068] In further embodiments, the method includes receiving a substrate with a recess defined by at least two opposing side walls and a bottom surface. A growth-control material is deposited within the recess and on the at least two opposing side walls such that the bottom surface is free of growth-control material. A filler material layer is deposited within the recess such that the filler material is located on top of the growth-control material and on the bottom surface. In some such embodiments, the growth-control material contains a metal nitride and / or a metal carbide. In some such embodiments, the growth-control material and the filler material layer contain at least one common metal.

[0069] In further embodiments, the semiconductor device comprises a substrate on which a gate structure is formed. The gate structure includes a gate dielectric layer arranged on the substrate, a growth control material arranged on a side face of the gate structure, and a gate electrode filler material arranged on the growth control material and on a bottom face that is free of the growth control material. In some embodiments, the gate structure further includes a barrier layer arranged between the growth control material and the gate dielectric layer, and between the gate electrode filler material and the gate dielectric layer. In some of these embodiments, the barrier layer differs in its composition from the growth control material.In some embodiments, the gate electrode filling material touches a first surface and a second surface that differ in their composition.

Claims

[1] Semiconductor device comprising the following: a substrate (102) on which a gate structure (212) is formed, which has a trench (404) with opposing side faces (414) and a bottom surface (416) defined on the substrate (102), wherein the gate structure includes the following: a gate dielectric layer (216) arranged along the opposite side faces (414) and the bottom face (416); a growth control material (412) arranged on upper sections of the opposite side surfaces (414) of the gate structure (212), wherein the lateral thickness of the growth control material (412) decreases continuously from the upper surface downwards; and a gate electrode filling material (418) arranged on the growth control material (412), on lower sections of the side surfaces (414) and on the bottom surface (416) of the gate structure (212), wherein the lower sections of the side surfaces (414) and the bottom surface (416) of the gate structure (212) are free of the growth control material (412). [2] Semiconductor device according to claim 1, wherein the gate structure further comprises a barrier layer (410) arranged between the growth control material (412) and the gate dielectric layer (216) and between the gate electrode filler material (418) and the gate dielectric layer (216), wherein the barrier layer differs in its composition from the growth control material. [3] Semiconductor device according to claim 1 or 2, wherein the growth control material (412) contains a metal carbide and / or a metal nitride, and wherein the growth control material (412) and the gate electrode filler material (418) contain at least one common metal. [4] Semiconductor device according to one of the preceding claims, wherein the gate electrode filler material (418) contacts a first surface and a second surface which are different in their composition. [5] Semiconductor device according to any of the preceding claims, wherein the growth control material (412) has a thickness of less than about 2 nm (20 Å).

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