SILICON CARBIDE SEMICONDUCTOR ELEMENT WITH TRENCH GATE STRUCTURES AND SHIELDING AREAS

Abstract

A semiconductor device (500) has gate structures (150) extending from a first surface (101) into a silicon carbide body (100), wherein a width (w1) of the gate structures (150) along a first horizontal direction (191) parallel to the first surface (101) is smaller than a vertical extent (v1) of the gate structures (150) perpendicular to the first surface (101). Contact structures (315) extend from the first surface (101) into the silicon carbide body (100), with the gate structures (150) and the contact structures (315) alternating along the first horizontal direction (191). Shielding regions (160) in the silicon carbide body (100) adjoin a base of the contact structures (315) and are spaced apart from the gate structures (150) along the first horizontal direction (191).

Description

BACKGROUND

[0001] Semiconductor components based on silicon carbide (SiC) benefit from the wide band gap and high breakdown strength of silicon carbide. However, a large number of interface states form at interfaces between a SiC semiconductor body and a dielectric layer, for example, the gate dielectric of a transistor cell of a SiC MOSFET (SiC metal oxide semiconductor field-effect transistor). These interface states can be occupied by more or fewer charge carriers depending on the operating state of the SiC MOSFET. Charge carriers occupying the interface states influence the mobility and concentration of free charge carriers, which form the field-controlled transistor channel when the transistor cells are switched on.In addition, the high breakdown strength of SiC is usually not fully exploited, since the field strength occurring in the gate dielectric and the reliability of the gate dielectric often limit the dielectric strength of the SiC MOSFET.

[0002] US Pat. No. 5,719,409 A describes a SiC MOSFET with gate trenches and source trenches, each extending through a p-doped epitaxial layer into an n-doped epitaxial layer. A conductive layer is formed in the gate trenches. P-doped regions are formed beneath the source trenches. Ohmic contacts are then formed in the source trenches, which border the p-doped regions at the bottom of the source trenches. US Pat. No. 2008 / 0 121 986 A1 describes a MOSFET with a trench gate.

[0003] The source contacts include a tungsten plug. Additional tungsten plugs extend into a polysilicon gate electrode.

[0004] The present application aims at a SiC semiconductor device that can exploit the intrinsic electric breakdown field strength of silicon carbide to a high degree. SUMMARY

[0005] The object of the application is achieved by the subject matter of the independent patent claims. Dependent claims relate to further embodiments.

[0006] The present disclosure relates to a semiconductor device having gate structures, contact structures, and shielding regions. The gate structures extend from a first surface into a silicon carbide body. A width of the gate structures along a first horizontal direction parallel to the first surface is smaller than a vertical extension of the gate structures perpendicular to the first surface. The contact structures also extend from the first surface into the silicon carbide body. The gate structures and the contact structures alternate along the first horizontal direction. The shielding regions are formed in the silicon carbide body adjacent to a bottom of the contact structures and spaced apart from the gate structures along the first horizontal direction.

[0007] The present disclosure also relates to a semiconductor device having gate structures and contact structures, each extending from a first surface into a silicon carbide body. The gate structures and the contact structures alternate along a first horizontal direction parallel to the first surface. Body regions are formed in mesa sections of the silicon carbide body between the gate structures and the contact structures. Shielding regions of a conductivity type of the body regions are formed along the bottom of the contact structures and are spaced from the gate structures along the first horizontal direction. A drift structure having a drift zone forms first pn junctions with the body regions and Schottky contacts with the contact structures.

[0008] The present disclosure further relates to a semiconductor device having gate structures and contact structures, each extending from a first surface into a silicon carbide body, wherein the gate structures and the contact structures alternate along a first horizontal direction parallel to the first surface. The gate structures comprise a gate dielectric and a gate electrode, wherein the gate electrode comprises first portions of a metal structure adjacent to the gate dielectric. The contact structures comprise second portions of the metal structure adjacent to the silicon carbide body. Shielding regions are formed along the bottom of the contact structures in the silicon carbide body and are spaced apart from the gate structures along the first horizontal direction.

[0009] Finally, the present disclosure relates to a method for manufacturing a semiconductor device. A silicon carbide substrate is formed, comprising a main layer, a body layer formed on a portion of the main layer, and a source layer formed on a portion of the body layer, wherein a conductivity type of the body layer is opposite to a conductivity type of the source layer and a drift layer formed in the main layer. Gate trenches and contact trenches are formed, extending through the source layer and the body layer and alternating along a first horizontal direction parallel to a first main surface of the silicon carbide substrate. A gate dielectric is formed in the gate trenches. A metal structure is formed, comprising first portions adjacent to the gate dielectric in the gate trenches and second portions in the contact trenches.The second sections border body regions formed from sections of the body layer and source regions formed from sections of the source layer. Third sections of the metal structure connecting the first sections to the second sections are removed.

[0010] Further features and advantages of the disclosed subject matter will become apparent to those skilled in the art upon reading the following detailed description and upon viewing the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings provide a further understanding of the invention and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present invention and, together with the description, explain the principles of the invention. Other embodiments of the invention and intended advantages will become apparent from an understanding of the following detailed description. Fig. 1 is a schematic cross-section of a portion of a SiC semiconductor device with trench gates and trench contacts according to an embodiment with an aspect ratio of the gate structures greater than 1. Fig. 2A is a schematic cross-section through a portion of a SiC semiconductor device with trench gates and trench contacts according to an embodiment with Schottky contacts at the trench contacts, wherein a vertical extension of the trench contacts corresponds to a vertical extension of the trench gates. Fig. 2B is a schematic cross-section through a portion of a SiC semiconductor device according to an embodiment with Schottky contacts at the trench contacts, wherein a vertical extension of the trench contacts is larger than that of the trench gates. Fig. 3 is a schematic cross-section of a portion of a SiC semiconductor device with trench gates and trench contacts according to an embodiment having a metal structure with first portions in the trench gates and second portions in the trench contacts. Fig. 4 is a schematic cross-section through a portion of a SiC semiconductor device according to an embodiment with body regions having more highly doped contact portions along trench contacts. Fig. 5A is a schematic cross-section through a portion of a SiC semiconductor device with trench gates and trench contacts according to an embodiment with trench gates whose sidewalls are parallel to (11-20) lattice planes. Fig. 5B is a schematic cross-section through a portion of a SiC semiconductor device according to another embodiment with trench gates whose sidewalls run parallel to (1-100) lattice planes. Fig. 5C is a schematic cross-section through a portion of a SiC semiconductor device according to another embodiment with highly doped contact portions and Schottky contacts to trench contacts. Fig. 5D is a schematic cross-section through a portion of a SiC semiconductor device according to another embodiment with highly doped contact portions, shielding regions, and Schottky contacts along deep trench contacts. Fig. 6 is a simplified flow diagram of a method for fabricating semiconductor devices with trench gates and trench contacts according to one embodiment. Fig. 7A is a schematic cross-sectional view of a portion of a silicon carbide substrate illustrating a method for fabricating semiconductor devices with trench gates and trench contacts according to an embodiment, including simultaneously forming a metal structure for the trench gates and the trench contacts after forming a silicon carbide substrate with a source layer, body layer, and drift layer. Fig. Figure 7B is a schematic cross-section of the silicon carbide substrate portion of the Fig. 7A after the introduction of gate trenches and contact trenches. Fig. Figure 7C is a schematic cross-section of the silicon carbide substrate portion of the Fig. 7B after forming a gate dielectric in the gate trenches. Fig. Figure 7D is a schematic cross-section of the silicon carbide substrate portion of the Fig. 7C after forming a metal structure with first sections in the gate trenches and second sections in the contact trenches. Fig. 8A is a schematic cross-sectional view of a portion of a silicon carbide substrate illustrating another method for fabricating semiconductor devices with trench gates and trench contacts according to another embodiment, including simultaneous formation of a metal structure for trench gates and trench contacts after forming a silicon carbide substrate with a source layer, body layer, and drift layer. Fig. Figure 8B is a schematic cross-section of the substrate section according to Fig. 8A after forming doped regions for highly doped contact sections of body regions and for shielding regions by means of an implantation mask. Fig. Figure 8C is a schematic cross-section of the substrate section according to Fig. 8B after removal of the implantation mask. Fig. Figure 8D is a schematic cross-section of the substrate section according to Fig. 8C after formation of a trench etch mask. Fig. Figure 8E is a schematic cross-section of the substrate section according to Fig. 8D after formation of gate trenches and contact trenches. Fig. Figure 8F is a schematic cross-section of the substrate section according to Fig. 8E after formation of a sacrificial oxide. Fig. Figure 8G is a schematic cross-section of the substrate section according to Fig. 8F after removal of the sacrificial oxide. Fig. Figure 8H is a schematic cross-section of the substrate section according to Fig. 8G after forming a gate dielectric layer. Fig. Figure 8I is a schematic cross-section of the substrate section according to Fig. 8H after forming an etching mask. Fig. Figure 8J is a schematic cross-section of the substrate section according to Fig. 8I after removing a portion of the gate dielectric layer from the contact trenches. Fig. Figure 8K is a schematic cross-section of the substrate section according to Fig. 8J after forming a metal structure with first sections in the gate trenches and second sections in the contact trenches. Fig. Figure 8L is a schematic cross-section of the substrate section according to Fig. 8K after removing third sections of the metal structure outside the gate trenches and contact trenches. Fig. 9A is a schematic cross-section through a portion of a silicon carbide substrate according to an embodiment comprising forming shielding regions by implantation through trench bottoms after forming doped regions for contact portions of body regions. Fig. Figure 9B is a schematic cross-section of the substrate section according to Fig. 9A after forming a trench etch mask. Fig. Figure 9C is a schematic cross-section of the substrate section according to Fig. 9B after formation of gate trenches and contact trenches. Fig. Figure 9D is a schematic cross-section of the substrate section according to Fig. 9C after formation of a sacrificial oxide. Fig. Figure 9E is a schematic cross-section of the substrate section according to Fig. 9D after forming doped regions for shielding regions using an implantation mask. Fig. Figure 9F is a schematic cross-section of the substrate section according to Fig. 9E after forming a gate dielectric layer. The Fig. Figure 9G is a schematic cross-section of the substrate section according to Fig. 9F after removing a portion of the gate dielectric layer from the contact trenches. Fig. 10 is a schematic illustration of a dopant distribution in shielding regions in a cross-section through a portion of a SiC semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0012] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which specific embodiments are shown for purposes of illustration. In this context, directional terminology such as "top," "bottom," "front," "back," "front," "rear," etc., refers to the orientation of the figures just described. Since the components of the embodiments can be positioned in different orientations, the directional terminology is for the purpose of explanation only and is not to be considered limiting in any way.

[0013] The terms "have," "contain," "comprise," "have," and the like are open-ended terms that, on the one hand, indicate the presence of the elements or characteristics in question, but, on the other hand, do not exclude the presence of further elements or characteristics. The indefinite and definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

[0014] Some figures represent relative dopant concentrations by indicating "-" or "+" next to the doping type. For example, "n-" indicates a dopant concentration that is lower than the dopant concentration of an "n"-doped region, while an "n+"-doped region has a higher dopant concentration than the "n"-doped region. The indication of the relative dopant concentration does not imply that doped regions with the same relative dopant concentration specification must have the same absolute dopant concentration, unless otherwise stated. For example, two different "n"-doped regions may have the same or different absolute dopant concentrations.

[0015] The term "electrically connected" describes a low-resistance connection between the electrically connected elements, for example, a direct contact between the elements in question or a connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements suitable for signal transmission may be present between the "electrically coupled" elements, for example, elements that can be controlled to establish a low-resistance connection in a first state and a high-resistance decoupling in a second state.

[0016] The Fig. 1 shows a semiconductor device 500 with transistor cells TC. The semiconductor device 500 can be an IGFET (insulated gate field-effect transistor), for example, a MOSFET (metal oxide semiconductor FET), an IGBT (insulated gate bipolar transistor), or an MCD (MOS controlled diode). In addition to the transistor cells TC, the semiconductor device 500 can also comprise further semiconductor elements, for example, one or more diode structures, such as a pn diode or a Schottky diode.

[0017] The semiconductor device 500 is based on a silicon carbide body 100 made of crystalline silicon carbide (SiC), e.g., 2H-SiC (2H polytype SiC), 6H-SiC, or 15R-SiC. According to one embodiment, the material of the silicon carbide body 100 is 4H-SiC. A first surface 101 on the front side of the silicon carbide body 100 is planar or ribbed. A normal 104 to a planar first surface 101 or to a midplane of a ribbed first surface 101 defines a vertical direction. Directions parallel to a planar first surface 101 or to the midplane of a ribbed first surface 101 are horizontal or lateral directions, respectively.

[0018] On the back side, the silicon carbide body 100 has a second surface 102 parallel to the first surface 101. The total thickness of the silicon carbide body 100 between the first surface 101 and the second surface 102 can be several hundred nanometers to several micrometers.

[0019] A drift structure 130 is formed in the silicon carbide body 100, which has at least one highly doped contact section 139 along the second surface 102 and a less heavily doped drift zone 131 of a first conductivity type between the first surface 101 and the highly doped contact section 139. When the transistor cells TC are switched on, the load current flows vertically through the drift zone 131. The vertical extension and doping in the drift zone 131 essentially determine the blocking capability of the semiconductor component 500.

[0020] The drift structure 130 comprises all doped regions between the transistor cells TC and the second surface 102 and, in addition to the drift zone 131 and the contact section 139, may have further doped regions, for example a buffer layer 138 which is significantly more highly doped than the drift zone 131 and which separates the drift zone 131 from the contact section 139, as well as further doped regions of the conductivity type of the drift zone 131 between the transistor cells TC and the drift zone 131.

[0021] The transistor cells TC are formed along gate structures 150 that extend from the first surface 101 into the silicon carbide body 100. The gate structures 150 can be aligned with the lattice of the crystalline silicon carbide body 100 such that both side surfaces of the gate structure 150 run parallel to the main lattice planes of the silicon carbide body 100. For example, the two side walls of the gate structures 150, which run orthogonal to the cross-sectional plane, lie in (11-20) lattice planes.

[0022] The gate structures 150 comprise a gate electrode 155, which may be electrically connected, for example, via a gate metallization 330, to a gate terminal G of the semiconductor component 500, and a gate dielectric 159 that separates the gate electrode 150 from the silicon carbide body 100. A layer thickness of the gate dielectric 159 may be less than 200 nm, for example less than 100 nm. The gate structures 150 may be strip gates, wherein a longitudinal extent along a second horizontal direction parallel to the first surface 101 and orthogonal to the cross-sectional plane is at least five times a width w1 of the gate structures 150 along a first horizontal direction 191 parallel to the first surface 101 in the cross-sectional plane.

[0023] Between each two adjacent gate structures 150, a contact structure 315 extends from the first surface 101 into the silicon carbide body 100. Gate structures 150 and contact structures 315 alternate along the first horizontal direction 191. Each gate structure 150 and contact structure 315 laterally delimits a mesa section 190 of the silicon carbide body 100.

[0024] Body regions 120 of a second conductivity type complementary to the first conductivity type are formed in the mesa sections 190. In the mesa sections 190, the body regions 120 form first pn junctions pn1 with the drift structure 130, for example, with the drift zone 131, as well as second pn junctions pn2 with source regions 110 formed between the first surface 101 and the body region 120. The source regions 110 and body regions 120 each directly border the respective gate structure 150 and the contact structure 315.

[0025] Body regions 120 and source regions 110 of each transistor cell TC are electrically connected to a first load terminal L1 of the semiconductor device 500 via a first load electrode 310. The highly doped contact section 139 is electrically connected to a second load terminal L2 of the semiconductor device 500 via a second load electrode 320.

[0026] Shielding regions 160 are formed between the contact structures 315 and the drift structure 130, which directly adjoin the bottom of the contact structures 315. The shielding regions 160 may adjoin the body regions 120, be formed symmetrically to the central axis of the contact structures 315, and extend along lower portions of the vertical sidewalls of the contact structures 315. A horizontal width w4 of the shielding regions 160 parallel to the first horizontal direction 191 may be greater than a horizontal width w2 of the contact structures, but is dimensioned such that the shielding regions 160 are laterally spaced from the gate structures 150. A distance v4 of a maximum dopant concentration in the shielding regions 160 from the first surface 101 may be greater than the vertical extent v1 of the gate structures 150.

[0027] The gate electrode 155 has or consists of a metal structure, wherein the metal structure can be composed of several sublayers made of different materials. For example, the gate electrode 155 comprises a first sublayer made of a first metal or a first metal compound, which directly adjoins the gate dielectric 159, and a fill structure made of a second metal or a second metal compound.

[0028] The contact structures 315 connect the source regions 110, the body regions 120, and the shielding region 160 and also have a metal structure or consist of a metal structure, wherein the metal structure may have several sublayers of different compositions. The contact structures 315 and the gate electrodes 155 may have the same structure.

[0029] In a gate structure 150 based on a gate electrode 155 having a metal structure, the series resistance of the gate electrode 155 along the second horizontal direction remains sufficiently small even with narrow gate structures 150, so that sufficiently homogeneous switching of the transistor cells TC can be ensured even if an aspect ratio of the gate structures 150, which is defined by the ratio of a vertical extension v1 of the gate structures 150 to their width, is selected to be greater than 1, e.g., greater than 1.5 or greater than 2.

[0030] This allows the transistor cells TC to be packed more densely, the overall width of field-controlled transistor channels in the semiconductor device 500 to be increased, and thus the on-resistance of the semiconductor device 500 to be drastically reduced. For example, a center-to-center distance p1 of adjacent gate structures 150 can be reduced to less than 2 µm, for example to less than 1 µm or less than 800 nm. The width w1 of the gate structures 150 can be provided to be less than 600 nm, for example less than 400 nm or less than 300 nm.

[0031] In addition, metallic gate lines formed above the first surface 101 for the low-resistance connection of those sections of the gate electrode 155 that are far away from a gate pad can be omitted. Eliminating such gate lines on the front side of the component increases the proportion of active component area.

[0032] Since the trenches underlying the gate structures 150 and the contact structures 315 can be defined with the same photolithographic mask, the relative position of the gate structures 150 to the contact structures 315 is very well defined and subject to hardly any fluctuations, so that the mesa sections 190 can also be designed very narrow. For example, a mesa width w3 of the mesa sections 190 is less than 500 nm, for example, less than 400 nm.

[0033] Due to the low specific resistance of the material of the gate electrode 155, the vertical extent v1 of the gate structures 150 and the vertical extent v2 of the contact structures 315 can also be reduced. With a smaller vertical extent v1 of the gate structures 150 and smaller vertical extents v2 of the contact structures 315, the distance between the shielding regions 160 and the first surface 101 also decreases, and the implantation energy required to implant the dopants defining the shielding regions 160 becomes smaller. Lower implantation energies, in turn, result in smaller lateral scattering of the dopants, so that this aspect also supports a smaller center-to-center distance p1 between adjacent gate structures 150 or transistor cells TC. In addition, the implantation mask for defining the shielding regions 160 can be designed as a less thick hard mask oras a photoresist mask, which leads to a further reduction of the deviations of the lateral extent w4 of the shielding regions 160.

[0034] The width w2 of the contact structures 315 can also be less than 600 nm, for example less than 400 nm, for example a maximum of 300 nm, wherein the widths w2, w4 of the gate structures 150 and the contact structures 315 can be the same or differ slightly from each other. For example, the width w2 of the contact structures 315 can be at least 10% larger than the width w1 of the gate structures 150.

[0035] In addition, the low-resistance connection of the shielding regions 160 via the contact structures 315 enables rapid removal and supply of charge carriers from and into the shielding regions 160 during switching operations and thus improves the switching behavior of the semiconductor component 500.

[0036] The dopants for the shielding regions 160 can also be introduced via trenches that were previously formed for the contact structures 315, wherein the implantation can be carried out with comparatively low energy and therefore lateral scattering of the dopants (straggling) is low, so that the distance between the shielding regions 160 relative to the gate structures 150 is well defined and is hardly subject to fluctuations, therefore the width w4 of the shielding regions 160 can also be very well adjusted and thus also a small mesa width w3 is supported. The shielding regions 160 reduce the influence of the drain potential on the body regions 120, so that the transistor cells TC can be provided with comparatively short channels, i.e. with a comparatively small vertical extension v1 of the gate structures 150.For a manufacturing-technically defined upper limit of the aspect ratio of the gate structures 150, a reduction of the vertical extension v1 leads to a further shrinkage of the lateral width w1.

[0037] The implantation through the bottom of the contact trenches reduces the required implantation energy and thus also the probability of generating crystal defects in the silicon carbide body 100, which can subsequently lead to bipolar degradation effects.

[0038] The Fig. 2A shows a semiconductor device 500 in which the shielding regions 160 are spaced apart from the body regions 120, such that lower portions of the sidewalls of the contact structures 315 directly adjoin the drift structure 130. For example, the drift zone 131 may adjoin the contact structures 315, or a further doped subregion of the drift structure 130, e.g., a current spreading layer, may adjoin it, wherein the further subregion has the same conductivity type as the drift zone 131, directly adjoins it, and has a higher dopant concentration than the drift zone 131, for example, at least twice, five times, or ten times. The interfaces between the contact structures 315 and the drift structure 130 form Schottky contacts SC, which, as a whole, act as a Schottky diode between the first load terminal L1 and the drift structure 130.In the case that the semiconductor device 500 is a SiC MOSFET, the Schottky contacts SC act as a whole as a Schottky diode that is electrically connected in parallel to the intrinsic body diode.

[0039] The integration of the Schottky contacts SC into the transistor cells TC ensures that, during reverse operation of the semiconductor component 500, instead of a bipolar current via the third pn junctions pn3, a unipolar current initially flows via the Schottky contacts SC. Since the threshold voltage of the Schottky diode formed by the Schottky contacts SC is lower than the threshold voltage of the pn diode formed by the third pn junctions, the Schottky contacts SC suppress, to a certain extent, a bipolar current flow within the drift zone 131, and thus reduce the recombination of charge carriers in the drift zone 131 as well as local heat generation resulting from the recombination of the charge carriers. The Schottky contacts SC suppress orIn this way, they dampen the growth of stacking faults, which, when heated sufficiently, can propagate from crystal defects along main lattice planes in the SiC crystal and worsen the on-resistance Rdson of the transistor cells TC.

[0040] In Fig. 2B, the semiconductor component 500 has contact structures 315, the vertical extent v2 of which is greater than the vertical extent v1 of the gate structures 150 and the lateral width w2 of which may be slightly greater than the lateral width w1 of the gate structures 150. The effective area of ​​the Schottky contacts SC is larger than in the embodiment of the Fig. 2A. In addition, the Fig. 2B body regions 120, which have highly doped contact sections 129 along the contact structures 315, in which a dopant concentration is significantly higher than in the main sections 121 of the body regions 120 outside the contact sections 129, for example, at least twice as high as in the main sections 121. Partial regions of the main sections 121 in which the transistor channels are formed are shielded from the contact sections 129 arranged laterally thereto, thereby reducing the clearing of these regions. The transistor cells TC can therefore be provided with shorter transistor channels, enabling a further reduction in the mesa width.

[0041] The Fig. 3 shows details of the gate electrode 155 and the contact structure 315, wherein the gate electrodes 155 and contact structures 315 have the same structure and can be formed simultaneously. The gate electrodes 155 have first sections 171 of a metal structure 170 that border the gate dielectric 159. The contact structures 315 form second sections 172 of the metal structure 170 that directly border the silicon carbide body 100.

[0042] The metal structure 170 has at least one sublayer that contains or consists of a metal, a metal compound, or a metal alloy. According to one embodiment, the metal structure 170 has a first sublayer 173 and a second sublayer 174, wherein a first portion of the first sublayer 173 in the gate structures 150 directly adjoins the gate dielectric 159 and a second portion of the first sublayer 173 in the contact structures 315 directly adjoins the silicon carbide body 100.

[0043] The first sublayer 173 can be designed as an adhesion layer for the second sublayer 174. The first section of the first sublayer 173 can have a suitable work function for a threshold voltage of the transistor cells TC in the range of 1.5V to 8V. The second section of the first sublayer 173 can form a good ohmic contact to n-doped and p-doped regions in silicon carbide.

[0044] The second section of the first sublayer 173 may have a different composition than the first section of the first sublayer 173. For example, the second section of the first sublayer 173 may comprise a metal-SiC material that may contain at least partially silicided metal, for example a nickel silicide, a platinum silicide, or a titanium silicide.

[0045] According to one embodiment, the first section and the second section of the first sublayer 173 have the same composition. For example, the first section and the second section of the first sublayer 173 contain at least titanium (Ti), molybdenum (Mo), or tantalum (Ta). According to one embodiment, both sections of the first sublayer 173 contain or consist of a titanium, titanium nitride, molybdenum, or molybdenum nitride, tantalum, or tantalum nitride layer.

[0046] The second sublayer 174 may contain a metal, a metal compound, or a metal alloy with good filling properties. For example, the second sublayer 174 contains tungsten (W). A portion of the second sublayer 174 in the second sections 172 of the metal structure 170 may have the same composition as a portion of the second sublayer 174 in the first sections 171 of the metal structure 170.

[0047] Fig. 4 shows a semiconductor device 500 with body regions 120 having highly doped contact sections 129 along the contact structures 315, in which a dopant concentration is significantly higher than a dopant concentration of main sections 121 of the body regions 120 outside the contact sections 129.

[0048] The semiconductor device 500 has gate structures 150 extending from a first surface 101 into a silicon carbide body 100, as well as contact structures 315 extending from the first surface 101 into the silicon carbide body 100, wherein the gate structures 150 and the contact structures 315 alternate along a first horizontal direction 191 parallel to the first surface 101. Body regions 120 are formed in mesa sections 190 of the silicon carbide body 100 between the gate structures 150 and the contact structures 315, which body regions have main sections 121 adjacent to the gate structures 150 and contact sections 129 adjacent to the contact structures 315 between the main sections 121 and the contact structures 315. Shielding regions 160 of the conductivity type of the body regions 120 extend at a bottom of the contact structures 315 and are spaced from the gate structures 150 along the first horizontal direction 191.

[0049] The semiconductor components 500 according to Fig. 5A to 5D are SiC TMOSFETs (SiC trench MOSFETs). A first load electrode 310 on the component front side is directly connected to the contact structures 315 through openings in an intermediate dielectric layer 210 and forms the source terminal S of the SiC TMOSFET or is electrically connected to such a source terminal S. A load electrode 320, which rests on the back side of the SiC TMOSFET on the second surface 102 and directly adjoins the contact section 139, forms the drain terminal D or is electrically connected to the drain terminal D with low resistance. The gate structures 150 have vertical sidewalls parallel to the main lattice planes in the SiC crystal of the silicon carbide body 100.

[0050] The SiC TMOSFET of the Fig. 5A comprises shielding regions 160 directly adjacent to the body regions 120. The body regions 120 comprise highly doped contact sections 129 along the contact structures 315. The <0001> The crystal direction is tilted relative to the cross-sectional plane in a plane perpendicular to the cross-sectional plane by an angular deviation of between 2° and 12°, for example by approximately 4°. The <11-20> crystal direction is parallel to the first surface 101 and parallel to the cross-sectional plane. The <1-100> crystal direction is tilted by 90° relative to the <0001> Crystal direction tilted. Vertical side surfaces of mesa sections 190 are (11-20) and (-1-120) lattice planes with approximately the same charge carrier mobility.

[0051] In the SiC TMOSFET of the Fig. 5B is the <0001> Crystal direction in a plane perpendicular to the cross-sectional plane is tilted by 4° relative to the cross-sectional plane. The <11-20> crystal direction is tilted by 90° relative to the <0001> Crystal direction tilted. The <1-100> crystal direction is parallel to the first surface 101 and the cross-sectional plane. Vertical side surfaces of the mesa sections 190 lie in the (1-100) and (-1100) lattice planes with high charge carrier mobility. Compared to the SiC TMOSFET of the Fig. 5A, the shielding regions 160 extend laterally further toward the adjacent gate structures 150.

[0052] In Fig. 5C, the shielding regions 160 are spaced apart from the body regions 120 such that Schottky contacts SC are formed along sidewalls of the contact structures 315 between the body regions 120 and the shielding regions 160.

[0053] The SiC TMOSFET of the Fig. 5D has contact structures 315 that extend deeper into the silicon carbide body 100 than the gate structures 150, so that Schottky contacts SC formed between the body regions 120 and the shielding regions 160 have a larger area per transistor cell TC.

[0054] The Fig. 6 relates to a method with which, for example, semiconductor components 500 can be produced as described above. A silicon carbide substrate is formed in which a body layer is formed on a portion of a main layer and a source layer is formed on a portion of the body layer, wherein a conductivity type of the body layer is opposite to a conductivity type of the source layer and a drift layer formed in the main layer (902). Gate trenches and contact trenches are introduced through the source layer and the body layer, alternating along a first horizontal direction parallel to a first main surface of the silicon carbide substrate (904). A gate dielectric is formed in the gate trenches (906).A metal structure is formed that has first sections that adjoin the gate dielectric in the gate trenches and second sections that adjoin body regions formed from sections of the body layer and source regions formed from sections of the source layer (908). Third sections of the metal structure that connect the first sections to the second sections of the metal structure are removed (910).

[0055] The simultaneous formation of gate trenches and contact trenches enables a close spacing between body trenches and contact trenches. The simultaneous formation of the metal structure in both the gate trenches and the contact trenches enables the use of metals or metal compounds commonly used in semiconductor technology, such as metal silicide, titanium, tantalum, titanium nitride, tantalum nitride, and tungsten, to form gate electrodes and contact structures.

[0056] The Fig. 7A to 7D relate to an embodiment of a manufacturing method for SiC semiconductor components in which the dopants for forming shielding regions are introduced through the bottom of contact trenches.

[0057] First, a silicon carbide substrate 700 is provided, which may have at least one heavily doped substrate section 739 and a layer section 790 formed on the substrate section 739, for example, by epitaxy. The substrate section 739 and a lower subsection of the layer section 790 adjacent to the substrate section 739 form a main layer 730, which, in addition to the substrate section 739, comprises at least one lightly doped drift layer 731. A body layer 720 is formed on a section of the main layer 730, and a source layer 710 is formed on a section of the body layer 720. An exposed surface of the layer section 790 on the front side of the silicon carbide substrate 700 forms a first main surface 701, and an exposed surface of the substrate section 739 on the back side of the silicon carbide substrate 700 forms a second main surface 702.The silicon carbide substrate 700 may be made of 2H-SiC, 4H-SiC, 6H-SiC, 15R-SiC, or a silicon carbide of another polytype.

[0058] Fig. 7A shows that the body layer 720 forms pn junctions with the main layer 730 and with the source layer 710, which extend parallel to the first main surface 701. Between the drift layer 731 and the substrate portion 739, the main layer 730 may include a buffer layer 738 of the same conductivity type as the drift layer 731. According to one embodiment, the body layer 720 is p-doped.

[0059] Gate trenches 750 and contact trenches 715 are introduced from the front side, extending into the main layer 730. Dopants of the conductivity type of the body layer 720 are selectively introduced through the bottom of the contact trenches 715.

[0060] According to Fig. 7B, gate trenches 750 and contact trenches 715 alternate along a first horizontal direction 191. Portions of the silicon carbide substrate 700 between adjacent gate trenches 750 and contact trenches 715 form mesa portions 190, wherein portions of the source layer 710 of the Fig. 7A between adjacent gate trenches 750 and contact trenches 715 body regions 120, source regions 110 and portions of the body layer 720 of the Fig. 7A, body regions 120 form between adjacent gate trenches 750 and contact trenches 715. The body regions 120 form first pn junctions pn1 with the main layer 730 and second pn junctions pn2 with the source regions 110 in the mesa sections 190.

[0061] The dopants introduced through the bottom of the contact trenches 715 form shielding regions 160 exclusively in the area of ​​the contact trenches 715, which are spaced apart from adjacent gate trenches 750 and extend deeper into the silicon carbide substrate 700 than the gate trenches 750. The shielding regions 160 form further pn junctions with the main layer 730, for example with the drift layer 731.

[0062] A gate dielectric 159 is formed in the gate trenches 750. For example, a silicon oxide is formed by thermal oxidation of exposed areas of the silicon carbide substrate 700 on the front side. Alternatively or additionally, one or more dielectric layers may be deposited, covering the first main surface 701, the bottoms of the gate trenches 750 and the contact trenches 715, as well as the sidewalls of the gate trenches 750 and the contact trenches 715 with a uniform layer thickness. Subsequently, an etch mask may be formed, selectively filling or covering the gate trenches 750, such that portions of the grown or deposited dielectric layers in the region of the contact trenches 715 can be removed in a masked etching process.

[0063] Fig. 7C shows the gate dielectric 159 in the gate trenches 750 as well as contact trenches 715 without gate dielectric.

[0064] A metal structure 170 is applied in two or more sub-processes, each sub-process forming a sub-layer or a portion of a sub-layer of the metal structure. For example, a thin first sub-layer 173 is first deposited, which, on the one hand, allows only a small number of surface states along the gate dielectric 159 and / or forms a low-resistance and reliable contact to silicon carbide and / or forms suitable Schottky contacts, e.g., a titanium nitride layer.

[0065] In a second step, a second sub-layer can be applied, which covers the remaining interior of the gate trenches 750 and the contact trenches 715 of the Fig. 7C. First sections 171 of the metal structure 170 fill the gate trenches 750, and second sections of the metal structure 170 fill the contact trenches 715. In a further step, third sections of the metal structure 170, which are formed above the first main surface 701 and which connect the first sections 171 to the second sections 172, are removed.

[0066] Fig. 7D shows a structure resulting from the described method, wherein the shielding regions 160 are self-aligned to form contact structures 315 formed by the second sections 172 of the metal structure 170. The first sections 171 of the metal structure 170, together with the gate dielectric 159, form gate structures 150.

[0067] The Fig. 8A to 8L relate to an embodiment of a manufacturing method for SiC semiconductor devices in which the dopants for forming shielding regions are introduced before the formation of contact trenches.

[0068] Fig. Figure 8A shows a silicon carbide substrate 700 with an n+ doped substrate portion 739 of the 4H polytype. According to one embodiment, the <0001> Crystal direction in a plane perpendicular to the cross-sectional plane tilted by an angular deviation between 2° and 12°, for example by about 4° against the normal 104, and the <11-20> crystal direction in the cross-sectional plane and parallel to the first main surface 701, so that subsequently trenches with vertical side surfaces can be formed along (11-10) lattice planes and thus the good channel properties in these lattice planes can be utilized.According to another embodiment, the <0001> Crystal direction in the plane perpendicular to the cross-sectional plane is tilted by the angular deviation against the normal 104 and the <1-1000> crystal direction is parallel to the cross-sectional plane and the first main surface 701, so that in the further course trenches with vertical side surfaces along the (1-100) lattice planes with comparatively good channel properties can be formed.

[0069] On the substrate section 739, an n-doped buffer layer 738 and an n --doped drift layer 731 is formed. A p-doped body layer 720 is formed on the drift layer 731, and an n++ doped source layer 710 is formed on the body layer 720. For example, the body layer 720 and the source layer 710 can be formed by implanting dopants into portions of an epitaxial layer grown on the buffer layer 738. A remaining portion of the epitaxial layer between the body layer 720 and the buffer layer 738 then forms the drift layer 731. The implantation of dopants to form the body layer 720 and the source layer 710, respectively, can be masked, so that the implantation of dopants into edge termination regions of device regions defined in the silicon carbide substrate 700 is omitted.

[0070] The Fig. 8A shows the silicon carbide substrate 700 with a main layer 730 comprising the substrate portion 739, the buffer layer 738, and the drift layer 731, with the body layer 720 formed only in active regions of device regions on the main layer 730, and with the source layer 710 also formed only in active regions.

[0071] A hard mask layer, which consists of or comprises, for example, a silicon oxide layer, is deposited on the first main surface 701 of the silicon carbide substrate 700, defined by the exposed surface of the source layer 710. A first photoresist layer is deposited on the hard mask layer and patterned using a lithography process. An etching process transfers the pattern of the developed first photoresist layer into the hard mask layer, forming a first hard mask 410 with first openings 415 from the hard mask layer. The developed photoresist layer is removed. Dopants of the conductivity type of the body layer 720 are implanted through the first openings 415 of the first hard mask 410 at different implantation energies.

[0072] The Fig. 8B shows the first hard mask 410 formed from the hard mask layer with the first openings 415. In the vertical projection of the first openings 415, the implanted dopants form first doped regions 128 and second doped regions 168, which may be vertically separated from one another. Each of the first and second doped regions 128, 168 may result from the implantation with several different implantation energies. The first doped region 128 is formed substantially within the body layer 720. The second doped region 168 is formed predominantly in the main layer 730 below the body layer 720. A lateral width of the first and second doped regions 128, 168 is larger than a corresponding width of the first openings 415 due to straggling effects.

[0073] The first hard mask 410 is removed and the implanted dopants can be activated, whereby the atoms of the dopant occupy regular lattice sites in the crystal lattice.

[0074] The Fig. Figure 8C shows the first and second doped regions 128, 168 with the activated dopants.

[0075] A second hard mask layer may be deposited and patterned by a second developed photoresist layer 422, wherein the second hard mask layer results in a trench etch mask 420 having first mask openings 425 and second mask openings 426.

[0076] Fig. 8D shows the second developed photoresist layer 422 and the trench etch mask 420 with the first and second mask openings 425, 426. The first mask openings 425 are formed in the vertical projection of the first and second doped regions 128, 168. The second mask openings 426 are each formed centrally between two adjacent first mask openings 425. The developed second photoresist layer 422 can be removed, and the pattern of the trench etch mask 420 can be transferred into the silicon carbide substrate 700, wherein trenches with approximately vertical side surfaces are etched in the silicon carbide substrate 700. According to another embodiment, two different trench etch masks can be generated successively, so that contact trenches 715 and gate trenches 750 can subsequently be formed independently of one another and with different depths.According to another embodiment, contact trenches 715 and gate trenches 750 are first etched together using the trench etch mask 420, and the contact trenches 715 are recessed selectively relative to the gate trenches 750 in a further step.

[0077] Fig. Figure 8E shows the contact trenches 715 resulting from the etching, which extend into the second doped regions 168 of the Fig. 8D and which separate the first doped regions 128 into separate contact sections 129 on both sides of the respective contact trench 715. The second doped regions 168 of the Fig. 8D form shielding regions 160. The gate trenches 750 are each formed at a distance from the shielding regions 160 and between each two adjacent contact trenches 715. According to one embodiment, inner edges of the gate trenches 750 and contact trenches 715 along the trench bottoms or outer edges of the gate trenches 750 and contact trenches 715 can be rounded at the first main surface 701, for example, by a heat treatment in a hydrogen-containing environment (H2 anneal).

[0078] By heat treatment in an oxygen-rich atmosphere, exposed portions of the silicon carbide substrate 700 on the front side can be oxidized.

[0079] The Fig. Figure 8F shows the sacrificial oxide layer 290 resulting from the heat treatment, which covers the silicon carbide substrate 700 on the front side in a uniform layer thickness. The sacrificial oxide layer 290 is removed.

[0080] Fig. 8G shows the silicon carbide substrate 700 after a material-selective removal of the sacrificial oxide layer 290 of the Fig. 8F. By forming and removing the sacrificial oxide layer 290, near-surface crystal defects are removed.

[0081] For example, a gate dielectric layer 158 is formed by thermal oxidation of the silicon carbide substrate 700. According to another embodiment, forming the gate dielectric layer 158 includes depositing silicon oxide, densifying the deposited silicon oxide at temperatures above 1100°C, and optionally post-oxidizing it in a low-hydrogen environment.

[0082] The gate dielectric layer 158 may optionally be post-treated by further heat treatment in an atmosphere containing nitrogen and oxygen. Post-treatment at high temperatures and under suitable ambient conditions increases the resilience of the gate dielectric layer 158 in subsequent process steps in which the gate dielectric layer 158 may be exposed to aggressive environmental conditions, e.g., a chlorine-containing atmosphere during metal deposition.

[0083] Fig. Figure 8H shows the gate dielectric layer 158 covering the silicon carbide substrate 700 on the front side with a uniform layer thickness. A third photoresist layer is applied and photolithographically patterned, with second openings 435 in the developed third photoresist layer 430 exposing the contact trenches 715.

[0084] Fig. 8I shows the third developed photoresist layer 430 filling or at least covering the gate trenches 750. The second openings 435 in the developed third photoresist layer 430 expose portions of the gate dielectric layer 158 in the contact trenches 715. The developed third photoresist layer 430 may cover mesa portions 190 of the silicon carbide substrate 700 between the contact trenches 715 on the one hand and the gate trenches 750 on the other.

[0085] Using the developed third photoresist layer 430 as an etch mask, exposed portions of the gate dielectric layer 158 are removed. The developed third photoresist layer 430 is then removed.

[0086] Fig. Figure 8J shows a gate dielectric layer 158 of the Fig. 8J, which lines the gate trenches 750 and can cover at least a portion of the mesa sections 190. The source regions 110 and contact sections 129 of the body regions 120 are exposed at the side surfaces of the contact trenches 715. The shielding region 160 is exposed at the bottom of the contact trenches 715 and, if appropriate, along lower sections of the side surfaces of the contact trenches 715.

[0087] A metal-containing first sublayer 173 made of metal or a metal compound is formed, for example, by atomic layer deposition (ALD) or a combination of ALD and a heat treatment. According to one embodiment, forming the first sublayer 173 comprises depositing a titanium nitride layer by ALD. A second sublayer 174 made of a metal or a metal compound can be applied, for example, by sputtering tungsten.

[0088] The Fig. Figure 8K shows a metal structure 170 formed from the first sublayer 173 and the second sublayer 174. The first sublayer 173 lines the gate trenches 750 and the contact trenches 715 with high conformality. A layer thickness of the first sublayer 173 may be several nanometers, for example, several tens of nanometers. The second sublayer 174 fills the interior of the contact trenches 715 as well as the interior of the gate trenches 750 of the Fig. 8J. The first sublayer 173 may, for example, be or comprise a metal silicide layer, a titanium layer, a tantalum layer, a titanium nitride layer, a tantalum nitride layer, or another layer containing at least titanium or tantalum.

[0089] First sections 171 of the metal structure 170 in the gate trenches 750 of the Fig. 8J form gate electrodes 155, wherein the gate electrodes 155 together with the gate dielectric 159 form gate structures 150. Second sections 172 of the metal structure 170 in the contact trenches 715 of the Fig. 8J form contact structures 315 with low-resistance transitions to the source regions 110, the contact sections 129 of the body regions 120, and to the shielding regions 160. Third sections 175 of the metal structure 170 above the first main surface 701 connect the first sections 171 to the second sections 172.

[0090] The third sections 175 of the metal structure 170 are removed, for example by a wet etch, optionally in conjunction with chemical mechanical polishing (CMP), wherein the exposure of sections of the gate dielectric 159 on the mesa sections 190 can serve as a stop signal for the polishing.

[0091] The Fig. Figure 8L shows the silicon carbide substrate 700 after removing the third portions 175 of the metal structure 170 of the Fig. 8K.

[0092] The Fig. 9A to 9G relate to the formation of shielding regions 160 by implantation through the bottom of contact trenches 715 before filling them with a metal structure.

[0093] The Fig. 9A shows a silicon carbide substrate 700 after implanting dopants to form the first doped regions 128 as described with reference to FIG. Fig. 8A and Fig. 8C.

[0094] According to Fig. 9B is as with reference to Fig. 8D, a trench etching mask 420 having first mask openings 425 and second mask openings 426 is formed on the first main surface 701, wherein the first mask openings 425 are formed in the vertical projection of the first doped regions 128 and the second mask openings 426 are each formed centrally between two adjacent first mask openings 425.

[0095] The pattern of the trench etch mask 420 is transferred to the silicon carbide substrate 700, forming contact trenches 715 and gate trenches 750 in the silicon carbide substrate 700. Edges at the bottom and opening of the contact trenches 715 and the gate trenches 750 may be rounded, for example, by a heat treatment in an atmosphere in which silicon carbide neither oxidizes nor forms a nitride layer, wherein the heat treatment appropriately rearranges the atoms of the silicon carbide crystal.

[0096] Fig. 9C shows the contact trenches 715 resulting from the etching, which extend into the drift layer 731 and separate the first doped regions 128 into separate contact sections 129 on either side of the respective contact trench 715. Remanent sections of the body layer 720 in mesa sections of the silicon carbide substrate 700 between the contact trenches 715 and the gate trenches 750 form body regions 120, and remanent sections of the source layer 710 in the mesa sections form source regions 110.

[0097] By heat treatment in an oxygen-rich atmosphere, exposed portions of the silicon carbide substrate 700 in the contact trenches 715 and in the gate trenches 750 may be oxidized.

[0098] As from the Fig. As can be seen in Figure 9D, a sacrificial oxide layer 290 produced by the heat treatment covers the inner surfaces of the contact trenches 715 and the gate trenches 750 in an approximately uniform layer thickness. A further mask layer is deposited and photolithographically patterned. Dopants of the conductivity type of the body regions 120 are introduced into the silicon carbide substrate 700 through the bottom of the contact trenches 715, for example, by an implantation process that includes implantations at at least two different energy levels.

[0099] According to Fig. 9E, mask openings 445 of an implantation mask 440 resulting from the further mask layer expose the first mask openings 425 of the trench etching mask 420 and fill or cover the second mask openings 426. Below the contact trenches 715, the dopants introduced through the trench bottom form shielding regions 160, which are spaced from adjacent gate trenches 750 and extend deeper into the silicon carbide substrate 700 than the gate trenches 750.

[0100] Compared to a formation of the shielding regions 160 by an implantation through the first main surface 701, the required implantation energy is reduced by an amount corresponding to the vertical extent of the contact trenches 715. Thus, for shielding regions 160 with a comparable vertical extent, the lateral scattering of the dopant and thus the achievable minimum distance between gate trenches 750 and contact trenches 715 is reduced. The initially saved energy budget can also be partially used for driving the shielding region 760 deeper into the drift layer 731.

[0101] The implantation mask 440, the trench etch mask 420, and the sacrificial oxide layer 290 are removed. Near-surface crystal defects are also removed along with the formation and removal of the sacrificial oxide layer 290. A gate dielectric layer 158 is formed.

[0102] Fig. 9F shows the gate dielectric layer 158 covering the silicon carbide substrate 700 on the front side in a uniform layer thickness. A third photoresist layer is applied and photolithographically patterned, with openings 435 in the developed third photoresist layer 430 exposing the contact trenches 715. The developed third photoresist layer 430 may cover mesa portions 190 of the silicon carbide substrate 700 between the contact trenches 715 on the one hand and the gate trenches 750 on the other. Using the developed third photoresist layer 430 as an etch mask, exposed portions of the gate dielectric layer 158 are removed.

[0103] Fig. 9G shows the third developed photoresist layer 430 filling or at least covering the gate trenches 750. During the etching of the gate dielectric layer 158, the developed third photoresist layer 430 may be partially undercut. Processing may continue with the formation of metal structures in the contact trenches 715 and the gate trenches 750 as described above.

[0104] Fig. 10 schematically shows the dopant distribution of a shielding region 160, which, for example, consists of the one described with reference to Fig. 9A to 9G, wherein the implantation of the dopant comprises at least two partial implantations at different acceleration energies.

[0105] The shielding region 160 comprises a first sub-region 161 with a net dopant concentration p1 that is higher than a net dopant concentration p2 in a second sub-region 162, which in turn is higher than a net dopant concentration p3 in a third sub-region 163, which in turn is higher than a net dopant concentration p4 in a fourth sub-region 164. The distance v4 of a deepest dopant maximum in the shielding regions 160 from the first surface 101 is significantly greater than the vertical extent v1 of the gate structures 150, e.g., v3 is at least 150% of v1. A lateral extent w5 of the shielding region 160 beyond the sidewall of the contact structure 315 is a maximum of 60% of the mesa width w3.

Claims

[1] Semiconductor device comprising: Gate structures (150) extending from a first surface (101) into a silicon carbide body (100), wherein a width (w1) of the gate structures (150) along a first horizontal direction (191) parallel to the first surface (101) is smaller than a vertical extent (v1) of the gate structures (150) perpendicular to the first surface (101); Contact structures (315) extending from the first surface (101) into the silicon carbide body (100), wherein the gate structures (150) and the contact structures (315) alternate along the first horizontal direction (191); Shielding regions (160) which, in the silicon carbide body (100), adjoin a bottom of the contact structures (315) and are spaced apart from the gate structures (150) along the first horizontal direction (191); Source regions (110) formed between the first surface (101) and body regions (120), wherein the body regions (120) form pn junctions (pn2) with the source regions (110), wherein the body regions (120) have main sections (121) adjacent to the gate structures (150) and contact sections (129) adjacent to the contact structures (315) between the main sections (121) and the contact structures (315), and a vertical extent (v2) of the contact structures (315) is greater than the vertical extent (v1) of the gate structures (150). [2] A semiconductor device according to claim 1, wherein the contact portions (129) have a higher dopant concentration than the main portions (121). [3] The semiconductor device of claim 1, wherein a width (w4) of the shielding regions (160) along the first horizontal direction (191) is greater than a width (w2) of the contact structures (315). [4] Semiconductor component according to one of claims 1 or 2, wherein mesa sections (190) of the silicon carbide body (100) formed between the gate structures (150) and the contact structures (315) have the body regions (120), wherein the body regions (120) form further pn junctions (pn1) with a drift structure (130), and wherein the drift structure (130) forms pn junctions (pn3) with the shielding regions (160). [5] Semiconductor component according to claim 3, wherein a mesa width (w3) of the mesa sections (190) along the first horizontal direction (191) is smaller than the vertical extent (v1) of the gate structures (150). [6] Semiconductor component according to one of claims 4 to 5, wherein portions of the contact structures (315) adjacent to the drift structure (130) form Schottky contacts (SC). [7] Semiconductor component according to one of claims 1 to 6, wherein a vertical extent (v2) of the contact structures (315) is greater than the vertical extent (v1) of the gate structures (150). [8] Semiconductor component according to one of claims 1 to 7, wherein the gate structures (150) comprise a gate dielectric (159) and a gate electrode (155), wherein the gate electrode (155) comprises first portions (171) of a metal structure (170) adjoining the gate dielectric (159). [9] The semiconductor device of claim 8, wherein the contact structures (315) comprise second portions (172) of the metal structure (170) adjacent to the silicon carbide body (100). [10] Semiconductor component according to one of claims 8 or 9, wherein the metal structure (170) has at least a first sub-layer (173) and a second sub-layer (174), wherein a first section of the first sub-layer (173) in the gate structures (150) adjoins the gate dielectric (159) and a second section of the first sub-layer (173) in the contact structures (315) adjoins the semiconductor body (100), and wherein the second sub-layer (174) rests on the first and the second section of the first sub-layer (173). [11] Semiconductor component according to one of claims 1 to 10, wherein a distance (v4) of a maximum dopant concentration in the shielding regions (160) from the first surface (101) is greater than the vertical extent (v1) of the gate structures (150). [12] Semiconductor component according to one of claims 1 to 11, wherein the gate structures (150) and the contact structures (315) are formed in stripes with longitudinal axes parallel to a second horizontal direction, wherein the second horizontal direction is parallel to the first surface (101) and orthogonal to the first horizontal direction (191). [13] Semiconductor device comprising: Gate structures (150) extending from a first surface (101) into a silicon carbide body (100), wherein a width (w1) of the gate structures (150) along a first horizontal direction (191) parallel to the first surface (101) is smaller than a vertical extent (v1) of the gate structures (150) perpendicular to the first surface (101); Contact structures (315) extending from the first surface (101) into the silicon carbide body (100), wherein the gate structures (150) and the contact structures (315) alternate along the first horizontal direction (191); a drift structure (130) formed in the silicon carbide body (100); and Shielding regions (160) which adjoin a bottom of the contact structures (315) in the silicon carbide body (100) and are spaced apart from the gate structures (150) along the first horizontal direction (191), wherein the shielding regions (160) are arranged between the contact structures (315) and the drift structure (130). [14] Semiconductor component according to the preceding claim, wherein the shielding regions (160) adjoin body regions (120). [15] Semiconductor component according to one of the two preceding claims, wherein the shielding regions (160) are formed symmetrically to a center of the contact structures (315). [16] Semiconductor device according to one of the three preceding claims, wherein the shielding regions (160) extend along lower portions of sidewalls of the contact structures (315). [17] Semiconductor component according to one of the four preceding claims, wherein a horizontal width of the shielding regions (160) parallel to the first horizontal direction (191) is greater than a horizontal width of the contact structures (315). [18] Semiconductor device according to one of the five preceding claims, wherein the shielding regions (160) extend vertically into the body regions (120). [19] Semiconductor device according to one of the six preceding claims, wherein the shielding regions (160) extend deeper into the silicon carbide body (100) than the gate structures (150). [20] Semiconductor component according to one of the seven preceding claims, wherein the shielding regions (160) form pn junctions (pn3) with the drift structure (130).

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