FINE FET CIRCUIT DEVICES WITH CUTS INSULATION AND ASSOCIATED MANUFACTURING PROCEDURES

Abstract

Procedures, encompassing the following: Obtaining a structure (100) which includes the following: a substrate (102) comprising a first well region (104A) with a first doping type and a second well region (104B) with a second doping type, which is opposite to the first doping type; and fins (106) which protrude from the substrate (102); Forming a structured etch mask (202, 204) on the structure (100), wherein the structured etch mask (202, 204) provides an opening (206) which is directly above a first fin (106b) of the fins (106), wherein the first fin (106b) is directly above the first trough area (104A); Etching of the structure (100) through the structured etching mask (202, 204), wherein the etching removes the first fin (106b) and forms a depression (302) in the substrate (102) which extends from the first depression area (104A) to the second depression area (104B); and Forming a dielectric material (402) between remaining sections of the fins (106) and within the depression (302), wherein a second fin (106c) of the fins (106) is immediately above the second depression area (104B) and is closest to the first fin (106b) along a fin width direction, and the opening (206) is immediately above a first section of the second depression area (104B) between the first fin (106b) and the second fin (106b), and a width of the first section is less than a width of the second depression area (104B) between the first fin (106b) and the second fin (106c) along the fin width direction.

Description

BACKGROUND

[0001] The integrated semiconductor (IS) industry has experienced rapid growth. As IS evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This process of scale-down generally provides benefits by increasing manufacturing efficiency and reducing associated costs. However, such scale-down is also accompanied by increased complexity in the design and fabrication of devices containing these IS. Parallel advances in manufacturing have enabled the production of increasingly complex designs with precision and reliability.

[0002] For example, advances in fabrication have enabled three-dimensional designs, such as fin-like field-effect transistors (FinFETs). FinFETs offer reduced short-channel effects, reduced leakage loss, and higher current flow compared to planar FETs. Because of these advantages, FinFETs are being used to further miniaturize IS. However, certain aspects of current FinFET fabrication can still be improved. For example, in FinFET CMOS designs, latch-up can occur due to leakage loss between an adjacent N-well and P-well.

[0003] US 2015 / 0021690A1 relates to a method for manufacturing semiconductor fin structures, wherein one or more fin structures of a first architecture type are formed in a first fin area and one or more fin structures of a second architecture type are formed in a second fin area.

[0004] US 9,899,267 B1 relates to a semiconductor device with a plurality of fin structures, each fin structure being extended in a first direction, and a trench isolation structure between the fin structures. A lower surface of a gate isolation structure is positioned lower than an upper surface of the trench isolation structure.

[0005] US 2016 / 0225906A1 relates to a semiconductor device structure with a fin structure over a substrate. The first dopant concentration of a doped region exposed by the fin structure is greater than the second dopant concentration of a doped region covered by the fin structure and an insulating layer on two opposite sides of the fin structure.

[0006] US 2016 / 0247728A1 relates to a method for manufacturing a semiconductor device comprising the formation of an isolation region defining a first active fin region and a second active fin region, and a gate cut opening overlapping a boundary between first and second well regions formed between the first and second active fin regions.

[0007] US 2018 / 0315664A1 relates to a FinFET semiconductor device with different layers for PFET and NFET, in which a first fin structure is located over an N-well and a second fin structure is located over a P-well, and different liner layers are used to optimize the performance of the respective transistor types, including the use of a silicon-germanium material.

[0008] US 2015 / 0249127A1 relates to a method for manufacturing fins for FinFET semiconductor devices, in which an initial plurality of fins is defined in a substrate and subsequently at least one fin to be removed is selectively removed by a cyclic etching process to make room for insulating material.

[0009] DE 10 2016 121 443 A1 relates to a process for etching a semiconductor substrate to form trenches, as well as the formation of semiconductor strips in these trenches, followed by the deposition and doping of dielectric layers to diffuse dopants into the semiconductor strips by annealing and thus to form doped semiconductor areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is best understood from the following detailed description when read with the accompanying figures. It should be emphasized that, in accordance with normal industry practice, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description. Fig. Figure 1 is a flowchart of a process according to various aspects of the present disclosure. Fig. 2 to Fig. Figure 3 are perspective representations of a workpiece according to different aspects of the present disclosure. Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 are cross-sectional views of a workpiece according to various aspects of the present disclosure, in which the cross-sectional view is shown along the line A―A in Fig. 3 is taken. Fig. Figure 12 illustrates a schematic diagram and an arrangement plan of an IS according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0011] The invention is defined by the subject matter of the independent claims. The dependent claims relate to corresponding embodiments. The following disclosure provides many different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the embodiment of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and it may also include embodiments in which additional features between the first and second features may be configured such that the first and second features need not be in direct contact.Furthermore, the design of a feature which is connected and / or coupled to another feature in the present disclosure may include embodiments in which the features are formed in direct contact, and it may also include embodiments in which additional features located between the features may be designed in such a way that the features do not have to be in direct contact.

[0012] In addition, relative spatial terms, such as "lower," "higher," "horizontal," "vertical," "above," "over," "below," "under," "up," "down," "above," "below," etc., and derivatives thereof (e.g., "horizontal," "downward," "upward," etc.), are used to simplify the present disclosure with regard to the relationship of one feature to another. The relative spatial terms are intended to cover different orientations of the device comprising the features. Furthermore, the present disclosure may repeat reference numerals and / or reference symbols in the various examples. This repetition serves the purpose of simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed beyond the scope described.Furthermore, when a number or range of numbers is described with "approximately," "about," or the like, the term is intended to include numbers that lie within a reasonable range encompassing the described number, such as within + / -10% of the described number or other values ​​as understood by average professionals. For example, the term "approximately 5 nm" encompasses the dimensional range of 4.5 nm to 5.5 nm.

[0013] With the continued miniaturization of devices, leakage current between oppositely doped well regions on an IC becomes a problem because it can trigger a latch-up in the circuit. This is of particular interest for current SRAM designs where NMOS and PMOS transistors (which include NMOS FinFETs and PMOS FinFETs) are placed close together. Fig. 12 explains an example of a latch-up. Fig. Figure 12 illustrates on the right-hand side an arrangement plan of a semiconductor device 100 comprising a 1-bit SRAM cell with CMOS circuitry, and on the left-hand side a circuit diagram representing the intrinsic bipolar transistors of a CMOS circuit of the 1-bit SRAM cell. When one of the two bipolar transistors is forward-biased (due to a leakage current flowing through the well or substrate, as illustrated as “N+ / NW →” and “P+ / PW →”), it feeds the base of the other transistor. This positive feedback increases the current until the circuit fails or burns out. This is called “latch-up.” One objective of the present disclosure is to prevent latch-up by providing well isolation features that separate well regions of the different doping types.For example, the trough insulation feature can be provided between an n-type doped trough area and a p-type doped trough area to significantly reduce leakage current between the two trough areas.

[0014] Some embodiments of the present disclosure are described with reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. 12 described. Fig. Figure 1 is a flowchart of a method 10 for manufacturing a semiconductor device with the well insulation feature according to the present disclosure. The method 10 is merely an example and is not intended to limit the present disclosure beyond what is explicitly described in the claims. Additional operations may be provided before, during, and after the method 10, and some of the described operations may be replaced, eliminated, or rearranged for additional embodiments of the method. The method 10 is subsequently described in conjunction with Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. Figure 11 describes various perspective and cross-sectional views of the semiconductor device 100 during the manufacturing steps according to method 10. Furthermore, it illustrates Fig. 12 an exemplary IS schematic and arrangement plans which were prepared in accordance with the present disclosure.

[0015] With reference to Fig. In operation 12, process 10 yields a structure (or workpiece) 100, which has a substrate with trough regions and semiconductor fins that protrude from the substrate. An example of structure 100 is shown in Fig. 2 shown.

[0016] With reference to Fig. 2 Structure 100 comprises a substrate 102, which represents any structure on which circuit devices can be formed. In various examples, the substrate 102 comprises an elemental (single-element) semiconductor, such as silicon or germanium in a crystal structure; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; a non-semiconductor material, such as soda-lime glass, silica glass, quartz glass, and / or calcium fluoride (CaF2); and / or combinations thereof.

[0017] The substrate 102 can have a uniform composition or it can comprise several layers. The layers can have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to subject the device to stress and thereby tune its performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates 102. In some such examples, one layer of the substrate 102 can comprise an insulator, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and / or other suitable insulator materials; and another layer of the substrate 102 comprises semiconductor materials. In some examples, the substrate 102 is a bulk semiconductor substrate, such as a bulk silicon wafer.

[0018] Doped regions, such as depressions, can be formed on the substrate 102. In this respect, some sections of the substrate 102 can be doped with p-type dopants, such as boron, BF₂, or indium, while other sections of the substrate 102 can be doped with n-type dopants, such as phosphorus or arsenic; and / or with other suitable dopants and combinations thereof. In the illustrated examples, a depression region 104A has a first doping type (e.g., n-type), a depression region 104B has a second doping type (e.g., p-type) opposite to the first doping type, and a depression region 104C has the first doping type. Accordingly, pn-doped regions can be formed at the interfaces between these depression regions 104.The inventor of this application discovered that these pn doping regions contribute to leakage currents and latch-up problems, particularly in SRAM designs where the device geometries are very small. Again, the three well regions 104A to C are merely examples. In various embodiments, the structure 100 can comprise at least two oppositely doped well regions.

[0019] In some examples, the devices to be formed on the substrate 102 may protrude from the substrate 102. For example, FinFETs and / or other non-planar devices may be formed on fin structures (or fins) 106 arranged on the substrate 102. The fins 106 represent any raised feature for forming FinFET devices as well as other raised active and passive devices on the substrate 102. The fins 106 may have a similar composition to the substrate 102, or they may be different. For example, in some embodiments, the substrate 102 may primarily comprise silicon, while the fins 106 may comprise one or more layers that are primarily germanium or a SiGe semiconductor.In some embodiments, the substrate 102 comprises a SiGe semiconductor, and the fins 106 comprise a SiGe semiconductor with a different silicon-to-germanium ratio than the substrate 102. In some embodiments, both the fins 106 and the substrate 102 primarily comprise silicon. Fig. Figure 2 illustrates six fins 106a, 106b, 106c, 106d, 106e, and 106f merely as examples. The structure 100 can comprise any number of fins 106 in various embodiments. In the following description, "fin 106" means any one of the fins 106a to f or any other fin not shown in the figures, and "fins 106" means at least any two of the fins 106a to f or any other fins not shown in the figures. The fins 106 are oriented lengthwise along a "Y" direction and spaced apart from each other along an "X" direction. The trough regions 104 are also oriented lengthwise along the "Y" direction.

[0020] Sections of the fins 106 can be doped differently from the sections of the substrate 102 from which they protrude. In some examples, each fin 106 has a lower section 108 (also referred to as semiconductor region 108) containing the same doping type as the well region 104 from which it protrudes, and an upper section 110 (also referred to as semiconductor region 110) containing the opposite doping type. In one specific example, the well regions 104A and 104C are n-type doped (i.e., an N-well), the semiconductor regions 108 of fins 106a, 106b, 106e, and 106f are also n-type doped, and the semiconductor regions 110 of fins 106a, 106b, 106e, and 106f are p-type doped. The well area 104B is p-doped (i.e., a p-well), the semiconductor areas 108 of the fins 106c and 106d are also p-doped, and the semiconductor areas 110 of the fins 106c and 106d are n-doped.

[0021] The fins 106 can be formed by etching sections of the substrate 102, by depositing different layers onto the substrate 102 and etching the layers, and / or by other suitable methods. For example, the fins 106 can be structured using one or more photolithography processes, comprising dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, which make it possible to produce structures that, for example, have grid dimensions that are smaller than what is otherwise obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate 102 and one or more hard mask layers (i.e.,The layers from which hard mask structures 112 and 114 are formed over the fins). The sacrificial layer is structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers are used to structure the substrate 102 and the hard mask layers by removing material not covered by the spacers. The remaining material becomes the fins 106, which, in the present embodiment, comprise the hard mask structures 112 and 114 over the fins.

[0022] The hard mask structures 112 and 114 over the fins can be used to control the etching process that defines the fins 106 and can protect the fins 106 during subsequent processing. Accordingly, the hard mask structures 112 and 114 over the fins can be selected to exhibit an etch selectivity that differs from that of the material(s) of other sections of the fins 106 and from each other. The hard mask structures 112 and 114 over the fins can comprise a dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, a semiconductor carbonitride, a semiconductor oxycarbonitride, and / or a metal oxide.

[0023] In some examples, the fins 106 are arranged in a repeating structure to facilitate the structuring process, and these fins 106, which are not part of the final circuit design, can subsequently be removed, as will be discussed later.

[0024] With reference to Fig. In operation 14, process 10 forms a dielectric lining layer 116 over the structure. Referring to Fig. 3 The dielectric lining layer 116 is formed over an upper surface 102U of the substrate 102 and on a top surface and side walls of the fins 106. In the present embodiment, the dielectric lining layer 116 is formed in a substantially conformal manner (i.e., its thickness is substantially uniform). The dielectric lining layer 116 can comprise silicon nitride (e.g., Si3N4) and can be deposited using chemical vapor deposition (CVD), such as low-pressure CVD (LPCVD) or plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable methods. The dielectric lining layer 116 can have a thickness of approximately 1 nm to approximately 5 nm in various embodiments. Operation 14 is optional and can be omitted in some embodiments.

[0025] Operations 16, 18 and 20 of the Fig. Section 1 describes the process for removing some of the fins 106. In brief, Operation 16 forms a structured hard mask over the structure 100, the structured hard mask having an opening directly above one of the fins 106 and over two trough regions 104; Operation 18 etches the structure 100 through the opening in the structured hard mask to form a depression extending into the substrate 102; and Operation 20 removes the structured hard mask. Operations 16, 18, and 20 are described in more detail below.

[0026] With reference to Fig. In procedure 10, during operation 16, a structured hard mask forms over the structure 100, and the structured hard mask provides openings 206 directly above sections of the fins 106 that are to be removed, as shown in Fig. Figure 4 shows that in the present embodiment, operation 16 involves several process steps, including depositing a hard mask layer (or a filler layer) 202 over the substrate 102 and filling the spaces between the fins 106, centrifugally coating a photoresist layer 204 over the hard mask layer 202, and performing a photolithography process to structure the photoresist layer 204 to form the openings 206. The structured hard mask can also be formed using other methods.

[0027] With reference to Fig. 4. The hard mask layer 202 surrounds the fins 106 and can be arranged on top of the hard masks 112 and 114 above the fins. Suitable materials for the hard mask layer 202 include dielectrics, polysilicon, and / or other suitable materials. The material of the hard mask layer 202 can be selected to have an etchant sensitivity different from that of the substrate 102. The fins 106 encompass the hard masks 112 and 114 above the fins. In some examples, the hard mask layer 202 includes a spin-deposited dielectric material. The hard mask layer 202 can be formed by any suitable process, including chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma-deposit CVD (HDP-CVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), flowable CVD (FCVD), spin deposition, and / or other suitable deposition methods.

[0028] A photoresist layer 204 is formed on the hard mask layer 202, e.g., by spin coating, and is structured to provide openings 206 therein. The photoresist layer 204 can be structured using any suitable photolithography process, such as dip lithography, electron beam lithography, and EUV lithography. In one embodiment, a photolithographic system exposes the photoresist 204 in a specific structure, which is defined by a mask, to radiation. Light passing through or reflected from the mask strikes the photoresist 204, thereby transferring a structure formed on the mask onto the photoresist 204.In another embodiment, the photoresist 204 is exposed using a direct-writing or maskless lithography process, such as laser structuring, electron beam structuring, and / or ion beam structuring. Once exposed, the photoresist 204 is developed, leaving behind the exposed portions of the resist, or, in alternative examples, the unexposed portions of the resist. An exemplary structuring process includes gentle firing of the photoresist 204, mask alignment, exposure, post-exposure firing, development of the photoresist 204, rinsing, and drying (e.g., hard firing). The structured photoresist 204 exposes portions of the hard mask layer 202, which are to be etched through the openings 206.

[0029] In the present embodiment, the openings 206 (one is in Fig. 4 shown) directly above sections of the fins 106 that are to be removed (which in this example is a section of fin 106b). To form trough insulation features according to the present embodiment, the opening 206 is wide enough to extend over a transition area (or boundary) between two trough areas with opposite doping types (such as trough area 104A and trough area 104B). In the Fig. In the example shown, if a distance W1 from the boundary of the trough areas 104A and 104B to the side wall of the fin 106c (which is the nearest fin to the trough area 104A below the fins on the trough area 104B) along the X-direction (the fin width direction), the opening 206 extends a distance W2 from the boundary of the trough areas 104A and 104B towards the fin 106c along the X-direction, and W2 is smaller than W1. In some embodiments, the distance W2 is controlled to be approximately half of W1, such as 40% to 60% of W1. This serves to accommodate process variation and still provide sufficient insulation between the trough areas 104A and 104B (as described later with reference to the trough insulation feature 404 in the Fig. 8, Fig. 9, Fig. 10 to Fig. (as described in section 11). If the distance W2 is too large (i.e., the edge of the opening 206 is very close to the fin 106c), subsequent etching processes may damage the fin 106c. If the distance W2 is too small (i.e., the edge of the opening 206 is very close to the boundary of the trough areas 104A and 104B, or the opening 206 does not even reach the trough area 104B), the insulating effects of the insulating feature 404 are lost. Additionally, the opening 206 is located immediately above the fin 106b, with sufficient clearance on both sides of it to ensure that the section of fin 106b is completely removed. In the present embodiment, the opening 206 extends a distance W3 from the boundary of the recess areas 104A and 104B in the direction of the fin 106b (which is the nearest fin to the recess area 104B below the fins on the recess area 104A) and beyond along the X-direction, and W3 is larger than W2. Although in Fig. As shown in Figure 4, an opening 206 is illustrated; operation 16 can form any number of openings 206 based on a circuit diagram. In the case of the Fig. In the example shown in Figure 12, two openings 206 are provided for removing sections of the fins 106a and 106b.

[0030] With reference to Fig. In Operation 18, Procedure 10 performs one or more etching processes to remove the exposed portions of the hard mask layer 202 and the underlying fins 106, which encompass the hard masks 112 and 114 over the fins, if present. In some examples, this includes a first etching process to remove the exposed portion of the hard mask layer 202, followed by a second etching process performed on the portions of the fins 106. The first etching processes may include any suitable etching method, such as wet etching, dry etching, reactive ion etching (RIE), ashing, and / or other etching methods. In some examples, the etchant is selected to etch the hard mask layer 202 without significantly etching the substrate 102 and the fins 106. As a result, a portion of the fin 106b is exposed in the opening 206, as shown in Fig. 5 shown. If the structure includes the optional lining layer 116, then a section of the lining layer 116 is exposed on a top surface and side walls of the fin 106b and on the upper surface of the substrate 102 in the opening 206, as shown in Fig. 5 shown. After etching the hard mask layer 202, the photoresist 204 can be removed.

[0031] The second etching process is then performed on the sections of the fins 106 (which may be covered by the optional lining layer 116) within the opening 206. In some embodiments, the second etching process includes a RIE etching process in which fluorine ions and / or other ion species are directed at the optional lining layer 116, the hard masks 112 and 114 over the fins, and the semiconductor areas 108 and 110 to be etched. The ions can remove material from these features due to the force of impact (sputtering) and / or react with the materials of the features to create a compound that is sensitive to a subsequent wet or dry etchant. In one embodiment, the second etching process uses a fluorine-containing etchant comprising one or more compounds of CF2, CH2F2, F2, SF6, and CH3F.Exemplary etching conditions include an etching power of approximately 300 W to 600 W and an etching bias voltage of approximately 400 V to 600 V. Additionally or alternatively, the etching process may include wet etching, dry etching, another RIE process and / or other suitable etching methods using an oxygen-based etchant, a fluorine-based etchant, a chlorine-based etchant, a bromine-based etchant, an iodine-based etchant, other suitable etchant gases or plasmas and / or combinations thereof.

[0032] In addition to removing the section of the fins 106 (e.g., 106b), the etching also cuts into the substrate 102, creating depressions 302 in it (this is referred to in some cases as "heavier etching" because it etches deeper than simply removing the fins), as in Fig. Figure 6 shows a depression 302. The depressions 302 are subsequently filled with dielectric material(s) to create well insulation features (such as the features 404 in Figure 6). Fig. 9, Fig. 10 to Fig. 11), which reduce the flow of leakage current between the trough regions (such as trough regions 104A and 104B). This provides a number of advantages. For example, reducing leakage current can itself be beneficial, as a reduced amount of leakage improves efficiency and reduces heat dissipation. As another example, the trough isolation features 404 can prevent latch-up, in which a conducting transistor causes another transistor to conduct regardless of the gate voltage. As device spacing decreases, latch-up can become more common. However, by reducing the flow of current between the trough regions, the trough isolation features 404 enable closer device spacing in cases of reduced latch-up.

[0033] The depression 302 extends across the boundary of the basin areas 104A and 104B. As in Fig. As shown in Figure 6, the recess 302 extends into recess 104B at a distance W2' from the boundary of recesses 104A and 104B, and extends into recess 104A at a distance W3' from the boundary of recesses 104A and 104B. In the present embodiment, W3' is larger than W2'. Furthermore, W2' is approximately 40% to 60% of W1. The dimensions W2' and W3' are essentially the same as the dimensions W2 and W3, respectively, taking into account any differences caused by the etching processes.

[0034] The depressions 302 can be etched to any suitable depth 304, and in examples where the fins 106 extend between approximately 100 nm and approximately 500 nm above the upper surface 102U of the substrate 102, the depression 302 can extend at least 25 nm below the upper surface 102U of the substrate 102, which is located between the fins 106a and 106c and immediately adjacent to the depression 302. In some embodiments, the depth 304 is between approximately 25 nm and approximately 75 nm below the upper surface 102U of the substrate 102. The depth 304 is designed such that the relatively more heavily doped portion of the depression regions 104A and 104B is removed from the depressions in order to substantially reduce leakage currents through the depression regions.As observed in real samples and from simulation data, the dopants in the trough regions 104 (such as 104A and 104B) tend to concentrate in the upper part of the trough regions, for example, within the upper 25 nm to 75 nm thickness from the upper surface of the substrate 102. By removing this part of the trough region and replacing it with a dielectric material (as feature 404 in . Fig. 8, Fig. 9, Fig. 10 to Fig. (As shown in Figure 11), the leakage currents through the trough regions are greatly reduced. The section of the trough regions 104 below the depression 302 is less densely doped than the removed section and has a relatively high electrical resistance. Consequently, it does not cause significant leakage currents. In one embodiment, the depression 302 extends at least 40 nm below the upper surface of the substrate 102 (i.e., the depth 304 is 40 nm or more) to ensure that the more densely doped section of the trough regions 104A and 104B is removed. In various embodiments, the substrate 102 is at least a few hundred nanometers or a few micrometers thick.

[0035] In various embodiments, operation 18 can use a timer and / or other methods to control the etch depth 304. For example, operation 18 can monitor the etch residue to determine when the second etching process has started to etch the well area 104 and then control the etch depth 304 based on the etching time and etch rate. The etch rate is influenced by the type, density, and / or flow rate of the etchant(s), the etching power, the etching bias, the material of the well area 104, and other factors. The etch rate can be determined from experiments and / or past process data. In some embodiments, the first and second etching processes described above can be performed continuously or as a single etching process (e.g., in the same etching chamber).

[0036] The recesses 302 can be etched to have different profiles. In the case of the Fig. In the example shown in Figure 6, the recess 302 has a substantially rectangular profile. This may result from a highly directional etching process. In another example, the recess 302 may be etched to have a tapered profile, such as with an upper opening that is wider than the lower opening. Such an example is shown in Figure 6. Fig. Figure 11 illustrates where the tapered contour of the well insulation feature 404 represents the profile of the recess 302. In this example, the recess 302 (as well as the well insulation feature 404) has rounded corners (rounded upper corners and / or rounded lower corners) resulting from the etching process. Furthermore, the upper opening of the recess 302 is wider than its lower opening in this example. A tapered profile in the recess 302 makes it easier to fill the dielectric material without voids, thereby increasing the reliability of the circuit.

[0037] With reference to Fig. In operation 20, following the etching of the fins 106 and the trough areas 104, process 10 removes the hard mask layer 202. Operation 20 can use any suitable etching process (such as wet etching, dry etching, and RIE) that is selective for the material(s) in the hard mask layer 202. The resulting structure 100 is in Fig. 7 shown, which is essentially the same as structure 100, which is shown in Fig. 3 is shown, but with removed sections of the fins 106 and the hollow areas 104.

[0038] With reference to Fig. 1. In operation 22, procedure 10 forms isolation features 402 over structure 100, which in particular fill the recesses 302. With reference to Fig. 8. Insulation features 402, such as shallow insulation trench features (STIs), are formed by depositing one or more dielectric materials, such as semiconductor oxides, semiconductor nitrides, semiconductor carbides, fluorosilicate glass (FSG), low k-value dielectric materials, and / or other suitable dielectric materials, onto the structure 100 between the fins 106, including in the recesses 302. The portion of the insulation features 402 within the recess 302 becomes a trough insulation feature 404. The material of the insulation features 402 can be formed by any suitable process, including CVD, PECVD, HDP-CVD, ALD, PEALD, PVD, FCVD, spin deposition, and / or other suitable deposition methods. In some embodiments, operation 22 may include a chemical-mechanical polishing (CMP) process to planarize the upper surface of the insulation features 402.The hard mask 114 over the fin can serve as the etch stop layer for the CMP process.

[0039] With reference to Fig. In operation 24, method 10 deepens (or etches back) the insulation features 402. In one embodiment, the insulation features 402 are deepened to a step that is at the same level as the transition area between the semiconductor area 110 and the semiconductor area 108, as shown in Fig. 9 shown. With reference to Fig. 9 The fins 106 protrude from an upper surface of the insulation features 402, and the trough insulation feature 404 (which is a section of the insulation features 402) extends into the substrate 102. A lower surface of the trough insulation feature 404 lies below the upper surface 102U of the substrate 102. In particular, the trough insulation feature 404 measures across the boundary between the trough areas 104A and 104B. The trough insulation feature 404 extends into trough area 104B at a distance W2' from the boundary of the trough areas 104A and 104B, and extends into trough area 104A at a distance W3' from the boundary of the trough areas 104A and 104B. In the present embodiment, W3' is greater than W2'. Furthermore, W2' is approximately 40% to 60% of W1. The profile of the trough insulation feature 404 essentially corresponds to that of the depression 302.If the depression 302 has an essentially rectangular profile (as in . Fig. 6), the trough insulation feature 404 also has an essentially rectangular profile (as shown in Fig. 9 shown). If the depression 302 has a conical profile, the trough insulation feature 404 also has a conical profile, as shown in Fig. Figure 11 shows in which the upper section of the recess insulation feature 404 is wider than the lower section of the recess insulation feature 404. In addition, the recess insulation feature 404 may have rounded corners (rounded upper corners and / or rounded lower corners) in some embodiments.

[0040] Fig. Figure 10 illustrates some of the advantages of the trough insulation features 404. With reference to Fig. Figure 10 illustrates an exemplary PNPN structure with a dashed line between fins 106a and 106c. Specifically, semiconductor area 110 of fin 106a is p-doped, semiconductor area 108 of fin 106a and well area 104A are n-doped, semiconductor area 108 of fin 106c and well area 104B are p-doped, and semiconductor area 110 of fin 106c is n-doped. This PNPN structure can trigger a latch-up in the circuit if there is a sufficient leakage amount between well areas 104A and 104B (as, for example, in the circuit diagram of the Fig. (Figure 12 is illustrated). Since, in the present embodiment, an upper section of the trough regions 104A and 104B is removed and replaced with the trough insulation feature 404, the leakage current between the trough regions 104A and 104B is greatly reduced, and the probability of this PNPN structure triggering a latch-up is also greatly reduced. The inventors have observed a reduction of up to two orders of magnitude (i.e., 100-fold) in leakage current and an improvement of up to 10% in latch-up trigger voltage (i.e., the supply voltage at which a latch-up occurs). In another embodiment, the doping types in regions 110, 108, and 104 can be reversed to create an NPNP structure.For example, semiconductor area 110 of fin 106a is n-type doped, semiconductor area 108 of fin 106a and the well area 104A are p-type doped, semiconductor area 108 of fin 106c and the well area 104B are n-type doped, and semiconductor area 110 of fin 106c is p-type doped. In this example, the well insulation feature 404 also reduces the probability that the NPNP structure will trigger a latch-up in the circuit.

[0041] With reference to Fig. In Operation 26, Procedure 10 performs further processes on the structure 100. For example, the structure 100 can be processed to form active and passive devices on it. In some examples, a transistor (e.g., FinFET) is formed on a fin 106 by forming a pair of source / drain features separated by a channel region. The source / drain features can comprise a semiconductor (e.g., Si, Ge, SiGe, etc.) and one or more dopants, such as p-type or n-type dopants. Similarly, the channel region can comprise a semiconductor and one or more dopants of the opposite type to those of the source / drain features, or it can simply be undoped.In some examples, a gate stack is formed adjacent to and wrapped around the channel region to control the flow of charge carriers (electrons for an n-channel FinFET and holes for a p-channel FinFET) through the channel region. An interlayer dielectric (ILD) layer may be formed on the structure 100. The ILD layer acts as an insulator, supporting and isolating conductive traces of a multi-stage electrical interconnection path structure that electrically connects elements of the structure 100, such as the source / drain features and the gate stack. The ILD layer may be a dielectric material (e.g., a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, etc.).The substrate may include spin-deposited glass (SOG), FSG, phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK® (Dow Chemical, Midland, Michigan), and / or combinations thereof. The ILD layer can be formed by any suitable process, including CVD, PVD, spin deposition, and / or other suitable processes.

[0042] Fig. Figure 12 illustrates on the right-hand side an arrangement plan of a semiconductor device 100 comprising a 1-bit SRAM cell, and on the left-hand side a circuit diagram representing part of the 1-bit SRAM cell. With reference to Fig. 12 The device comprises 100 fins 106 (comprising fins 106a to d, 106e' and 106f') oriented lengthwise along the “Y” direction, and gate stacks 500 oriented lengthwise along the “X” direction perpendicular to the “Y” direction. The line A―A of the Fig. 12 is the same as line A―A of the Fig. 3. The incised structure 206 marks the areas of the fins 106 and the depression areas 104 which are to be etched (corresponding to the opening 206 in Fig. 4) In this embodiment, the incised structure 206 extends from one edge of a gate stack 500 to the edge of another gate stack 500. It should be noted that the "incising" process (i.e., etching of the fins 106 and the trough regions 104) occurs before the gate stacks 500 are formed. Therefore, the "incising" process does not damage the gate stacks 500 that form subsequently. Furthermore, the gate stacks 500 on either side of the incised structure 206 in the PMOS region do not function as a gate, since there is no source or drain on either side of the gate, but they can function as a connecting path in some embodiments. The fins 106e' and 106f' are the fins 106e and 106f, respectively, of the Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. 11 equivalent, but they are arranged on the left side of fin 106a. Fins 106e and 106f of the Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. 11 are part of the SRAM cell to the right of the one in Fig. The 12 shown are not illustrated in this figure. The trough insulation features 404 occupy a space in the trough areas 104, which corresponds to the incised structure 206.

[0043] Although not intended as limiting features, one or more embodiments of the present disclosure provide many advantages for a semiconductor device and its design. For example, embodiments of the present disclosure provide well isolation features in a FinFET circuit, particularly FinFET SRAM cells. The well isolation features reduce leakage between two adjacent and oppositely doped well regions, thereby reducing the probability of triggering a latch-up by PNPN or NPNP structures in the circuit.

[0044] By way of example, the present disclosure relates to a method. The method comprises obtaining a structure comprising a substrate, including a first well region with a first doping type and a second well region with a second doping type opposite to the first doping type; and fins projecting from the substrate. The method further comprises forming a structured etch mask on the structure, the structured etch mask providing an opening immediately above a first fin of the fins, the first fin being immediately above the first well region.The process further comprises etching the structure through the structured etching mask, wherein the etching removes the first fin and forms a depression in the substrate measuring from the first depression area to the second depression area; and forming a dielectric material between remaining sections of the fins and within the depression.

[0045] In one embodiment, the method further comprises forming a dielectric lining over the substrate and over the top surfaces and side walls of the fins prior to forming the structured etching mask, wherein the opening exposes the dielectric lining which is arranged over the top surfaces and side walls of the first fin.

[0046] In one embodiment of the method, a second fin is located directly above the second trough area and is closest to the first fin along a fin width direction, and the opening is located directly above a first section of the second trough area between the first fin and the second fin. In another embodiment, the width of the first section is 40% to 60% of the width of the second trough area between the first fin and the second fin along the fin width direction.

[0047] In another embodiment of the method, the depression is at least 40 nm deep from an upper surface of the substrate. In another embodiment, the depth of the depression is controlled using a timer during the etching of the structure. In yet another embodiment, a first section of the first depression and the second depression, which is removed by the etching, is more heavily doped than a second section of the first depression and the second depression, which remains below the depression.

[0048] In one embodiment of the method, an upper section of the depression is wider than a lower section. In another embodiment, the first doping type is n-type and the second doping type is p-type. In yet another embodiment, the method further includes removing the structured etch mask after etching the structure and before forming the dielectric material.

[0049] In another exemplary aspect, the present disclosure relates to a method. The method comprises obtaining a structure comprising a substrate, including an N-well region and a P-well region adjacent to the N-well region; and fin structures projecting from the substrate, the method further comprising forming a dielectric lining over an upper surface of the substrate and over the top surfaces and sidewalls of the fin structures. The method further comprises forming a structured etch mask over the structure, the structured etch mask having an opening, wherein a first fin structure of the fin structures is located in the opening, the first fin structure being immediately above the N-well region.The process further comprises etching the first fin structure and the substrate through the opening, the etching forming a depression in the substrate which intersects a boundary between the N-well region and the P-well region; and forming a dielectric material between remaining sections of the fin structures and within the depression.

[0050] In one embodiment of the method, forming the structured etch mask comprises forming a filler layer over the dielectric lining and around the fin structures; forming a photoresist layer on the filler layer; structuring the photoresist layer to arrive at a structured photoresist layer; and etching the filler layer through the structured photoresist layer to provide the aperture.

[0051] In another embodiment of the method, each fin structure comprises a semiconductor fin connected to the substrate and a hard mask positioned over the semiconductor fin. In yet another embodiment, the opening exposes a section of the dielectric lining directly above the P-well region.

[0052] In one embodiment of the method, the distance from an upper surface of the substrate to a lower surface of the depression is at least 25 nm. In another embodiment, the depression has a tapered profile, wherein a top surface of the depression is wider than a bottom surface of the depression.

[0053] In yet another exemplary aspect, the present disclosure relates to a circuit device. The circuit device comprises a substrate comprising a first well region with a first doping type and a second well region with a second doping type that differs from the first doping type; fins projecting from the substrate; a dielectric material arranged between the fins such that the fins project above an upper surface of the dielectric material; and a well insulation feature comprising a section of the dielectric material extending into the substrate, wherein a lower surface of the well insulation feature is below an upper surface of the substrate extending between the well insulation feature and a first fin of the fins.

[0054] In one embodiment of the circuit device, the lower surface of the trough insulation feature is at least 40 nm below the upper surface of the substrate. In another embodiment, the trough insulation feature has rounded lower corners. In yet another embodiment, the trough insulation feature is arranged over both the first and second trough areas, with a larger portion of the trough insulation feature located over the first trough area than over the second trough area.

Claims

[1] Procedure, comprising the following: Obtaining a structure (100) which includes the following: a substrate (102) comprising a first well region (104A) with a first doping type and a second well region (104B) with a second doping type, which is opposite to the first doping type; and fins (106) which protrude from the substrate (102); Forming a structured etch mask (202, 204) on the structure (100), wherein the structured etch mask (202, 204) provides an opening (206) which is directly above a first fin (106b) of the fins (106), wherein the first fin (106b) is directly above the first trough area (104A); Etching of the structure (100) through the structured etching mask (202, 204), wherein the etching removes the first fin (106b) and forms a depression (302) in the substrate (102) which extends from the first depression area (104A) to the second depression area (104B); and Forming a dielectric material (402) between remaining sections of the fins (106) and within the depression (302), wherein a second fin (106c) of the fins (106) is immediately above the second depression area (104B) and is closest to the first fin (106b) along a fin width direction, and the opening (206) is immediately above a first section of the second depression area (104B) between the first fin (106b) and the second fin (106b), and a width of the first section is less than a width of the second depression area (104B) between the first fin (106b) and the second fin (106c) along the fin width direction. [2] The method of claim 1, further comprising the following before forming the structured etching mask: Forming a dielectric lining (116) over the substrate (102) and over the top surfaces and side walls of the fins (106), wherein the opening (206) exposes the dielectric lining (116) which is arranged over the top surfaces and side walls of the first fin (106a). [3] Method according to claim 1 or 2, wherein the width of the first section is 40% to 60% of the width of the second trough area (104B) between the first fin (106b) and the second fin (106c) along the fin width direction. [4] Method according to any of the preceding claims, wherein the depression (302) is at least 40 nm deep in the substrate (102) from an upper surface (102U). [5] Method according to one of the preceding claims, wherein a depth (304) of the depression (302) is controlled using a timer during the etching of the structure (100). [6] Method according to one of the preceding claims, wherein a first section of the first trough area (104A) and the second trough area (104B), which is removed by etching, is more heavily doped than a second section of the first trough area (104A) and the second trough area (104B), which remains below the depression (302). [7] Method according to any of the preceding claims, wherein an upper section of the depression (302) is wider than a lower section of the depression (302). [8] Method according to any of the preceding claims, wherein the first doping type is n-conducting and the second doping type is p-conducting. [9] A method according to any one of the preceding claims, further comprising: Removing the structured etch mask (202) after etching the structure (100) and before forming the dielectric material (402). [10] Procedures, comprising the following: Obtaining a structure (100) which includes the following: a substrate (102) comprising an N-well region (104A) and a P-well region (104B) adjacent to the N-well region (104A); and Fin structures (106) which protrude from the substrate (102); Forming a dielectric lining (116) over an upper surface (102U) of the substrate (102) and over a top surface and side walls of the fin structures (106); Forming a structured etch mask (202) over the structure (100), wherein the structured etch mask (202) has an opening (206), wherein a first fin structure (106b) of the fin structures (106) is located in the opening (206), wherein the first fin structure (106b) is directly above the N-well region (104A); wherein a second fin structure (106c) of the fin structures (106) is located immediately above the P-trough area (104B) and is closest to the first fin structure (106b) along a fin-width direction, and wherein the opening (206) is located immediately above a first section of the P-trough area (104B) between the first fin structure (106b) and the second fin structure (106c), and a width of the first section is less than a width of the P-trough area (104B) between the first fin structure (106b) and the second fin structure (106c) along the fin-width direction, Etching of the first fin structure (106b) and the substrate (102) through the opening (206), wherein the etching forms a depression (302) in the substrate (102) which intersects a boundary between the N-well region (104A) and the P-well region (104B); and Forming a dielectric material (402) between remaining sections of the fin structures (106) and within the recess (302), wherein each of the fin structures (106) comprises a semiconductor fin (108, 110) which is connected to the substrate (102) and a hard mask (112, 114) over the fins (106) which is arranged over the semiconductor fin (108, 110). [11] Method according to claim 10, wherein forming the structured etching mask comprises: Forming a fill layer (202) over the dielectric lining (116) and around the fin structures (116); Formation of a photoresist layer (204) on the filler layer (202); Structuring the photoresist layer (204) to obtain a structured photoresist layer (204); and Etching of the filler layer (202) through the structured photoresist layer (204) to provide the opening (206). [12] Method according to one of the preceding claims 10 or 11, wherein the opening (206) exposes a section of the dielectric lining (116) directly above the P-trough area (104B). [13] Method according to any one of the preceding claims 10 to 12, wherein the distance from an upper surface (102U) of the substrate (102) to a lower surface of the depression (302) is at least 25 nm. [14] Method according to any one of the preceding claims 10 to 13, wherein the depression (302) has a conically tapered profile, wherein a top surface of the depression (302) is wider than a bottom surface of the depression (302). [15] Circuit device (100) comprising the following: a substrate (102) comprising a first well area (104A) with a first doping type and a second well area (104B) with a second doping type which is different from the first doping type; fins (106) which protrude from the substrate (102); a dielectric material (402) which is arranged between the fins (106) such that the fins (106) protrude above an upper surface of the dielectric material (402); and a trough insulation feature (404) comprising a section of the dielectric material (402) extending into the substrate (102), wherein a lower surface of the trough insulation feature (404) is below an upper surface (102U) of the substrate (102) extending between the trough insulation feature (404) and a first fin (106a) of the fins (106), wherein the trough insulation feature (404) is arranged over both the first trough area (104A) and the second trough area (104B), and wherein a larger section of the trough insulation feature (404) is arranged over the first trough area (104A) than over the second trough area (104B). [16] Circuit device (100) according to claim 15, wherein the lower surface of the trough insulation feature (404) is at least 40 nm below the upper surface of the substrate (102). [17] Circuit device (100) according to claim 15 or 16, wherein the trough insulation feature (404) has rounded lower corners.

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