Semiconductor-on-insulator substrate (SOI substrate) and method for its formation

Abstract

Semiconductor-on-insulator substrate, SOI substrate, comprising: a handling substrate (104); a device layer (108) that lies above the handling substrate (104); and an insulating layer (106) separating the handling substrate (104) from the device layer (108), wherein the insulating layer (106) meets the device layer (108) at a first interface and meets the handling substrate (104) at a second interface, wherein the insulating layer (106) has a getter material with a getter concentration profile, the getter concentration profile having a first peak concentration at the first interface, a second peak concentration at the second interface and a trough concentration at a location between the first interface and the second interface, wherein the trough concentration is smaller than each of the first peak concentration and the second peak concentration, the getter material contains fluorine.

Description

GENERAL STATE OF THE ART

[0001] Integrated circuits are typically fabricated on bulk semiconductor substrates. In recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative to bulk semiconductor substrates. An SOI substrate comprises a handling substrate, an insulating layer above the handling substrate, and a device layer above the insulating layer. Among other advantages, an SOI substrate results in reduced stray capacitance, reduced leakage current, reduced latch-up, and improved semiconductor device performance (e.g., lower power consumption and higher switching speed).

[0002] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates a cross-sectional view of some embodiments of a semiconductor-on-insulator (SOI) substrate with a getter material arranged in the insulating layer. Fig. Figures 2A-2I illustrate cross-sectional views showing different getter concentration profiles of the SOI substrate. Fig. Show 1. Fig. Figure 3 illustrates a cross-sectional view of some embodiments of an SOI substrate with a getter material arranged in the insulating layer. Fig. Figure 4 illustrates a cross-sectional view showing a getter concentration profile of the SOI substrate. Fig. 3 shows. Fig. Figure 5 illustrates a cross-sectional view of some embodiments of an SOI substrate with a getter material arranged in the insulating layer. Fig. Figure 6 illustrates a cross-sectional view showing a getter concentration profile of the SOI substrate. Fig. 5 shows. Fig. Figure 7 illustrates a top view of some embodiments of the SOI substrate of Fig. 1. Fig. Figure 8 illustrates a cross-sectional view of some embodiments of a semiconductor structure in which the SOI substrate is made of Fig. 1 application is found. Fig. Figure 9 illustrates a manufacturing method according to some embodiments of Fig. 1 and Fig. 2A-2I. Fig. Figure 10 illustrates a manufacturing method according to some embodiments of Fig. 3 and Fig. 4. Fig. Figure 11 illustrates a manufacturing method according to some embodiments of Fig. 5 and Fig. 6. Fig. Figures 12-23 illustrate different embodiments of methods for forming SOI substrates. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and not intended as limitations. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not itself establish any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatial terms such as "below," "under," "lower," "above," "upper," and the like can be used here for simple description to convey the relationship of one element or feature to one or more other elements or features depicted in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptors used here can be interpreted accordingly.

[0006] Several embodiments of the present application relate to methods for forming an SOI substrate and to chips comprising such an SOI substrate. As is apparent from certain aspects of the present disclosure, some SOI substrates have an insulating layer containing mobile metal contaminants, such as sodium and / or potassium. These mobile metal contaminants can unintentionally penetrate the insulating layer of the SOI substrate during processing and tend to cause a higher leakage current and / or a reduction in the breakdown voltage of the insulating layer. To mitigate the effects of these metal contaminants, certain aspects of the present disclosure therefore include an SOI substrate where the insulating layer is reinforced with a getter material having a getter concentration profile. The getter material may contain a halogen, such as fluorine (F) or chlorine (Cl).The getter material binds to mobile metal contaminants to reduce current leakage and / or increase the breakdown voltage in the insulating layer. Thus, the presence of the getter material in the insulating layer binds these metal contaminants, thereby reducing leakage current and / or increasing the breakdown voltage of the insulating layer.

[0007] With reference to Fig. Figure 1 shows a cross-sectional view of some embodiments of an SOI substrate 102. The SOI substrate 102 comprises a handling substrate 104, an insulating layer 106 lying above the handling substrate 104, and a fixture layer 108 lying above the insulating layer 106. The insulating layer 106 separates the handling substrate 104 from the fixture layer 108. The insulating layer 106 has an upper insulating region 106u that covers an upper surface 104u of the handling substrate 104 in order to separate the upper surface 104u of the handling substrate 104 from the fixture layer 108. In some embodiments, the insulating layer 106 also has a lower insulating area 106l that covers a lower surface 104l of the handling substrate 104, and sidewall insulating areas 106s that cover sidewalls 104s of the handling substrate 104.In some embodiments, the upper insulating region 106u has a first thickness t1, as measured between the upper surface 104u of the handling substrate 104 and the device layer 108, while the lower insulating region 106l and sidewall insulating regions 106s have a second thickness t2. In some embodiments, the first thickness t1 is greater than the second thickness t2.

[0008] In some embodiments of Fig. In the insulating layer 106, a getter material with a specific getter concentration profile is present. The getter material may contain a halogen, such as fluorine (F) or chlorine (Cl). The getter material binds to mobile metal contaminants, such as alkali metals containing sodium (Na) and / or potassium (K), which are generated in the insulating layer 106 during the fabrication and / or processing of the SOI substrate. Without the getter material, these metal contaminants would cause a higher leakage current and / or decrease the breakdown voltage in the insulating layer 106. Therefore, the presence of the getter material in the insulating layer 106 binds these metal contaminants, thereby reducing the leakage current and / or increasing the breakdown voltage of the insulating layer.

[0009] In some cases, the embodiments of Fig. 1 according to Fig. 9 are formed, wherein a first insulating layer 902 is formed around a handling substrate 104 and a second insulating layer 904 is formed around a device substrate 108. The handling substrate 104 and the device substrate 108 are then bonded together (906) so that the first insulating layer 902 and the second insulating layer 904 come into contact with each other to establish the upper insulating region 106u, sidewall insulating regions 106s and the lower insulating region 106l. In some embodiments, sidewall sections and an upper surface section of the second insulating layer 904 around the device substrate 108 are removed, for example by an etching and a chemical-mechanical planarizing or grinding operation (far right section of Fig. 9). In particular, in Fig. 9. At least one of the first insulating layer 902 and the second insulating layer 904 are formed to have a getter material with a getter concentration profile. Therefore, in some embodiments, only the first insulating layer 902 has a getter material, while the second insulating layer 904 does not; while in other embodiments, only the second insulating layer 904 has a getter material, while the first insulating layer 902 does not. In still other embodiments, both the first insulating layer 902 and the second insulating layer 904 have a getter material.

[0010] When considering Fig. 1 together with Fig. It is evident in section 9 that the getter concentration profile can take different forms depending on the implementation, as now shown in Fig. 2A-2I is described. Fig. Figures 2A-2I show various non-restrictive examples of getter concentration profiles, representing different embodiments of Fig. 1 correspond to those in accordance with Fig. 9 were manufactured.

[0011] In Fig. 2A-2C both have getter material in the first insulating layer 902, which surrounds the handling substrate 104, and in the second insulating layer 904, which surrounds the device substrate 108. Fig. In Figures 2A-2C, the first insulating layer 902 surrounding the handling substrate 104 has a first getter concentration profile that is generally symmetrical around a central region of the handling substrate 104. Thus, the first insulating layer 902 has the first getter concentration profile, which has an upper region with an upper getter concentration profile 202 and a lower region with a lower getter concentration profile 204. The second insulating layer 904 surrounding the device substrate 108 has a second getter concentration profile 206, which may be the same or different from the first getter concentration profile. Thus, in the examples of Fig. 2A-2C the upper region of the first insulating layer 902 and the second insulating layer 904 together the upper insulating region 106u of Fig. 1 one.

[0012] In particular, in Fig. 2A a complete getter concentration profile for the upper isolation area 106u a first peak concentration 208 at a first interface 105, a second peak concentration 208 at a second interface 107 and a trough concentration 210 at a location between the first interface and the second interface. In the example of Fig. 2A, the first peak concentration 208 is equal to the second peak concentration 208, and the trough concentration 210 is smaller than either the first peak concentration 208 or the second peak concentration 208. The lower region of the first insulating layer 106l has a getter concentration profile 204 that is generally symmetrical with the getter concentration profile 202 of the upper insulating region 106u of the first insulating layer 902. In some embodiments, the first peak concentration 208 and the second peak concentration 208 each range from 1 x 10 18 atoms / cm² 3 up to 5 x 10 21atoms / cm² 3 of chlorine or fluorine and the trough level concentration 210 ranges from 1 x 10 14 atoms / cm² 3 up to 2 x 10 17 atoms / cm² 3 of chlorine or fluorine. This getter concentration profile 204 provides a high concentration of chlorine and / or fluorine atoms at the interfaces 108 / 106 and 104 / 106. These chlorine and / or fluorine ions are mobile metal ions and reduce the source of metal ions at the interfaces (e.g., Na+ (ion) + Cl- (ion) → NaCl (stable compound)), thereby reducing interfacial leakage and improving the breakdown voltage of the first insulating layer 902.

[0013] In Fig. 2B has a total getter concentration profile for the upper isolation area 106u again a first peak concentration 212 at the first interface 105, a second peak concentration 212 at the second interface 107 and a trough concentration 216 at a point between the first interface 105 and the second interface 107. In Fig. However, in 2B, the entire getter concentration profile has a maximum peak concentration of 214 at a central region of the upper isolation area of ​​106u. Defects in the interfaces tend to trap metal ions, leading to a leakage path. The concentration [Cl][F] in Fig. 2A has a higher probability of trapping metal ions in defects at the interfaces and thus improves the breakdown voltage of the upper insulating region 106u. In the example of Fig. In 2A, the first peak concentration 212 is equal to the second peak concentration 212, and the trough concentration 216 is lower than both the first peak concentration 212 and the second peak concentration 212. The lower isolation region 106l of the first isolation layer 902 has a getter concentration profile 204, which is generally symmetrical with the getter concentration profile 202 of the upper isolation region 106u of the first isolation layer 902. In some embodiments, the first peak concentration 212 and the second peak concentration 212 each range from 1 x 10 18 atoms / cm² 3 up to 5 x 10 21 atoms / cm² 3 of chlorine or fluorine and the trough level concentration 216 ranges from 1 x 10 14 atoms / cm² 3 up to 2 x 10 17 atoms / cm² 3 of chlorine or fluorine.

[0014] In Fig. 2C has a total getter concentration profile for the upper isolation area 106u again a first peak concentration 218 at the first interface 105, a second peak concentration 218 at the second interface 107 and a trough concentration 220 at a point between the first interface 105 and the second interface 107. In Fig. However, in 2C, the entire getter concentration profile has a maximum peak concentration 218 at a central region of the upper isolation region 106u, where the maximum peak concentration 218 at the central region is equal to the first peak concentration 218 and the second peak concentration 218. The lower isolation region 106l of the first isolation layer 902 has a getter concentration profile 204, which is again generally symmetrical with the getter concentration profile 202 for the upper isolation region 106u of the first isolation layer 902. In other embodiments, the first and second peak concentrations and trough concentrations can each be equal, and the chlorine or fluorine concentration can be flat over the upper isolation region 106u, the lower isolation region 106l, and / or the first isolation layer 902, and / or the second isolation layer 904.In some embodiments, the first peak concentration 218 and the second peak concentration 218 each range from 1 x 10. 18 atoms / cm² 3 up to 5 x 10 21 atoms / cm² 3 of chlorine or fluorine and the trough level concentration 220 ranges from 1 x 10 14 atoms / cm² 3 up to 2 x 10 17 atoms / cm² 3 of chlorine or fluorine.

[0015] In Fig. 2D-2F has only the first insulating layer 902 containing getter material, and the second insulating layer 904 does not contain any getter material. This can streamline the machining of the fixture substrate 108 and thus represents a good solution in some respects, as it streamlines the machining while still providing an SOI substrate with reduced leakage and enhanced breakdown voltage, since the getter material binds metal contaminants that could otherwise adversely affect leakage and / or breakdown voltage. Fig. In 2D, the first peak concentration 222 is greater than the second peak concentration 224, and a trough concentration 226 is smaller than both the first peak concentration 222 and the second peak concentration 224. Fig. 2E, the first peak concentration 228 is smaller than the second peak concentration 230, and a trough concentration 232 is smaller than both the first peak concentration 228 and the second peak concentration 230. In Fig. 2F, the first peak concentration 234 is equal to the second peak concentration 234, and a trough concentration 236 is smaller than both the first peak concentration 234 and the second peak concentration 234. In some embodiments, the first peak concentration 222, 230, 234 and the second peak concentration 224, 228 and / or 234 each range from 1 x 10 18 atoms / cm² 3 up to 5 x 10 21 atoms / cm² 3of chlorine or fluorine and the trough level concentration 226, 232 and / or 236 each ranges from 1 x 10 14 atoms / cm² 3 up to 2 x 10 17 atoms / cm² 3 of chlorine or fluorine.

[0016] In Fig. 2G-2I has only the second insulating layer 904 getter material, and the first insulating layer 902 has no getter material. This can streamline the machining of the handling substrate 104 and thus represents a good solution in some respects, as machining is streamlined while still providing an SOI substrate with reduced leakage and enhanced breakdown voltage, since the getter material binds metal contaminants that could otherwise adversely affect leakage and / or breakdown voltage. Fig. 2G, the first peak concentration 238 is greater than the second peak concentration 240, and a trough concentration 242 is smaller than both the first peak concentration 238 and the second peak concentration 240. In Fig. 2H, the first peak concentration 244 is smaller than the second peak concentration 246, and a trough concentration 248 is smaller than both the first peak concentration 244 and the second peak concentration 246. In Fig. 2I the first peak concentration 250 is equal to the second peak concentration 250 and a trough concentration 252 is smaller than both the first peak concentration 250 and the second peak concentration 250. In some embodiments, the first peak concentration 238, 246 and / or 250 and the second peak concentration 240, 244 and / or 250 each range from 1 x 10 18 atoms / cm² 3 up to 5 x 10 21 atoms / cm² 3of chlorine or fluorine and the trough level concentration 242, 248 and / or 252 each ranges from 1 x 10 14 atoms / cm² 3 up to 2 x 10 17 atoms / cm² 3 of chlorine or fluorine.

[0017] With reference to Fig. Figure 3 shows another embodiment in which the SOI substrate 102 comprises a handling substrate 104, a fixture layer 108 located above the handling substrate 104, and an insulating layer 106 separating the handling substrate 104 from the fixture layer 108. The insulating layer 106 meets the fixture layer 108 at a first interface 107 and meets the handling substrate 104 at a second interface 105. The second interface 105 corresponds to a point where the upper surface 104u of the handling substrate 104 meets the insulating layer 106.

[0018] As in Fig. 4 illustrates, in some embodiments of Fig. 3 The insulating layer 106 is a getter material with a getter concentration profile. The getter concentration profile has a first peak concentration 402 at the first interface 107, a second peak concentration 404 at the second interface 105, and a trough concentration 406 at a location 408 between the first interface 105 and the second interface 107. The first peak concentration 402 is smaller than the second peak concentration 404, but in other embodiments it could be greater than or equal to the second peak concentration 404. Further, as in Fig. As shown in section 4, in some embodiments it extends from Fig. 3 the getter material into a section of the device layer 108 at a first concentration and extends into a section of the handling substrate 104 at a second concentration, wherein the first concentration is less than the second concentration.

[0019] In some cases, the embodiments of Fig. 3-4 according to Fig. 10 are formed, wherein a first insulating layer 902 is formed around a handling substrate 104. The handling substrate 104 and the first insulating layer 902 are then bonded to a device substrate 108 (1006), such that the first insulating layer 902 establishes the upper insulating region 106u, side wall insulating regions 106s, and the lower insulating region 106l. In some embodiments, an upper surface section of the device substrate 108 is then removed, for example, by etching and / or a chemical-mechanical planarization or grinding process (far right section of Fig. 10). In particular, in Fig. 10 the first insulating layer 902 is formed to have a getter material with a getter concentration profile as in Fig. 4 shown. Although Fig. Figure 4 shows an exemplary doping concentration profile; alternatively, other exemplary doping concentrations, such as those in Figure 4, can be used. Fig. 2A-2I depicted and / or described in Fig. 4 can be used.

[0020] Fig. Figure 5 shows another embodiment, where the SOI substrate 102 comprises a handling substrate 104, a fixture layer 108 located above the handling substrate 104, and an insulating layer 106 separating the handling substrate 104 from the fixture layer 108. The insulating layer 106 is bounded between the fixture layer 108 and the handling substrate 104, such that a bottom surface of the insulating layer 106 corresponds to a top surface of the handling substrate 104, and a top surface of the insulating layer 106 corresponds to a bottom surface of the fixture layer 108.

[0021] As in Fig. As illustrated in Figure 6, the insulating layer 106 exhibits in some embodiments of Fig. 5 a getter material with a getter concentration profile. The getter concentration profile has a first peak concentration at the first interface 105, a second peak concentration at the second interface 107, and a trough concentration at a point between the first interface 105 and the second interface 107. In Fig. 6 means the first peak concentration is smaller than the second peak concentration.

[0022] In some cases, the embodiments of Fig. 5-6 according to Fig. 11, wherein a second insulating layer 904 is formed around a device substrate 108. The device substrate 108 and the second insulating layer 904 are then bonded to a handling substrate 104 (1106), such that the second insulating layer 904 forms the upper insulating region 106u. In some embodiments, an upper surface section of the device substrate 108 and sections of the second insulating layer 904 are then removed, for example by an etching and / or a chemical-mechanical planarization or grinding operation (far right section of Fig. 11). In particular, in Fig. 11 the second insulating layer 904 is formed to have a getter material with a getter concentration profile as in Fig. 6 shown. Although Fig. Figure 6 shows an exemplary doping concentration profile; alternatively, other exemplary doping concentrations, such as those shown in Figure 6, can be used. Fig. 2A-2I depicted and / or described in Fig. 6 can be used.

[0023] Thus, in each of Fig. 9-11 a handling substrate 104 is received, and a device substrate 108 is also received. At least one of the handling substrate 104 and the device substrate 108 has an insulating layer, such as the upper insulating region 106u, for example in the form of an oxide, on one of its surfaces, wherein the oxide layer contains metal contaminants. For example, the handling substrate 104 may have a first insulating layer 902 and / or the device substrate 108 may have a second insulating layer 904, wherein the first and / or second insulating layer 902 / 904 may contain metal contaminants. The handling substrate 104 is bonded to the device substrate 108 such that the oxide layer (the upper insulating region 106u) separates the handling substrate 104 from the device substrate 108.Before the handling substrate 104 is bonded to the device substrate 108, the insulating layer (902 or 904) undergoes a gettering process in which a halogen species is introduced into the insulating layer to getter away the metal contaminants. For example, the gettering process can be used during the initial formation of the first insulating layer 902 and / or second insulating layer 904, or it can be used as a cleaning / purification process applied to the first insulating layer 902 and / or second insulating layer 904 after these layers have been formed.

[0024] In some embodiments, the gettering process comprises exposing the first insulating layer 902 and / or the second insulating layer 904 to an atmosphere that has been exposed for 0.5 hours to 27 hours to a temperature in the range between 950 °C and 1150 °C, wherein the atmosphere contains trans-1,2-dichloroethylene, nitrogen and oxygen.

[0025] In some embodiments, after the gettering process, the first insulating layer 902 and / or the second insulating layer 904 have a chlorine concentration profile with a first peak chlorine concentration in the range of 5 x 10 18 atoms / cm² 3 up to 2 x 10 21 atoms / cm² 3 on an outer surface area of ​​the insulating layer. The first insulating layer 902 and / or the second insulating layer 904 also have a minimum chlorine concentration lower than the first peak chlorine concentration in an inner area of ​​the first insulating layer 902 and / or the second insulating layer 904.

[0026] In some embodiments, the gettering process exposes the first insulating layer 902 and / or the second insulating layer 904 to a first atmosphere, which is heated to a first temperature in the range of 700 °C to 950 °C for 5 to 30 minutes with an HCl gas flow rate between 0.1 standard liters per minute (slm) and 10 slm, an oxygen gas flow rate between 0.5 slm and 20 slm, and a nitrogen gas flow rate between 1.0 slm and 30 slm. In other embodiments, the first temperature can be increased and range from 950 °C to 1100 °C. After the first insulating layer 902 and / or second insulating layer 904 have been exposed to the first atmosphere, the first insulating layer 902 and / or second insulating layer 904 are exposed to a second atmosphere which is heated to a temperature in the range of 950 °C and 1100 °C for between 0.5 hours and 24 hours, the second atmosphere containing hydrogen, nitrogen and oxygen.In some embodiments, after the gettering process, the first insulating layer 902 and / or the second insulating layer 904 have a chlorine concentration profile at an outer surface area of ​​the first insulating layer 902 and / or the second insulating layer 904, with a first peak chlorine concentration in the range of 5 x 10. 18 atoms / cm² 3 up to 2 x 10 21 atoms / cm² 3 and in an interior area of ​​the insulating layer, a minimum chlorine concentration is lower than the first peak chlorine concentration.

[0027] In some embodiments, the gettering process exposes the first insulating layer 902 and / or the second insulating layer 904 to a first atmosphere heated to a temperature of approximately 400 °C for 5 to 30 minutes, the first atmosphere containing fluorine gas. After exposure to the first atmosphere, the first insulating layer 902 and / or the second insulating layer 904 are exposed to a second atmosphere heated to a temperature between 950 °C and 1100 °C for 0.5 to 24 hours, the second atmosphere containing hydrogen, nitrogen, and oxygen. In some embodiments, after the gettering process, the first insulating layer 902 and / or the second insulating layer 904 have a fluorine concentration profile with a first peak fluorine concentration in the range of 1 x 10 18 atoms / cm² 3 up to 1 x 10 20 atoms / cm² 3on an outer surface area of ​​the first insulating layer 902 and / or second insulating layer 904 and a minimum chlorine concentration smaller than the first peak fluorine concentration in an inner area of ​​the first insulating layer 902 and / or second insulating layer 904.

[0028] The SOI substrates that are in Fig. The SOI substrates illustrated in Figures 1, 2A-2I, and 3-6 can be used in various contexts. For example, the SOI substrates can be used with high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, and other devices. The high-voltage devices can be, for example, devices that operate at voltages greater than approximately 100 volts. In some embodiments, the SOI substrate 102 has a circular top layout and / or a diameter of approximately 200, 300, or 450 millimeters. In other embodiments, the SOI substrate 102 has a different shape and / or different dimensions. Furthermore, in some embodiments, the SOI substrate 102 is a semiconductor wafer. The handling substrate 104 can be, for example, monocrystalline silicon, another silicon material, another semiconductor material, or any combination of the aforementioned.

[0029] In some embodiments, the handling substrate 104 has a high resistance and / or a low oxygen concentration. The high resistance can be, for example, greater than about 1, 3, 4, or 9 kiloohms per centimeter (kΩ / cm) and / or can be, for example, about 1–4 kΩ / cm, about 4–9 kΩ / cm, or about 1–9 kΩ / cm. The low oxygen concentration can be, for example, less than about 1, 2, or 5 parts per million (ppm) and / or can be, for example, between about 0.1–2.5 ppmm, about 2.5–5.0 ppmm, or about 0.1–5.0 ppmm. The low oxygen concentration and the high resistance individually reduce substrate and / or radio frequency (RF) loss. In some embodiments, the handling substrate 104 has a low resistance. The low resistance reduces the cost of the handling substrate 104, but can lead to increased substrate and / or RF losses.The low resistance can be, for example, less than about 8, 10, or 12 Ω / cm and / or can be, for example, between about 8–12 Ω / cm, about 8–10 Ω / cm, or about 10–12 Ω / cm. In some embodiments, the handling substrate 104 is doped with p- or n-type dopants. The resistance of the handling substrate 104 can be controlled, for example, by the doping concentration of the handling substrate 104. For example, increasing the doping concentration can decrease resistance, while decreasing the doping concentration can increase resistance, or vice versa. In some embodiments, a thickness T is... hs of the handling substrate 104 approximately 720-780 micrometers, approximately 720-750 micrometers or approximately 750-780 micrometers.

[0030] The insulating layer 106 lies above the handling substrate 104 and can be, for example, silicon dioxide, silicon-rich oxide (SRO), another oxide, another dielectric, or any combination thereof. In some embodiments, the insulating layer 106 completely covers an upper surface 104us of the handling substrate 104. In some embodiments, the insulating layer 106 completely encloses the handling substrate 104. The insulating layer 106 has a first insulating thickness T1 on an upper surface of the handling substrate 104, between the device layer 108 and the handling substrate 104. The first insulating thickness T1 is sufficient to provide a high degree of electrical insulation between the handling substrate 104 and the device layer 108.The high degree of electrical insulation can, for example, enable a reduced leakage current between devices (not shown) on the device layer 108 and / or can, for example, increase the performance of the devices. In some embodiments, the first insulator thickness T1 is approximately 0.2–2.5 micrometers, approximately 0.2–1.35 micrometers, or approximately 1.35–2.5 micrometers and / or is greater than approximately 1 or 2 micrometers. In some embodiments, the insulating layer 106 has a second insulator thickness T2 at a base of the handling substrate 104 and / or along side walls of the handling substrate 104. In some embodiments, the second insulator thickness T2 is less than the first insulator thickness T1. In some embodiments, the second insulator thickness T2 is approximately 20-6000 Ångström, approximately 20-3010 Ångström or approximately 3010-6000 Ångström.

[0031] In some embodiments, such as in Fig. 1 or Fig. 3, the insulating layer 106 has stepped profiles at SOI edge sections 102e of the SOI substrate 102, each located on opposite sides of the SOI substrate 102. In some embodiments, the insulating layer 106 has upper surfaces located at the SOI edge sections 102e and recessed below a cover surface of the insulating layer 106 by a vertical recess VR. i are recessed. The vertical recession extent VR i For example, it can be approximately 20-6000 angstroms, approximately 20-3010 angstroms, or approximately 3010-6000 angstroms. In some embodiments, the sum of the vertical recess dimensions VR is iand the second insulator thickness T2 is equal to or approximately equal to the first insulator thickness T1. In some embodiments, the insulating layer 106 has first outer sidewalls located at the inner edge of the SOI edge section 102e and separated laterally from the second outer sidewalls at an outer edge of the insulating layer 106 by an insulator-side lateral recess LR i are recessed. The insulator-side recession dimension LR i It could be, for example, approximately 0.8-1.2 millimeters, approximately 0.8-1.0 millimeters, or approximately 1.0-1.2 millimeters.

[0032] The fixture layer 108 lies above the insulating layer 106 and can be, for example, monocrystalline silicon, another silicon material, another semiconductor material, or any combination thereof. In some embodiments, the fixture layer 108 and the handling substrate 104 are the same semiconductor material (e.g., monocrystalline silicon). The fixture layer 108 has a thickness T d , which is large. The large thickness of the device layer 108 can, for example, enable the formation of large semiconductor junctions (e.g., PN junctions), on which certain devices (e.g., NIR image sensors) may depend. In some embodiments, the thickness T dThe device layer 108 is large in that it is larger than approximately 0.2, 0.3, 1.0, 5.0, or 8.0 micrometers and / or that it is approximately 0.2–8.0 micrometers, approximately 0.2–4.0 micrometers, or approximately 4.0–8.0 micrometers. In some embodiments, the device layer 108 has sidewalls that lie at the SOI edge section 102e and that are each laterally separated from sidewalls of the handling substrate 104 by a device-side recess dimension LR. d are recessed. The device-side recession dimension LR d For example, it can be approximately 1.4–2.5 millimeters, approximately 1.4–1.9 millimeters, or approximately 1.9–2.5 millimeters. Furthermore, the device-side recess dimension LR can be... d for example, greater than or equal to the insulator-side recess dimension LR i be.

[0033] With reference to Fig. Figure 7 is a top view of 700 of some embodiments of the SOI substrate 102 of Fig. 1. The SOI substrate 102 is circular and has several IC dies 702 arranged in a grid over the device layer 108. For the sake of clarity, only some of the IC dies 702 are labeled 702. In some embodiments, the diameter D of the SOI substrate 102 is approximately 150, 200, 300, or 450 millimeters. In some embodiments, a first outer side wall 106sw1 of the insulating layer 106 is laterally separated from a second outer side wall 106sw2 of the insulating layer 106 by an insulator-side recess dimension LR. i recessed. In some embodiments, a side wall 108sw of the device layer 108 is laterally separated from a side wall 104sw (shown in phantom lines) of the handling substrate 104 by a device-side recess dimension LR d recessed. The insulator-side recession dimension LR iFor example, it can be approximately 0.8–1.2 millimeters, approximately 0.8–1.0 millimeters, or approximately 1.0–1.2 millimeters. The device-side recess dimension LR d can, for example, be larger than the insulator-side recess dimension LR i It may be, for example, approximately 1.4-2.5 millimeters, approximately 1.4-1.9 millimeters, or approximately 1.9-2.5 millimeters.

[0034] With reference to Fig. Figure 8 is a cross-sectional view of some embodiments of a semiconductor structure in accordance with Fig. 7 provided and in which the SOI substrate 102 of Fig. 1. The semiconductor structure features several semiconductor devices 802 spaced laterally above the device layer 108. The semiconductor devices 802 can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), other metal-oxide-semiconductor devices (MOS devices), other insulated-gate field-effect transistors (IGFETs), other semiconductor devices, or any combination thereof. Furthermore, the semiconductor devices 802 can be, for example, high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, other devices, or any combination thereof.

[0035] In some embodiments, the semiconductor devices 802 have corresponding source / drain regions 804, corresponding selectively conductive channels 806, corresponding gate dielectric layers 808, corresponding gate electrodes 810, and corresponding spacers 812. For the sake of simplicity, only some of the source / drain regions 804 are labeled 804, only one of the selectively conductive channels 806 is labeled 806, only one of the gate dielectric layers 808 is labeled 808, only one of the gate electrodes 810 is labeled 810, and only one of the spacers 812 is labeled 812. The source / drain regions 804 and the selectively conductive channels 806 are located in the device layer 108. The source / drain regions 804 are located at the ends of the selectively conductive channels 806, and each of the selectively conductive channels 806 extends from one of the source / drain regions 804 to another of the source / drain regions 804.The source / drain regions 804 have a first doping type and are directly adjacent to sections of the device layer 108, which has a second doping type opposite to the first doping type.

[0036] The gate dielectric layers 808 are each located over the selectively conductive channels 806, and the gate electrodes 810 are each located over the gate dielectric layers 808. The gate dielectric layers 808 can be, for example, silicon oxide and / or another dielectric material, and / or the gate electrodes 810 can be, for example, doped polysilicon, metal, another conductive material, or any combination thereof. The spacers 812 are located over the source / drain regions 804 and line the sidewalls of the gate electrodes 810 and the sidewalls of the gate dielectric layers 808. The spacers 812 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another dielectric, or any combination thereof.

[0037] A backend-of-line interconnect (BEOL) structure 814 covers the SOI substrate 102 and the semiconductor devices 802. The BEOL interconnect structure 814 comprises an interconnect dielectric layer 816, several wires 818, and several vias 820. For the sake of simplicity, only some of the wires 818 and only some of the vias 820 are labeled 820. The interconnect dielectric layer 816 can be, for example, boron phosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicon glass (USG), another low-κ dielectric, silicon oxide, another dielectric, or any combination thereof. As used here, a low k-dielectric can, for example, be or contain a dielectric with a dielectric constant κ less than about 3.9, 3, 2 or 1.

[0038] The wires 818 and the vias 820 are stacked alternately in the interconnect dielectric layer 816 and define conductive paths extending to the semiconductor devices 802. These conductive paths can, for example, electrically couple the semiconductor devices 802 to other devices (e.g., other semiconductor devices), contact pads, or other structures. The wires 818 and the vias 820 can be made of, for example, copper, aluminum-copper, aluminum, tungsten, another metal, or any combination thereof. In some embodiments, the uppermost wires of the wires 818 are thicker than the underlying wires of the wires 8418.

[0039] While Fig. 7 and Fig. 8 in relation to embodiments of the SOI substrate 102 in Fig. As described in 1, it is clear that embodiments of the SOI substrate 102 in Fig. 7-8 alternatively with the SOI substrate characteristics of Fig. 2A-2I and / or Fig. 3-6 can be used.

[0040] With reference to Fig. Figures 12-23 provide a series of cross-sectional views 1200-2300 of some embodiments of a method for forming and using an SOI substrate 102. While the method is described as forming embodiments of the SOI substrate 102 in Fig. As illustrated in Figure 1, the method can alternatively be used in embodiments of the SOI substrate 102 in Fig. 3, Fig. 5 and / or other embodiments of the SOI substrate 102. While furthermore the in Fig. Since the cross-sectional views 12-23 shown in Figures 12-23 are described with reference to a procedure, it is clear that the in Fig. The structures shown in 12-23 are not limited to the procedure and can stand alone, without the procedure.

[0041] As seen in the cross-sectional view 500 of Fig. As illustrated in Figure 12, a handling substrate 104 is provided. In some embodiments, the handling substrate 104 is or contains monocrystalline silicon, another silicon material, another semiconductor material, or any combination thereof. In some embodiments, the handling substrate 104 has a circular top layout and / or a diameter of approximately 200, 300, or 450 millimeters. In other embodiments, the handling substrate 104 has a different shape and / or dimensions. Furthermore, in some embodiments, the handling substrate 104 is a semiconductor wafer. In some embodiments, the handling substrate 104 has a high resistance and / or a low oxygen concentration. The high resistance and the low oxygen concentration individually reduce substrate and / or RF losses.The high resistance can be, for example, greater than approximately 1, 3, 4, or 9 kΩ / cm and / or can be, for example, between approximately 1–4 kΩ / cm, approximately 4–9 kΩ / cm, or approximately 1–9 kΩ / cm. The low oxygen concentration can be, for example, less than approximately 1, 2, or 5 parts per million (ppm) and / or can be, for example, between approximately 0.1–2.5 ppmm, approximately 2.5–5.0 ppmm, or approximately 0.1–5.0 ppmm. In some embodiments, the handling substrate 104 has a low resistance to reduce substrate costs, since a substrate with high resistance can be more expensive than a substrate with low resistance. The low resistance can be, for example, less than approximately 8, 10, or 12 Ω / cm and / or can be, for example, approximately 8–12 Ω / cm, approximately 8–10 Ω / cm, or approximately 10–12 Ω / cm. In some embodiments, the handling substrate 104 is doped with p- or n-type dopants.The resistance of the handling substrate 104 can be controlled, for example, by adjusting the doping concentration of the handling substrate 104. In some embodiments, a thickness T is required. hs of the handling substrate 104 approximately 720-780 micrometers, approximately 720-750 micrometers or approximately 750-780 micrometers.

[0042] As well as through the cross-sectional view 1200 of Fig. As illustrated in Figure 12, a first insulating layer 106a is formed on an upper surface 104us of the handling substrate 104. In some embodiments, the first insulating layer 106a completely covers the upper surface 104us of the handling substrate 104. In at least some embodiments, where the handling substrate 104 has high resistance, complete coverage of the upper surface 104us can, for example, prevent arcing during subsequent plasma processing. In some embodiments, the first insulating layer 106a completely encloses the handling substrate 104. In some embodiments, the first insulating layer 106a is or contains silicon dioxide and / or another dielectric. In some embodiments, a thickness T fi' the first insulating layer 106a approximately 0.2-2.0 micrometers, approximately 0.2-1.1 micrometers or approximately 1.1-2.0 micrometers.

[0043] In some embodiments, a process for forming the first insulating layer 106a comprises depositing the first insulating layer 106a by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), another deposition process, or any combination thereof. For example, the first insulating layer 106a may be deposited by a dry oxidation process using oxygen gas (e.g., O2) or another gas as an oxidizing agent. As another example, the first insulating layer 106a may be deposited by a wet oxidation process using water vapor as an oxidizing agent. In some embodiments, the first insulating layer 106a is formed at temperatures of about 800–1100 degrees Celsius (°C), about 800–950°C, or about 950–1100°C. If the first insulating layer 106a is formed, for example, by thermal oxidation (e.g.,(a wet or dry oxidation process) is formed, the first insulating layer 106a can be formed at these temperatures.

[0044] As seen in the cross-sectional view 1300 of Fig. As illustrated in Figure 13, a sacrificial substrate 1302 is provided. In some embodiments, the sacrificial substrate 1302 is or contains monocrystalline silicon, another silicon material, another semiconductor material, or any combination thereof. In some embodiments, the sacrificial substrate 1302 is doped with p- or n-type dopants and / or has a low resistivity. The low resistivity may be, for example, less than about 0.01 or 0.02 Ω / cm and / or may be, for example, about 0.01–0.2 Ω / cm. In some embodiments, the sacrificial substrate 1302 has a lower resistivity than the handling substrate 104. In some embodiments, the sacrificial substrate 1302 has a circular top layout and / or has a diameter of about 200, 300, or 450 millimeters. In other embodiments, the sacrificial substrate 1302 has a different shape and / or different dimensions.In some embodiments, the sacrificial substrate 1302 is a bulk semiconductor substrate and / or is a semiconductor wafer. In some embodiments, a thickness T is present. ss The thickness of the sacrificial substrate 1302 is approximately 720–780 micrometers, approximately 720–750 micrometers, or approximately 750–780 micrometers. In some embodiments, the thickness T ss of the sacrificial substrate 1302 the same or approximately the same as the thickness T hs of the handling substrate 104.

[0045] Likewise, through the cross-sectional view 13600 of Fig. As illustrated in Figure 13, a device layer 108 is formed on the sacrificial substrate 1302. The device layer 108 has a thickness T. d In some embodiments, the thickness T dapproximately 0.7–10.0 micrometers, approximately 0.7–5.0 micrometers, or approximately 5.0–10.0 micrometers, and / or is larger than approximately 0.7, 5.0, or 10.0 micrometers. In some embodiments, the device layer 108 is or contains monocrystalline silicon, another silicon material, another semiconductor material, or any combination thereof. In some embodiments, the device layer 108 is or contains the same semiconductor material as the sacrificial substrate 1302, has the same doping type as the sacrificial substrate 1302, has a lower doping concentration than the sacrificial substrate 1302, or any combination thereof. For example, the sacrificial substrate 1302 may be or contain P+ monocrystalline silicon, while the device layer 108 may be or contain P- monocrystalline silicon. In some embodiments, the device layer 108 has a low resistance.The low resistance can, for example, be greater than that of the sacrificial substrate 1302. Furthermore, the low resistance can, for example, be less than approximately 8, 10, or 12 Ω / cm and / or can be, for example, approximately 8–12 Ω / cm, approximately 8–10 Ω / cm, or approximately 10–12 Ω / cm. In some embodiments, the device layer 108 has the same doping type, the same doping concentration, the same resistance, or any combination thereof as the handling substrate 104. In some embodiments, a process for forming the device layer 108 comprises molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), another epitaxial process, or any combination thereof.

[0046] As seen in the cross-sectional view 1400 of Fig. As illustrated in Figure 14, the fixture layer 108 and the sacrificial substrate 1302 are structured. The structuring removes edge regions 1304 defined by the fixture layer 108 and the sacrificial substrate 1302. Removing these edge regions 1304 prevents defects from forming during subsequent grinding and / or chemical wet setting. Edge defects tend to concentrate at the edge regions 604 and negatively affect the quality of the fixture layer 108. Furthermore, the structuring forms a rib 1402 at an edge of the sacrificial substrate 1302. The rib 1402 is defined by the sacrificial substrate 1302 and has a pair of rib segments on opposite sides of the sacrificial substrate 1302. In some embodiments, the rib 1402 has an upper layout that extends along an edge of the sacrificial substrate 1302 in an annular path or another closed path.In some embodiments, the strip 1402 has a width W of approximately 0.8–1.2 millimeters, approximately 0.8–1.0 millimeters, or approximately 1.0–1.2 millimeters. In some embodiments, the strip 1402 is recessed below an upper or covering surface of the device layer 108 by a distance of approximately 30–120 micrometers, approximately 30–75 micrometers, or approximately 75–120 micrometers. In some embodiments, the strip 1402 is recessed further below an upper or covering surface of the sacrificial substrate 1302.

[0047] In some embodiments, the structuring is performed by a photolithography / etching process or another structuring process. Furthermore, in some embodiments, the structuring comprises forming a mask 1404 over the device layer 108, performing an etch into the device layer 108 and the sacrificial substrate 1302 with the mask 1404 in place, and removing the mask 1404. The mask 1404 can, for example, be formed such that the device layer 108 and the sacrificial substrate 1302 are completely covered, except at the edge regions 1304. In some embodiments, the mask 1404 is or contains silicon nitride, silicon oxide, another hard mask material, photoresist, another mask material, or any combination thereof. In some embodiments, the mask 1404 is formed using a wafer edge exposure (WEE) process tool.For example, a process for forming the mask 1404 may include: depositing a photoresist layer on the device layer 108; selectively exposing an edge section of the photoresist layer with radiation using the WEE process tool; and developing the photoresist layer to form the mask 1404.

[0048] As seen in the cross-sectional view 1500 of Fig. As illustrated in Figure 15, the device layer 108 and the sacrificial substrate 1302 are cleaned to remove etch residues and / or other unwanted byproducts produced during preceding processes. In some embodiments, the cleaning process scrubs the device layer 108 and the sacrificial substrate 1302 using a physical brush or a water jet. In other embodiments, the cleaning process cleans the device layer 108 and the sacrificial substrate 1302 using a chemical solution. The chemical solution may be, for example, hydrofluoric acid or another chemical solution. In some embodiments, the cleaning increases the distance D to which the bar 1402 is recessed below the top or cover surface of the device layer 108.

[0049] As seen in the cross-sectional view 1600 of Fig. As illustrated in Figure 16, a second insulating layer 106b is formed on an upper surface 108us of the device layer 108. In some embodiments, the second insulating layer 106b completely covers the upper surface 108us of the device layer 108. In some embodiments, the second insulating layer 106b completely encloses the sacrificial substrate 1302 and the device layer 108. In some embodiments, the second insulating layer 106b is or contains silicon dioxide and / or another dielectric. In some embodiments, the second insulating layer 106b is the same dielectric material as the first insulating layer 106a. In some embodiments, a thickness T si' the second insulating layer 106b approximately 20-6000 Ångström, approximately 20-3010 Ångström or approximately 3010-6000 Ångström.

[0050] In some embodiments, a process for forming the second insulating layer 106b comprises depositing the second insulating layer 106b by thermal oxidation, CVD, PVD, another deposition process, or any combination thereof. For example, the second insulating layer 106b can be deposited by a dry oxidation process using oxygen gas (e.g., O2) or another gas as an oxidizing agent. As another example, the second insulating layer 106b can be deposited by a wet oxidation process using steam as an oxidizing agent. In some embodiments, the second insulating layer 106b is formed at temperatures of about 750–1100°C, about 750–925°C, or about 925–1100°C. For example, if the second insulating layer 106b is formed by thermal oxidation (e.g., a wet or dry oxidation process), the second insulating layer 106b can be formed at these temperatures.In some embodiments, the second insulating layer 106b is formed at a lower temperature than that of the first insulating layer 106a.

[0051] As seen in the cross-sectional view 1700 of Fig. As illustrated in Figure 17, the sacrificial substrate 1302 is bonded to the handling substrate 104, such that the device layer 108, the first insulating layer 106a, and the second insulating layer 106b are located between the handling substrate 104 and the sacrificial substrate 1302. Bonding presses the first and second insulating layers 106a and 106b together, forming a bond 1702 at an interface where the first insulating layer 106a and the second insulating layer 106b are in direct contact. Bonding can be performed, for example, by fusion bonding, vacuum bonding, or another bonding process. Fusion bonding can be performed, for example, at a pressure of approximately 1 standard atmosphere (atm), approximately 0.5–1.0 atm, approximately 1.0–1.5 atm, or approximately 0.5–1.5 atm. Vacuum bonding can be performed, for example, at a pressure of approximately 0.5-100 millibar (mbar), approximately 0.5-50 mbar or approximately 50-100 mbar.

[0052] In some embodiments, bond annealing is performed to strengthen bond 1702. In some embodiments, the bond annealing is performed at a temperature of approximately 300–1150°C, approximately 300–725°C, or approximately 735–1150°C. In some embodiments, the bond annealing is performed for approximately 2–5 hours, approximately 2–3.5 hours, or approximately 3.5–5 hours. In some embodiments, the bond annealing is performed at a pressure of approximately 1 atm, approximately 0.5–1.0 atm, approximately 1.0–1.5 atm, or approximately 0.5–1.5 atm. In some embodiments, the bond annealing is performed while nitrogen gas (e.g., N2) and / or another gas is passed over the structure of Fig. 17. The flow rate for the gas can be, for example, about 1-20 standard liters per minute (slm), about 1-10 slm, or about 10-20 slm.

[0053] As seen in the cross-sectional view 1800 of Fig. As illustrated in Figure 18, a first thinning process is carried out in the second insulating layer 106b and the sacrificial substrate 1302. The first thinning process removes an upper section of the second insulating layer 106b and further removes an upper section of the sacrificial substrate 1302. In some embodiments, the first thinning process is carried out in the second insulating layer 106b and the sacrificial substrate 1302 until the apparatus layer 108 and the sacrificial substrate 1302 together have a predetermined thickness T. pd have the predetermined thickness T pd It could be, for example, approximately 20-45 micrometers, approximately 20-32.5 micrometers, or approximately 32.5-45 micrometers.

[0054] In some embodiments, the first thinning process is carried out partially or completely by mechanical grinding. In some embodiments, the first thinning process is carried out partially or completely by chemical-mechanical polishing (CMP). In some embodiments, the first thinning process is carried out by a mechanical grinding process followed by CMP. As noted above, removing the edge region prevents the formation of edge defects at edge region 1304 during grinding. The edge defects tend to form and concentrate at edge region 604 during grinding and negatively affect the quality of the device layer 108.

[0055] As seen in the cross-sectional view from 1900 Fig. As illustrated in Figure 19, an etching process is carried out into the sacrificial substrate 1302. The etching stops at the device layer 108 and removes the sacrificial substrate 1302. In some embodiments, the etching further removes a section of the second insulating layer 106b on the side walls of the sacrificial substrate 1302 and the side walls of the device layer 108. Furthermore, in some embodiments, the etching laterally etches side walls 108sw of the device layer 108. Due to the lateral etching, the side walls 108sw of the device layer 108 can, for example, be curved and / or concave. After completion of the etching, the thickness T d The thickness of the device layer 108, for example, may be approximately 0.6–9.5 micrometers, approximately 0.6–5.05 micrometers, or approximately 5.05–9.5 micrometers. In some embodiments, the etching reduces the thickness T. d the device layer 108 due to, for example, over-etching is minimal.

[0056] In some embodiments, the etching is performed by a hydrogen fluoride / nitric acid / acetic acid (HNA) etching, another wet etching, a dry etching, or some other etching process. The HNA etching, for example, can etch the sacrificial substrate 1302 with a chemical solution containing hydrogen fluoride, nitric acid, and acetic acid. The etching has a first etch rate for material of the sacrificial substrate 1302 and a second etch rate for material of the device layer 108, which is lower than the first etch rate. In some embodiments, the first etch rate is approximately 90–100, 90–95, or 95–100 times higher than the second etch rate. These embodiments of the first and second etch rate can arise, for example, when the first etching is carried out by HNA etching, the sacrificial substrate 1302 P+ is or contains monocrystalline silicon, and the device layer 108 P- is or contains monocrystalline silicon.

[0057] Due to the use of etching (e.g., HNA etching) to remove the sacrificial substrate 1302, the removal of the sacrificial substrate 1302 can be, for example, highly controlled. Therefore, the thickness T can be d The device layer 108, for example, can be extremely uniform across the device layer, and the total thickness variation (TTV) of the device layer 108 can be, for example, small. The TTV can be lower, for example, by being less than about 500 or 1500 angstroms. In some embodiments, the TTV decreases with thickness T. d the device layer 108. For example, the TTV can be less than about 500 angstroms if the thickness T d the device layer 108 is smaller than about 3000 angstroms, and the TTV can be larger than about 500 angstroms but smaller than about 1500 angstroms if the thickness T d The device layer 108 has a temperature of more than approximately 3000 Ångströms.

[0058] As seen in the cross-sectional view 2000 of Fig. As illustrated in Figure 20, the device layer 108 is structured. The structuring removes edge sections 108e of the device layer 108. By removing the edge sections 108e, edge defects that form at the edge sections 108e during etching are eliminated. These edge defects reduce the quality of the device layer 108 and form due to lateral etching into the side walls 108sw of the device layer 108 during etching. The structuring further deepens the side walls 108sw of the device layer 108 laterally. In some embodiments, after removal of the edge sections 108e, the side walls 108sw of the device layer 108 are laterally recessed by side walls of the handling substrate 104 by a device-side recession dimension LR. d recessed. The device-side recession dimension LR dIt could be, for example, approximately 1.4-2.5 millimeters, approximately 1.4-1.95 millimeters, or approximately 1.95-2.5 millimeters.

[0059] In some embodiments, the structuring is formed by a photolithography / etching process or another structuring process. Furthermore, in some embodiments, the structuring comprises forming a mask 2002 over the device layer 108, performing an etch into the device layer 108 with the mask 2002 in place, and removing the mask 2002. The mask 2002 may, for example, be or contain silicon nitride, silicon oxide, another hard mask material, photoresist, another mask material, or any combination thereof. The mask 2002 may, for example, be formed such that the device layer 108 is completely covered except at the edge sections 108e, and / or may, for example, be formed using a wafer edge exposure process tool (WEE process tool).In some embodiments, a process for forming the mask 2002 using the WEE process tool comprises: depositing a photoresist layer onto the fixture layer 108; selectively exposing an edge portion of the photoresist layer to radiation using the WEE process tool; and developing the photoresist layer to form the mask 2002. The etching can be performed, for example, by dry etching or another type of etching and / or can stop, for example, on the first and second insulating layers 106a, 106b. In some embodiments, where the handling substrate 104 has a high resistance (e.g., a resistance greater than about 1 kΩ / cm) and the etching is performed using dry etching, the first and second insulating layers 106a, 106b prevent arcing by completely covering and / or completely enclosing the handling substrate 104.The 2002 mask can be removed, for example, by plasma ashing or other removal methods. Plasma ashing can, for example, involve exposing the 2002 mask to O2 plasma and can be performed, for example, if the 2002 mask is or contains photoresist.

[0060] In some embodiments, a cleaning process is performed after structuring to remove etch residues and / or other unwanted byproducts generated during structuring. In some embodiments, the cleaning process removes oxide that forms on the device layer 108 during structuring. The cleaning process may, for example, involve cleaning using hydrofluoric acid (HF acid) or another chemical solution. Hydrofluoric acid may, for example, constitute approximately 0.1–2.0%, approximately 0.1–1.0%, or approximately 1.0–2.0% of the HF acid by volume. The remainder of the HF acid may, for example, be deionized water or another type of water.

[0061] As shown in the cross-sectional view 2100 of Fig. As illustrated in Figure 21, a second thinning process is carried out in the device layer 108 to reduce the thickness T. dto reduce the thickness of the device layer 108. In some embodiments, the second thinning process reduces the thickness T. d to approximately 0.3–8.0 micrometers, approximately 0.3–4.15 micrometers, or approximately 4.15–8.0 micrometers, and / or to more than approximately 0.3, 1.0, 2.0, 5.0, or 8.0 micrometers. Together, the device layer 108, the first insulating layer 106a, the second insulating layer 106b, and the handling substrate 104 define an SOI substrate 102. In some embodiments, the second thinning process is carried out by CMP, another thinning process, or any combination thereof.

[0062] Since the device layer 108 is formed by epitaxy and transferred to the handling substrate 104, the device layer 108 can be formed with a large thickness (e.g., a thickness greater than approximately 0.3 micrometers). Epitaxy is not subject to the thickness limitations associated with other methods for forming the device layer. Furthermore, since epitaxy is not affected by the thickness of the first and second insulating layers 106a, 106b, the first and second insulating layers 106a can be formed individually and / or together with a large thickness (e.g., a thickness greater than approximately 1 micrometer). The large thickness of the device layer 108 can, for example, enable the formation of large semiconductor junctions (e.g., PN junctions), upon which certain devices (e.g., NIR image sensors) may depend.The increased thickness of the first and second insulating layers 106a can, for example, facilitate enhanced electrical insulation between devices on the device layer 108 and / or reduce leakage current between the devices. Devices that can benefit from the increased thickness include, for example, high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, other devices, or any combination thereof.

[0063] As through the cross-section 2200 of Fig.As illustrated in Figure 22, several semiconductor devices 802 are formed on the device layer 108. In some embodiments, where the handling substrate 104 has a high resistance (e.g., a resistance greater than about 1 kΩ / cm), the first and second insulating layers 106a, 106b prevent arcing during plasma processing (e.g., plasma etching), which is carried out by completely covering and / or completely enclosing the handling substrate 104 to form the semiconductor devices 802. The semiconductor devices 802 can be, for example, high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, other devices, or any combination thereof. The high-voltage devices can, for example, be devices that operate at more than about 100 volts.

[0064] In some embodiments, the semiconductor devices 802 have corresponding source / drain regions 804, corresponding selectively conductive channels 806, corresponding gate dielectric layers 808, corresponding gate electrodes 810, and corresponding spacers 812. For the sake of simplicity, only some of the source / drain regions 804 are labeled 804, only one of the selectively conductive channels 806 is labeled 806, only one of the gate dielectric layers 808 is labeled 808, only one of the gate electrodes 810 is labeled 810, and only one of the spacers 812 is labeled 812. The source / drain regions 804 and the selectively conductive channels 806 are located in the device layer 108. The source / drain regions 804 are located at the ends of the selectively conductive channels 806, and each of the selectively conductive channels 806 extends from one of the source / drain regions 804 to another of the source / drain regions 804.The gate dielectric layers 808 are each located over the selectively conductive channels 806, and the gate electrodes 810 are each located over the gate dielectric layers 808. The spacers 812 are located over the source / drain regions 804 and each line the side walls of the gate electrodes 810.

[0065] In some embodiments, a process for forming the semiconductor devices 802 comprises depositing a dielectric layer covering the device layer 108 and further depositing a conductive layer covering the dielectric layer. The conductive layer and the dielectric layer are structured into the gate electrodes 810 and the gate dielectric layers 808 (e.g., by a photolithography / etching process). Dopants are implanted in place into the device layer 108 with the gate electrodes 810 to define lightly doped sections of the source / drain regions 804, and a spacer layer is formed covering the source / drain regions 804 and the gate electrodes 810. The spacer layer is etched back to form the spacers 812, and dopants are implanted into the fixture layer 108 with the spacers 812 in place to extend the source / drain regions 804.

[0066] Thus, some embodiments of the present disclosure relate to a semiconductor-on-insulator (SOI) substrate comprising a handling substrate, a fixture layer above the handling substrate, and an insulating layer separating the handling substrate from the fixture layer. The insulating layer interacts with the fixture layer at a first interface and with the handling substrate at a second interface. The insulating layer comprises a getter material with a getter concentration profile. The getter concentration profile has a first peak concentration at the first interface, a second peak concentration at the second interface, and a trough concentration at a location between the first and second interfaces. The trough concentration is lower than both the first and second peak concentrations.

[0067] Other embodiments relate to a method for forming a semiconductor-on-insulator (SOI) substrate. In the method, a handling substrate is received. A device substrate is also received, wherein at least one of the handling substrate and the device substrate has an oxide layer on one face. The oxide layer contains metal contaminants. The handling substrate is bonded to the device substrate such that the oxide layer separates the handling substrate from the device substrate. Before the handling substrate is bonded to the device substrate, the oxide layer is subjected to a gettering process in which a halogen species is provided in the oxide layer to getter away the metal contaminants.

[0068] Further embodiments relating to an integrated circuit comprise a handling substrate, an insulating layer arranged above the handling substrate, and a device layer containing monocrystalline silicon arranged above the insulating layer. One or more semiconductor devices are arranged in or above the device layer, and an interconnect structure is arranged above the device layer. The interconnect structure couples the one or more semiconductor devices to each other in an operational manner. The insulating layer separates the handling substrate from the device layer, and the insulating layer includes a getter material embedded in insulating material within the insulating layer.

Claims

[1] Semiconductor-on-insulator substrate, SOI substrate, comprising: a handling substrate (104); a device layer (108) that lies above the handling substrate (104); and an insulating layer (106) separating the handling substrate (104) from the device layer (108), wherein the insulating layer (106) meets the device layer (108) at a first interface and meets the handling substrate (104) at a second interface, wherein the insulating layer (106) has a getter material with a getter concentration profile, the getter concentration profile having a first peak concentration at the first interface, a second peak concentration at the second interface and a trough concentration at a location between the first interface and the second interface, wherein the trough concentration is smaller than each of the first peak concentration and the second peak concentration, the getter material contains fluorine. [2] SOI substrate according to claim 1: wherein the device layer (108) is arranged above an upper surface of the handling substrate (104); and wherein the insulating layer (106) covers the upper surface of the handling substrate (104) to separate the upper surface of the handling substrate (104) from the device layer (108), covers a lower surface of the handling substrate (104) and covers side walls of the handling substrate (104). [3] SOI substrate according to claim 2, wherein the second interface corresponds to a point where the upper surface of the handling substrate (104) meets the insulating layer (106) and the first peak concentration is lower than the second peak concentration. [4] SOI substrate according to claim 2, wherein the second interface corresponds to a point where the upper surface of the handling substrate (104) meets the insulating layer (106) and the first peak concentration is equal to the second peak concentration. [5] SOI substrate according to claim 4, wherein the getter material is present in the device layer (108) at a first concentration and is present in the handling substrate (104) at a second concentration, the first concentration being lower than the second concentration. [6] SOI substrate according to any one of claims 1 to 2 and 4 to 5 above, wherein the first peak concentration is equal to the second peak concentration. [7] SOI substrate according to any one of claims 1 to 3 or 5 above, wherein the first peak concentration is lower than the second peak concentration. [8] SOI substrate according to claim 7, wherein the insulating layer (106) is limited between the device layer (108) and the handling substrate (104), such that a bottom surface of the insulating layer corresponds to a top surface of the handling substrate (104) and a top surface of the insulating layer (106) corresponds to a bottom surface of the device layer (108). [9] SOI substrate according to any of the preceding claims, wherein the first peak concentration and the second peak concentration are each at least 1 x 10 18 atoms / cm² 3 of chlorine or fluorine and the trough level concentration of 1 x 10 14 atoms / cm² 3 up to 2 x 10 17 atoms / cm² 3 suffices. [10] Method for forming a semiconductor-on-insulator substrate, SOI substrate, the method comprising: Receiving a handling substrate (104); Receiving a device substrate (108) and an oxide layer (106), wherein the oxide layer (106) is arranged on a surface of at least one of the handling substrate (104) and the device substrate (108), wherein the oxide layer (106) contains metal contaminants; Bonding of the handling substrate (104) to the device substrate (108) such that the oxide layer (106) separates the handling substrate (104) from the device substrate (108); and wherein, prior to bonding the handling substrate (104) to the device substrate (108), the oxide layer (106) is subjected to a gettering process in which a halogen species is provided in the oxide layer (106) to getter away the metal contaminants, the gettering process includes: Exposure of the oxide layer for 5 minutes to 30 minutes to a first atmosphere heated to a first temperature of approximately 400 °C, the first atmosphere containing fluorine gas; and After the oxide layer (106) has been exposed to the first atmosphere, the oxide layer (106) is exposed for 0.5 hours to 24 hours to a second atmosphere heated to a temperature in the range of 950 °C to 1100 °C, the second atmosphere containing hydrogen, nitrogen and oxygen. [11] Method according to claim 10, wherein the gettering process comprises: Exposure of the oxide layer (106) for 0.5 hours to 27 hours to an atmosphere heated to a temperature in the range of 950 °C to 1150 °C, wherein the atmosphere contains trans-1,2-dichloroethylene, nitrogen and oxygen. [12] Method according to one of the preceding claims 10 or 11, wherein the oxide layer (106) after the gettering process has a fluorine concentration profile with a first peak fluorine concentration in the range of 1 x 10 18 atoms / cm² 3 up to 1 x 10 20 atoms / cm² 3at an outer surface region of the oxide layer (106) and has a minimum chlorine concentration smaller than the first peak fluorine concentration in an inner region of the oxide layer (106). [13] Integrated circuit comprising: a handling substrate (104); an insulating layer (106) arranged above the handling substrate (104); a device layer (108) containing monocrystalline silicon arranged above the insulating layer (106), wherein one or more semiconductor devices are arranged in or above the device layer (108); and an interconnect structure arranged above the device layer (108), wherein the interconnect structure couples the one or more semiconductor devices to each other in an operational manner; and wherein the insulating layer (106) separates the handling substrate (104) from the device layer (108) and wherein the insulating layer (106) comprises a getter material embedded in insulating material of the insulating layer (106), wherein the insulating layer (106) meets the device layer (108) at a first interface and meets the handling substrate (104) at a second interface, wherein the getter material has a getter concentration profile, the getter concentration profile having a first peak concentration at the first interface, a second peak concentration at the second interface and a trough concentration at a location between the first interface and the second interface, wherein the trough concentration is smaller than either the first peak concentration or the second peak concentration, the getter material contains fluorine. [14] Integrated circuit according to claim 13, wherein the insulating material comprises an oxide. [15] Integrated circuit according to claim 13 or 14, wherein the getter material has a concentration in the range of 1 x 10 14 atoms / cm² 3 up to 1 x 10 20 atoms / cm² 3 has.

Images