An SOI substrate-based LDMOS device, a manufacturing method thereof and application
By introducing a conductive channel for the drain on the SOI substrate, the heat dissipation and capacitance problems of LDMOS devices are solved, realizing the design of LDMOS devices with high heat dissipation and low capacitance, which is suitable for RF chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU WATECH ELECTRONICS CO LTD
- Filing Date
- 2021-08-03
- Publication Date
- 2026-05-22
AI Technical Summary
Existing LDMOS devices on SOI substrates suffer from large PN junction capacitance and limited heat dissipation. In addition, the drain being led out from the front of the substrate increases the complexity of circuit design and parasitic capacitance.
By leading out a conductive channel for the drain on the SOI substrate, the drain is brought out from below the substrate, forming a conductive channel and connecting it with the metal layer, reducing the junction capacitance of the drift region and providing a heat dissipation path.
It improves the heat dissipation performance of the device, reduces parasitic capacitance, meets the application requirements of having the drain at the bottom in the circuit, and simplifies the circuit design.
Smart Images
Figure CN115706162B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor devices, specifically relating to an LDMOS device based on an SOI substrate, its fabrication method, and its application. Background Technology
[0002] Existing LDMOS devices have a large PN junction capacitance in the drift region, which limits the efficiency of LDMOS. SOI-based LDMOS devices can reduce the junction capacitance in the drift region and improve the device efficiency. However, the thermal conductivity of the insulating oxide layer of the SOI substrate is only one percent of that of silicon. Therefore, the heat dissipation capability of SOI-based LDMOS devices is limited by the insulating oxide layer.
[0003] Meanwhile, in existing LDMOS devices, the drain is generally led out from the front of the substrate, which limits the application requirements of "draindown" in the circuit and increases the complexity of circuit design. Leading the drain out from the front of the substrate also increases the parasitic capacitance between the drain trace and the source and gate traces, resulting in low efficiency of LDMOS devices. Summary of the Invention
[0004] The main objective of this invention is to provide an LDMOS device based on an SOI substrate, its fabrication method, and its application, in order to overcome the shortcomings of the prior art.
[0005] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:
[0006] This invention provides an LDMOS device, comprising: a support substrate, wherein a polysilicon layer, a first insulating oxide layer, and a top silicon layer are sequentially stacked on the top surface of the support substrate, and a second insulating oxide layer and a metal layer are sequentially stacked on the bottom surface of the support substrate; a body region and a drift region are formed in the top silicon layer; a body region contact region and a source region are formed in the body region; a drain region is formed in the drift region; and a polysilicon gate is also disposed on the top silicon layer; wherein the drain region is electrically connected to the metal layer through a conductive channel, the conductive channel continuously penetrating the second insulating oxide layer, the support substrate, the polysilicon layer, and the first insulating oxide layer along the thickness direction of the support substrate, and the conductive channel is electrically isolated from the polysilicon layer and the support substrate through a third insulating oxide layer.
[0007] Furthermore, the conductive channel includes a conductive material filled in a conductive via, which continuously penetrates the second insulating oxide layer, the supporting substrate, the polysilicon layer, and the first insulating oxide layer along the thickness direction of the supporting substrate.
[0008] Furthermore, the conductive material includes tungsten metal.
[0009] Furthermore, the conductive via includes a cylindrical via or a rectangular via.
[0010] Furthermore, the diameter of the cylindrical through hole is greater than 0.2 μm and less than 1 μm.
[0011] Furthermore, the cross-sectional area of the rectangular through hole is greater than 0.2μm*1μm and less than 3μm*20μm.
[0012] Furthermore, the LDMOS device also includes a second metal layer, which is disposed in the upper region of the SOI substrate and electrically connected to the source region and the body region through contact vias.
[0013] Furthermore, the LDMOS device also includes a source field plate, which is disposed in the region above the drift region.
[0014] This invention also provides a method for fabricating the above-mentioned LDMOS device, comprising:
[0015] An SOI substrate is provided, comprising a support substrate, a polysilicon layer, a first insulating oxide layer and a top silicon layer sequentially stacked along a predetermined direction;
[0016] A polysilicon gate is fabricated in a corresponding region on the top silicon layer;
[0017] A body region and a drift region are formed in a corresponding region in the top silicon layer, and a body region contact region and a source region are formed in the body region, and a drain region is formed in the drift region;
[0018] A via is formed in the corresponding region below the drain region, such that the via passes through the support substrate, the polysilicon layer, and the first insulating oxide layer sequentially along the thickness direction of the support substrate, and contacts the drain region.
[0019] The through-holes are filled with insulating oxide and a second insulating oxide layer is formed on the bottom surface of the supporting substrate;
[0020] The insulating oxide is etched to form a conductive via, which sequentially penetrates the second insulating oxide layer, the supporting substrate, the polysilicon layer, and the first insulating oxide layer along the thickness direction of the supporting substrate, and contacts the drain region.
[0021] The conductive vias are filled with a conductive material to form conductive channels;
[0022] A first metal layer is formed on the bottom surface of the second insulating oxide layer, and the first metal layer is electrically connected to the conductive channel.
[0023] Furthermore, the fabrication method further includes: forming a silicide layer above the body region, and electrically connecting the source region and the body region contact region through the silicide layer.
[0024] Furthermore, the manufacturing method also includes:
[0025] A cured oxide layer is formed in the space above the top silicon layer, and contact vias are formed therein;
[0026] A first metal layer is formed on top of the cured oxide layer, and the first metal layer is electrically connected to the silicide layer through the contact via.
[0027] This invention also provides an RF chip, which includes the above-mentioned LDMOS device, wherein the drain of the LDMOS device is disposed below the chip substrate.
[0028] Compared with the prior art, the LDMOS device based on SOI substrate, its fabrication method and application provided by the present invention have at least the following beneficial effects:
[0029] 1) By leading the drain of the LDMOS device out from below the SOI substrate through a conductive channel, a downward heat dissipation path is provided, which improves the heat dissipation performance of the device and thus improves the efficiency of the device.
[0030] 2) Leading the drain of the LDMOS device out from under the SOI substrate can avoid coupling between the drain trace and the source and gate traces, and reduce the parasitic capacitance of the device.
[0031] 3) The drain of the LDMOS device is led out from the bottom of the SOI substrate, which meets the application requirements of the device drain in the circuit and provides convenience for circuit designers.
[0032] 4) The provided SOI substrate utilizes the charge induced in the drift region of the polysilicon layer trap to reduce the junction capacitance of the drift region, thereby reducing the thickness of the insulating oxide layer of the SOI substrate and significantly improving the heat dissipation performance of the SOI substrate. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic cross-sectional view of an LDMOS device based on an SOI substrate according to an embodiment of the present invention;
[0035] Figures 2a to 2hThis is a schematic diagram of the fabrication process of an LDMOS device based on an SOI substrate according to an embodiment of the present invention. Detailed Implementation
[0036] In view of the deficiencies of the prior art, the inventors of this case, through long-term research and extensive practice, have proposed the technical solution of this invention. The technical solution of this invention will be clearly and completely described below. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0037] This invention provides an LDMOS device, such as... Figure 1 As shown, it includes: a support substrate 212, on the top surface of the support substrate 212 a polysilicon layer 211, a first insulating oxide layer 210 and a top silicon layer 222 are stacked in sequence, and on the bottom surface of the support substrate 212 a second insulating oxide layer 213 and a first metal layer 216 are stacked in sequence. The top silicon layer 222 has a body region 25 and a drift region 23. The body region 25 has a body contact region 26 and a source region 22. The drift region 23 has a drain region 24. A polysilicon gate 20 is also disposed on the top silicon layer 222.
[0038] The drain region 24 is electrically connected to the first metal layer 216 through a conductive channel 214. The conductive channel 214 continuously penetrates the second insulating oxide layer 213, the supporting substrate 212, the polysilicon layer 211 and the first insulating oxide layer 210 along the thickness direction of the supporting substrate 212. The conductive channel 214 is electrically isolated from the polysilicon layer 211 and the supporting substrate 212 through a third insulating oxide layer 215.
[0039] Specifically, the thickness of the top silicon layer 222 can be between 0.2 μm and 5 μm, the thickness of the first insulating oxide layer 210 can be between 0.2 μm and 3 μm, the thickness of the polysilicon layer 211 can be between 0.2 μm and 5 μm, and the thicknesses of the second insulating oxide layer 213 and the third insulating oxide layer 215 can be between 0.1 μm and 3 μm.
[0040] Furthermore, the conductive channel 214 includes conductive material filled in the conductive via, which continuously penetrates the second insulating oxide layer 213, the supporting substrate 212, the polysilicon layer 211, and the first insulating oxide layer 210 along the thickness direction of the supporting substrate 212.
[0041] The conductive material can be tungsten metal, and the conductive through-hole can be cylindrical, rectangular, or other shapes, as long as it can achieve the effects of heat dissipation and conductivity.
[0042] Furthermore, the diameter of the cylindrical through hole can be greater than 0.2μm and less than 1μm, and the cross-sectional area of the rectangular through hole can be greater than 0.2μm*1μm and less than 3μm*20μm.
[0043] Furthermore, the LDMOS device also includes a second metal layer 28, which is disposed in the upper region of the SOI substrate and electrically connected to the source region 22 and the body contact region 26 through a contact via 27. A silicide layer 30 is also formed above the source region 22 and the body contact region 26. The silicide layer 30 is used to connect the source region 22 and the body contact region 26. The second metal layer 28 is electrically connected to the silicide layer 30 through the contact via 27, and then electrically connected to the source region 22 and the body contact region 2.
[0044] Furthermore, the LDMOS device also includes a source field plate 29, which is disposed in the region above the drift region 23.
[0045] This invention also provides a method for fabricating the above-mentioned LDMOS device, such as... Figures 2a to 2h As shown, it includes:
[0046] First, an SOI substrate is provided, which includes a support substrate 212, a polysilicon layer 211, a first insulating oxide layer 210 and a top silicon layer 222, which are sequentially stacked along a set direction.
[0047] Subsequently, a polysilicon gate 20 is fabricated in the corresponding region on the top silicon layer 222, wherein the polysilicon gate 20 and the top silicon layer 222 are also covered by a gate oxide layer 21, wherein the gate oxide layer 21 can be made of silicon dioxide and the thickness can be between 0.005μm and 0.5μm.
[0048] Furthermore, by means of ion implantation, a body region 25 and a drift region 23 are formed in the corresponding regions of the top silicon layer 222, and a body contact region 26 and a source region 22 are formed in the body region 25, and a drain region 24 is formed in the drift region 23.
[0049] Furthermore, a silicide layer 30 is formed above the body region 25, and the source region 22 and the body region contact region 26 are electrically connected through the silicide layer 30.
[0050] Furthermore, a cured oxide layer is formed in the space above the top silicon layer 222 and its surface is smoothed, and contact vias 27 are formed. The material forming the cured oxide layer can be silicon dioxide, and the thickness of the cured oxide layer can be between 0.8 μm and 2 μm.
[0051] Furthermore, a first metal layer 28 is formed above the cured oxide layer, and the first metal layer 28 is electrically connected to the silicide layer 30 through the contact via 27, and then electrically connected to the source region 22 and the body region contact region 26.
[0052] Furthermore, a via 223 is formed in the corresponding area below the drain region 24, so that the via 223 passes through the support substrate 212, the polysilicon layer 211, and the first insulating oxide layer 210 in sequence along the thickness direction of the support substrate 212, and contacts the drain region 24.
[0053] Furthermore, the through-hole 223 is filled with insulating oxide, and a second insulating oxide layer 213 is formed on the bottom surface of the support substrate 212.
[0054] Furthermore, the insulating oxide is etched to form a conductive via, and the conductive via sequentially penetrates the second insulating oxide layer 213, the supporting substrate 212, the polysilicon layer 211, and the first insulating oxide layer 210 along the thickness direction of the supporting substrate, and contacts the drain region 24. The remaining insulating oxide in the via 223 forms the third insulating oxide layer 215 around the conductive channel.
[0055] Furthermore, conductive channels 214 are formed by filling conductive vias with conductive materials, wherein the conductive material may be tungsten metal.
[0056] Finally, a first metal layer 216 is formed on the bottom surface of the second insulating oxide layer 213 by chemical vapor deposition, and the first metal layer 216 is electrically connected to the conductive channel, so that the drain in the drain region 24 is led out from below the SOI substrate, thus completing the fabrication of the LDMOS device.
[0057] This invention also provides an RF chip, which includes the above-mentioned LDMOS device, wherein the drain of the LDMOS device is disposed below the chip substrate.
[0058] In summary, the SOI-based LDMOS device structure of this invention connects the drain region and the metal on the back side of the substrate through a conductive channel, forming a "Drain Down" device. This provides a downward-facing heat dissipation path for the drain region, improving heat dissipation capabilities. Simultaneously, the "Drain Down" device structure meets the application requirements of having the drain at the bottom in circuits, providing convenience for circuit designers. Furthermore, leading the drain out from the bottom avoids coupling between the drain, source, and gate traces caused by surface-leading drains, reducing parasitic capacitance.
[0059] In the description of this invention, it should be noted that the terms "middle", "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0060] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0061] It should be understood that the technical solutions of the present invention are not limited to the specific embodiments described above. Any technical modifications made to the technical solutions of the present invention without departing from the spirit and scope of the claims are within the scope of protection of the present invention.
Claims
1. An LDMOS device based on an SOI substrate, characterized in that... The device includes a support substrate. A polysilicon layer, a first insulating oxide layer, and a top silicon layer are sequentially stacked on the top surface of the support substrate. A second insulating oxide layer and a first metal layer are sequentially stacked on the bottom surface of the support substrate. A body region and a drift region are formed in the top silicon layer. A body region contact region and a source region are formed in the body region. A drain region is formed in the drift region. A polysilicon gate is also disposed on the top silicon layer. The drain region is electrically connected to the first metal layer via a conductive channel. The conductive channel continuously penetrates the second insulating oxide layer, the support substrate, the polysilicon layer, and the first insulating oxide layer along the thickness direction of the support substrate. Furthermore, the conductive channel is electrically isolated from the polysilicon layer and the support substrate via a third insulating oxide layer. The conductive channel includes a conductive material filled in a conductive via; the conductive via continuously penetrates the second insulating oxide layer, the supporting substrate, the polysilicon layer, and the first insulating oxide layer along the thickness direction of the supporting substrate. The conductive via includes a cylindrical via with a diameter greater than 0.2 μm and less than 1 μm; or, the conductive via includes a rectangular via with a cross-sectional area greater than 0.2 μm × 1 μm and less than 3 μm × 20 μm. The thickness of the first insulating oxide layer is between 0.2 μm and 3 μm; The thickness of the second insulating oxide layer is between 0.1 μm and 3 μm.
2. The LDMOS device according to claim 1, characterized in that, The conductive material includes tungsten metal.
3. The LDMOS device according to claim 1, characterized in that... It also includes a second metal layer, which is disposed in the upper region of the SOI substrate and electrically connected to the contact region of the body region through a contact via.
4. The LDMOS device according to claim 1, characterized in that... It also includes a source field plate, which is disposed in the area above the drift region.
5. A method for fabricating an LDMOS device according to any one of claims 1-4, characterized in that... include: An SOI substrate is provided, comprising a support substrate, a polysilicon layer, a first insulating oxide layer and a top silicon layer sequentially stacked along a predetermined direction; The thickness of the first insulating oxide layer is between 0.2 μm and 3 μm; A polysilicon gate is fabricated in a corresponding region on the top silicon layer; A body region and a drift region are formed in a corresponding region in the top silicon layer, and a body region contact region and a source region are formed in the body region, and a drain region is formed in the drift region; A via is formed in the corresponding region below the drain region, such that the via passes through the support substrate, the polysilicon layer, and the first insulating oxide layer sequentially along the thickness direction of the support substrate, and contacts the drain region. The through-holes are filled with an insulating oxide and a second insulating oxide layer is formed on the bottom surface of the supporting substrate; the thickness of the second insulating oxide layer is between 0.1 μm and 3 μm. The insulating oxide is etched to form conductive vias, which sequentially penetrate the second insulating oxide layer, the supporting substrate, the polysilicon layer, and the first insulating oxide layer along the thickness direction of the supporting substrate, and contact the drain region; the conductive vias include cylindrical vias with a diameter greater than 0.2 μm and less than 1 μm; or, the conductive vias include rectangular vias with a cross-sectional area greater than 0.2 μm × 1 μm and less than 3 μm × 20 μm; The conductive vias are filled with a conductive material to form conductive channels; A first metal layer is formed on the bottom surface of the second insulating oxide layer, and the first metal layer is electrically connected to the conductive channel.
6. The manufacturing method according to claim 5, characterized in that... Also includes: A silicide layer is formed above the body region, and the source region and the body region contact region are electrically connected through the silicide layer.
7. The manufacturing method according to claim 6, characterized in that... Also includes: A cured oxide layer is formed in the space above the top silicon layer, and contact vias are formed therein; A first metal layer is formed on top of the cured oxide layer, and the first metal layer is electrically connected to the silicide layer through the contact via.
8. A radio frequency chip, characterized in that... The device includes the LDMOS device according to any one of claims 1-4, wherein the drain of the LDMOS device is disposed below the chip substrate.