Semiconductor device and method for manufacturing the same

Abstract

Semiconductor device comprising: a memory cell capacitor configured to store data, the memory cell capacitor comprising: a plurality of bottom electrodes (BE) on a substrate (100) extending in a vertical direction (D2) with respect to a top surface (100U) of the substrate (100), the plurality of bottom electrodes (BE) being spaced apart from one another in a first direction (D1) parallel to the top surface (100U) of the substrate (100); an upper support pattern (130U) on upper lateral surfaces of the plurality of bottom electrodes (BE);and a lower support pattern (130L) on lower lateral surfaces of the plurality of bottom electrodes (BE), wherein the lower support pattern (130L) is arranged between the substrate (100) and the upper support pattern (130U), and wherein a first bottom electrode of the plurality of bottom electrodes (BE) includes a first depression (150a) adjacent to a bottom surface (130LL) of the lower support pattern (130L), wherein the first bottom electrode further includes a third depression (150c) adjacent to a bottom surface (130UL) of the upper support pattern (130U) and a fourth depression (150d) adjacent to a top surface of the upper support pattern (130U).

Description

background The present inventive concepts relate to a semiconductor device and in particular to a semiconductor device containing a capacitor. As semiconductor devices with high integration are developed, it is desirable for capacitors to exhibit high capacitance within a limited area. The capacitance of a capacitor is proportional to the surface area of ​​an electrode and the dielectric constant of a dielectric layer, while it is inversely proportional to the equivalent oxide thickness of the dielectric layer. The higher the aspect ratio of a capacitor's base electrode, the greater its capacitance. Therefore, various research efforts have been conducted on process technologies for producing capacitors with high aspect ratios. US 2014 / 0134839A1 discloses: The methods comprise successively forming a first form film, a first carrier film, a second form film, and a second carrier film on a substrate, forming a contact hole through the second carrier film, the second form film, the first carrier film, and the first form film, forming an electrode in the contact hole, and removing portions of the second carrier film, the second form film, and the first form film to leave a portion of the first carrier film as a first carrier pattern surrounding the electrode and a portion of the second carrier film as a second carrier pattern surrounding the electrode. US 2013 / 0230961A1 discloses: A method for manufacturing semiconductor memory devices comprises successively forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate; forming lower electrodes that penetrate the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate; structuring the second support layer to form a second support pattern with an opening; removing the second mold layer to expose portions of the sidewalls of the lower electrodes; and etching the exposed sidewalls of the lower electrodes. US 2018 / 0166447A1 discloses: A semiconductor device comprising a substrate, first, second, and third structures arranged on the substrate and spaced apart from one another in a first direction, each of the first, second, and third structures containing lower electrodes, and a support pattern that carries the first, second, and third structures and comprises a first region and a second region, the first region exposing first portions of sidewalls of the first, second, and third structures, and the second region surrounding second portions of the sidewalls of the first, second, and third structures. A first length of a sidewall of the support pattern between the first and second structures is greater than a first distance between the first and second structures. A second length of a sidewall of the support pattern between the second and third structures is greater than a second distance between the second and third structures. Summary The invention is defined in the independent claims. Specific embodiments are defined in the dependent claims. Some embodiments of the present inventive concepts provide for a semiconductor device with improved electrical properties and a method for manufacturing the same. Some embodiments of the present inventive concepts provide for a highly integrated semiconductor device and a method for manufacturing the same. According to an embodiment of the present invention, a semiconductor device includes a memory cell capacitor for storing data. The memory cell capacitor comprises a plurality of bottom electrodes on a substrate, extending in a vertical direction with respect to a top surface of the substrate. The plurality of bottom electrodes are spaced apart from one another in a first direction parallel to the top surface of the substrate. An upper support pattern is located on the upper lateral surfaces of the plurality of bottom electrodes, and a lower support pattern is located on the lower lateral surfaces of the plurality of bottom electrodes. The lower support pattern is arranged between the substrate and the upper support pattern, and a first bottom electrode of the plurality of bottom electrodes has a first depression adjacent to a bottom surface of the lower support pattern. According to an embodiment of the present invention, a method for manufacturing a semiconductor device comprises the sequential formation of a first mold layer, a lower support layer, a second mold layer, and an upper support layer on a substrate; the formation, on the substrate, of a plurality of bottom electrodes penetrating the first mold layer, the lower support layer, the second mold layer, and the upper support layer; the patterning of the upper support layer to form an upper support pattern having at least one upper opening; the removal of the second mold layer through the at least one upper opening to partially expose upper lateral surfaces of the plurality of bottom electrodes; the patterning of the lower support layer to form a lower support pattern having at least one lower opening; and the removal of at least one section of the first mold layer through the at least one lower opening.to partially expose the lower lateral surfaces of the majority of the bottom electrodes, and after removing at least one section of the first mold layer, etching the exposed lower lateral surfaces of the majority of the bottom electrodes and the exposed upper lateral surfaces of the majority of the bottom electrodes. Brief description of the drawings Fig. 1 shows a top view of a semiconductor device according to some embodiments of the present inventive concepts. Fig. 2 shows a cross-sectional view along line II' from Fig. 1. Figs. 3A and 3B show enlarged views, each showing sections R1 and R2 from Fig. 2. Figs. 4 to 9 and 11 show cross-sectional views along line II' from Fig. 1, illustrating a method for manufacturing a semiconductor device according to some embodiments of the present inventive concepts. Figs. 10A and 10B show enlarged views, each showing sections R3 and R4 from Fig. 9. Figs. 12 and 13 show cross-sectional views along line II' from Fig. 1, illustrating a method for manufacturing a semiconductor device according to some embodiments of the present inventive concepts. Fig. 14 shows a cross-sectional view along line II' from Fig.Fig. 1 shows a semiconductor device according to some embodiments of the present inventive concepts. Fig. 15 shows an enlarged view showing section R5 from Fig. 14. Figs. 16, 17, 18, 19, 20 to 21 show cross-sectional views along line II' from Fig. 1, showing a method for manufacturing a semiconductor device according to some embodiments of the present inventive concepts. Fig. 22 shows a cross-sectional view along line II' from Fig. 1, showing a semiconductor device according to some embodiments of the present inventive concepts. Fig. 23 shows a circuit diagram showing a unit memory cell of a semiconductor device according to some embodiments of the present inventive concepts.Figure 24 shows a top view partially depicting a semiconductor device according to some embodiments of the present inventive concepts. Figure 25 shows a cross-sectional view along line II-II' from Figure 24. Detailed description of the embodiments In the following, some exemplary embodiments of the present inventive concepts are described in detail with reference to the attached drawings. Fig. 1 shows a top view of a semiconductor device according to some embodiments of the present inventive concepts. Fig. 2 shows a cross-sectional view along line II' from Fig. 1. Figs. 3A and 3B show enlarged views, each showing sections R1 and R2 from Fig. 2. Referring to Fig. 1 and Fig. 2, a dielectric intermediate layer 102 can be arranged on a substrate 100. The substrate 100 can contain a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (Si-Ge) substrate. The dielectric intermediate layer 102 can, for example, contain at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. Conductive contacts 110 and contact pads 115 can be arranged in the dielectric intermediate layer 102. Each of the conductive contacts 110 can penetrate a lower section of the dielectric intermediate layer 102 and can have an electrical connection with the substrate 100. The contact pads 115 can be arranged on corresponding conductive contacts 110. The contact pads 115 can penetrate an upper section of the dielectric intermediate layer 102 and can have electrical connections with corresponding conductive contacts 110. The conductive contacts 110 and the contact pads 115 can contain at least one selected from semiconductor materials (e.g., polycrystalline silicon), metal-semiconductor compounds (e.g., tungsten silicide), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride), and metals (e.g., titanium, tungsten, and / or tantalum). An insulating layer 120 can be arranged on the dielectric intermediate layer 102. The insulating layer 120 can cover at least one section of a surface of the dielectric intermediate layer 102 and at least sections of surfaces of the contact pads 115. For example, the insulating layer 120 can contact at least one section of the surface of the dielectric intermediate layer 102 and at least sections of the surfaces of the contact pads 115. The insulating layer 120 can, for example, contain at least one selected oxide, nitride, and oxynitride. A plurality of bottom electrodes BE can be arranged horizontally spaced apart from one another on the dielectric intermediate layer 102. For example, the plurality of bottom electrodes BE can be spaced apart from one another along a first direction D1 parallel to a cover surface 100U of the substrate 100. The plurality of bottom electrodes BE can penetrate the insulating layer 120 and can have connections with corresponding contact pads 115. According to some embodiments, each of the plurality of bottom electrodes BE can have a column shape. A lower support pattern 130L can be arranged on the lower lateral surfaces (i.e., a first section of lateral surfaces) of the plurality of bottom electrodes BE. The lower support pattern 130L can contact the lower lateral surfaces of the plurality of bottom electrodes BE. The lower support pattern 130L can be vertically spaced from the dielectric intermediate layer 102 and the insulating layer 120 along a second direction D2 perpendicular to the top surface 100U of the substrate 100. The lower support pattern 130L can have at least one lower opening 180L. In one embodiment, the plurality of bottom electrodes BE can include a plurality of first bottom electrodes BE1, which are exposed through the plurality of lower openings 180L, and a plurality of second bottom electrodes BE2, which are surrounded by the lower support pattern 130L.For example, the lower lateral surfaces of the plurality of first bottom electrodes BE1 may be partially exposed by the lower openings 180L and partially covered by the lower support pattern 130L, and the lower lateral surfaces of the plurality of second bottom electrodes BE2 may be surrounded by the lower support pattern 130L. Viewed from a top view, the at least one lower opening 180L may extend along a third direction D3, which is parallel to the top surface 100U of the substrate 100 and intersects the first direction D1, and may also extend along the lower lateral surfaces of the plurality of first bottom electrodes BE1. In one embodiment, the first direction D1 and the third direction D3 may form an acute angle between them. According to some embodiments, the lower support pattern 130L may have a plurality of lower openings 180L that are horizontally spaced apart from one another.Each of the majority of lower openings 180L can extend along the lower lateral surfaces of corresponding one of the majority of first bottom electrodes BE1. An upper support pattern 130U can be arranged on the upper lateral surfaces (i.e., a second section of the lateral surfaces) of the plurality of bottom electrodes BE. The upper support pattern 130U can contact the upper lateral surfaces of the plurality of bottom electrodes BE. The upper support pattern 130U can be vertically spaced from the lower support pattern 130L along the second direction D2. The upper support pattern 130U can have at least one upper opening 180U. In one embodiment, the plurality of first bottom electrodes BE1 can be exposed through the plurality of upper openings 180U, and the plurality of second bottom electrodes BE2 can be surrounded by the upper support pattern 130U.For example, the upper lateral surfaces of the plurality of first bottom electrodes BE1 may be partially exposed by the upper openings 180U and partially covered by the upper support pattern 130U, and the upper lateral surfaces of the plurality of second bottom electrodes BE2 may be surrounded by the upper support pattern 130U. Viewed from a top view, the at least one upper opening 180U may extend along the third direction D3 and may also extend along the upper lateral surfaces of the plurality of first bottom electrodes BE1. The at least one upper opening 180U may vertically overlap the at least one lower opening 180L along the second direction D2. In some embodiments, the upper support pattern 130U may have a plurality of upper openings 180U that are horizontally spaced apart from one another.Each of the plurality of upper openings 180U can extend along the upper lateral surfaces of corresponding one of the plurality of first bottom electrodes BE1. The plurality of upper openings 180U can vertically overlap the plurality of lower openings 180L along the second direction D2. The plurality of bottom electrodes BE can penetrate the upper support pattern 130U, the lower support pattern 130L, and the insulating layer 120, and can have connections with corresponding contact pads 115. Each of the plurality of bottom electrodes BE can have a top surface BE_U at substantially the same height as that of a cover surface 130UU of the upper support pattern 130U, although the present inventive concepts are not necessarily limited to this. Contrary to what has been shown, the top surface BE_U of each of the plurality of bottom electrodes BE can be positioned at a height lower than that of the cover surface 130UU of the upper support pattern 130U. In this disclosure, the term "height" can be a measured distance to the cover surface 100U of the substrate 100.Terms such as "same," "identical," "planar," or "coplanar," as used herein, encompass variations that are nearly identical and may arise, for example, due to manufacturing processes. The term "essentially" may be used herein to emphasize this meaning unless the context or other statements indicate otherwise. A cover electrode TE can be arranged on the dielectric intermediate layer 102 and can cover the majority of bottom electrodes BE, the lower support pattern 130L, and the upper support pattern 130U. The cover electrode TE can fill a space between the majority of bottom electrodes BE, a space between the dielectric intermediate layer 102 and the lower support pattern 130L, and a space between the lower support pattern 130L and the upper support pattern 130U. The insulating layer 120 can be inserted between the cover electrode TE and the dielectric intermediate layer 102. The cover electrode TE can penetrate the upper support pattern 130U and the lower support pattern 130L by passing through at least one upper opening 180U and at least one lower opening 180L. The cover electrode TE can penetrate the upper carrier pattern 130U and the lower carrier pattern 130L by filling at least one upper opening 180U and at least one lower opening 180L.For example, the cover electrode TE can completely fill at least one upper opening 180U and at least one lower opening 180L. A dielectric layer 140 can be inserted between the top electrode TE and each of the plurality of bottom electrodes BE, between the top electrode TE and the lower support pattern 130L, and between the top electrode TE and the upper support pattern 130U. The dielectric layer 140 can extend between the top electrode TE and the insulating layer 120. The dielectric layer 140 can separate the plurality of bottom electrodes BE from the top electrode TE. The majority of the bottom electrodes BE and the top electrode TE may contain at least one selected from polysilicon, metal, metal silicide and metal nitride. The dielectric layer 140 can contain at least one selected from oxide (e.g., a silicon oxide layer), nitride (e.g., a silicon nitride layer), oxynitride (e.g., a silicon oxynitride layer), and high-k dielectrics (e.g., a hafnium oxide layer). Both the lower and upper support patterns 130L and 130U can contain a dielectric material. For example, both the lower and upper support patterns 130L and 130U can contain at least one selected from oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), and oxynitride (e.g., silicon oxynitride). In one embodiment, the lower and upper support patterns 130L and 130U can be formed from the same material or from different materials. Hereinafter, the reference numeral "BE" can be used generally to describe lateral surfaces of the plurality of first bottom electrodes BE1 and lateral surfaces of the plurality of second bottom electrodes BE2. Referring to Fig. 2 and Fig. 3A, at least one of the plurality of bottom electrodes BE can contain a first depression 150a adjacent to a bottom surface 130LL of the lower support pattern 130L. The first depression 150a can be a region that is recessed into the at least one bottom electrode BE from a lateral surface of the at least one bottom electrode BE. The dielectric layer 140 can cover the bottom surface 130LL of the lower support pattern 130L and can fill at least a portion of the first depression 150a. The at least one bottom electrode BE can further contain a second depression 150b adjacent to a top surface 130LU of the lower support pattern 130L. The second depression 150b can be a region that is recessed into the at least one bottom electrode BE from a lateral surface of the at least one bottom electrode BE.The dielectric layer 140 can cover the top surface 130LU of the lower support pattern 130L and can fill at least one section of the second recess 150b. The at least one bottom electrode BE can include a first part P1 in the lower support pattern 130L and a second part P2 below the lower support pattern 130L. The second part P2 of the at least one bottom electrode BE can have a maximum width W2 that is greater than the maximum width W1 of the first part P1 of the at least one bottom electrode BE. In this disclosure, the term "width" can be a distance measured along a direction (e.g., the first direction D1) parallel to the top surface 100U of the substrate 100. The at least one bottom electrode BE can include a third part P3 between the upper support pattern 130U and the lower support pattern 130L. The third part P3 of the at least one bottom electrode BE can have a maximum width W3 that is greater than the maximum width W1 of the first part P1 of the at least one bottom electrode BE.The first recess 150a can be positioned at the boundary between the first part P1 of the at least one ground electrode BE and the second part P2 thereof. The second recess 150b can be positioned at the boundary between the first part P1 of the at least one ground electrode BE and the third part P3 thereof. In one embodiment, the first part P1 of the at least one ground electrode BE can include a first section that contacts the lower support pattern 130L. The first section of the first part P1 can be arranged between the first recess 150a and the second recess 150b. The first part P1 of the at least one ground electrode BE can further include a second section spaced apart from the lower support pattern 130L, with a section of the dielectric layer 140 that fills the first recess 150a between them.The first part P1 of the at least one bottom electrode BE can further include a third section spaced apart from the lower support pattern 130L with a section of the dielectric layer 140 that fills the second depression 150b in between. Referring to Fig. 2 and Fig. 3B, the at least one bottom electrode BE can further comprise a third recess 150c adjacent to a bottom surface 130UL of the upper support pattern 130U. The third recess 150c can be a region recessed into the at least one bottom electrode BE from the lateral surface of the at least one bottom electrode BE. The dielectric layer 140 can cover the bottom surface 130UL of the upper support pattern 130U and can fill at least a portion of the third recess 150c. The at least one bottom electrode BE can further comprise a fourth recess 150d adjacent to the top surface 130UU of the upper support pattern 130U. The fourth recess 150d can be a region recessed into the at least one bottom electrode BE from the top surface BEU of the at least one bottom electrode BE.The fourth well 150d can expose a boundary between the at least one bottom electrode BE and the upper support pattern 130U. The dielectric layer 140 can cover the top surface 130UU of the upper support pattern 130U and can fill at least a section of the fourth well 150d. The at least one bottom electrode BE can include a fourth part P4 in the upper support pattern 130U. The maximum width W3 of the third part P3 of the at least one bottom electrode BE can be greater than the maximum width W4 of the fourth part P4 of the at least one bottom electrode BE. The third recess 150c can be positioned at the boundary between the third part P3 of the at least one bottom electrode BE and the fourth part P4 thereof. The fourth recess 150d can be arranged along the rounded corner of the top surface BE_U of the at least one bottom electrode BE. In one embodiment, the fourth part P4 of the at least one bottom electrode BE can include a first section that contacts the upper support pattern 130U. The first section of the fourth part P4 can be arranged between the third recess 150c and the fourth recess 150d.The fourth part P4 of the at least one bottom electrode BE can further comprise a second section spaced apart from the upper support pattern 130U, with a section of the dielectric layer 140 that fills the third recess 150c between them. The first part P1 of the at least one bottom electrode BE can further comprise a third section spaced apart from the lower support pattern 130L, with a section of the dielectric layer 140 that fills the fourth recess 150d between them. Referring again to Fig. 1 and Fig. 2, a capacitor can be formed from the plurality of bottom electrodes BE, the lower support pattern 130L, the upper support pattern 130U, the top electrode TE and the dielectric layer 140. The plurality of bottom electrodes BE can each have a relatively large aspect ratio to increase the capacitor's capacitance, and the lower support pattern 130L and the upper support pattern 130U can be used to ensure the structural stability of the plurality of bottom electrodes BE. In this case, during the process of forming the plurality of bottom electrodes BE, the plurality of bottom electrodes BE may be configured such that they exhibit the relatively large widths between the upper and lower support patterns 130U and 130L and below the lower support pattern 130L, which can cause leakage current to occur between adjacent bottom electrodes BE. According to the present inventive concepts, an etching process can be carried out between the upper and lower support patterns 130U and 130L and below the lower support pattern 130L to partially etch the lateral surfaces of the plurality of bottom electrodes BE. The etching process can reduce the widths of the plurality of bottom electrodes BE and, consequently, the leakage current between the plurality of bottom electrodes BE can be minimized. Additionally, during the etching process, the at least one bottom electrode BE can be configured to include the first, second, third, and fourth recesses 150a, 150b, 150c, and 150d. Figures 4 to 9 and 11 show cross-sectional views along line II' from Figure 1, illustrating a method for manufacturing a semiconductor device according to some embodiments of the present inventive concepts. Figures 10A and 10B show enlarged views, each showing sections R3 and R4 from Figure 9. For the sake of brevity, deletions may be made to avoid duplicate descriptions of the semiconductor device described above with reference to Figures 1, 2, 3A, and 3B. Referring to Fig. 4, a dielectric intermediate layer 102 can be formed on a substrate 100, and conductive contacts 110 and contact pads 115 can be formed in the dielectric intermediate layer 102. The formation of the conductive contacts 110 and the contact pads 115 can include: forming contact holes (not shown) to penetrate a lower section of the dielectric intermediate layer 102, forming pad holes (not shown) to penetrate an upper section of the dielectric intermediate layer 102, and forming conductive layers to fill the contact holes and the pad holes. An insulating layer 120 can be formed on the dielectric intermediate layer 102, and then a first mold layer 162, a lower support layer 132, a second mold layer 164, and an upper support layer 134 can be formed sequentially on the insulating layer 120. The first mold layer 162 and the second mold layer 164 can, for example, be formed from a silicon oxide layer. The insulating layer 120, the lower support layer 132, and the upper support layer 134 can be formed from a material with etch selectivity with respect to the first and second mold layers 162 and 164. For example, the insulating layer 120, the lower support layer 132, and the upper support layer 134 can contain at least one selected from SiN, SiCN, TaO, and TiO₂. The upper support layer 134 can be designed such that it has a thickness that is essentially equal to or greater than that of the lower support layer 132.In this disclosure, the term "thickness" can be a distance measured in one direction (e.g., the second direction D2) perpendicular to a cover surface 100U of the substrate 100. A deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), can be carried out to form both the insulating layer 120 and the first mold layer 162, the lower support layer 132, the second mold layer 164, and the upper support layer 134. Referring to Fig. 5, vertical holes 170 can be formed in the stacked layers 120, 162, 132, 164, and 134. Each of the vertical holes 170 can penetrate the upper support layer 134, the second mold layer 164, the lower support layer 132, the first mold layer 162, and the insulating layer 120, and can expose a corresponding contact pad 115. The vertical holes 170 can be horizontally spaced apart on the dielectric intermediate layer 102. The formation of the vertical holes 170 can, for example, include: forming a mask pattern (not shown) with a plurality of openings on the upper support layer 134 to define areas in which the vertical holes 170 are formed, and sequentially etching the upper support layer 134, the second mold layer 164, the lower support layer 132, the first mold layer 162 and the insulating layer 120 using the mask pattern as an etching mask. For example, a dry etching process can be used to etch the upper support layer 134, the second mold layer 164, the lower support layer 132, the first mold layer 162, and the insulating layer 120. During the dry etching process, a bending phenomenon caused by ion scattering can occur such that the vertical holes 170 are defined by concave lateral surfaces of the first and second mold layers 162 and 164. In some embodiments, the first and second mold layers 162 and 164 can be etched more extensively during the dry etching process than the upper and lower support layers 134 and 132, and thus each of the vertical holes 170 can be configured to have a relatively large width in the first and second mold layers 162 and 164.For example, each of the vertical holes 170 formed in the lower support layer 132 can have a first maximum width 170W1, and each of the vertical holes 170 formed in the first mold layer 162 can have a second maximum width 170W2, which is larger than the first maximum width 170W1. Each of the vertical holes 170 formed in the second mold layer 164 can have a third maximum width 170W3, which is larger than the first maximum width 170W1, and each of the vertical holes 170 formed in the upper support layer 134 can have a fourth maximum width 170W4, which is smaller than the third maximum width 170W3. Referring to Fig. 6, a plurality of bottom electrodes BE can be formed in vertical holes 170. The formation of the bottom electrodes BE can, for example, include: forming a bottom electrode layer on the upper support layer 134 to fill the vertical holes 170, and planarizing the bottom electrode layer until the upper support layer 134 is exposed. The bottom electrodes BE can be horizontally spaced apart on the dielectric intermediate layer 102 and can be connected to the contact pads 115. If the vertical holes 170 have lateral surfaces caused by the bending phenomenon described with reference to Fig. 5, adjacent bottom electrodes BE formed in the vertical holes 170 can have a reduced interval in the first and second mold layers 162 and 164. Accordingly, a leakage current can occur between the bottom electrodes BE. Referring to Fig. 1 and Fig. 7, the upper support layer 134 can be patterned to form an upper support pattern 130U with at least one upper opening 180U. The at least one upper opening 180U can expose upper lateral surfaces of the majority of first bottom electrodes BE1 and can also expose a top surface of the second mold layer 164. The second mold layer 164 can be removed through the at least one upper opening 180U. The removal of the second mold layer 164 can involve selective etching of the second mold layer 164 with respect to the upper support pattern 130U and the lower support layer 132. For example, the second mold layer 164 can be removed by performing an isotropic etching process using phosphoric acid. The removal of the second mold layer 164 can partially expose a top surface of the lower support layer 132 and the upper lateral surfaces of the bottom electrodes BE. Referring to Fig. 1 and Fig. 8, the lower support layer 132 can be patterned to form a lower support pattern 130L with at least one lower opening 180L. The at least one lower opening 180L can expose lower lateral surfaces of the majority of first bottom electrodes BE1 and can also expose a top surface of the first mold layer 162. An upper portion of the first mold layer 162 can be removed through the at least one lower opening 180L. Removing the upper portion of the first mold layer 162 can involve selective etching of the first mold layer 162 with respect to the upper support pattern 130U and the lower support pattern 130L. For example, the first mold layer 162 can be removed by performing an isotropic etching process using phosphoric acid.Removing the upper section of the first mold layer 162 can expose the lateral surfaces of the bottom electrodes BE and can allow a lower section of the first mold layer 162 to remain on the dielectric intermediate layer 102. Referring to Figs. 9, 10A, and 10B, the exposed lateral surfaces of the bottom electrodes BE can be partially etched. The exposed lateral surfaces of the bottom electrodes BE can be etched by a wet etching process with high etch selectivity. During the wet etching process, the exposed lateral surfaces of the bottom electrodes BE can be selectively etched with respect to the upper support pattern 130U, the lower support pattern 130L, and the first mold layer 162. Accordingly, each of the bottom electrodes BE can have a reduced width between the upper and lower support patterns 130U and 130L and below the lower support pattern 130L. According to some embodiments, as shown in Figs. 9 and 10A, each of the bottom electrodes BE can include a first part P1 in the lower support pattern 130L and a second part P2 below the lower support pattern 130L.The second part P2 can have a maximum width W2 that is greater than the maximum width W1 of the first part P1. Each of the bottom electrodes BE can contain a third part P3 between the upper and lower support patterns 130U and 130L, and the third part P3 can have a maximum width W3 that is greater than the maximum width W1 of the first part P1. As shown in Fig. 9 and Fig. 10B, each of the bottom electrodes BE can contain a fourth part P4 in the upper support pattern 130U. The maximum width W3 of the third part P3 can be greater than the maximum width W4 of the fourth part P4. The wet etching process can form a first depression 150a adjacent to a bottom surface 130LL of the lower support pattern 130L, a second depression 150b adjacent to a top surface 130LU of the lower support pattern 130L, a third depression 150c adjacent to a bottom surface 130UL of the upper support pattern 130, and a fourth depression 150d adjacent to a top surface 130UU of the upper support pattern 130U in each of the bottom electrodes BE. The first, second, and third depressions 150a, 150b, and 150c can be areas recessed into the bottom electrode BE from the side surface of the bottom electrode BE. The fourth depression 150d can be an area recessed into the bottom electrode BE from a top surface BE_U of the bottom electrode BE and can expose a boundary between the bottom electrode BE and the upper support pattern 130U. According to the present inventive concepts, the wet etching process allows each bottom electrode BE to have a reduced width between the upper and lower support patterns 130U and 130L and below the lower support pattern 130L. Thus, leakage current between the majority of bottom electrodes BE can be minimized, or leakage current due to an electrical short circuit between the majority of bottom electrodes BE can be avoided. Referring to Fig. 11, a lower section of the first mold layer 162 can be removed after the wet etching process. Removing the lower section of the first mold layer 162 can involve selective etching of the first mold layer 162 with respect to the upper support pattern 130U, the lower support pattern 130L, and the insulating layer 120. For example, the lower section of the first mold layer 162 can be removed by performing an isotropic etching process using phosphoric acid. Removing the lower section of the first mold layer 162 can expose a top surface of the insulating layer 120. Referring again to Figs. 1 and 2, a dielectric layer 140 and a cover electrode TE can be sequentially formed on the dielectric intermediate layer 102. The cover electrode TE can fill a space between the plurality of bottom electrodes BE, a space between the dielectric intermediate layer 102 and the lower support pattern 130L, and a space between the lower support pattern 130L and the upper support pattern 130U. The insulating layer 120 can be inserted between the cover electrode TE and the dielectric intermediate layer 102. The dielectric layer 140 can be inserted between the cover electrode TE and each of the plurality of bottom electrodes BE, between the cover electrode TE and the lower support pattern 130L, and between the cover electrode TE and the upper support pattern 130U. The dielectric layer 140 can extend between the cover electrode TE and the insulating layer 120.The dielectric layer 140 and the cover electrode TE can be conformally formed by using a layer deposition technique such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In one embodiment, a processing condition of the layer deposition technique can be controlled such that a step coverage of the dielectric layer 140 is sufficient for conformal coverage of exposed surfaces of the majority of bottom electrodes BE, exposed surfaces of the lower support pattern 130L, exposed surfaces of the upper support pattern 130U, and exposed surfaces of the insulating layer 120. In one embodiment, a processing condition of the layer deposition technique can be controlled such that a step covering of the top electrode TE can fill spaces under the majority of bottom electrodes BE, the top electrode TE, the lower support pattern 130L, the upper support pattern 130U and the insulating layer 120. Figures 12 and 13 show cross-sectional views along line II' from Figure 1, illustrating a method for manufacturing a semiconductor device according to some embodiments of the present inventive concepts. To condense the description, the focus below is on the differences compared to the method for manufacturing a semiconductor device described with reference to Figures 4 to 9, 10A, 10B, and 11. As described with reference to Figs. 7 and 8, the upper support layer 134 can be patterned to form the upper support pattern 130U with the at least one upper opening 180U, and the second mold layer 164 can be removed through the at least one upper opening 180U. Subsequently, the lower support layer 132 can be patterned to form the lower support pattern 130L with the at least one lower opening 180L. Referring to Fig. 12, the first mold layer 162 can be removed through the at least one lower opening 180L. Removing the first mold layer 162 can involve selective etching of the first mold layer 162 with respect to the upper support pattern 130U and the lower support pattern 130L. For example, the first mold layer 162 can be removed by performing an isotropic etching process using phosphoric acid. Removal of the first mold layer 162 can be carried out until the insulating layer 120 is exposed. Removing the first mold layer 162 can expose sections of the lateral surfaces of the bottom electrodes BE and a top surface of the insulating layer 120. Referring to Fig. 13, the exposed lateral surfaces of the bottom electrodes BE can be partially etched. The exposed lateral surfaces of the bottom electrodes BE can be etched by the same method as described with reference to Figs. 9, 10A, and 10B. A method for manufacturing a semiconductor device according to the present embodiment can be essentially the same as the method for manufacturing a semiconductor device described with reference to Figs. 4 to 9, 10A, 10B, and 11, except for the differences mentioned above. Fig. 14 shows a cross-sectional view along line II' from Fig. 1, illustrating a semiconductor device according to some embodiments of the present inventive concepts. Fig. 15 shows an enlarged view of section R5 from Fig. 14. To condense the description, the focus below is on the differences compared to the semiconductor device described with reference to Fig. 1, Fig. 2, Fig. 3A, and Fig. 3B. Referring to Fig. 1 and Fig. 14, a central support pattern 130M can, according to some embodiments, be arranged on the central lateral surfaces of the plurality of ground electrodes BE. The central support pattern 130M can contact the central lateral surfaces of the plurality of ground electrodes BE. The central support pattern 130M can be arranged between the lower support pattern 130L and the upper support pattern 130U. The central support pattern 130M can be vertically spaced from the lower support pattern 130L along the second direction D2, and the upper support pattern 130U can be vertically spaced from the central support pattern 130M along the second direction D2. The central support pattern 130M can have at least one central opening 180M. Viewed from a top view, the at least one central opening 180M can extend along the third direction D3 and can also extend along the central lateral surfaces of the plurality of first bottom electrodes BE1. The at least one central opening 180M can vertically overlap the at least one lower opening 180L and the at least one upper opening 180U along the second direction D2. According to some embodiments, the central support pattern 130M can have a plurality of central openings 180M that are horizontally spaced apart. Each of the plurality of central openings 180M can extend along the central lateral surfaces of corresponding one of the plurality of first bottom electrodes BE1.The majority of middle openings 180M can vertically overlap the majority of lower openings 180L along the second direction D2 and can also vertically overlap the majority of upper openings 180U along the second direction D2. Each of the majority of the ground electrodes BE can penetrate the upper support pattern 130U, the middle support pattern 130M, the lower support pattern 130L and the insulating layer 120 and can have a connection with a corresponding contact pad 115. The cover electrode TE can be arranged on the dielectric intermediate layer 102 and can cover the majority of the bottom electrodes BE, the lower support pattern 130L, the middle support pattern 130M, and the upper support pattern 130U. The cover electrode TE can fill a space between the majority of the bottom electrodes BE, a space between the dielectric intermediate layer 102 and the lower support pattern 130L, a space between the lower support pattern 130L and the middle support pattern 130M, and a space between the middle support pattern 130M and the upper support pattern 130U. The cover electrode TE can penetrate the at least one upper opening 180U, the at least one middle opening 180M, and the at least one lower opening 180L, and can penetrate the upper support pattern 130U, the middle support pattern 130M, and the lower support pattern 130L.In one embodiment, the cover electrode TE can fill at least one upper opening 180U, at least one middle opening 180M and at least one lower opening 180L. The dielectric layer 140 can be placed between the top electrode TE and any of the majority of bottom electrodes BE, between the top electrode TE and the lower support pattern 130L, between the top electrode TE and the middle support pattern 130M, and between the top electrode TE and the upper support pattern 130U. The middle support pattern 130M can contain a dielectric material, for example, at least one selected from oxide, nitride, and oxynitride. As described with reference to Fig. 3A, at least one of the plurality of bottom electrodes BE can include a first depression 150a adjacent to the bottom surface 130LL of the lower support pattern 130L and a second depression 150b adjacent to the top surface 130LU of the lower support pattern 130L. The dielectric layer 140 can cover the bottom surface and the top surfaces 130LL and 130LU of the lower support pattern 130L and can fill at least a portion of both the first and second depressions 150a and 150b. The at least one bottom electrode BE can include a first part P1 in the lower support pattern 130L and a second part P2 below the lower support pattern 130L. The second part P2 of the at least one bottom electrode BE can have a maximum width W2 that is greater than a maximum width W1 of the first part P1 of the at least one bottom electrode BE. As described with reference to Fig. 3B, the at least one of the plurality of bottom electrodes BE can further comprise a third recess 150c adjacent to the bottom surface 130UL of the upper support pattern 130U and a fourth recess 150d adjacent to the top surface 130UU of the upper support pattern 130U. The dielectric layer 140 can cover the bottom surface and the top surfaces 130UL and 130UU of the upper support pattern 130U and can fill at least a portion of both the third and fourth recesses 150c and 150d. The at least one bottom electrode BE can comprise a third part P3 between the upper support pattern 130U and the middle support pattern 130M and a fourth part P4 within the upper support pattern 130U. The third part P3 of the at least one bottom electrode BE can have a maximum width W3 that is greater than the maximum width W4 of the fourth part P4 of the at least one bottom electrode BE. Referring to Figures 14 and 15, the at least one bottom electrode can further comprise a fifth recess 150e adjacent to a bottom surface 130ML of the central support pattern 130M. The fifth recess 150e can be a region recessed into the at least one bottom electrode BE from the lateral surface of the at least one bottom electrode BE. The dielectric layer 140 can cover the bottom surface 130ML of the central support pattern 130M and can fill at least a portion of the fifth recess 150e. The at least one bottom electrode BE can further comprise a sixth recess 150f adjacent to a top surface 130MU of the central support pattern 130M. The sixth recess 150f can be a region recessed into the at least one bottom electrode BE from the lateral surface of the at least one bottom electrode BE.The dielectric layer 140 can cover the top surface 130MU of the middle support pattern 130M and can fill at least one section of the sixth recess 150f. The at least one ground electrode BE may further comprise a fifth part P5 between the lower support pattern 130L and the middle support pattern 130M, and a sixth part P6 within the middle support pattern 130M. The fifth part P5 of the at least one ground electrode BE may have a maximum width W5 that is greater than the maximum width W1 of the first part P1 of the at least one ground electrode BE and greater than the maximum width W6 of the sixth part P6 of the at least one ground electrode BE. The maximum width W3 of the third part P3 of the at least one ground electrode BE may be greater than the maximum width W6 of the sixth part P6 of the at least one ground electrode BE. Referring again to Fig. 1 and Fig. 14, a capacitor can be formed from the plurality of bottom electrodes BE, the lower support pattern 130L, the middle support pattern 130M, the upper support pattern 130U, the top electrode TE and the dielectric layer 140. Figures 16, 17, 18, 19, 20 to 21 show cross-sectional views along line II' from Figure 1, illustrating a method for manufacturing a semiconductor device according to some embodiments of the present inventive concepts. To condense the description, the focus below is on the differences compared to the method for manufacturing a semiconductor device described with reference to Figures 4 to 9, 10A, 10B, and 11. Referring to Fig. 16, the first mold layer 162, the lower support layer 132, the second mold layer 164, and the upper support layer 134 can be formed sequentially on the insulating layer 120. According to some embodiments, a third mold layer 166 can be formed between the lower support layer 132 and the second mold layer 164, and a middle support layer 136 can be formed between the third mold layer 166 and the second mold layer 164. The third mold layer 166 can, for example, be formed from a silicon oxide layer. The middle support layer 136 can be formed from a material with etch selectivity with respect to the first, second, and third mold layers 162, 164, and 166. For example, the middle support layer 136 can contain at least one selected from SiN, SiCN, TaO, and TiO₂.The middle support layer 136 can have a thickness that is substantially equal to or greater than that of the lower support layer 132. The upper support layer 134 can have a thickness that is substantially equal to or greater than that of the middle support layer 136. The third mold layer 166 and the middle support layer 136 can be formed by carrying out a deposition process, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). Referring to Fig. 17, vertical holes 170 can be formed in the stacked layers 120, 162, 132, 166, 136, 164 and 134. Each of the vertical holes 170 can penetrate the upper support layer 134, the second mold layer 164, the middle support layer 136, the third mold layer 166, the lower support layer 132, the first mold layer 162 and the insulating layer 120 and can expose a corresponding contact pad 115. The vertical holes 170 can be formed by essentially the same process (e.g., the dry etching process) as described with reference to Fig. 5. During the dry etching process, the first, second, and third mold layers 162, 164, and 166 can be etched more than the upper support layer 134, the middle support layer 136, and the lower support layer 132. Thus, each of the vertical holes 170 can be formed such that it has a relatively large width in the first, second, and third mold layers 162, 164, and 166. For example, each of the vertical holes 170 formed in the lower support layer 132 can have a first maximum width 170W1, and each of the vertical holes 170 formed in the first mold layer 162 can have a second maximum width 170W2 that is larger than the first maximum width 170W1.Each of the vertical holes 170 formed in the second mold layer 164 can have a third maximum width 170W3, and each of the vertical holes 170 formed in the upper support layer 134 can have a fourth maximum width 170W4, which is smaller than the third maximum width 170W3. Each of the vertical holes 170 formed in the third mold layer 166 can have a fifth maximum width 170W5, which is larger than the first maximum width 170W1, and each of the vertical holes 170 formed in the middle support layer 136 can have a sixth maximum width 170W6, which is smaller than the fifth maximum width 170W5. The third maximum width 170W3 of each of the vertical holes 170 can be larger than the sixth maximum width 170W6 of each of the vertical holes 170. Referring to Fig. 18, the bottom electrodes BE can be formed in corresponding vertical holes 170. The bottom electrodes BE can be formed by essentially the same method as described with reference to Fig. 6. If the vertical holes 170 have lateral surfaces caused by the bending phenomenon described with reference to Fig. 5, adjacent bottom electrodes BE formed in the vertical holes 170 may have a reduced interval in the first, second, and third mold layers 162, 164, and 166. Accordingly, a leakage current may occur between the bottom electrodes BE. Referring to Fig. 1 and Fig. 19, the upper support layer 134 can be patterned to form an upper support pattern 130U with at least one upper opening 180U. The second mold layer 164 can be removed through the at least one upper opening 180U. Removing the second mold layer 164 can expose a top surface of the middle support layer 136 and lateral surfaces of the bottom electrodes BE. Referring to Fig. 1 and Fig. 20, the middle support layer 136 can be patterned to form a middle support pattern 130M with at least one middle opening 180M. The at least one middle opening 180M can expose middle lateral surfaces of the majority of first bottom electrodes BE1 and can also expose a top surface of the third mold layer 166. The third mold layer 166 can be removed through the at least one middle opening 180M. The removal of the third mold layer 166 can involve selective etching of the third mold layer 166 with respect to the upper support pattern 130U, the middle support pattern 130M, and the lower support layer 132. For example, the third mold layer 166 can be removed by performing an isotropic etching process using phosphoric acid.Removing the third mold layer 166 can partially expose a top surface of the lower support layer 132 and lateral surfaces of the bottom electrodes BE. The lower support layer 132 can be patterned to form a lower support pattern 130L with at least one lower opening 180L. The at least one lower opening 180L can expose lower lateral surfaces of the majority of first bottom electrodes BE1 and can also expose a top surface of the first mold layer 162. An upper section of the first mold layer 162 can be removed through the at least one lower opening 180L. Removing the upper section of the first mold layer 162 can partially expose the lateral surfaces of the bottom electrodes BE and can allow a lower section of the first mold layer 162 to remain on the dielectric intermediate layer 102. Referring to Fig. 21, the exposed lateral surfaces of the bottom electrodes BE can be partially etched. The exposed lateral surfaces of the bottom electrodes BE can be etched essentially by the same method as described with reference to Fig. 9, Fig. 10A, and Fig. 10B. Thus, each of the bottom electrodes BE can have a reduced width between the upper support pattern 130U and the middle support pattern 130M, between the middle support pattern 130M and the lower support pattern 130L, and below the lower support pattern 130L.While in some embodiments the exposed lateral surfaces of the bottom electrodes BE are partially etched, in each of the bottom electrodes BE a fifth recess 150e adjacent to a bottom surface 130ML of the central support pattern 130M can be formed, and a sixth recess 150f adjacent to a top surface 130MU of the central support pattern 130M can be formed, as described with reference to Fig. 15. A method for manufacturing a semiconductor device according to the present embodiment can be the same as the method for manufacturing a semiconductor device described with reference to Figs. 4 to 9, 10A, 10B, and 11, except for the differences mentioned above. According to the present inventive concepts, since the middle support pattern 130M is arranged between the upper support pattern 130U and the lower support pattern 130L, each of the plurality of bottom electrodes BE can have a larger aspect ratio compared to the bottom electrodes BE described with reference to Fig. 2. Thus, it may be possible to increase the capacitance of a capacitor containing the plurality of bottom electrodes BE by increasing its aspect ratio. Furthermore, each of the bottom electrodes BE can have a reduced width between the upper support pattern 130U and the middle support pattern 130M, between the middle support pattern 130M and the lower support pattern 130L, and below the lower support pattern 130L.Accordingly, a leakage current between the majority of ground electrodes BE can be minimized, or a leakage current due to an electrical short circuit between the majority of ground electrodes BE can be avoided. Fig. 22 shows a cross-sectional view along line II' from Fig. 1, illustrating a semiconductor device according to some embodiments of the present inventive concepts. To condense the description, the focus below is on the differences compared to the semiconductor device described with reference to Fig. 1, Fig. 2, Fig. 3A and Fig. 3B. Referring to Fig. 22, each of the plurality of ground electrodes BE can have a hollow cylindrical shape, one end of which (e.g., a bottom end) is closed. In this case, each of the plurality of ground electrodes BE can have an inner surface and an outer surface that face each other. The lower support pattern 130L can be arranged on and in contact with the lower outer surfaces of the majority of ground electrodes BE. The lower support pattern 130L can have at least one lower opening 180L, and this at least one lower opening 180L can extend along the lower outer surfaces of the majority of first ground electrodes BE1. The upper support pattern 130U can be arranged on and in contact with the upper outer surfaces of the majority of ground electrodes BE. The upper support pattern 130U can have at least one upper opening 180U, and this at least one upper opening 180U can extend along the upper outer surfaces of the majority of first ground electrodes BE1. The cover electrode TE can cover the outer surface of each of the plurality of bottom electrodes BE and can extend onto the inner surface of each of the plurality of bottom electrodes BE. The dielectric layer 140 can be placed between the cover electrode TE and the outer surface of each of the plurality of bottom electrodes BE and between the cover electrode TE and the inner surface of each of the plurality of bottom electrodes BE. A semiconductor device according to the present embodiment can be substantially the same as the semiconductor device described with reference to Fig. 1, Fig. 2, Fig. 3A and Fig. 3B, except for the differences mentioned above. Fig. 23 shows a circuit diagram illustrating a unit memory cell of a semiconductor device according to some embodiments of the present inventive concepts. Referring to Fig. 23, a memory cell MC can be arranged between an intersecting word line WL and a bit line BL, and can electrically connect the word line WL and the bit line BL. The memory cell MC can include a transistor TR connected to the word line WL and a capacitor CA connected to the transistor TR. The transistor TR can have a drain region connected to the bit line BL and a source region connected to the capacitor CA. The transistor TR can be configured to control a charge flow between the bit line BL and the capacitor CA. The memory cell MC can store data of "0" or "1" depending on whether the capacitor CA stores charge. Fig. 24 shows a top view partially depicting a semiconductor device according to some embodiments of the present inventive concepts. Fig. 25 shows a cross-sectional view along line II-II' from Fig. 24. Referring to Figures 24 and 25, a substrate 100 can contain a device insulating layer ST defining an active region ACT. The substrate 100 can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The device insulating layer ST can, for example, contain one or more silicon oxide layers, silicon nitride layers, and silicon oxynitride layers. When viewed from a top view, the active region ACT can have a bar shape and can be arranged such that its main axis is allowed to rest in an S-direction that intersects an X-direction and a Y-direction. The X-, Y-, and S-directions can intersect each other while being parallel to a cover surface 100U of the substrate 100. The substrate 100 can contain word conduction structures (WLS) that extend across the active region (ACT). The WLS can extend in the Y direction and can be arranged along the X direction. Each WLS can contain: a gate electrode (GE) buried in the substrate 100; a dielectric gate pattern (GI) between the gate electrode (GE) and the active region (ACT) and between the gate electrode (GE) and the device insulating layer (ST); and a gate closure pattern (CAP) on a cover face of the gate electrode (GE). The gate closure pattern (CAP) can have a cover face substantially coplanar with that of the gate closure pattern (CAP).In some embodiments, the gate closure pattern CAP can have a bottom surface that contacts a top surface of the dielectric gate pattern GI and can have opposing side walls that contact the active area ACT and / or the device insulating layer ST. In some other embodiments, the dielectric gate pattern GI can extend between the gate closure pattern CAP and the active area ACT and / or between the gate closure pattern CAP and the device insulating layer ST. The gate electrode GE can contain a conductive material. For example, the conductive material can be one of doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), or metal-semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.). The dielectric gate pattern GI can, for example, contain one or more silicon oxide layers, silicon nitride layers, and silicon oxynitride layers. The gate closure pattern CAP can, for example, contain one or more silicon oxide layers, silicon nitride layers, and silicon oxynitride layers. The active region ACT can contain a first impurity region SD1 and second impurity regions SD2, with the second impurity regions SD2 being spaced apart from each other across the first impurity region SD1. The first impurity region SD1 can be located within the active region ACT between a pair of adjacent word-guiding structures WLS. Each of the second impurity regions SD2 can be located within the active region ACT on one side of a corresponding pair of word-guiding structures WLS. For example, the second impurity regions SD2 can be spaced apart from each other across the pair of word-guiding structures WLS. The first impurity region SD1 can extend deeper into substrate 100 than the second impurity regions SD2. The first impurity region SD1 can contain the same conductive impurity as those in the second impurity regions SD2. A bitline structure BLS can be arranged on the substrate 100 and can extend over the wordline structures WLS. The bitline structure BLS can extend in the X direction. The bitline structure BLS can include: a conductive contact 210 electrically connected to the first contamination area SD1, a conductive line 230 on the conductive contact 210 extending in the X direction, and a barrier pattern 220 between the conductive contact 210 and the conductive line 230. The conductive contact 210 can touch the first contamination area SD1. The conductive contact 210 can have a bottom surface at a height lower than that of the top surface 100U of the substrate 100. The conductive contact 210 can have opposing lateral surfaces that are aligned with corresponding lateral surfaces of the conductive line 230.The bit conductor structure BLS can include a closure pattern 240 on a top face of the conductive conductor 230 and spacing patterns 250 on side surfaces of the conductive conductor 230. The closure pattern 240 and the spacing patterns 250 can extend in the X direction along the top face and the side surfaces of the conductive conductor 230. The spacing patterns 250 can cover side surfaces of the closure pattern 240, the blocking pattern 220, and the conductive contact 210, and can touch the first contamination area SD1. The conductive contact 210 can, for example, contain one of doped semiconductor materials (doped silicon, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal-semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.). The conductive line 230 and the barrier pattern 220 can each contain one of the following: conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal-semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide, etc.). The closure pattern 240 and the spacing patterns 250 can each contain, for example, one or more silicon nitride layers, silicon oxide layers, and silicon oxynitride layers. A dielectric intermediate layer 102 can be arranged on the substrate 100 and can cover the active region ACT, the device insulating layer ST, the word line structures WLS, and the bit line structure BLS. The dielectric intermediate layer 102 can, for example, contain at least one selected from silicon oxide, silicon nitride, and silicon oxynitride. Conductive contacts 110 and contact pads 115 can be arranged in the dielectric intermediate layer 102. The conductive contacts 110 can penetrate a lower section of the dielectric intermediate layer 102 and can form an electrical connection with corresponding second impurity regions SD2. The contact pads 115 can be arranged on corresponding conductive contacts 110. The contact pads 115 can penetrate an upper section of the dielectric intermediate layer 102 and can form electrical connections with corresponding conductive contacts 110. An insulating layer 120 can be arranged on the dielectric intermediate layer 102, and a capacitor structure CAS can be arranged on the insulating layer 120. According to some embodiments, the capacitor structure CAS can include the plurality of bottom electrodes BE, the lower support pattern 130L, the upper support pattern 130U, the top electrode TE, and the dielectric layer 140, which are described with reference to Figs. 1, 2, 3A, and 3B. According to some other embodiments, the capacitor structure CAS can further include the middle support pattern 130M, which is described with reference to Figs. 14 and 15. According to some other embodiments, the plurality of bottom electrodes BE of the capacitor structure CAS can each have a hollow cylindrical shape, one end of which is closed, as described with reference to Fig. 22. According to the present inventive concepts, a plurality of vertically spaced support patterns can be used to provide structural stability to a plurality of bottom electrodes, each having a relatively large aspect ratio. Each of the bottom electrodes can have a reduced width between the plurality of support patterns and below a lowermost one of the plurality of support patterns, thus minimizing leakage current between adjacent bottom electrodes or preventing leakage current due to an electrical short circuit between the plurality of bottom electrodes. Accordingly, a semiconductor device with improved electrical properties and a method for manufacturing the same can be provided.

Claims

Semiconductor device comprising: a memory cell capacitor configured to store data, the memory cell capacitor comprising: a plurality of bottom electrodes (BE) on a substrate (100) extending in a vertical direction (D2) with respect to a top surface (100U) of the substrate (100), the plurality of bottom electrodes (BE) being spaced apart from one another in a first direction (D1) parallel to the top surface (100U) of the substrate (100); an upper support pattern (130U) on upper lateral surfaces of the plurality of bottom electrodes (BE);and a lower support pattern (130L) on lower lateral surfaces of the plurality of ground electrodes (BE), wherein the lower support pattern (130L) is arranged between the substrate (100) and the upper support pattern (130U), and wherein a first ground electrode of the plurality of ground electrodes (BE) includes a first depression (150a) adjacent to a ground surface (130LL) of the lower support pattern (130L), wherein the first ground electrode further includes a third depression (150c) adjacent to a ground surface (130UL) of the upper support pattern (130U) and a fourth depression (150d) adjacent to a top surface of the upper support pattern (130U). Device according to claim 1, wherein the first bottom electrode further comprises a second recess adjacent to a top surface of the lower support pattern. Device according to claim 1 or 2, further comprising: a cover electrode (TE) which covers the plurality of bottom electrodes (BE), the upper support pattern (130U) and the lower support pattern (130L) and is arranged between the substrate (100) and the lower support pattern (130L) and between the lower support pattern (130L) and the upper support pattern (130U); and a dielectric layer (40, 140) between the cover electrode (TE) and both the upper support pattern (130U) and the lower support pattern (130L) and between the cover electrode (TE) and each of the plurality of bottom electrodes (BE). Device according to claim 3, wherein the first bottom electrode comprises a first part (P1) surrounded by the lower support pattern (130L) and a second part (P2) surrounded by the top electrode (TE), wherein the second part (P2) is below the first part (P1) in the vertical direction (D2), wherein the first recess (150a) is at a boundary between the first part (P1) and the second part (P2), and wherein a maximum width of the second part (P2) is greater than a maximum width of the first part (P1). Device according to claim 4, wherein the first bottom electrode comprises a third part (P3) surrounded by the top electrode (TE) and a fourth part (P4) surrounded by the upper support pattern (130U), wherein the third part (P3) is located between the fourth part (P4) and the first part (P1), wherein the second recess (150b) is located at a boundary between the first part (P1) and the third part (P3), wherein the third recess (150c) is located at a boundary between the third part (P3) and the fourth part (P4), and wherein a maximum width of the third part (P3) is greater than the maximum width of the first part (P1). Device according to claim 3, wherein the dielectric layer (40, 140) fills at least one section of the first depression (150a). Device according to claim 3, further comprising: a dielectric intermediate layer (102) between the substrate (100) and the plurality of bottom electrodes (BE); a plurality of conductive contacts in the dielectric intermediate layer (102) which is connected to the plurality of bottom electrodes (BE); and an insulating layer (120) between the dielectric intermediate layer (102) and the lower support pattern (130L), wherein the plurality of bottom electrodes (BE) penetrates the insulating layer (120) and is connected to the plurality of conductive contacts, wherein the top electrode (TE) is arranged between the lower support pattern (130L) and the insulating layer, and wherein the dielectric layer (40, 140) extends between the top electrode (TE) and the insulating layer. Device according to claim 3, wherein the upper support pattern (130U) includes at least one upper opening (180U), the lower support pattern (130L) includes at least one lower opening (180L), and the cover electrode (TE) is configured to fill the at least one upper opening (180U) and the at least one lower opening (180L). Device according to claim 8, wherein the at least one upper opening (180U) and the at least one lower opening vertically overlap each other. Device according to claim 1, wherein the first bottom electrode comprises: a first part (P1) in the lower support pattern (130L); and a second part (P2) below the lower support pattern (130L) in the vertical direction (D2), wherein a maximum width of the second part (P2) is greater than a maximum width of the first part (P1). Device according to claim 10, wherein the first bottom electrode further comprises: a second depression (150b) adjacent to a top surface (130LU) of the lower support pattern (130L); and a third depression (150c) adjacent to a bottom surface (130UL) of the upper support pattern (130U). Device according to claim 11, wherein the first bottom electrode further comprises a third part (P3) between the upper support pattern (130U) and the lower support pattern (130L), and wherein a maximum width of the third part (P3) is greater than the maximum width of the first part (P1). Device according to claim 12, wherein the first bottom electrode further comprises a fourth part (P4) surrounded by the upper support pattern (130U), wherein the third part (P3) is between the fourth part (P4) and the first part (P1), and wherein the maximum width of the third part (P3) is greater than a maximum width of the fourth part (P4). A method for fabricating a semiconductor device, comprising: sequentially forming a first mold layer (162), a lower support layer, a second mold layer (164), and an upper support layer (134) on a substrate (100); forming, on the substrate (100), a plurality of bottom electrodes (BE) penetrating the first mold layer (162), the lower support layer (132), the second mold layer (164), and the upper support layer (134); patterning the upper support layer (134) to form an upper support pattern (130U) having at least one upper opening (180U); removing the second mold layer (164) through the at least one upper opening (180U) to partially expose upper lateral surfaces of the plurality of bottom electrodes (BE); and patterning the lower support layer (132) to form a lower support pattern (130L) having at least one lower opening (180L) has;Removing at least one section of the first mold layer (162) through the at least one lower opening (180L) to partially expose the lower lateral surfaces of the plurality of bottom electrodes (BE); and after removing the at least one section of the first mold layer (162), etching the exposed lower lateral surfaces of the plurality of bottom electrodes (BE) and the exposed upper lateral surfaces of the plurality of bottom electrodes (BE), wherein a first bottom electrode of the plurality of bottom electrodes (BE) includes a first depression (150a) adjacent to a bottom surface (130LL) of the lower support pattern (130L), wherein the first bottom electrode further includes a third depression (150c) adjacent to a bottom surface (130UL) of the upper support pattern (130U) and a fourth depression (150d) adjacent to a top surface of the upper support pattern (130U).

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