Processing of ternary symbols

The method of determining and processing ternary symbols in ternary memory cells through multiple binary sequences addresses the challenge of converting ternary data into binary form, improving data processing and error correction in ternary memory systems.

DE102025101278B3Active Publication Date: 2026-04-30INFINEON TECHNOLOGIES AG
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Application Number
DE102025101278
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-01-15
Publication Date
2026-04-30
Estimated Expiration
2045-01-15

AI Technical Summary

Technical Problem

Existing technologies face challenges in efficiently processing and correcting errors in ternary memory cells, particularly in transforming ternary symbols into binary terms for effective data storage and retrieval.

Method used

A method and device for processing ternary symbols in ternary memory cells by determining a first binary sequence based on ternary symbols H and M, a second binary sequence based on H and M, and a third binary sequence with reduced bits, followed by forming a composite binary value, which is then processed.

Benefits of technology

This approach allows for efficient conversion of ternary symbols to binary sequences with reduced bit count, enhancing data processing efficiency and error correction in ternary memory systems.

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Abstract

An approach is proposed for processing a value determined from a set of N ternary memory cells, comprising the steps of: (i) reading the set of ternary memory cells and determining the ternary symbol H, M, or L contained in each ternary memory cell, (ii) determining a first binary sequence based on the ternary symbols H of the set of read ternary memory cells, (iii) determining a second binary sequence based on the ternary symbols H and M of the set of read ternary memory cells, (iv) determining a third binary sequence based on the first binary sequence and the second binary sequence, reducing the number of bits in the third binary sequence compared to the number of bits in the first binary sequence and the second binary sequence.(v) Determining a composite binary value based on the binary-coded first binary sequence and the binary-coded third binary sequence and (vi) processing the composite binary value.
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Description

[0001] From DE 10 2013 007 692 A1, it is known to transform binary data into ternary data and to store it as ternary data in a storage device. In this process, corrupted ternary data can be identified and corrected when read from the storage device.

[0002] DE 699 05 237 T2 relates to a method for correcting errors in a binary word stored in multi-level memory cells without requiring additional cells.

[0003] DE 10 2019 107 139 A1 describes a method for transforming a first binary signal read from a memory. The first binary signal is transformed into a second binary signal if the first binary signal is a codeword. Alternatively, the first binary signal is transformed into a predefined signal if the first binary signal is not a codeword.

[0004] It is known that more than two values ​​can be stored in a memory cell. For example, three different physical states (also referred to as three symbols) can be stored in a memory cell. The three physical states are called trivalent symbols, ternary symbols, ternary values, or ternary symbols, and the corresponding memory cell is called a trivalent memory cell or ternary memory cell.

[0005] When reading a ternary memory cell, different physical values ​​or values ​​derived from different physical values ​​can be determined. For example, different read currents can result from different resistance values ​​stored in a memory cell. The obtained physical value, e.g., read current, can be compared with at least one reference value to determine which ternary symbol was stored in the memory cell.

[0006] It is also an option to consider the time domain during readout in order to make an assignment. In this regard, reference is made, for example, to DE 10 2018 124 296 B4 or US 9,805,771 B2. These documents explain that a read current in a capacitor can be integrated to a voltage, and the time until a voltage reaches a specific reference value can be determined.

[0007] One task is to handle ternary memory cells efficiently and, in particular, to create an efficient way to process ternary symbols stored in ternary memory cells in binary terms.

[0008] The examples proposed herein can be based on at least one of the following solutions. In particular, combinations of the following features can be used to achieve a desired result. The features of the device can be combined with features of the method, or vice versa.

[0009] To solve the problem, a procedure is given for processing a value determined from a set of N ternary memory cells, comprising: - Reading the set of ternary memory cells and determining the ternary symbol H, M or L contained in the respective ternary memory cell, - Determining a first binary sequence based on the ternary symbols H of the set of read ternary memory cells, - Determining a second binary sequence based on the ternary symbols H and M of the set of read ternary memory cells, - Determining a third binary sequence based on the first binary sequence and the second binary sequence, where the number of bits of the third binary sequence is reduced compared to the number of bits of the first binary sequence and the second binary sequence, - Determining a composite binary value based on the binary-coded first binary sequence and the binary-coded third binary sequence, - Processing the composite binary value.

[0010] It should be noted that the ternary symbols H, M and L are used for differentiation and generally denote a first, second and third ternary symbol.

[0011] The respective ternary symbol can be determined depending on (at least) one physical value. It is also possible for the respective ternary symbol to be determined based on a value derived from a physical value.

[0012] Reading the set of N ternary memory cells thus yields a sequence of N ternary symbols, where each ternary symbol has a position within the sequence determined by the sequence. These positions are taken into account when determining the first and second binary sequences. For example, if the third ternary symbol within the sequence of N ternary symbols is a ternary symbol H, then the third bit of the first binary sequence has the value 1.

[0013] It is a further development that determining the first binary sequence includes: determining the first binary sequence, whereby only the ternary memory cell with the ternary symbol H is assigned the binary value 1 and the remaining ternary memory cells with either the ternary symbol M or the ternary symbol L are assigned the binary value 0.

[0014] It should be noted that, generally, the “value 0” represents a first binary value and the “value 1” represents a second binary value that is different from (i.e., inverse of) the first binary value.

[0015] It is a further development that includes determining the second binary sequence: determining the second binary sequence, whereby the binary value 1 is assigned to the ternary memory cells with the ternary symbol H or the ternary symbol M, and the binary value 0 is assigned to the remaining ternary memory cells with the ternary symbol L.

[0016] It is a further development that includes determining the third binary sequence: determining the third binary sequence, where the third binary sequence is determined from the bits of the second binary sequence, in whose place the bits of the first binary sequence are equal to 0.

[0017] The third binary sequence is therefore reduced by a number of bits where the first binary sequence equals 1.

[0018] It is a further development that determining the third binary sequence includes: determining the third binary sequence by removing from the second binary sequence the at least one bit for which the value 1 was determined in the first binary sequence.

[0019] It is a further development that, in the error-free case, the first binary sequence is a codeword of a first error code.

[0020] It is further training that the first error code is an N H -from-N-code, where N H The number of ternary values ​​H in the set of N ternary memory cells is.

[0021] It is a further development that, in the error-free case, the second binary sequence is a codeword of a second error code.

[0022] It is further training that the second error code contains at least one (NH+NMi)−off−N−code exhibits, whereby NMi an i-th number of ternary values ​​M in the N ternary memory cells.

[0023] If there is more than one value for i, the second error code is a multi-code. If i equals 1, it is a single error. (NH+NM')−from−N−code where NM' a number of ternary values ​​M in the N memory cells.

[0024] It is a further development that, in the error-free case, the third binary sequence is a codeword of a third error code, where the third error code has at least one NMi−out−(N−NH)−code exhibits.

[0025] It is a further education course that - the first binary sequence is uniquely and reversibly mapped to MSBs, - the third binary sequence is uniquely and reversibly mapped to LSBs, - the composite binary value is determined from MSBs and LSBs.

[0026] It is a further development that the ternary symbols H are determined by a readout in the time domain.

[0027] It is a further development that the ternary symbols M and L are determined by comparison with a reference value.

[0028] A device is also specified for processing a value determined from a set of N ternary memory cells, wherein the device is configured to - Reading the set of ternary memory cells from a memory and determining the ternary symbol H, M or L contained in the respective ternary memory cell, - Determining a first binary sequence based on the ternary symbols H of the set of read ternary memory cells, - Determining a second binary sequence based on the ternary symbols H and M of the set of read ternary memory cells, - Determining a third binary sequence based on the first binary sequence and the second binary sequence, where the number of bits of the third binary sequence is reduced compared to the number of bits of the first binary sequence and the second binary sequence, - Determining a composite binary value based on the binary-coded first binary sequence and the binary-coded third binary sequence, - Processing the composite binary value.

[0029] It is a further development that the device is a circuit arrangement or comprises one.

[0030] It is a further development that the storage is part of the device or designed separately from it.

[0031] The properties, characteristics, and advantages described above, as well as the manner in which they are achieved, are further explained in connection with the following schematic description of exemplary embodiments, which are further clarified in conjunction with the drawings. For clarity, identical or equivalent elements may be designated with the same reference numerals.

[0032] They show: Fig. Figure 1 shows an exemplary schematic circuit for determining a third binary sequence from a first binary sequence and a second binary sequence, wherein the first and second binary sequences are based on ternary symbols read from ternary memory cells. Fig. Figure 2 shows a table illustrating a dependency between control signals c1 to c7 and bits x1 to x8 of the binary sequence X. Fig.Figure 3 shows a table of a possible implementation (“mapping rule”) of the bits x1 to x8 of the binary sequence X onto 3 MSBs. Fig. Figure 4 shows a symbolic diagram with three frequency distributions for ternary symbols H, M and L over a cell stream Icell.

[0033] As an example, ternary memory cells are considered below, where each of the ternary memory cells can store the different ternary symbols H, M and L.

[0034] When reading a set of ternary memory cells, a mapping to binary values ​​is performed as an example. Further processing of these binary values ​​can be flexibly carried out using conventional digital technology.

[0035] For example, the following steps can be performed: (1) Reading several (e.g. a set or sequence) ternary memory cells and determining the ternary symbol H, M or L contained in the respective ternary memory cell (or the physical value corresponding to the ternary symbol). (2) Determining a first binary sequence based on the ternary symbols of the read ternary memory cells, assigning the binary value 1 only to the ternary memory cell with the ternary symbol H and assigning the binary value 0 to the remaining ternary memory cells with either the ternary symbol M or the ternary symbol L. (3) Determining a second binary sequence based on the ternary symbols of the read ternary memory cells, assigning the binary value 1 to the ternary memory cells with the ternary symbol H or M and assigning the binary value 0 to the remaining ternary memory cells with the ternary symbol L. (4) Determining a third binary sequence based on the first binary sequence and the second binary sequence, wherein the third binary sequence is determined from the bits of the second binary sequence where the bits of the first binary sequence are equal to 0. This involves reducing the third binary sequence by a number of bits where the first binary sequence is equal to 1. (5) Determining a composite binary value W based on a binary encoding of the first binary sequence and a binary encoding of the third binary sequence. (6) Processing the binary value W.

[0036] The third binary sequence can be determined from the second binary sequence by removing the bits from the second binary sequence for which the value 1 was assigned in the first binary sequence. The bits of the third binary sequence correspond to the memory cells for which the ternary symbols M or L were assigned during readout. The third binary sequence therefore has fewer bits than the first binary sequence and fewer bits than the second binary sequence.

[0037] Binary encoding can be understood here as follows: If there are n possible assignments for a sequence of m bits, then the number n can be used to uniquely identify one of the assignments by establishing an assignment rule that assigns each of the values ​​1 to n to one of the possible assignments. The number n can now be encoded in binary such that 2 k≥ n. In this case, binary encoding can be done with k bits. For example, a 1-out-of-9 code is defined by the fact that there are exactly n=9 possible assignments for the m=9 bits. To encode the numbers 1 to 9 in binary, 4 bits (2 4 =16) is necessary, whereby only 9 of the total possible 16 states are required by the assignment rule.

[0038] It should be noted that the binary values ​​0 and 1 have been assigned here as examples. Generally, there are two distinct values ​​in binary: "0" represents the first binary value and "1" the second. Accordingly, a binary description (interchanging 0 and 1) is possible. EXAMPLE: 8 STORAGE CELLS

[0039] The ternary symbols H, M and L exist.

[0040] N=8 ternary memory cells are considered as an example.

[0041] There are exactly 8 ways in which the 8 memory cells can be assigned exactly one single symbol H: The symbol H can occur in each of the 8 memory cells. The remaining 7 memory cells contain either the symbol M or the symbol L.

[0042] A first value, W1, indicates at which position of the 8 memory cells the symbol H is stored. The value range of W1 extends from 0 to 7; these 8 values ​​can be encoded with 3 bits (binary) (2 3 =8).

[0043] For each first value W1 there are 2 7 Possible assignments of the remaining 7 bits with the symbols M or L.

[0044] For example, when reading the 8 memory cells, the sequence MHMLLMLL determined. The first binary sequence is calculated as follows: 0 1 0 0 0 0 0 0.

[0045] Only the symbol H is represented by a 1 in the first binary sequence; otherwise, the symbols M and L are set to 0 for the first binary sequence.

[0046] The second binary sequence is given by 1 1 1 0 0 1 0 0.

[0047] The symbols H and M are replaced with a 1, and the symbols L with a 0.

[0048] The third binary sequence is determined based on the first binary sequence and the second binary sequence: first binary sequence: 0100 0000 second binary sequence: 1110 0100 third binary sequence: 1.10 0100

[0049] The dot in the third binary sequence indicates that it starts with the second binary sequence, but one bit is omitted (the bit that is equal to 1 in the first binary sequence). Thus, the third binary sequence has only 7 bits and reads: 1100100. The third binary sequence corresponds to a second value W2.

[0050] In this example, the value W stored in the 10 (=7+3) memory cells is determined by W=W1⋅27+W2.

[0051] The value W1 can be stored in three bits (three binary memory cells) and the value W2 can be stored in seven bits (seven binary memory cells).

[0052] Another way to write it is: W=W1|W2, where “|” signifies a concatenation of the two values ​​W1 and W2.

[0053] The first value W1 represents the three most significant bits (MSBs) and the second value W2 represents the seven least significant bits (LSBs) of the value W. EXAMPLE: 9 STORAGE CELLS

[0054] Below, we consider N=9 ternary memory cells in which ternary symbols H, M and L can be stored.

[0055] For example, 2 symbols H, 4 symbols M and 3 symbols L are stored in the 9 ternary memory cells.

[0056] For example, when reading the 9 ternary memory cells, the sequence HMHLMMLLM determined. The first binary sequence is thus: 1 0 1 0 0 0 0 0 0.

[0057] Only the symbol H is represented by a 1; otherwise, the symbols M and L are set to 0 for the first binary sequence. The 9 bits of the first binary sequence can be considered a codeword of a 2-out-of-9 code.

[0058] The second binary sequence is given by 111011001.

[0059] A 1 is set in the positions of the symbols H and M, and a 0 is set in the positions of the symbols L. The bits of the second binary sequence are a codeword of a 6-out-of-9 code.

[0060] The third binary sequence is formed using those bits of the second binary sequence where the bits of the first binary sequence are equal to 0: first binary sequence: 1 0 1 0 0 0 0 0 0 second binary sequence: 1 1 1 0 1 1 0 0 1 third binary sequence: . 1 . 0 1 1 0 0 1

[0061] The dots in the third binary sequence indicate that one bit is omitted here (because it is equal to 1 in the first binary sequence). Therefore, the third binary sequence has only 7 bits and reads: 1011001. The bits of the third binary sequence constitute a codeword of a 4-out-of-7 code. DETERMINATION OF TERNARY SYMBOLS

[0062] It is an option to determine the bits of the first and second binary sequences in the time domain or to determine them in the time domain taking into account an order, as described, for example, in DE 10 2018 124 296 B4 or in US 9,805,771.

[0063] It is also possible to determine the ternary symbols H within the time domain, meaning, for example, that the fastest reading of a ternary cell is assigned the ternary symbol H. A comparison can be made, for instance, with respect to a given set of cells (e.g., 8 cells): only the cell that delivers the highest cell stream most quickly is assigned the ternary symbol H. If, for example, there are to be 2 ternary symbols H for 8 cells, the two cells (out of the 8 cells) that deliver the highest cell stream most quickly are assigned the ternary symbols H.

[0064] Next, it is determined whether the remaining cells in the set should be assigned the ternary value M or the ternary value L. This is done, for example, by means of a threshold comparison: The threshold can be a reference current, which is used, for example, for the set of cells. If the cell current is below the reference current, the cell is assigned the ternary symbol L; otherwise (i.e., if the reference current is exceeded), the cell is assigned the ternary symbol M.

[0065] Fig.Figure 4 shows a symbolic diagram with three frequency distributions: 401 for the ternary symbol H, 402 for the ternary symbol Mund, and 403 for the ternary symbol L, over a cell current Icell. Frequency distribution 401 corresponds to the ternary symbol H, which, as explained above, identifies, for a set of (e.g., 8 or 9) ternary memory cells, at least one ternary memory cell that delivers the highest cell current. This can be done, for example, by comparing the set of read ternary memory cells in the time domain (the largest current, e.g., cell current or read current of the read memory cell, is integrated, and the cell with the largest read current is determined, i.e., the current that reaches a given voltage most quickly upon integration; see in particular the prior art mentioned above).

[0066] Once at least one ternary symbol H has been determined, it is ascertained for the remaining ternary memory cells (of the set mentioned here) whether they contained the ternary symbol L or the ternary symbol M. This is done by comparison with a reference current Iref: If the cell current of the read ternary memory cell is smaller than the reference current Iref, it is assigned the ternary symbol L; if the cell current is larger than the reference current Iref, it is assigned the ternary symbol M. It can be predefined whether the ternary symbol L or the ternary symbol M is assigned when the cell current is equal to the reference current Iref. MAPPING AND CONNECTING TO A VALUE W

[0067] To determine the first binary sequence, for example, the two fastest bits of the total 9 bits can be determined. To determine the second binary sequence, the six fastest bits of the 9 bits can be determined. The bits of the third binary sequence are those bits of the second binary sequence that are not the two fastest bits of the first binary sequence.

[0068] There are (92)=36>25 Different codewords for the 2-out-of-9 code, and therefore 36 different first binary sequences. Accordingly, there are (74)=35>25 different codewords of the 4-out-of-7 code and thus 35 different third binary sequences.

[0069] This allows a maximum of 10 bits to be encoded: 210<36⋅35=1260<211, if 2 memory cells store the ternary symbol H, 4 memory cells store the ternary symbol M, and 3 memory cells store the ternary symbol L.

[0070] One option is to use only 32 of the 36 possible codewords of the 2-out-of-9 code, since 32 can be represented as the value W1 by a five-digit binary value. These five bits are used as the MSB of the value W.

[0071] It remains an option to use only 32 of the 35 possible codewords of the 4-out-of-7 code and to represent the second value W2 accordingly as a five-digit binary value. The second value W2 is used as the LSB of the value W.

[0072] The stored value W is calculated as follows: W=W1|W2. Thus, when reading the 9 trivalent memory cells, a mapping to the 10-bit value W with 5 MSBs and 5 LSBs is obtained. MULTICODE WITH DIFFERENT TERNARY SYMBOLS M

[0073] It is an option to have a number N H to store a first ternary symbol H in the N ternary memory cells, and in the NN HMemory cells in which the ternary symbol H is not stored, a further number NM1 or NM2 or NM3 or to store a further number of ternary symbols M. For example, the difference between the number of stored ternary symbols M can be at least 2.

[0074] The following example assumes that the other numbers NM1, NM2 and NM3 be used: The first binary sequence is again a codeword of an N. H -determined from N codes. The second binary sequence consists of code words of a - (NH+NM1)−from−N−codes, - (NH+NM2)−from−N−codes or - (NH+NM3)−from−N−codes A code that includes multiple error codes can also be called a multi-code. The third binary sequence yields code words. - one NM1−from−(N−NH)−codes, - one NM2−out−(N−NH)−codes and - one NM3−from−(N−NH)−codes.

[0075] For example, is N=9,NH=1,NM1=1,NM2=3,NM3=5,NM4=7, The bits of the first binary sequence form a codeword of the 1-out-of-9 code, the bits of the second binary sequence a codeword of the 2-out-of-9 code, the 4-out-of-9 code, the 6-out-of-9 code, or the 8-out-of-9 code. The bits of the third binary sequence form a codeword of the 1-out-of-8 code, the 3-out-of-8 code, the 5-out-of-8 code, and the 7-out-of-8 code. EXAMPLE EXECUTION WITH N=8

[0076] Fig.Figure 1 shows an exemplary schematic circuit for determining a third binary sequence from a first binary sequence and a second binary sequence. Here, the number N of the ternary memory cells is 8. When reading the ternary memory cells, a first binary sequence X with bits x1 to x8 and a second binary sequence Y with bits y1 to y8, each with 8 bits, are determined.

[0077] When reading the ternary memory cells, one ternary symbol H and three ternary symbols M are determined for 8 ternary memory cells.

[0078] The binary sequence X (first binary sequence) thus represents one of the 8 possible codewords of the 1-out-of-8 code, where exactly one single bit is equal to 1 and all other 7 bits are equal to 0.

[0079] The binary sequence Y (second binary sequence) is determined as codewords of a 4-out-of-8 code. The four binary values ​​1 result at the positions where the ternary memory cell contains either the ternary symbol H or the ternary symbol M (but not the ternary symbol L). The binary sequence Y therefore consists of four ones and four zeros.

[0080] The bits of a binary sequence Z (third binary sequence) are formed from those bits of the binary sequence Y that correspond to the bits of the binary sequence X that are equal to 0. If the bit of the binary sequence X is equal to 1, it is omitted from the binary sequence Z. Therefore, the binary sequence Z has 7 bits.

[0081] An example of the bit assignment and the resulting binary sequence Z is as follows: Binary sequence X: 0 1 0 0 0 0 0 0 Binary sequence Y: y1 y2 y3 y4 y5 y6 y7 y8 Binary sequence Z: y1 y3 y4 y5 y6 y7 y8

[0082] In forming the binary sequence Z, the second bit y2 of the binary sequence Y was removed because the bit of the binary sequence X is equal to 1 at this point.

[0083] Fig.1 comprises a register 19 for storing the binary sequence X, a register 111 for storing the binary sequence Y, and a register 110 for storing the binary sequence Z. Furthermore, it shows Fig. Seven multiplexers 11 to 17, each having a control input to connect either a 0 input or a 1 input to an output. A combinational circuit 18 is also provided, which, based on bits x1 to x8 of the binary sequence X, determines control signals c1 to c7, each of which is applied to one of the control inputs of the multiplexers 11 to 17.

[0084] Fig. Figure 2 shows a table illustrating the dependence of the control signals c1 to c7 on the bits x1 to x8 of the binary sequence X. This dependence can be implemented, for example, by means of a combinational circuit 18.

[0085] For example, regarding the second row of the table with X=01000000 for the control signals c1 to c7 0111111.

[0086] Multiplexer 11 is connected to input 0, while multiplexers 12 through 17 are connected to input 1. The output of multiplexer 11 provides the value of bit y1 as the first bit of the binary sequence Z. The second bit of the binary sequence Z is the value of bit y3 (multiplexer 12 is connected to input 1), and so on. As a result, the value of bit y2 is eliminated from the binary sequence Z.

[0087] Fig.Figure 3 shows a table of a possible mapping rule for bits x1 to x8 of the binary sequence X onto 3 MSBs. There are exactly 8 different binary sequences X, and a unique identification (or reversible unique assignment) of one of these binary sequences can be achieved using three binary states. The combinational circuit 18 also provides this mapping rule for the 3 MSBs. This mapping rule can be implemented using fixed programming (e.g., using a read-only memory) or a combinational circuit.

[0088] The bits of the binary sequence Z can form 35 different codewords of the 3-out-of-7 code. If only 32 of the 35 possible codewords are used, these 32 codewords can be represented (i.e., uniquely encoded) using 5 bits (each assignment of the 5 bits identifies exactly one of the 32 codewords). Such a conversion or mapping rule can be implemented using fixed programming (e.g., using a read-only memory) or a combinational circuit.

[0089] In this example, this results in 5 LSBs, which can be combined with the aforementioned 3 MSBs to form a value W. The result is that a selection of ternary values, which can be stored in 8 ternary memory cells, is mapped to binary values ​​W, where each binary value has an MSB part of 3 bits and an LSB part of 5 bits.

Claims

[1] A method for processing a value determined from a set of N ternary memory cells, comprising: - Reading the set of ternary memory cells and determining the ternary symbol H, M or L contained in the respective ternary memory cell, - Determining a first binary sequence based on the ternary symbols H of the set of read ternary memory cells, - Determining a second binary sequence based on the ternary symbols H and M of the set of read ternary memory cells, - Determining a third binary sequence based on the first binary sequence and the second binary sequence, where the number of bits of the third binary sequence is reduced compared to the number of bits of the first binary sequence and the second binary sequence, - Determining a composite binary value based on the binary-coded first binary sequence and the binary-coded third binary sequence, - Processing the composite binary value. [2] Method according to claim 1, wherein determining the first binary sequence comprises: determining the first binary sequence, wherein only the ternary memory cell with the ternary symbol H is assigned the binary value 1 and the remaining ternary memory cells with either the ternary symbol M or the ternary symbol L are assigned the binary value 0. [3] Method according to any of the preceding claims, wherein determining the second binary sequence comprises: determining the second binary sequence, wherein the binary value 1 is assigned to the ternary memory cells with the ternary symbol H or the ternary symbol M and the binary value 0 is assigned to the remaining ternary memory cells with the ternary symbol L. [4] Method according to any of the preceding claims, wherein determining the third binary sequence comprises: determining the third binary sequence, wherein the third binary sequence is determined from the bits of the second binary sequence in whose place the bits of the first binary sequence are equal to 0. [5] Method according to any of the preceding claims, wherein determining the third binary sequence comprises: determining the third binary sequence by removing from the second binary sequence the at least one bit for which the value 1 was determined in the first binary sequence. [6] Method according to any of the preceding claims, wherein in the error-free case the first binary sequence is a codeword of a first error code. [7] Method according to claim 6, wherein the first error code is an N H -from-N-code, where N H The number of ternary values ​​H in the set of N ternary memory cells is. [8] Method according to one of claims 6 or 7, wherein in the error-free case the second binary sequence is a codeword of a second error code. [9] Method according to claim 8, wherein the second error code includes at least one (NH+NMi)−off−N−code exhibits, whereby NMi an i-th number of ternary values ​​M in the N ternary memory cells. [10] The method of claim 9, wherein in the error-free case the third binary sequence is a codeword of a third error code, wherein the third error code is at least one NMi−out−(N−NH)−code exhibits. [11] Method according to any one of the preceding claims, - where the first binary sequence is uniquely and reversibly mapped to MSBs, - where the third binary sequence is uniquely mapped to LSBs in a reversible manner, - where the composite binary value is determined from MSBs and LSBs. [12] Method according to any of the preceding claims, wherein the ternary symbols H are determined by reading in the time domain. [13] Method according to claim 12, wherein the ternary symbols M and L are determined by comparison with a reference value. [14] Device for processing a value determined from a set of N ternary memory cells, wherein the device is configured to - Reading the set of ternary memory cells from a memory and determining the ternary symbol H, M or L contained in the respective ternary memory cell, - Determining a first binary sequence based on the ternary symbols H of the set of read ternary memory cells, - Determining a second binary sequence based on the ternary symbols H and M of the set of read ternary memory cells, - Determining a third binary sequence based on the first binary sequence and the second binary sequence, where the number of bits of the third binary sequence is reduced compared to the number of bits of the first binary sequence and the second binary sequence, - Determining a composite binary value based on the binary-coded first binary sequence and the binary-coded third binary sequence, - Processing the composite binary value. [15] Device according to claim 14, wherein the device is a circuit arrangement. [16] Device according to one of claims 14 or 15, wherein the storage device is part of the device or separate from it.

Citation Information

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