Integrated circuit structures with uniform grid metal gate and trench contact cut for CFET architectures

Abstract

Integrated circuit structures with a uniform grid-metal gate and trench contact interface for cFET architectures are described. In one example, a structure comprises a first vertical stack of horizontal nanowires above a second vertical stack of horizontal nanowires, with an intermediate insulator structure positioned vertically between the first and second vertical stacks. A gate structure is located above the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intermediate insulator structure. A conductive trench contact is adjacent to the gate structure. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact.The first and second dielectric cut plug structures extend through the gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.

Description

STATE OF THE ART In recent decades, the scaling of features in integrated circuits has been a driving force behind the ever-expanding semiconductor industry. Scaling down to ever smaller features enables increased densities of functional units on the limited usable area of ​​semiconductor chips. For example, shrinking transistor size allows for the integration of a greater number of memory or logic devices onto a single chip, enabling the production of higher-capacity products. However, this trend toward ever-increasing capacities also presents challenges. The need to optimize the performance of each device is becoming increasingly critical. In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more common with the ongoing downward scaling of device dimensions. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and because they allow for a less complex tri-gate fabrication process. Another challenge in device fabrication is maintaining improved mobility and short-channel control when scaling microelectronic device dimensions below the 10-nanometer (nm) node. Nanowires used in device fabrication offer improved short-channel control. However, scaling up multi-gate and nanowire transistors is not without consequences. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and the sheer number of these basic components fabricated in a given area increases, the limitations on the lithographic processes used to pattern them have become overwhelming. In particular, there can be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A-1D illustrate oblique cross-sectional views representing various operations in methods for fabricating an integrated circuit structure with a uniform grid-metal gate and trench contact cut, according to one embodiment of the present disclosure. Figures 1E-1G illustrate oblique cross-sectional views representing various operations in methods for fabricating an integrated circuit structure with contacts to connections for a uniform grid-metal gate and trench contact cut, according to one embodiment of the present disclosure. Figure 1H shows an oblique cross-sectional view and planar cross-sectional views representing an integrated circuit structure with contacts to connections for a uniform grid-metal gate and trench contact cut, according to one embodiment of the present disclosure.Figures 1I-1J illustrate cross-sectional views representing an integrated circuit structure with a uniform lattice metal gate and trench contact cut for cFET architectures according to an embodiment of the present disclosure. Figure 2A illustrates a cross-sectional view of an integrated circuit structure with a fin and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Figure 2B illustrates a cross-sectional view of an integrated circuit structure with a fin and a metal gate dielectric cut plug according to an embodiment of the present disclosure. Figure 3A illustrates a cross-sectional view of an integrated circuit structure with nanowires and a pre-metal gate dielectric plug according to an embodiment of the present disclosure.Figure 3B illustrates a cross-sectional view of an integrated circuit structure with nanowires and a metal-gate dielectric cut-off plug according to an embodiment of the present disclosure. Figure 4A illustrates a cross-sectional view of an integrated circuit structure with nanowires and a pre-metal-gate dielectric cut-off plug according to an embodiment of the present disclosure. Figure 4B illustrates a cross-sectional view of an integrated circuit structure with nanowires and a metal-gate dielectric cut-off plug according to an embodiment of the present disclosure. Figures 5A-5C show top views of comparable integrated circuit structures according to an embodiment of the present disclosure. Figures 6A-6C show cross-sectional views of comparable integrated circuit structures according to an embodiment of the present disclosure.Figures 7A-7J illustrate cross-sectional views of various operations in a method for fabricating a gate-all-around integrated circuit structure according to an embodiment of the present disclosure. Figure 8 illustrates a cross-sectional view of a non-planar integrated circuit structure along a gate line according to an embodiment of the present disclosure. Figure 9 illustrates cross-sectional views through nanowires and fins for a non-endcap architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure. Figure 10 illustrates cross-sectional views representing various operations in a method for fabricating a self-aligned gate endcap (SAGE) structure with gate all-round devices according to an embodiment of the present disclosure.Figure 11A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure. Figure 11B illustrates a source or drain cross-sectional view of the nanowire-based integrated circuit structure from Figure 11A along the a-a' axis according to an embodiment of the present disclosure. Figure 11C illustrates a channel cross-sectional view of the nanowire-based integrated circuit structure from Figure 11A along the b-b' axis according to an embodiment of the present disclosure. Figure 12 illustrates a computer device according to an implementation of an embodiment of the disclosure. Figure 13 illustrates an interposer comprising one or more embodiments of the disclosure. DESCRIPTION OF THE EXECUTION FORMS Integrated circuit structures with a uniform grid-metal-gate and trench contact interface for cFET architectures and methods for fabricating integrated circuit structures with a uniform grid-metal-gate and trench contact interface for cFET architectures are described. Numerous specific details, such as specific integration and material specifications, are set forth in the following description to provide a comprehensive understanding of embodiments of this disclosure. It is understood by a person skilled in the art that embodiments of this disclosure can also be implemented in practice without these specific details. In other cases, known features, such as the layout of integrated circuits, are not described in detail in order to avoid unnecessarily obscuring the embodiments of this disclosure.Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. Certain terminology may be used in the following description solely for reference purposes and is therefore not intended to be restrictive. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings being referenced. Terms such as "front," "back," "rear," and "side" describe the orientation and / or location of parts of the component within a uniform but arbitrary frame of reference, which becomes clear by referring to the text and the associated drawings in which the component in question is described. Such terminology may include the words explicitly mentioned above, derivatives thereof, and words with similar meanings. The embodiments described here can involve front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first stage of integrated circuit (IC) manufacturing, in which the individual devices (e.g., transistors, capacitors, resistors, etc.) are structured within the semiconductor substrate or semiconductor layer. FEOL generally covers everything up to (but not including) the deposition of metallic interconnect layers. Following the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires). The embodiments described here can relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second stage of IC manufacturing, in which the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected via wiring on the wafer, such as the metallization layer(s). BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. During the BEOL stage of the manufacturing process, contacts (contact pads), interconnects, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added in BEOL. The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both. Even if an exemplary processing scheme is illustrated using an FEOL processing scenario, these approaches can also be applied to BEOL processing. Likewise, even if an exemplary processing scheme is illustrated using a BEOL processing scenario, these approaches can be equally applied to FEOL processing. One or more embodiments described herein are directed towards integrated circuit structures fabricated to include a uniform grid of metal gate and trench contact cuts, which may be referred to as a pixel structure. One or more embodiments described herein relate to pixel cuts for complementary field-effect transistor (cFET) or cFET technology. It is understood that, unless otherwise specified, references to nanowires herein may refer to nanowires, nanoribbons, or nanosheets. One or more embodiments described herein relate to contacts for connections to cut structures with plugs therein. To provide context, it may be advantageous to simplify a trench contact and polycut (gate-cut) process, for example to improve fixture performance and reduce process variation. According to one or more embodiments of the present disclosure, a metal gate process and a trench contact without plugs are performed. A single, infinitely long grid is then used to generate every possible trench contact and gate cut plug (as a unified dielectric cut plug). The resulting structure can be referred to as a pixel structure. The pixel structure can then be subjected to local plug removal to effectively rejoin or reconnect cut gate sections and / or rejoin cut contact sections. As an exemplary processing scheme, Figures 1A-1D illustrate oblique cross-sectional views representing various operations in methods for fabricating an integrated circuit structure with a uniform grid-metal gate and trench contact cut, according to one embodiment of the present disclosure. It is understood that the described and illustrated embodiments may also be applicable to a fin structure instead of a stack of nanowires, nanoribbons, or nanosheets. Referring to Fig. 1A, a starter structure 100 is shown prior to a nanowire exposure and replacement gate process. The starter structure 100 has sub-fins 104 extending from a substrate 102, such as silicon sub-fins extending from a silicon substrate. The sub-fins 104 extend through a shallow trench insulation (STI) structure 106, such as a silicon oxide or silicon dioxide trench insulation structure. One or more stacks of horizontal nanowires 108, such as stacks of horizontal silicon nanowires, are located above a corresponding sub-fin 104. In this stage, an intervening sacrificial layer 110, such as an intervening silicon germanium sacrificial layer, alternates with the horizontal nanowires 108 in the stacks of nanowires. A sacrificial gate oxide 112, such as a silicon oxide or silicon dioxide sacrificial gate oxide, is located above the stacks of horizontal silicon nanowires 108.A sacrificial gate structure 114, such as a polysilicon sacrificial gate structure, is located above the sacrificial gate oxide 112 and above channel regions of the stacks of horizontal nanowires 108. A hard mask layer 116, such as a silicon nitride hard mask layer, may be contained on the sacrificial gate structure 114, as shown. A gate spacer forming material 118, such as a silicon nitride gate spacer forming material 118, is contained above and along the sides of the sacrificial gate structure 114. Referring again to Fig. 1A, epitaxial source or drain structures 120, such as epitaxial silicon or epitaxial silicon germanium source or drain structures, are located at the ends of the stacks of horizontal nanowires 108 at positions between adjacent sacrificial gate structures 114. Internal gate spacers 126, such as internal silicon nitride gate spacers 126, can be formed by inserting the intervening sacrificial layer 110 and depositing the internal gate spacer material prior to the formation of the epitaxial source or drain structures 120. The epitaxial source or drain structures 120 can be formed above a lower spacer depression filling 122, such as a silicon nitride spacer filling, which can be formed simultaneously with internal gate spacers 126 and / or gate spacer forming material 118.A contact insulator structure 128, such as a silicon oxide or silicon dioxide structure, is contained above the epitaxial source or drain structures 120 and can occupy locations where conductive trench contacts are ultimately formed. Referring to Fig. 1B, the starter structure 100 is subjected to a replacement gate and nanowire exposure process flow. In particular, the structure 100 is planarized and / or etched to expose the sacrificial gate structure 114. Planarization can remove the hard mask layer 116, form gate spacers 118A from the gate spacer forming material 118, and form a planarized contact insulator structure 128A. The sacrificial gate structure 114 and the sacrificial gate oxide 112 are then removed by selective etching. The sacrificial intermediate layer 110 is then removed by selective etching. A permanent gate dielectric structure 132, such as a gate dielectric structure incorporating a high-k dielectric layer, is then formed in the resulting trenches and cavities, including around the channel region of each of the nanowires 108.A permanent gate electrode 134, such as a gate electrode containing a metal, is formed over the permanent gate dielectric structure 132, including at locations around the channel regions of the nanowires 108. A gate insulating cap layer 136, such as a silicon nitride cap layer, can be formed on the resulting permanent gate electrode structure 134, for example, by vacating the gate structure and filling it with a dielectric. Referring to Fig. 1C and Fig. 1D, a pixel structure 149 is shown with a cross-sectional view of an exposed trench contact (Fig. 1C) and with a cross-sectional view of an exposed gate structure (Fig. 1D). The pixel structure 149 is formed by first replacing the planarized contact insulator structure 128A with trench contact material. At this stage, the trench contact material is “infinite” along each contact trench extending across all source / drain structures along a given trench contact line, effectively short-circuiting all trench contacts along a single trench contact line. Likewise, at this stage, the gate electrode material is “infinite” along each gate trench extending across all nanowire stack channel regions along a given gate line, effectively short-circuiting all gates along a single gate line contact line.The gate insulation cap layer 136 may have been removed at this stage. Subsequently, non-selective cuts are made along a direction orthogonal to the gate and trench contact lines, effectively cutting and insulating all trench contacts along a single trench contact line and all gate electrodes along a single gate line. The cuts are then filled with dielectric plugs 148 extending through all trench contact lines and all gate lines. The resulting “pixel” structure 149 has a plurality of insulated / cut trench contact structures 140, which may have an insulating cap 142 on them. A trench contact structure 140 may be in contact with a silicide layer 146 on a corresponding epitaxial source or drain structure 120 at a location exposed by an etch stop layer 144. The resulting “pixel” structure 149 also has a plurality of insulated / cut gate structures, e.g.Structures that feature a cut-gate dielectric 132A and a cut-gate electrode 134A. Referring again to Fig. 1C and Fig. 1D, an integrated circuit structure 149 according to an embodiment of the present disclosure has a vertical stack of horizontal nanowires 108. A gate electrode 134A is located above the vertical stack of horizontal nanowires 108. A conductive trench contact 140 is adjacent to the gate electrode 134A. A dielectric sidewall spacer 118A is located between the gate electrode 134A and the conductive trench contact 140. A first dielectric cut-plug structure 148 extends through the gate electrode 134A, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. A second dielectric cut-plug structure 148 extends through the gate electrode 140, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140.The second dielectric cut plug structure 148 is laterally spaced from and parallel to the first dielectric cut plug structure 148. It is understood that the pixel structure 149 can then be subjected to selective reassembly / reconnection of individual isolated / cut-trench contact structures 140 and / or selective reassembly / reconnection of individual isolated / cut-gate structures 132A / 134A. In another aspect, one or more embodiments described herein are directed, for example, to integrated circuit structures manufactured using a trench-contact plug removal (TCN plug removal) and / or metal-gate cut-plug removal (MGC plug removal) etching process, e.g., as the removal of a selective section of a dielectric cut-plug structure. In such an embodiment, dimensional modification etching is used. To provide context, complex processing schemes can be used to effectively remove metal gate cut plugs (MGC plugs) added during trench contact plug structuring (TCN plug structuring) to restore continuity in a gate metal. Such an approach may involve a lithography pass, multiple sacrificial layer depositions, etching, and cleaning, which is expensive and can introduce more variation. According to one or more embodiments disclosed herein, such an approach is avoided to improve robustness and simplify an MGC plug removal process. Advantages of implementing embodiments disclosed herein may include a reduction in process costs and an increase in robustness (e.g., self-aligned plug removal may provide maximum process span). To provide further context, local connections such as trench vias and / or gate vias can be a key aspect of a pixel architecture. According to one or more embodiments of the present disclosure, after the formation of a conductive connection, a connection between a conductive via and a conductive link is established by extending the conductive via to overlap with a corresponding trench contact and / or gate electrode. As an exemplary processing scheme, Figures 1E-1G illustrate oblique cross-sectional views representing various operations in methods for fabricating an integrated circuit structure with contacts to connections for a uniform grid-metal gate and trench contact cut, according to one embodiment of the present disclosure. Figure 1H shows an oblique cross-sectional view and planar cross-sectional views representing an integrated circuit structure with contacts to connections for a uniform grid-metal gate and trench contact cut, according to one embodiment of the present disclosure. It is understood that the described and illustrated embodiments may also be applicable to a fin structure instead of a stack of nanowires, nanoribbons, or nanosheets. Referring to Fig. 1E, a starter structure 150 is shown after metal-gate and trench contact cutting processes, e.g. as an exemplary version of the pixel structure 149 from Fig. 1C and Fig. 1D. The starter structure 150 includes a gate electrode 158, such as a metal-gate electrode, and a gate dielectric layer 156, such as a high-k-gate dielectric layer. Dielectric sidewall spacers, which may have external spacer sections 162 and internal spacer sections 164A, such as silicon nitride or carbon-doped silicon nitride spacers, are located along sides of the gate electrodes 158 and the gate dielectric layers 156. Each gate structure 158 / 156 is located over one or more plurality of horizontally stacked nanowires (or nanoribbons or nanosheets or alternatively one or more fins) 154, such as silicon nanowires (which, as shown, may be located over corresponding sub-fins 152). Referring again to Fig. 1E, epitaxial source or drain structures 160, such as epitaxial silicon or silicon germanium source or drain structures, are laterally adjacent to the dielectric sidewall spacers 162 / 164A. In one embodiment, each of the epitaxial source or drain structures 160 is located at one end of a corresponding plurality of horizontally stacked nanowires (or at one end of a corresponding fin) covered by a gate electrode 158 and a gate dielectric layer 156. In another embodiment, the epitaxial source or drain structures 160 are located vertically above remaining internal spacer sections 164B, as shown. Referring again to Fig. 1E, a conductive trench contact 168, such as a contact structure with a conductive lining and a tungsten (W) filler material, is located over upper portions of the epitaxial source or drain structures 160. In one embodiment, a silicide layer 166 is located between the conductive trench contacts 168 and the corresponding epitaxial source or drain structures 160, as shown. Dielectric cut-plug structures 170, such as dielectric SiN, SiON, SiO, and / or SiC plugs, cut selected areas of the gate electrode 158 (such as gate cut-plug portions) and extend into portions of the conductive trench contact 168 (such as conductive trench contact cut-plug portions), completely insulating them, e.g., as in a pixel structure, as shown.In one embodiment, one or more of the dielectric cut plug structures 170 interrupt the continuity of the trench contact 168 at a point that is to be electrically connected. In previous approaches, a next-level intermediate connection could be used to electrically join two parts of a conductive trench contact 168 that are otherwise insulated by a dielectric clevis plug 170 extending into the conductive trench contact 168. Alternatively, according to one or more embodiments of the present disclosure, part of the dielectric clevis plug 170 is removed and replaced by a conductive connecting element, as described, for example, in connection with Fig. 1F. As shown in Fig. 1F, portions of the dielectric cut plug structures 170 are subjected to a masking and dielectric etching process to obtain recessed dielectric cut plug structures 170A. In one embodiment, the etching process is selectively directed against the conductive trench contact 168. In another embodiment, the dielectric etching process is performed using an anisotropic etching process, an angled directional etching process, an isotropic etching process, or combinations thereof. In each case, the dielectric etching process ensures that the recessed dielectric cut plug structures 170A have a recess that is laterally adjacent to the conductive trench contacts and exposes one side of each of the conductive trench contacts 168 at locations where the dielectric cut plug structures 170 are recessed.A conductive material is then formed in the resulting depression and subsequently planarized to create one or more conductive connections, such as conductive connections 172 and 174. Conductive connection 174 occupies a depression of a dielectric-cut plug structure 170A and connects a first and a second conductive contact section 168A along a longitudinal direction of the first and second conductive contact sections 168A. Conductive connection 172 occupies a depression of a dielectric-cut plug structure 170A and couples a first and a second gate electrode section 158A along a longitudinal direction of the first and second gate electrode sections 158A. In one embodiment, the conductive connection 174 can have the same or a different conductive composition than the sections of the recessed conductive trench contact 168A (e.g., they can all be made of tungsten). In both cases, seams can be observed between the conductive connection 174 and the first and second structures of the conductive trench contact 168A, as shown. In another embodiment, the conductive connection 172 can have the same or a different conductive composition than the gate electrode sections 158A (e.g., they can all be made of tungsten). In both cases, seams can be observed between the conductive connection 172 and the first and second structures of the conductive trench contact 158A, as shown. As shown in Fig. 1G, a dielectric layer 176, e.g., a dielectric interlayer material, is formed over the structure of Fig. 1F and structured to include openings that expose the conductive junctions 172 and 174. A conductive material is then formed in the openings and subsequently planarized to provide a structure 189 that includes one or more conductive vias, such as conductive vias 178 and 180. In one embodiment, the conductive via 178 is a gate-contact via and terminates on a conductive junction 172. In another embodiment, the conductive via 180 is a trench-contact via and terminates on a conductive junction 174. Referring to Fig. 1H, cross-sectional views along the dashed lines of structure 189 highlight features of the structure. The upper right cross-section shows a conductive via 178 (e.g., a gate-contact via) in contact with the conductive connection 172. In one embodiment, the conductive via 178 overlaps the first and second gate-electrode sections 158A, which can lead to an improved connection for linked gate-electrode sections 158A compared to simply contacting the conductive connection 172. In another embodiment, the top surfaces of the conductive connection 172 and the linked gate-electrode sections 158A are coplanar, and the conductive via 178 is located on the coplanar surfaces, as shown. The lower right cross-section shows a conductive via 180 (e.g., a trench contact via) in contact with the conductive connection 174. In one embodiment, the conductive via 180 overlaps the first and second conductive trench contact sections 168A, which can lead to an improved connection for linked conductive trench contact sections 168A compared to simply landing on the conductive connection 174. In another embodiment, the top surfaces of the conductive connection 174 and the linked conductive trench contact sections 168A are coplanar, and the conductive via 180 is located on the coplanar surfaces, as shown. In another aspect, there may be applications where a pixel architecture is suitable for one area of ​​a die and a non-pixel architecture is suitable for another area of ​​a die. According to one or more embodiments of the present disclosure, selected pixel-only regions on a die have plugs defined by metal gate cuts (MGC) for both trench contact (TCN) and gate. According to one or more embodiments of the present disclosure, non-pixel regions have MGC-defined plugs for gate and TCN plugs for source or drain (S / D). According to one or more embodiments of the present disclosure, a pixel region has TCN and gate connections that link devices. According to one or more embodiments of the present disclosure, a non-pixel region has TCN connections, wherein newly connected TCNs interrupted by MGC and gate have no connection because poly cut (PCT) defines a final connectivity. In another aspect, pixel cuts and plugs are implemented for complementary field-effect transistor and cFET technologies, respectively. To provide context, a cFET architecture is an architecture in which two transistors are stacked on top of each other. In a cFET architecture, the upper device can be either NMOS or PMOS, and the lower device is typically the opposite type to the upper one. To provide further context, a nanowire-based (e.g., ribbon FET) process is currently reaching manufacturing maturity. However, downscaling from ribbons may reach its feature size limit after a few technology generations. To keep Moore's Law alive, new transistor architectures beyond ribbon FET are being explored. Complementary field-effect transistor (cFET) fabrication technology is expected to become an established process. In the cFET process, the N-channel (nch) and P-channel (pch) are vertically stacked. One embodiment implements a pixel-based process flow for a cFET architecture. As exemplary structures, Figs. 1I-1J illustrate cross-sectional views representing an integrated circuit structure with uniform grid metal gate and trench contact section for cFET architectures according to an embodiment of the present disclosure. Referring to Fig. 1I, a gate section in a channel region of an integrated circuit structure 190A shows a first vertical stack of horizontal nanowires 192B above a second vertical stack of horizontal nanowires 192A, which may be located above a sub-fin (as shown) and a substrate or insulator structure 191. An intermediate insulator structure 193A (which may include additional layers 193B) is located vertically between the first vertical stack of horizontal nanowires 192B and the second vertical stack of horizontal nanowires 192A. A gate dielectric layer 194, such as a high-k gate dielectric layer, surrounds the first vertical stack of horizontal nanowires 192B and the second vertical stack of horizontal nanowires 192A and may also surround the intermediate insulator structure 193A, as shown. A gate electrode 195 is located above the gate dielectric layer 194.The dielectric cutting plug structures 196 separate individual of the above such stacks of nanowires. Referring again to Fig. 1I, in one embodiment the first vertical stack of horizontal nanowires 192B is contained in an N-type device and the second vertical stack of horizontal nanowires 192A is contained in a P-type device. In another embodiment, the first vertical stack of horizontal nanowires 192B is contained in a P-type device and the second vertical stack of horizontal nanowires 192A is contained in an N-type device. In yet another embodiment, the first vertical stack of horizontal nanowires 192B is contained in a first N-type device and the second vertical stack of horizontal nanowires 192A is contained in a second N-type device. In yet another embodiment, the first vertical stack of horizontal nanowires 192B is contained in a first P-type device and the second vertical stack of horizontal nanowires 192A is contained in a second P-type device. In one embodiment, the gate structure 194 / 195 includes a gate electrode 195 that extends between the first vertical stack of horizontal nanowires 192B and the second vertical stack of horizontal nanowires 192A, as shown. In another embodiment, the gate structure includes an upper gate electrode above the first vertical stack of horizontal nanowires 192B and a lower gate electrode above the second vertical stack of horizontal nanowires 192A, the lower gate electrode being different from the upper gate electrode. Referring to Fig. 1J, a source or drain section of an integrated circuit structure 190B (e.g., in or out of the side of structure 190A from Fig. 1I) shows an upper epitaxial source or drain structure 199C, e.g., coupled to the first vertical stack of horizontal nanowires 192B from Fig. 1I, and a lower epitaxial source or drain structure 199A, e.g., coupled to the second vertical stack of horizontal nanowires 192A from Fig. 1I. An upper conductive trench contact 199D is coupled to the upper epitaxial source or drain structure 199C, and a lower conductive trench contact 199B is coupled to the lower epitaxial source or drain structure 199A. In another location, a conductive via 199E extends through both upper and lower source or drain structures, e.g.for access to backside contacts, such as the backside contact 298A (which may contain multiple backside metallization structures 198). Referring again to Fig. 1J, in one embodiment the upper epitaxial source or drain structure 199C is an N-type source or drain structure and the lower epitaxial source or drain structure 199A is a P-type source or drain structure. In another embodiment, the upper epitaxial source or drain structure 199C is a P-type source or drain structure and the lower epitaxial source or drain structure 199A is an N-type source or drain structure. In yet another embodiment, the upper epitaxial source or drain structure 199C and the lower epitaxial source or drain structure 199A are N-type source or drain structures. In another embodiment, the upper epitaxial source or drain structure 199C and the lower epitaxial source or drain structure 199A are P-type source or drain structures. Referring to both Fig. 1I and Fig. 1J, an etch stop layer 197A, a dielectric layer 197B, one or more metallization layers (e.g. conductive conductors 197C and vias 197E in a dielectric layer 197D) can be included over the stacks of nanowires and the source or drain structures. Referring again to Figures 1I and 1J, one embodiment of the present disclosure provides a pixel architecture in which each device is intersected and separated by every other device. In one embodiment, lower devices are connected using a backside contact. In another embodiment, upper devices are contacted using a busbar and vias on a top side. In yet another embodiment, source or drain links and / or gate links, such as the conductive links described above, are used to connect (guide) devices as required. Another aspect is that reducing cell height in a future or scaled-up technology node requires shrinking both the gate end cap size and the gate cut size. Cutting the gate before filling the gate cut with metal can limit the effective end cap available for operation and complicate the ability to fill with metal in a confined space. The defect can be exacerbated if the gate is not properly aligned from one end to the other, further reducing the end cap space. According to one or more embodiments of the present disclosure, when addressing the problems outlined above, a metal gate cutting process is implemented after completion of gate dielectric and working-function metal deposition and structuring. In each embodiment, gate plugs formed after metal gate formation (“plug-last”) and / or gate plugs formed before metal gate formation (“plug-first”), both of which are described below, can be used for the gate / contact plugs previously described in connection with Figures 1A-1J. Advantages of implementing the approaches described here include a so-called "plug-last" (plug-last) approach, which results in a gate dielectric layer (such as a high-k gate dielectric layer) not being deposited on a gate-plug sidewall, effectively saving additional space for working-function metal deposition. In contrast, with a conventional "plug-first" approach, a metallic gate filler material can be trapped between the plug and the fin. The space for the metal fill can be narrower due to the incorrect plug orientation in the latter method, potentially leading to voids in the metal fill. In the embodiments described here, the deposition of metal in the working function can be seamless (e.g., gapless) by using a "plug-last" approach. According to one or more embodiments of the present disclosure, an integrated circuit structure has a clean interface between a gate-plug dielectric and a gate metal. It is understood that many embodiments can benefit from the approaches described here, such as plug-load approaches. A metal gate cut on a FinFET device, for example, is described below in conjunction with Fig. 2B. A metal gate cut scheme can be implemented for a gate-allaround (GAA) device, as described below in conjunction with Figs. 3B and 4B. Furthermore, a metal gate cut and plug formation can vary depending on the incoming structure. The plug can, for example, land on a shallow trench insulation (STI) structure, as in conjunction with Figs. 2B and 4B.3B, or on a prefabricated gate wall of dielectric, as described in conjunction with Fig. 4B. A metal gate-cutting approach can be selective for a gate-spacer dielectric, as described in conjunction with Figs. 5B and 6B, or it can be non-selective for a gate-spacer material, as described in conjunction with Figs. 5C and 6C. A non-selective metal gate-cutting variant may require an alternative contact metal scheme to accommodate a dielectric plug between the epi-source and drain. The selectivity of the plug etching for epi-source / drain material is optional. However, if the epitaxial source / drain is subject to plug etching in an embodiment (e.g., due to a device dimension), the etching can anisotropically trim the source / drain, as described below in conjunction with Fig. 5C. This approach allows for narrow end cap spacing. A dielectric gate plug can be fabricated for a FinFET device. As a comparative example, Fig. 2A shows a cross-sectional view of an integrated circuit structure with a Fin and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 2B illustrates a cross-sectional view of an integrated circuit structure with a Fin and a metal gate dielectric cut-off plug according to an embodiment of the present disclosure. Referring to Fig. 2A, an integrated circuit structure 200 has a fin 202 with a portion that protrudes above a shallow trench insulation (STI) structure 204. A gate dielectric material layer 206, such as a high-k gate dielectric layer, is located above the protruding portion of the fin 202 and above the STI structure 204. Although not shown, an oxidized portion of the fin 202 may be located between the protruding portion of the fin 202 and the gate dielectric material layer 206, forming a gate dielectric structure together with the gate dielectric material layer 206. A conductive gate layer 208, such as a working-function metal layer, is located above the gate dielectric material layer 206 and may be located directly on the gate dielectric material layer 206, as shown.A conductive gate filler material 210 is located above the conductive gate layer 208 and can, as shown, lie directly on the conductive gate layer 208. A dielectric gate cap 212 is located on the conductive gate filler material 210. A dielectric gate plug 214 is spaced laterally from the fin 202 and is located on the STI structure 204. The gate dielectric material layer 206 and the conductive gate layer 208 are located along sides of the dielectric gate plug 214. Referring to Fig. 2B, an integrated circuit structure 250 has a fin 252 with a portion that protrudes above a shallow trench insulation (STI) structure 254. A gate dielectric material layer 256, such as a high-k gate dielectric layer, is located above the protruding portion of the fin 252 and above the STI structure 254. Although not shown, an oxidized portion of the fin 252 may be located between the protruding portion of the fin 252 and the gate dielectric material layer 256, forming a gate dielectric structure together with the gate dielectric material layer 256. A conductive gate layer 258, such as a working-function metal layer, is located above the gate dielectric material layer 256 and may be located directly on the gate dielectric material layer 256, as shown.A conductive gate filler material 260 is located above the conductive gate layer 258 and can, as shown, lie directly on the conductive gate layer 258. A dielectric gate cap 262 is located on the conductive gate filler material 260. In one embodiment, a dielectric gate plug 264 is spaced laterally from the fin 252 and is located on the STI structure 254, but does not extend through it. Later in the disclosure, a dielectric plug described as being "on, but not through" an STI structure may refer to a dielectric plug that has landed on an upper or topmost surface of the STI, or it may refer to a plug that extends into the STI but does not penetrate it. In other embodiments, a plug described herein may extend completely through or pierce the STI. In one embodiment, the gate dielectric material layer 256 and the conductive gate layer 258 are not located along the sides of the dielectric gate plug 264. Instead, the conductive gate filler material 260 is in contact with the sides of the dielectric gate plug 264. As a result, a region between the dielectric gate plug 264 and the fin 252 has only one layer of the gate dielectric material layer 256 and only one layer of the conductive gate layer 258, which reduces space constraints in such a narrow region of the structure 250. Reducing space constraints can improve metal filling and / or facilitate the structuring of multiple VTs. Referring again to Fig. 2B, in one embodiment the dielectric gate plug 264 is formed after the formation of the gate dielectric material layer 256, the conductive gate layer 258, and the conductive gate filler material 260. As a result, the gate dielectric material layer 256 and the conductive gate layer 258 are not formed along sides of the dielectric gate plug 264. In one embodiment, the dielectric gate plug 264 has a top surface coplanar with a top surface of the dielectric gate cap 262, as shown. In another embodiment, not shown, no dielectric gate cap 262 is included, and the dielectric gate plug 264 has a top surface coplanar with a top surface of the conductive gate filler material 260, for example, along a plane 280. A dielectric gate plug can be fabricated for a nanowire device. As a comparative example, Fig. 3A shows a cross-sectional view of an integrated circuit structure with nanowires and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 3B illustrates a cross-sectional view of an integrated circuit structure with nanowires and a metal gate dielectric cut-off plug according to an embodiment of the present disclosure. Referring to Fig. 3A, an integrated circuit structure 300 has a sub-fin 302 with a section projecting above a shallow trench insulation (STI) structure 304. A plurality of horizontally stacked nanowires 305 are located above the sub-fin 302. A gate dielectric material layer 306, e.g. For example, a high-k gate dielectric layer is located above the protruding portion of the sub-fin 302, above the STI structure 304, and surrounds the horizontally stacked nanowires 305. It is understood that, although not shown, an oxidized section of the sub-fin 302 and horizontally stacked nanowires 305 may be located between the protruding portion of the sub-fin 302 and the gate dielectric material layer 306, and between the horizontally stacked nanowires 305 and the gate dielectric material layer 306, and may be contained together with the gate dielectric material layer 306 to form a gate dielectric structure.A conductive gate layer 308, such as a working-function metal layer, is located above the gate dielectric material layer 306 and can be located directly on the gate dielectric material layer 306, as shown. A conductive gate filler material 310 is located above the conductive gate layer 308 and can, as shown, be located directly on the conductive gate layer 308. A dielectric gate cap 312 is located on the conductive gate filler material 310. A dielectric gate plug 314 is spaced laterally from the sub-fin 302 and the plurality of horizontally stacked nanowires 305 and is located on the STI structure 304. The gate dielectric material layer 306 and the conductive gate layer 308 are located along sides of the dielectric gate plug 314. Referring to Fig. 3B, an integrated circuit structure 350 has a sub-fin 352 with a section projecting above a shallow trench insulation (STI) structure 354. A plurality of horizontally stacked nanowires 355 are located above the sub-fin 352. A gate dielectric material layer 356, e.g. For example, a high-k gate dielectric layer is located above the protruding portion of the sub-fin 352, above the STI structure 354, and surrounds the horizontally stacked nanowires 355. It is understood that, although not shown, an oxidized section of the sub-fin 352 may be located between the protruding portion of the sub-fin 352 and the gate dielectric material layer 356, and between the horizontally stacked nanowires 355 and the gate dielectric material layer 356, and may be contained together with the gate dielectric material layer 356 to form a gate dielectric structure.A conductive gate layer 358, such as a working-function metal layer, is located above the gate dielectric material layer 356 and can be situated directly on the gate dielectric material layer 356, as shown. A conductive gate filler material 360 is located above the conductive gate layer 358 and can, as shown, be situated directly on the conductive gate layer 358. A dielectric gate cap 362 is located on the conductive gate filler material 360. A dielectric gate plug 364 is spaced laterally from the sub-fin 352 and the multiple horizontally stacked nanowires 355 and is located on the STI structure 354, but does not extend through it. However, the gate dielectric material layer 356 and the conductive gate layer 358 are not located along the sides of the dielectric gate plug 364. Instead, the conductive gate filler material 360 is in contact with the sides of the dielectric gate plug 364.As a result, an area between the dielectric gate plug 364 and the combination of the sub-fin 352 and the multitude of horizontally stacked nanowires 355 includes only one layer of the gate dielectric material layer 356 and only one layer of the conductive gate layer 358, thereby reducing space constraints in such a narrow area of ​​the structure 350. Referring again to Fig. 3B, in one embodiment the dielectric gate plug 364 is formed after the formation of the gate dielectric material layer 356, the conductive gate layer 358, and the conductive gate filler material 360. As a result, the gate dielectric material layer 356 and the conductive gate layer 358 are not formed along sides of the dielectric gate plug 364. In one embodiment, the dielectric gate plug 364 has a top surface coplanar with a top surface of the dielectric gate cap 362, as shown. In another embodiment, not shown, no dielectric gate cap 362 is included, and the dielectric gate plug 364 has a top surface coplanar with a top surface of the conductive gate filler material 360, for example, along a plane 380. A dielectric gate plug can be fabricated on a gate endcap wall for a nanowire device. For comparison, Fig. 4A shows a cross-sectional view of an integrated circuit structure with nanowires and a pre-metal gate dielectric plug according to an embodiment of the present disclosure. Fig. 4B illustrates a cross-sectional view of an integrated circuit structure with nanowires and a metal gate dielectric cut-off plug according to an embodiment of the present disclosure. Referring to Fig. 4A, an integrated circuit structure 400 has a sub-fin 402 with a section projecting above a shallow trench insulation (STI) structure 404. A plurality of horizontally stacked nanowires 405 are located above the sub-fin 402. A gate endcap structure 403, such as a self-aligned gate endcap structure, is located on the STI structure 404 and is laterally spaced from the sub-fin 402 and the plurality of horizontally stacked nanowires 405. A gate dielectric material layer 406, such as a high-k gate dielectric layer, is located above the protruding section of the sub-fin 402, above the STI structure 404, along sides of the gate endcap structure 403 and surrounds the horizontally stacked nanowires 405.It is understood that, although not shown, an oxidized section of the sub-fin 402 and horizontally stacked nanowires 405 may be located between the protruding section of the sub-fin 402 and the gate dielectric material layer 406, and between the horizontally stacked nanowires 405 and the gate dielectric material layer 406, and may be contained together with the gate dielectric material layer 406 to form a gate dielectric structure. A conductive gate layer 408, such as a working-function metal layer, is located above the gate dielectric material layer 406 and may be located directly on the gate dielectric material layer 406, as shown. A conductive gate filler material 410 is located above the conductive gate layer 408 and may, as shown, be located directly on the conductive gate layer 408. A dielectric gate cap 412 is located on the conductive gate filler material 410.A dielectric gate plug 414 is located on the gate end cap structure 403. The gate dielectric material layer 406 and the conductive gate layer 408 are located along sides of the dielectric gate plug 414. Referring to Fig. 4B, an integrated circuit structure 450 has a sub-fin 452 with a section projecting above a shallow trench insulation (STI) structure 454. A plurality of horizontally stacked nanowires 455 are located above the sub-fin 452. A gate endcap structure 453, such as a self-aligned gate endcap structure, is located on the STI structure 454 but does not pass through it and is laterally spaced from the sub-fin 452 and the plurality of horizontally stacked nanowires 455. A gate dielectric material layer 456, such as a high-k gate dielectric layer, is located above the protruding section of the sub-fin 452, above the STI structure 454, along sides of the gate endcap structure 453 and surrounds the horizontally stacked nanowires 455.It is understood that, although not shown, an oxidized section of the sub-fin 452 may be located between the protruding section of the sub-fin 452 and the gate dielectric material layer 456, and between the horizontally stacked nanowires 455 and the gate dielectric material layer 456, and may be contained together with the gate dielectric material layer 456 to form a gate dielectric structure. A conductive gate layer 458, such as a working-function metal layer, is located above the gate dielectric material layer 456 and may be located directly on the gate dielectric material layer 456, as shown. A conductive gate filler material 460 is located above the conductive gate layer 458 and may, as shown, be located directly on the conductive gate layer 458. A dielectric gate cap 462 is located on the conductive gate filler material 460.A dielectric gate plug 464 is located on the gate endcap structure 453. However, the gate dielectric material layer 456 and the conductive gate layer 458 are not located along the sides of the dielectric gate plug 464. Instead, the conductive gate filler material 460 is in contact with the sides of the dielectric gate plug 464. Referring again to Fig. 4B, in one embodiment the dielectric gate plug 464 is formed after the formation of the gate dielectric material layer 456, the conductive gate layer 458, and the conductive gate filler material 460. As a result, the gate dielectric material layer 456 and the conductive gate layer 458 are not formed along sides of the dielectric gate plug 464. In one embodiment, the dielectric gate plug 464 has a top surface coplanar with a top surface of the dielectric gate cap 462, as shown. In another embodiment, not shown, no dielectric gate cap 462 is included, and the dielectric gate plug 464 has a top surface coplanar with a top surface of the conductive gate filler material 460, for example, along a plane 480. In another aspect, selective or non-selective versions of a metal gate cut can be implemented. Figures 5A-5C, for example, show top views of comparable integrated circuit structures according to one embodiment of the present disclosure. Figure 5A represents a conventional "plug-first" approach, illustrating two gate plugs in adjacent gates. Figure 5B represents a selective metal gate cut approach, illustrating two gate plugs in adjacent gates. Figure 5C represents a non-selective metal gate cut approach, illustrating a long gate plug spanning multiple gates. Referring to Fig. 5A, an integrated circuit structure 500 has gate lines between dielectric spacers 517 and conductive source or drain contacts 518. Each gate line comprises a gate dielectric material layer (506), a conductive gate layer (508), e.g., a metal layer for the working function, and a conductive gate filler material (510). Dielectric gate plugs 514 can interrupt sections of a corresponding gate line. The dielectric gate plugs 514 are in contact with the conductive gate layer 508, but not with the gate dielectric material layer 506 or the conductive gate filler material 510. The top view of Fig. 5A can correspond to the structures of Fig. 2A, Fig. 3A, or Fig. 4A.Although referred to above as conductive source or drain contacts 518, in earlier stages of the process or at other locations in an integrated circuit structure a placeholder dielectric or a dielectric plug may take the place of the conductive source or drain contacts 518. Referring to Fig. 5B, an integrated circuit structure 550 has gate lines between dielectric spacers 567 and conductive source or drain contacts 568. Each gate line comprises a gate dielectric material layer (556), a conductive gate layer (558), e.g., a metal layer for the working function, and a conductive gate filler material (560). Dielectric gate plugs 564 can interrupt sections of a corresponding gate line. The dielectric gate plugs 564 are in contact with the conductive gate filler material 560. The top view of Fig. 5B can correspond to the structures of Fig. 2B, Fig. 3B, or Fig. 4B. Although referred to above as conductive source or drain contacts 568, in earlier stages of the process or at other locations in an integrated circuit structure a placeholder dielectric or a dielectric plug may take the place of the conductive source or drain contacts 568. Referring to Fig. 5C, an integrated circuit structure 570 has gate lines between dielectric spacers 587 and conductive source or drain contacts 588. Each gate line comprises a gate dielectric material layer (576), a conductive gate layer (578), e.g., a metal layer for the working function, and a conductive gate filler material (580). A single dielectric gate plug 584 can interrupt sections of the gate lines and can extend through dielectric spacers 587 and even partially or completely into one or more of the conductive source or drain contacts 588. The dielectric gate plug 584 is in contact with the conductive gate filler material 580. The top view of Fig. 5C can correspond to the structures of Fig. 2B, Fig. 3B, or Fig. 4B. With reference again to Fig. 5C, it is understood that, although previously designated as conductive source or drain contacts 588, in earlier stages of the process or at other locations in an integrated circuit structure, a placeholder dielectric or a dielectric plug is present instead of the conductive source or drain contacts 588. In one embodiment, an etch used to form an opening in which a single dielectric gate plug 584 is ultimately formed is referred to as a non-selective etch. If the conductive source or drain contacts 588 are already formed, the non-selective etch can etch into the conductive material of the conductive source or drain contacts 588.In other embodiments, if a placeholder dielectric or a dielectric plug is located at the site of the conductive source or drain contacts 588, the non-selective etching can etch into the placeholder dielectric or the dielectric plug. In both cases, the non-selective etching can etch through and possibly detach epitaxial semiconductor material from source or drain regions formed below the conductive source or drain contacts 588. If conductive source or drain contacts 588 have already been formed, the epitaxial semiconductor material of the source or drain regions may contain silicified portions. Figures 6A-6C show cross-sectional views of comparable integrated circuit structures according to an embodiment of the present disclosure. Figure 6A shows a conventional "plug-first" approach. Figure 6B shows a selective metal-gate-cut approach. Figure 6C shows a non-selective metal-gate-cut approach. Referring to Fig. 6A, an integrated circuit structure 600 has a dielectric gate plug 614 between dielectric spacers 617 and conductive source or drain contacts 618. The cross-sectional view from Fig. 6A can be an orthogonal view corresponding to the structures from Fig. 2A, Fig. 3A, Fig. 4A, or Fig. 5A. Referring to Fig. 6B, an integrated circuit structure 650 has a dielectric gate plug 664 between dielectric spacers 667 and conductive source or drain contacts 668. The cross-sectional view of Fig. 6B can be an orthogonal view corresponding to the structures of Fig. 2B, Fig. 3B, Fig. 4B, or Fig. 5B. Referring to Fig. 6C, an integrated circuit structure 670 has a single dielectric gate plug 684 between conductive source or drain contacts 688. The dashed box 690 shows where a corresponding discrete gate plug, such as the gate plug 664, would be oriented in the case of Fig. 6B. The dashed boxes 692 show where the non-recessed source or drain contacts 668 would be oriented in the case of Fig. 6B. The areas between the dashed box 690 and the dashed boxes 692 show where the dielectric spacers 667 would be located in the case of Fig. 6B. The cross-sectional view of Fig. 6C can be an orthogonal view corresponding to the structures of Fig. 2B, Fig. 3B, Fig. 4B, or Fig. 5C. In one embodiment, the metal work function can be: (a) the same metal system in NMOS and PMOS, (b) a different metal system between NMOS and PMOS, and / or (c) single-material or multi-layer metals (e.g., W, TiN, TixAlyCz, TaN, Mo, MoN). In one embodiment, the etching chemistry for metal cutting comprises chlorine- or fluorine-containing etchants, with optional carbon- or silicon-containing components for passivation. It is understood that the embodiments described here may also include other implementations, such as nanowires and / or nanoribbons with different widths, thicknesses, and / or materials, including, but not limited to, Si and SiGe. For example, materials from groups III-V may be used. It is understood that in a particular embodiment, nanowires or nanoribbons, or intervening sacrificial layers, may consist of silicon. As used throughout, a silicon layer can be used to describe a silicon material composed of a very substantial amount of, if not all of, silicon. However, it is understood that virtually 100% pure Si can be difficult to form and therefore might contain a minute percentage of carbon, germanium, or tin. Such impurities may be present as unavoidable foreign matter or components during the deposition of Si, or they may "contaminate" the Si upon diffusion during a post-deposition treatment. Therefore, embodiments described herein relating to a silicon layer may include a silicon layer containing a relatively small amount, e.g., a "foreign matter level," of non-Si atoms or species, such as Ge, C, or Sn.A silicon layer, as described here, can be undoped or doped with dopant atoms such as boron, phosphorus, or arsenic. It is understood that in a particular embodiment, nanowires or nanoribbons, or intervening sacrificial layers, may consist of silicon germanium. The term "silicon germanium layer" refers to a silicon germanium material consisting substantially of silicon and germanium, for example, at least 5% of each. In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, a silicon germanium layer contains approximately 60% germanium and approximately 40% silicon (Si40Ge60). In other embodiments, the amount of silicon is greater than the amount of germanium. In certain embodiments, a silicon germanium layer contains approximately 30% germanium and approximately 70% silicon (Si70Ge30).It is understood that in practice it can be difficult to form 100% pure silicon germanium (generally referred to as SiGe), and therefore a minute percentage of carbon or tin may be present. Such impurities may be present as unavoidable contaminants or components during the deposition of SiGe, or they may "contaminate" the SiGe during diffusion during post-deposition processing. Therefore, embodiments described here relating to a silicon germanium layer may contain a silicon germanium layer that includes a relatively small amount, e.g., a "foreign matter level," of non-Ge and non-Si atoms or species, such as carbon or tin. It is understood that a silicon germanium layer as described here may be undoped or doped with dopant atoms such as boron, phosphorus, or arsenic. The following describes various fixtures and processing schemes that can be used to fabricate a device that can be combined with a cut-metal gate. It is understood that the exemplary embodiments do not necessarily require all of the described features or may include more features than described. For example, nanowire exposure processing can be performed by a substitute gate trench. Examples of such exposure processes are described below. Furthermore, backend (BE) interconnect scaling can lead to lower performance and higher manufacturing costs due to structuring complexity. The embodiments described here can be implemented to enable integration of the front- and back-end interconnects for nanowire transistors.The embodiments described here can offer an approach to achieving a relatively larger connection spacing. This can lead to improved product performance and lower structuring costs. These embodiments can be implemented to enable robust functionality of scaled nanowire or nanoband transistors with low power consumption and high performance. One or more embodiments described herein are directed towards dual epitaxial connections (EPI connections) for nanowire or nanoribbon transistors using a partial source or drain (SD) and an asymmetric trench contact depth (TCN depth). In one embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire / nanoribbon transistors that are partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trenching on one of the source or drain sides allows direct contact with a backside interconnect plane. As an exemplary process flow for manufacturing another gate-all-around device of a gate-all-around integrated circuit structure, Figs. 7A-7J illustrate cross-sectional views of various operations in a method for manufacturing a gate-all-around integrated circuit structure according to an embodiment of the present disclosure. Referring to Fig. 7A, a method for fabricating an integrated circuit structure involves forming a starter stack comprising alternating sacrificial layers 704 and nanowires 706 above a fin 702, such as a silicon fin. The nanowires 706 can be described as a vertical array of nanowires. A protective cap 708 can be formed over the alternating sacrificial layers 704 and nanowires 706, as shown in the figure. A relaxed buffer layer 752 and a defect modification layer 750 can be formed beneath the alternating sacrificial layers 704 and nanowires 706, as also shown. Referring to Fig. 7B, a gate stack 710 is formed above the vertical array of horizontal nanowires 706. Parts of the vertical array of horizontal nanowires 706 are then exposed by removing portions of the sacrificial layers 704 to create recessed sacrificial layers 704' and cavities 712, as shown in Fig. 7C. It is understood that the structure shown in Fig. 7C can be completely fabricated without first performing the deep etching and asymmetric contact processing described below. In both cases (e.g., with or without asymmetric contact processing), a fabrication process in one embodiment involves the use of a process scheme that provides a gate-all-around integrated circuit structure with epitaxial studs, which can be vertically discrete source or drain structures. Referring to Fig. 7D, upper gate spacers 714 are formed on the side walls of the gate structure 710. The cavity spacers 716 are formed in the cavities 712 below the upper gate spacers 714. Subsequently, deep trench contact etching is optionally performed to form trenches 718 and recessed nanowires 706'. A patterned relaxed buffer layer 752' and a patterned defect modification layer 750' may also be present, as shown in the figure. A sacrificial material 720 is then formed in the trenches 718, as shown in Fig. 7E. In other process schemes, an isolated trench bottom or a silicon trench bottom may be used. Referring to Fig. 7F, a first epitaxial source or drain structure (e.g., left features 722) is formed at a first end of the vertical arrangement of horizontal nanowires 706'. A second epitaxial source or drain structure (e.g., right features 722) is formed at a second end of the vertical arrangement of horizontal nanowires 706'. In one embodiment, the epitaxial source or drain structures 722, as shown, are vertically discrete source or drain structures and can be referred to as epitaxial studs. An interlayer dielectric (ILD) material 724 is then formed on the sides of the gate electrode 710 and adjacent to the source or drain structures 722, as shown in Fig. 7G. Referring to Fig. 7H, a replacement gate process is used to form a permanent gate dielectric 728 and a permanent gate electrode 726. The ILD material 724 is then removed, as shown in Fig. 7I. The sacrificial material 720 is then removed from one of the source-drain sites (e.g., on the right side) to form the trench 732, but is not removed from the other source-drain site to form the trench 730. Referring to Fig. 7J, a first conductive contact structure 734 is formed, coupled to the first epitaxial source or drain structure (e.g., the features 722 on the left). A second conductive contact structure 736 is formed, coupled to the second epitaxial source or drain structure (e.g., the features 722 on the right). The second conductive contact structure 736 extends deeper along the fin 702 than the first conductive contact structure 734. In one embodiment, although not shown in Fig. 7J, the method further includes forming an exposed surface of the second conductive contact structure 736 on a bottom surface of the fin 702. Conductive contacts can include a contact resistance-reducing layer and a primary contact electrode layer, examples of which can be Ti, Ni, Co (for the former and W, Ru, Co for the latter). In one embodiment, the second conductive contact structure 736 is located deeper along the fin 702 than the first conductive contact structure 734, as shown. In another embodiment, the first conductive contact structure 734 is not located along the fin 702, as shown. In yet another embodiment, not shown, the first conductive contact structure 734 is located partially along the fin 702. In one embodiment, the second conductive contact structure 736 is located along an assembly of the fin 702. In another embodiment, although not shown, the second conductive contact structure 736 has an exposed surface on the underside of the fin 702 in the event that the underside of the fin 702 is exposed by a backside substrate removal process. In one embodiment, the structure of Fig. 7J or related structures of Fig. 7A-7J can be formed using an offset gate-cut approach as previously described. To enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structures described here can be fabricated using a backside exposure of frontside structures. In some exemplary embodiments, backside exposure of a transistor or other device structure involves backside processing at the wafer level. Unlike conventional TSV-type technology, backside exposure of a transistor as described here can be performed at the device cell density and even within subregions of a device.Furthermore, such backside exposure of a transistor can be performed to essentially remove the entire donor substrate on which a device layer was placed during frontside device processing. Therefore, micrometer-deep TSV becomes unnecessary, with the thickness of a semiconductor in the device cells following backside exposure potentially being only tens or hundreds of nanometers. The exposure techniques described here can enable a paradigm shift from bottom-up fixture fabrication to center-out fabrication, where the center is any layer that is inserted during front-side fabrication, exposed from the back, and then inserted again during back-side fabrication. Processing both a front and an exposed back of a fixture structure can address many of the challenges associated with 3D IC fabrication when primarily relying on front-side processing. One approach for exposing the back side of a transistor can be used, for example, to remove at least a portion of a support layer and an intermediate layer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a support layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the support layer can be employed. For example, if the support layer is a group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor can be used. Likewise, any wet etching or plasma etching process known to be suitable for thinning the group IV semiconductor can be employed. In some embodiments, the foregoing is preceded by splitting the support layer along a fracture plane that is substantially parallel to the intervening layer. The splitting or fracture process can be used to remove a substantial portion of the support layer as a bulk mass, thereby reducing the polishing or etching time required to remove the support layer. For example, if a support layer has a thickness of 400–900 µm, 100–700 µm can be split off by applying any area-wide implantation known to promote at-wafer-level fracture. In some embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the support layer where the fracture plane is desired.Following such a cleavage process, the remaining thickness of the support layer in the donor-host substrate assembly can be polished or etched to complete the removal. Alternatively, if the support layer is not cleaved, the grinding, polishing, and / or etching process can be used to remove a greater thickness of the support layer. Next, the exposure of an intermediate layer is detected. Detection is used to identify a point where the back surface of the donor substrate has almost reached the device layer. It is known that any endpoint detection technique suitable for detecting a transition between the materials used for the support layer and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting a change in the optical absorption coefficient or emission of the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are associated with a change in the optical absorption coefficient or emission of byproducts during polishing or etching of the back surface of the donor substrate.For example, the absorption coefficients or emission wavelengths associated with the byproducts of substrate etching can change depending on the different compositions of the substrate and the interlayer. In other embodiments, the endpoint criteria are associated with a change in the mass of species in byproducts of polishing or etching the back surface of the donor substrate. For example, the processing byproducts can be sampled by a quadrupole mass analyzer, and a change in species mass can be correlated with the different compositions of the substrate and the interlayer. In another exemplary embodiment, the endpoint criteria are associated with a change in the friction between a back surface of the donor substrate and a polishing surface in contact with the back surface of the donor substrate. Detection of the intermediate layer can be improved if the removal process is selective with respect to the substrate relative to the intermediate layer, as any non-uniformity of the substrate removal process can be mitigated by an etch rate delta between the substrate and the intermediate layer. Detection can even be skipped if the grinding, polishing, and / or etching process removes the intermediate layer at a rate sufficiently lower than the rate at which the substrate is removed. If no endpoint criteria are used, a grinding, polishing, and / or etching process of a predetermined fixed duration can stop at the intermediate layer material if the thickness of the intermediate layer is sufficient for etch selectivity. In some examples, the ratio of substrate etch rate to intermediate layer etch rate is 3:1–10:1 or greater. When exposing the interlayer, at least a portion of the interlayer can be removed. For example, one or more component layers of the interlayer can be removed. A thickness of the interlayer can be removed uniformly, for instance, by polishing. Alternatively, a thickness of the interlayer can be removed using a masked or full-surface etching process. This process can employ the same polishing or etching process as that used to thin the support, or it can be a separate process with its own parameters. For example, if the interlayer provides an etch stop for the support removal process, the latter can employ a different polishing or etching process that favors the removal of the interlayer compared to the removal of the fixture layer.When removing an intermediate layer less than a few hundred nanometers thick, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than the process used to remove the substrate layer. For example, in a CMP process, a slurry can be used that offers very high selectivity (e.g., 100:1 to 300:1 or more) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO₂) that surrounds the device layer and is embedded in the intermediate layer, for example, as electrical insulation between adjacent device areas. For embodiments in which the fixture layer is exposed by complete removal of the intervening layer, backside processing can commence on an exposed backside of the fixture layer or on specific fixture regions therein. In some embodiments, the backside fixture layer processing includes further polishing or wet / dry etching through a thickness of the fixture layer located between the intervening layer and a fixture region previously fabricated in the fixture layer, such as a source or drain region. In some embodiments where the substrate, interlayer, or backside of the device layer is deepened by wet and / or plasma etching, such etching can be a structured etch or a materially selective etch, imparting significant non-planarity or topography to the backside surface of the device layer. As described below, the structuring can be within a device cell (i.e., “intra-cell structuring”) or can extend across device cells (i.e., “inter-cell structuring”). In some embodiments with structured etching, at least a partial thickness of the interlayer is used as a hard mask for backside device layer structuring. Therefore, a masked etching process can precede a correspondingly masked device layer etching. The processing scheme described above can result in a donor-host substrate arrangement featuring IC devices that have an exposed backside of an intermediate layer, a backside of the device layer, and / or a backside of one or more semiconductor regions within the device layer, and / or a frontside metallization. Additional backside processing of any of these exposed regions can then be performed during a downstream processing step. It is understood that the structures resulting from the foregoing exemplary processing schemes can be used in the same or a similar form for subsequent processing operations to complete a device fabrication, such as a PMOS and / or NMOS device fabrication. As an example of a completed device, Fig. 8 illustrates a cross-sectional view of a non-planar integrated circuit structure along a gate line according to one embodiment of the present disclosure. With reference to Fig. 8, a semiconductor structure or device 800 has a non-planar active region (e.g., a fin structure, including a protruding fin section 804 and a sub-fin region 805) within a trench isolation region 806. In one embodiment, instead of a solid fin, the non-planar active region is divided into nanowires (such as nanowires 804A and 804B) above the sub-fin region 805, as represented by the dashed lines. In both cases, for the sake of simplicity, a non-planar active region 804 is hereinafter referred to as a protruding fin section in the non-planar integrated circuit structure 800. In one embodiment, the sub-fin region 805 also includes a layer of a relaxed buffer 842 and a defect modification layer 840, as shown. A gate line 808 is arranged over the protruding sections 804 of the non-planar active region (including, where applicable, the surrounding nanowires 804A and 804B) and over a section of the trench insulation region 806. As shown, the gate line 808 has a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also have a dielectric cap layer 854. A gate contact 814 and an overlying gate contact via 816 are also viewed from this perspective, together with an overlying metal intermediate 860, all of which are arranged in interlayer dielectric stacks or layers 870. As can also be seen from the perspective of Fig. 8, in one embodiment the gate contact 814 is arranged above the trench isolation area 806, but not above the non-planar active areas.In another embodiment, the gate contact 814 is located above the non-planar active areas. In one embodiment, the semiconductor structure or device 800 is a non-planar device, such as, among others, a FinFET device, a tri-gate device, a nanoband device, or a nanowire device. In such an embodiment, a corresponding semiconducting channel region consists of or is formed within a three-dimensional body. In such an embodiment, the gate electrode stacks of the gate lines 808 surround at least one top surface and a pair of side walls of the three-dimensional body. As also shown in Fig. 8, in one embodiment there is an interface 880 between a protruding fin section 804 and a sub-fin region 805. The interface 880 can be a transition region between a doped sub-fin region 805 and a lightly or undoped upper fin section 804. In such an embodiment, each fin is about 10 nanometers wide or less, and sub-fin dopants are optionally supplied from an adjacent solid doping layer at the sub-fin site. In a particular embodiment, each fin is less than 10 nanometers wide. Although not shown in Fig. 8, it is understood that source or drain regions are located on or adjacent to the protruding fin sections 804 on both sides of the gate line 808, i.e., extending into and out of the side. In one embodiment, the material of the protruding fin sections 804 at the source or drain location is removed and replaced by another semiconductor material, e.g., by epitaxial deposition, to form epitaxial source or drain structures. The source or drain regions may extend below the height of the dielectric layer of the trench insulation region 806, i.e., into the sub-fin region 805. According to one embodiment of the present disclosure, the more heavily doped sub-fin regions, i.e., the doped sections of the fins below the interface 880, prevent source-to-drain leakage through this section of the bulk semiconductor fins.In one embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as described above in conjunction with Fig. 7J. Referring again to Fig. 8, the fins 804 / 805 (and possibly the nanowires 804A and 804B) in one embodiment consist of a crystalline silicon germanium layer doped with a charge carrier, such as, among others, phosphorus, arsenic, boron, gallium or a combination thereof. In one embodiment, the trench isolation area 806 and trench isolation areas (trench isolation structures or trench isolation layers) described throughout can consist of a material suitable for ultimately electrically isolating or contributing to the insulation of sections of a permanent gate structure from an underlying bulk substrate, or for isolating active regions formed within an underlying bulk substrate, such as active fin regions. In one embodiment, the trench isolation area 806 consists, for example, of a dielectric material such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride, but is not limited to such materials. The gate conductor 808 can consist of a gate electrode stack comprising a gate dielectric layer 852 and a gate electrode layer 850. In one embodiment, the gate electrode of the gate electrode stack is a metal gate, and the gate dielectric layer is a high-k material. In another embodiment, the gate dielectric layer 852 is, for example, a material such as hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc cniobate, or a combination thereof. In addition, part of the dielectric gate layer 852 may contain a layer of native oxide formed from the top few layers of the substrate fin 804.In one embodiment, the dielectric gate layer 852 consists of an upper high-k portion and a lower portion composed of an oxide of a semiconductor material. In another embodiment, the gate dielectric layer 852 consists of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure comprising a lower portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the upper surface of the substrate. In one embodiment, the gate electrode layer 850 consists of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a particular embodiment, the gate electrode 850 consists of a non-work function-setting filler material formed above a work function-setting metal layer. The gate electrode layer 850 can consist of a p-type or n-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer 850 can consist of a stack of two or more metal layers, wherein one or more metal layer(s) are work function metal layers and at least one metal layer is a conductive filler layer.For a PMOS transistor, metals that can be used for the gate electrode include ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, such as ruthenium oxide. A p-type metal layer allows the formation of a PMOS gate electrode with a work function between approximately 4.9 eV and approximately 5.2 eV. For an NMOS transistor, metals that can be used for the gate electrode, but are not limited to, include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will allow the formation of an NMOS gate electrode with a work function between approximately 3.9 eV and approximately 4.2 eV.In some implementations, the gate electrode may consist of a "U"-shaped structure having a lower section that is substantially parallel to the surface of the substrate and two sidewall sections that are substantially perpendicular to the upper surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the upper surface of the substrate and has no sidewall sections that are substantially perpendicular to the upper surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers. Spacers associated with the gate electrode stacks can be made of a material suitable for ultimately electrically isolating or contributing to the isolation of a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are made of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. The gate contact 814 and the overlying gate contact via 816 can be made of a conductive material. In one embodiment, one or more of the contacts or vias are made of a metal species. The metal species can be a pure metal, such as tungsten, nickel, or cobalt, or it can be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (such as a silicide material). In one embodiment (although not shown), a contact structure is formed that is essentially perfectly aligned with an existing gate structure 808, while eliminating the use of a lithographic step with an extremely tight overlap accuracy budget. In one embodiment, the contact structuring is a vertically symmetrical contact structuring or an asymmetrical contact structuring, as described, for example, in conjunction with Fig. 7J. In other embodiments, all contacts are connected on the front side and are not asymmetrical. In such an embodiment, the self-aligned approach enables the use of an intrinsically highly selective wet etching (e.g., compared to conventionally implemented dry or plasma etching) to create contact openings.In one embodiment, a contact structure is formed by using an existing gate structure in combination with a contact plug lithography process. In such an embodiment, the approach eliminates the need for an otherwise critical lithography process to create a contact structure, as used in conventional approaches. In one embodiment, a trench contact grid is not structured separately but is instead formed between poly(gate) lines. For example, in such an embodiment, a trench contact grid is formed after the gate grid structuring but before gate grid cuts. In one embodiment, providing structure 800 involves fabricating gate-stack structure 808 by a replacement-gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride column material, can be removed and replaced by a permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed in this process, rather than being carried over from a previous processing step. In one embodiment, dummy gates are removed by a dry-etching or wet-etching process. In another embodiment, dummy gates consist of polycrystalline silicon or amorphous silicon and are removed in a dry-etching process that involves the use of SF6.In another embodiment, dummy gates consist of polycrystalline silicon or amorphous silicon and are removed by a wet etching process involving the use of aqueous NH4OH or tetramethylammonium hydroxide. In another embodiment, dummy gates consist of silicon nitride and are removed by a wet etching process involving aqueous phosphoric acid. Referring again to Fig. 8, in the arrangement of the semiconductor structure or device 800, the gate contact is placed over insulating regions. Such an arrangement can be considered an inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact sections of a gate electrode formed over an active region, e.g., over a Fin 805, and in the same layer as a trench contact via. In one embodiment, the structure of Fig. 8 can be formed using an offset gate-cut approach, as previously described. It is understood that not all aspects of the processes described herein need to be implemented to fall within the nature and scope of protection of embodiments of this disclosure. Furthermore, the processes described herein can be used to manufacture one or more semiconductor devices. The semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal-oxide-semiconductor (MOS) transistors for logic or memory, or they are bipolar transistors. In another embodiment, the semiconductor devices have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, a dual-gate device with independent access, or a FIN-FET.One or more embodiments may be particularly useful for manufacturing semiconductor devices with a sub-10 nanometer technology node (sub-10 nm technology node). In an embodiment used throughout this description, the interlayer dielectric material (ILD material) consists of, or comprises, a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known from the prior art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods. In one embodiment, also used throughout this description, metal conductors or an interconnect material (and via material) consist of one or more metal or other conductive structures. A common example is the use of copper conductors and structures, which may or may not have barrier layers between the copper and the surrounding ILD material. As used here, the term "metal" includes alloys, stacks, and other combinations of several metals. For example, the metal interconnects may have barrier layers (e.g., layers having one or more of Ta, TaN, Ti, or TiN), stacks of different metals or alloys, etc. Thus, the interconnects may be a single layer of material, or they may be formed from multiple layers having conductive lining layers and filler layers.Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form interconnects. In one embodiment, the interconnects consist of a conductive material, including but not limited to Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. These interconnects are sometimes also referred to in technical terms as conductors, wires, conductors, metal, or simply as interconnects. In one embodiment, also used throughout this description, hard mask materials, cap layers, or plugs consist of dielectric materials different from the interlayer dielectric material. In another embodiment, different hard mask, cap, or plug materials can be used in different regions to provide varying growth or etch selectivity with respect to each other and to underlying dielectric and metal layers. In some embodiments, a hard mask layer, cap layer, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both or a combination thereof. Other suitable materials may be carbon-based.Depending on the specific implementation, other hard mask, cap, or plug layers known in the art can be used. These hard mask, cap, or plug layers can be formed by CVD, PVD, or other deposition processes. In one embodiment, also used throughout this description, lithographic processes are performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, or the like. A positive or negative photoresist may be used. In one embodiment, a lithographic mask is a three-layer mask consisting of a topographic masking section, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking section is a carbon hard mask (CHM) layer, and the ARC layer is a silicon ARC layer. In another aspect, one or more embodiments involve adjacent semiconductor structures or devices separated by self-aligned gate endcap (SAGE) structures. Certain embodiments may involve the integration of multi-width (multi-Wsi) nanowires and nanoribbons within a SAGE architecture and separated by a SAGE wall. In one embodiment, multi-Wsi nanowires / nanoribbons are integrated within a SAGE architecture section of a front-end process flow. Such a process flow may involve the integration of nanowires and nanoribbons of different Wsi widths to provide robust, low-power, high-performance next-generation transistor functionality. Associated epitaxial source or drain regions may be embedded (e.g.,Sections of nanowires are removed, and then source or drain growth (S / D growth) is performed. To provide further context, advantages of a self-aligned gate endcap (SAGE) architecture can include enabling higher layout density and, in particular, scaling diffusion-to-diffusion spacing. To provide an illustrative comparison, Fig. 9 shows cross-sectional views through nanowires and fins for a non-endcap architecture (left side (a)) compared to a self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure. Referring to the left side (a) of Fig. 9, an integrated circuit structure 900 has a substrate 902 with fins 904 projecting from it by a quantity 906 above an insulating structure 908 that laterally surrounds the lower sections of the fins 904. The upper sections of the fins can contain a relaxed buffer layer 922 and a defect modification layer 920, as shown in the figure. Corresponding nanowires 905 are located above the fins 904. A gate structure can be formed over the integrated circuit structure 900 to fabricate a device. However, discontinuities in such a gate structure can be compensated for by increasing the spacing between the fin 904 / nanowire 905 pairs. In contrast, with reference to the right side (b) of Fig. 9, an integrated circuit structure 950 has a substrate 952 with fins 954 that protrude by a quantity 956 above an insulating structure 958, which laterally surrounds the lower sections of the fins 954. The upper sections of the fins may contain a relaxed buffer layer 972 and a defect modification layer 970, as shown in the figure. Corresponding nanowires 955 are located above the fins 954. Insulating SAGE walls 960 (which may have a hard mask on them, as shown) are contained within the insulating structure 952 and between adjacent pairs of fin 954 / nanowire 955. The distance between an insulating SAGE wall 960 and the nearest pair of Fin 954 / nanowire 955 defines the gate end cap spacing 962.A gate structure can be formed over the integrated circuit structure 900 between insulating SAGE walls to fabricate a device. Interruptions in such a gate structure are caused by the insulating SAGE walls. Since the insulating SAGE walls 960 are self-aligned, limitations of conventional approaches can be minimized to allow for more aggressive diffusion-to-diffusion spacing. Because gate structures have interruptions at all locations, individual gate structure sections can furthermore be a layer connected by local interconnects formed over the insulating SAGE walls 960. In one embodiment, as shown, the SAGE walls 960 each comprise a lower dielectric section and a dielectric cap on the lower dielectric section. According to one embodiment of the present disclosure, a fabrication process for structures as shown in Fig.9 are assigned the use of a process scheme that provides a gate-all-around integrated circuit structure with epitaxial source or drain structures. In one embodiment, the structure of part (a) of Fig. 9 can be formed using an offset gate-cutting approach, as described above. In another embodiment, the structure of part (b) of Fig. 9 can be formed using an offset gate-cutting approach, as described above. A self-aligned gate endcap (SAGE) manufacturing scheme involves the fabrication of gate / trench contact endcaps that are self-aligned by fins without requiring additional length to compensate for mask misalignments. This allows for the implementation of embodiments that enable a reduction in transistor layout area. Embodiments described here may include the fabrication of gate endcap isolation structures, also known as gate walls, isolation gate walls, or self-aligned gate endcap walls (SAGE walls). In an exemplary processing scheme for structures with SAGE walls separating adjacent devices, Fig. 10 illustrates cross-sectional views representing various operations in a method for manufacturing a self-aligned gate end cap structure (SAGE structure) with gate all-around devices according to an embodiment of the present disclosure. Referring to part (a) of Fig. 10, a starting structure has a nanowire structuring stack 1004 above a substrate 1002. A lithographic structuring stack 1006 is formed above the nanowire structuring stack 1004. The nanowire structuring stack 1004 contains alternating sacrificial layers 1010 and nanowire layers 1012, which may be located above a relaxed buffer layer 1082 and a defect modification layer 1080, as shown. A protective mask 1014 is located between the nanowire structuring stack 1004 and the lithographic structuring stack 1006. In one embodiment, the lithographic structuring stack 1006 is a three-layer mask consisting of a topographic masking section 1020, an antireflection coating (ARC) layer 1022, and a photoresist layer 1024.In a particular embodiment, the topographic masking section 1020 is a carbon hard mask layer (CHM) and the antireflection layer 1022 is a silicon arc layer. Referring to part (b) of Fig. 10, the stack of part (a) is lithographically structured and then etched to provide an etched structure including a structured substrate 1002 and trenches 1030. Referring to part (c) of Fig. 10, the structure of part (b) features an insulating layer 1040 and a SAGE material 1042 formed in trenches 1030. The structure is then planarized, leaving the patterned topographic masking layer 1020' as the exposed upper layer. Referring to part (d) of Fig. 10, the insulation layer 1040 is recessed below an upper surface of the structured substrate 1002, for example to define a protruding fin section and to provide a trench insulation structure 1041 under SAGE walls 1042. Referring to part (e) of Fig. 10, the sacrificial layers 1010 are removed, at least in the channel region, to expose nanowires 1012A and 1012B. After forming the structure of part (e) of Fig. 10, gate stacks can be formed around the nanowires 1012B or 1012A, over protruding fins of the substrate 1002, and between the SAGE walls 1042. In one embodiment, the remaining part of the protective mask 1014 is removed before the formation of the gate stacks. In another embodiment, the remaining part of the protective mask 1014 is retained as an insulating fin cap artifact of the processing scheme. With further reference to part (e) of Fig. 10, it is understood that a channel view is shown, with source or drain regions extending into and out of the side. In one embodiment, the channel region with the nanowires 1012B has a narrower width than the channel region with the nanowires 1012A. Thus, in one embodiment, an integrated circuit structure incorporates multi-width nanowires (multi-Wsi nanowires). Although the structures of 1012B and 1012A can be distinguished as nanowires and nanoribbons, respectively, both structures are commonly referred to here as nanowires. It is also understood that a reference to or representation of a fin / nanowire pair throughout may refer to a structure comprising a fin and an overlying nanowire, or multiple overlying nanowires (e.g., two overlying nanowires are shown in Fig. 10).According to one embodiment of the present disclosure, a manufacturing process for structures associated with Fig. 10 includes the use of a process scheme that provides a gate-all-around integrated circuit structure with epitaxial source or drain structures. In one embodiment, the structure of part (e) of Fig. 10 can be formed using an offset gate-cut approach as previously described. In one embodiment, as described throughout, self-aligned gate endcap insulating structures (SAGE insulating structures) can consist of a material or materials suitable for ultimately electrically isolating or contributing to the isolation of sections of permanent gate structures. Exemplary materials or material combinations have a single-material structure, such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations have a multilayer stack with a lower section of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper section of a material with a higher dielectric constant, such as hafnium oxide. To highlight an exemplary integrated circuit structure with three vertically arranged nanowires, Fig. 11A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure. Fig. 11B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Fig. 11A along the a-a' axis. Fig. 11C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of Fig. 11A along the b-b' axis. Referring to Fig. 11A, an integrated circuit structure 1100 comprises a vertically stacked nanowire or multiple vertically stacked nanowires (set 1104) above a substrate 1102. In one embodiment, as shown, a relaxed buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are contained within the substrate 1102. An optional fin located below the lowest nanowire and formed from the substrate 1102 is omitted for illustrative purposes to emphasize the nanowire portion. The embodiments shown here are intended for both single-wire and multi-wire devices. As an example, three nanowire-based devices with nanowires 1104A, 1104B, and 1104C are shown for illustrative purposes.To simplify the description, the nanowire 1104A is used as an example, with the description focusing on one of the nanowires. It is understood that when attributes of one nanowire are described, embodiments based on a plurality of nanowires may have the same or substantially the same attributes for each of the nanowires. Each of the nanowires 1104 has a channel region 1106 within the nanowire. The channel region 1106 has a length (L). Referring to Fig. 11C, the channel region also has a perimeter (Pc) perpendicular to the length (L). Referring to Fig. 11A and Fig. 11C, a gate electrode stack 1108 surrounds the entire perimeter (Pc) of each of the channel regions 1106. The gate electrode stack 1108 includes a gate electrode together with a gate dielectric layer between the channel region 1106 and the gate electrode (not shown). In one embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack 1108 without any intervening material, such as underlying substrate material or overlying channel fabrication materials. Accordingly, the channel regions 1106 of the nanowires in embodiments with a plurality of nanowires 1104 are also discrete relative to each other. Referring to both Fig. 11A and 11B, the integrated circuit structure 1100 has a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 is located on both sides of the channel regions 1106 of the plurality of vertically stacked nanowires 1104. Furthermore, the pair of non-discrete source or drain regions 1110 / 1112 borders the channel regions 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment, not shown, the pair of non-discrete source or drain regions 1110 / 1112 directly adjoins the channel regions 1106 vertically in that epitaxial growth occurs on and between nanowire segments extending beyond the channel regions 1106, with nanowire ends shown within the source or drain structures. In another embodiment, as shown in Fig.As shown in Figure 11A, the pair of non-discrete source or drain regions 1110 / 1112 indirectly borders vertically on the channel regions 1106, as they are formed at the ends of the nanowires and not between the nanowires. In one embodiment, as shown, the source or drain regions 1110 / 1112 are non-discrete in that there are no individual and discrete source or drain regions for each channel region 1106 of a nanowire 1104. Accordingly, in embodiments with a plurality of nanowires 1104, the source or drain regions 1110 / 1112 of the nanowires are global or unified source or drain regions, as opposed to discrete ones for each nanowire. That is, the non-discrete source or drain regions 1110 / 1112 are global in the sense that a single unified feature is used as a source or drain region for a plurality (in this case, 3) of nanowires 1104 and, in particular, for more than one discrete channel region 1106.In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel regions 1106, each of the pair of non-discrete source or drain regions 1110 / 1112 is approximately rectangular with a lower tapered section and an upper vertex section, as shown in Fig. 11B. In other embodiments, however, the source or drain regions 1110 / 1112 of the nanowires are relatively larger, but discrete, non-vertically fused epitaxial structures such as the knobs described in connection with Figs. 7A-7J. According to one embodiment of the present disclosure and as shown in Figs. 11A and 11B, the integrated circuit structure 1100 further comprises a pair of contacts 1114, each contact 1114 being located on one of the pair of non-discrete source or drain regions 1110 / 1112. In such an embodiment, in a vertical sense, each contact 1114 completely surrounds the respective non-discrete source or drain region 1110 / 1112. In another aspect, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 may not be accessible for contact with the contacts 1114, and the contact 1114 thus only partially surrounds the non-discrete source or drain regions 1110 / 1112, as shown in Fig. 11B. In a contrasting embodiment not shown, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 is surrounded by the contacts 1114 along the a-a' axis. Referring again to Fig. 11A, the integrated circuit structure 1100 in one embodiment further comprises a pair of spacers 1116. As shown, outer sections of the pair of spacers 1116 can overlap sections of the non-discrete source or drain regions 1110 / 1112, thereby providing “embedded” sections of the non-discrete source or drain regions 1110 / 1112 below the pair of spacers 1116. As also shown, the embedded sections of the non-discrete source or drain regions 1110 / 1112 may not extend below the entirety of the pair of spacers 1116. The substrate 1102 can consist of a material suitable for fabricating an integrated circuit structure. In one embodiment, the substrate 1102 has a lower bulk substrate consisting of a single crystal of a material that may include, among others, silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a group III-V compound semiconductor material. An upper insulator layer, consisting of a material that may include, among others, silicon dioxide, silicon nitride, or silicon oxynitride, is located on the lower bulk substrate. Thus, the structure 1100 can be fabricated from an initial semiconductor-on-insulator substrate. Alternatively, the structure 1100 is formed directly from a bulk substrate, and local oxidation is used to form electrically insulating sections instead of the upper insulator layer described above.In another alternative embodiment, the structure 1100 is formed directly from a bulk substrate, and doping is used to form electrically isolated active regions, such as nanowires, on it. In such an embodiment, the first nanowire (i.e., near the substrate) has the form of an omega-FET-type structure. In one embodiment, the nanowires 1104 can be dimensioned as wires or ribbons, as described below, and can have right-angled or rounded corners. In another embodiment, the nanowires 1104 consist of a material such as silicon, germanium, or a combination thereof. In such an embodiment, the nanowires are single-crystal. For example, for a silicon nanowire 1104, a single-crystal nanowire can be arranged in a global (100) orientation, e.g., with a <100> The orientation is based on the plane in the z-direction. As described below, other orientations can also be considered. In one embodiment, the dimensions of the nanowires 1104, viewed from a cross-sectional perspective, are in the nanometer range. For example, in one specific embodiment, the smallest dimension of the nanowires 1104 is less than approximately 20 nanometers.In one embodiment, the nanowires 1104 consist of a material under mechanical stress, particularly in the channel areas 1106. Referring to Fig. 11C, in one embodiment each of the channel regions 1106 has a width (Wc) and a height (Hc), where the width (Wc) is approximately equal to the height (Hc). That is, in both cases, the channel regions 1106 are square in cross-sectional profile or, if with rounded corners, circular. In another aspect, the width and height of the channel region need not be equal, as in the case of nanoribbons, as described throughout. In one embodiment as described throughout, an integrated circuit structure comprises non-planar devices, such as a FinFET or a tri-gate device, with one or more corresponding overlying nanowire structures. In such an embodiment, a corresponding semiconducting channel region consists of, or is formed within, a three-dimensional body with one or more discrete nanowire channel segments lying above or within the three-dimensional body. In such an embodiment, the gate structures surround at least one top surface and a pair of side walls of the three-dimensional body and further surround each of the one or more discrete nanowire channel segments. In one embodiment, the structure of Fig. 11A-11C can be formed using an offset gate-cut approach, as previously described. In one embodiment, as described throughout, an underlying substrate may consist of a semiconductor material capable of surviving a fabrication process and capable of charge migration. In one embodiment, the substrate is a bulk substrate consisting of a crystalline silicon, silicon / germanium, or germanium layer doped with a charge carrier, such as phosphorus, arsenic, boron, gallium, or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in a bulk substrate is greater than 97%. In another embodiment, a bulk substrate consists of an epitaxial layer grown on a distinct crystalline substrate, such as an epitaxial silicon layer grown on a boron-doped monocrystalline bulk silicon substrate. Alternatively, a bulk substrate may consist of a Group III-V material.In one embodiment, a bulk substrate consists of a group III-V material, such as gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In another embodiment, a bulk substrate consists of a group III-V material, and the charge carrier dopant atoms include, for example, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium. The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include processors, chipset components, graphics processing units (GPUs), digital signal processors (DSPs), microcontrollers, and the like. In other embodiments, semiconductor memory can be manufactured. Furthermore, the integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., a desktop computer, laptop, server), mobile phones, consumer electronics, etc. The integrated circuits can be coupled to a bus and other components in the systems. For example, a processor can be coupled to a memory, a chipset, etc., via one or more buses.Each of the processor, memory, and chipset can potentially be manufactured using the approaches revealed here. Fig. 12 shows a computing device 1200 according to an implementation of an embodiment of the present disclosure. A circuit board 1202 is housed in the computing device 1200. The circuit board 1202 can comprise a number of components, including, among others, a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the circuit board 1202. In some implementations, the at least one communication chip 1206 is also physically and electrically coupled to the circuit board 1202. In other implementations, the communication chip 1206 forms part of the processor 1204. Depending on its applications, the computer device 1200 may include other components, which may or may not be physically and electrically coupled to the circuit board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen control, a battery, an audio codec, a video codec, a power amplifier, a global positioning system device (GPS device), a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), and the like). The 1206 communication chip enables wireless communication for the transmission of data to and from the 1200 computing device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices contain no wires whatsoever, although this may be the case in some embodiments. The 1206 communication chip can implement any number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), and IEEE 802.11.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The computing device 1200 can incorporate multiple communication chips 1206. For example, a first communication chip 1206 can be designated for shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip 1206 can be designated for longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The processor 1204 of the computing device 1200 includes an integrated circuit die that is packaged within the processor 1204. The integrated circuit die of the processor 1204 can include one or more structures, such as uniform grid-metal-gate and trench-contact integrated circuit gate structures for cFET architectures, constructed according to implementations of embodiments of the present disclosure. The term "processor" can refer to any device or any section of a device that processes electronic data from registers and / or a memory to convert such electronic data into other electronic data that can be stored in registers and / or a memory. The communication chip 1206 also includes an integrated circuit die that is housed within the communication chip 1206. The integrated circuit die of the communication chip 1206 can include one or more structures, such as uniform grid-metal-gate and trench contact-cut integrated circuit gate structures for cFET architectures, constructed according to implementations of embodiments of the present disclosure. In further implementations, another component housed within the computing device 1200 may contain an integrated circuit die that includes one or more structures, such as integrated circuit gate all-around structures with a uniform grid metal gate and trench contact cut for cFET architectures constructed according to implementations of embodiments of the present disclosure. In various implementations, the Computing Device 1200 can be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultramobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, the Computing Device 1200 can be any other electronic device that processes data. Fig. 13 illustrates an interposer 1300 comprising one or more embodiments of the present disclosure. The interposer 1300 is an intermediate substrate used as a bridge from a first substrate 1302 to a second substrate 1304. The first substrate 1302 can, for example, be an integrated circuit die. The second substrate 1304 can, for example, be a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of an interposer 1300 is to spread a connection to a wider grid dimension or to redirect a connection to another connection. For example, an interposer 1300 can couple an integrated circuit die to a ball grid array (BGA) 1306, which can then be coupled to the second substrate 1304.In some embodiments, the first and second substrates 1302 / 1304 are attached to opposite sides of the interposer 1300. In other embodiments, the first and second substrates 1302 / 1304 are attached to the same side of the interposer 1300. And in further embodiments, three or more substrates are connected to each other via the interposer 1300. The Interposer 1300 can be made from an epoxy resin, a glass fiber-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the Interposer 1300 can be made from alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The Interposer 1300 can include metal interconnects 1308 and vias 1310, including, but not limited to, silicon vias (TSVs) 1312. The Interposer 1300 can further include embedded devices 1314, including both passive and active devices. These devices include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, can also be implemented on the Interposer 1300.According to embodiments of the disclosure, the facilities or processes disclosed herein can be used in the manufacture of the Interposer 1300 or in the manufacture of components contained in the Interposer 1300. Thus, embodiments of the present disclosure include integrated circuit structures with a uniform grid-metal gate and trench contact cut for cFET architectures and methods for fabricating integrated circuit structures with a uniform grid-metal gate and trench contact cut for cFET architectures. The above description of illustrated implementations of embodiments of the disclosure, including the description in the abstract, is not intended to be exhaustive or to limit the disclosure to the specific forms disclosed. Although specific implementations of the disclosure and examples thereof are described here for illustrative purposes, various equivalent modifications are possible within the scope of protection of the disclosure, as those skilled in the art in the field will recognize. These modifications can be made to the disclosure in light of the above detailed description. The designations used in the following claims are not to be understood as limiting the disclosure to the specific implementations disclosed in the description and the claims. Even though specific embodiments have been described above, these embodiments are not intended to limit the scope of protection of the present disclosure, even if only a single embodiment is described with respect to a particular feature. Examples of features listed in the disclosure are intended to be illustrative rather than limiting, unless otherwise stated. The foregoing description is intended to cover such alternatives, modifications, and equivalents as are obvious to a person skilled in the art with knowledge of the present disclosure. The scope of protection afforded by the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, regardless of whether it mitigates any or all of the problems addressed herein. Accordingly, during an examination of the present application (or an application claiming priority thereof), new claims may be formulated for any such combination of features. In particular, with reference to the accompanying claims, features from dependent claims may be combined with those of the independent claims, and features from respective independent claims may be combined in any suitable manner, not limited to the specific combinations listed in the accompanying claims. Various embodiments or aspects of the disclosure are described herein. In some implementations, the different embodiments are implemented separately. However, the embodiments are not limited to isolated implementations. For example, two or more different embodiments can be combined to be implemented as a single device, a single process, a single structure, or the like. In some cases, the entirety of different embodiments can also be combined with one another. In other cases, parts of a first embodiment can be combined with parts of one or more other embodiments.For example, a part of a first embodiment can be combined with a part of a second embodiment, or a part of a first embodiment can be combined with a part of a second embodiment and a part of a third embodiment. The following examples relate to further embodiments. The various features of the different embodiments can be combined in different ways, including some features and excluding others to enable a wide variety of applications. Exemplary embodiment 1: An integrated circuit structure comprises a first vertical stack of horizontal nanowires above a second vertical stack of horizontal nanowires, with an intermediate insulator structure positioned vertically between the first and second vertical stacks. A gate structure is located above the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intermediate insulator structure. A conductive trench contact is adjacent to the gate structure. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact. A first dielectrically cut plug structure extends through the gate structure, the dielectric sidewall spacer, and the conductive trench contact.A second dielectric cut plug structure extends through the gate structure, through the dielectric sidewall spacer and through the conductive trench contact, wherein the second dielectric cut plug structure is spaced laterally from and parallel to the first dielectric cut plug structure. Exemplary embodiment 2: The integrated circuit structure from Exemplary embodiment 1, wherein the first vertical stack of horizontal nanowires is contained in an N-type device and the second vertical stack of horizontal nanowires is contained in a P-type device. Exemplary embodiment 3: The integrated circuit structure from Exemplary embodiment 1, wherein the first vertical stack of horizontal nanowires is contained in a P-type device and the second vertical stack of horizontal nanowires is contained in an N-type device. Exemplary embodiment 4: The integrated circuit structure from Exemplary embodiment 1, 2 or 3, wherein the gate structure includes a gate electrode that extends between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires. Exemplary embodiment 5: The integrated circuit structure from Exemplary embodiment 1, 2 or 3, wherein the gate structure includes an upper gate electrode above the first vertical stack of horizontal nanowires and a lower gate electrode above the second vertical stack of horizontal nanowires, wherein the lower gate electrode differs from the upper gate electrode. Exemplary embodiment 6: The integrated circuit structure from exemplary embodiment 1, 2, 3, 4 or 5, further comprising a second conductive trench contact on a side of the gate structure opposite the conductive trench contact, wherein the first and the second dielectric section plug structure extend through the second conductive trench contact. Exemplary embodiment 7: The integrated circuit structure from exemplary embodiment 1, 2, 3, 4, 5 or 6, further comprising a second gate structure on a side of the conductive trench contact opposite the gate structure, wherein the first and the second dielectric section plug structure extend through the second gate structure. Exemplary embodiment 8: An integrated circuit structure comprises a pixel architecture. A pixel of several pixels includes a first vertical stack of horizontal nanowires above a second vertical stack of horizontal nanowires with an insulator structure positioned vertically between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires. Exemplary embodiment 9: The integrated circuit structure from Exemplary embodiment 8, wherein the first vertical stack of horizontal nanowires is contained in an N-type device and the second vertical stack of horizontal nanowires is contained in a P-type device. Exemplary embodiment 10: The integrated circuit structure from Exemplary embodiment 8, wherein the first vertical stack of horizontal nanowires is contained in a P-type device and the second vertical stack of horizontal nanowires is contained in an N-type device. Exemplary embodiment 11: A computing device comprises a circuit board and a component coupled to the circuit board. The component includes an integrated circuit structure comprising a first vertical stack of horizontal nanowires above a second vertical stack of horizontal nanowires, with an intermediate insulator structure positioned vertically between the first and second vertical stacks of horizontal nanowires. A gate structure is located above the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intermediate insulator structure. A conductive trench contact is adjacent to the gate structure. A dielectric sidewall spacer is located between the gate electrode and the conductive trench contact.A first dielectrically cut plug structure extends through the gate structure, the dielectric sidewall spacer, and the conductive trench contact. A second dielectrically cut plug structure extends through the gate structure, the dielectric sidewall spacer, and the conductive trench contact, the second dielectrically cut plug structure being laterally spaced from and parallel to the first dielectrically cut plug structure. Exemplary embodiment 12: The computing device from exemplary embodiment 11, wherein the first vertical stack of horizontal nanowires is contained in an N-type device and the second vertical stack of horizontal nanowires is contained in a P-type device. Exemplary embodiment 13: The computing device from exemplary embodiment 11, wherein the first vertical stack of horizontal nanowires is contained in a P-type device and the second vertical stack of horizontal nanowires is contained in an N-type device. Exemplary embodiment 14: The computing device from exemplary embodiment 11, 12 or 13, which further comprises a memory coupled to the circuit board. Exemplary embodiment 15: The computing device from exemplary embodiment 11, 12, 13 or 14, which further comprises a communication chip coupled to the circuit board. Exemplary embodiment 16: The calculating device from exemplary embodiment 11, 12, 13, 14 or 15, which further comprises a battery coupled to the circuit board. Exemplary embodiment 17: The computing device from exemplary embodiments 11, 12, 13, 14, 15 or 16, which further comprises a camera coupled to the circuit board. Exemplary embodiment 18: The calculating device from exemplary embodiment 11, 12, 13, 14, 15, 16 or 17, which further comprises a display coupled to the circuit board. Exemplary embodiment 19: The computing device from Exemplary embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a housed integrated circuit die. Exemplary embodiment 20: The computing device from Exemplary embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

Integrated circuit structure comprising: a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, with an intermediate insulator structure positioned vertically between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires; a gate structure over the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intermediate insulator structure; a conductive trench contact adjacent to the gate structure; a dielectric sidewall spacer between the gate electrode and the conductive trench contact; a first dielectric cut plug structure extending through the gate structure, the dielectric sidewall spacer, and the conductive trench contact;and a second dielectric cut plug structure extending through the gate structure, through the dielectric sidewall spacer, and through the conductive trench contact, wherein the second dielectric cut plug structure is spaced laterally from and parallel to the first dielectric cut plug structure. Integrated circuit structure according to claim 1, wherein the first vertical stack of horizontal nanowires is contained in an N-type device and the second vertical stack of horizontal nanowires is contained in a P-type device. Integrated circuit structure according to claim 1, wherein the first vertical stack of horizontal nanowires is contained in a P-type device and the second vertical stack of horizontal nanowires is contained in an N-type device. Integrated circuit structure according to claim 1, 2 or 3, wherein the gate structure includes a gate electrode that extends between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires. Integrated circuit structure according to claim 1, 2 or 3, wherein the gate structure comprises an upper gate electrode above the first vertical stack of horizontal nanowires and a lower gate electrode above the second vertical stack of horizontal nanowires, wherein the lower gate electrode differs from the upper gate electrode. Integrated circuit structure according to claim 1, 2, 3, 4, or 5, further comprising: a second conductive trench contact on a side of the gate structure opposite the conductive trench contact, wherein the first and second dielectric section plug structures extend through the second conductive trench contact. Integrated circuit structure according to claim 1, 2, 3, 4, 5 or 6, further comprising: a second gate structure on a side of the conductive trench contact opposite the gate structure, wherein the first and second dielectric section plug structures extend through the second gate structure. Integrated circuit structure comprising: a pixel architecture, wherein a pixel of several pixels comprises a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, with an intermediate insulator structure located vertically between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires. Integrated circuit structure according to claim 8, wherein the first vertical stack of horizontal nanowires is contained in an N-type device and the second vertical stack of horizontal nanowires is contained in a P-type device. Integrated circuit structure according to claim 8, wherein the first vertical stack of horizontal nanowires is contained in a P-type device and the second vertical stack of horizontal nanowires is contained in an N-type device. Computing device comprising: a circuit board and a component coupled to the circuit board, the component comprising an integrated circuit structure comprising: a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, an intermediate insulator structure positioned vertically between the first vertical stack of horizontal nanowires and the second vertical stack of horizontal nanowires; a gate structure over the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires, and the intermediate insulator structure; a conductive trench contact adjacent to the gate structure; and a dielectric sidewall spacer between the gate electrode and the conductive trench contact.a first dielectric cut-plug structure extending through the gate structure, the dielectric sidewall spacer, and the conductive trench contact; and a second dielectric cut-plug structure extending through the gate structure, the dielectric sidewall spacer, and the conductive trench contact, wherein the second dielectric cut-plug structure is spaced laterally from and parallel to the first dielectric cut-plug structure. Computing device according to claim 11, wherein the first vertical stack of horizontal nanowires is contained in an N-type device and the second vertical stack of horizontal nanowires is contained in a P-type device. Computing device according to claim 11, wherein the first vertical stack of horizontal nanowires is contained in a P-type device and the second vertical stack of horizontal nanowires is contained in an N-type device. Computing device according to claim 11, 12 or 13, further comprising: a memory coupled to the circuit board. Computing device according to claim 11, 12, 13 or 14, further comprising: a communication chip coupled to the circuit board. Computing device according to claim 11, 12, 13, 14 or 15, further comprising: a battery connected to the circuit board. Computing device according to claim 11, 12, 13, 14, 15 or 16, further comprising: a camera coupled to the circuit board. Computing device according to claim 11, 12, 13, 14, 15, 16 or 17, further comprising: a display coupled to the circuit board. Computing device according to claim 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is an enclosed integrated circuit die. Computing device according to claim 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

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