LOW STANDBY CURRENT WITH FAST START-UP FOR NON-FLORANT STORAGE DEVICES

Abstract

A device comprising: a non-volatile memory system (102) comprising a plurality of drivers; and a standby control circuit (126) coupled to the non-volatile memory system (102), wherein the standby control circuit (126) comprising: a standby detection circuit to detect a standby state; a wake-up detection circuit to detect a wake-up state; and a bias control circuit (210) coupled to the plurality of drivers, the standby detection circuit, and the wake-up detection circuit, wherein the bias control circuit (210) will control bias currents supplied to the plurality of drivers based on the standby state and / or the wake-up state, wherein an output frequency of at least one of the drivers is adjustable in response to a change in the bias current.

Description

RELATED REGISTRATIONS

[0001] This application is an international application of US patent application No. 14 / 966,990, filed on December 11, 2015, claiming priority over US preliminary application No. 62 / 212,296, filed on August 31, 2015, both of which are incorporated herein by reference in their entirety. STATE OF THE ART

[0002] Non-volatile memory devices are used in electronic components that require the retention of information when electrical power is unavailable. Non-volatile memory devices can include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM). Some memory arrays utilize transistors and gate structures that may include a charge-capture layer. The charge-capture layer can be programmed to store data based on voltages applied to or received from the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present revelation is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which:

[0004] Fig. 1 is a block diagram illustrating a computer system comprising a non-volatile storage system according to one embodiment.

[0005] Fig. 2 is a block diagram illustrating a standby control circuit arrangement of a non-volatile memory system according to one embodiment.

[0006] Fig. Figure 3A is a block diagram illustrating a circuit arrangement of a standby generator according to one embodiment.

[0007] Fig. Figure 3B is a timing diagram illustrating an operating standby generator according to one embodiment.

[0008] Fig. Figure 4 is a block diagram illustrating a bias control circuit arrangement according to one embodiment.

[0009] Fig. Figure 5 is a block diagram illustrating a circuit arrangement of an analog driver according to one embodiment.

[0010] Fig. Figure 6 is a block diagram illustrating another embodiment of a standby control circuit arrangement of a non-volatile memory system according to one embodiment.

[0011] Fig. Figure 7 is a block diagram illustrating a circuit arrangement of a voltage booster according to one embodiment.

[0012] Fig. 8 is a flowchart of processes of transitioning into and out of a standby mode according to one embodiment. DETAILED DESCRIPTION

[0013] Non-volatile memory device (NVM) read operations can use analog circuitry to provide bias voltages for capture circuitry, generating boost voltages for word line and column drivers, as well as protection voltages for level shifters in a read path of the NVM device. In some implementations, an NVM device can have an active operating state and a standby operating state. For example, an NVM device can enter a standby operating state if it has not received any read or write instructions for a specified period of time. The standby state may consume less current than an active operating state; however, the lower current slows down the operation of the circuitry within the NVM device, resulting in reduced performance when read instructions are executed.

[0014] During the transition from a standby to an active operating state, analog circuits charge various capacitors and other circuit elements in the memory system's read path. To avoid delays during a high-speed read operation, the analog circuits in the read path can consume high standby currents, so that fewer circuit elements are charged during the transition to an active mode.

[0015] On the other hand, providing large standby currents in the standby mode of a storage system can result in excessive power consumption for certain applications. For example, low-power system-on-chip (SoC) circuits can be used in applications with limited energy capacity to provide standby currents and sufficient operating time between battery charging or replacement. Such applications might include portable devices and the Internet of Things (IoT), where low power consumption extends the usefulness of the product or device. Low-power devices can also benefit from fast power-on and wake-up from sleep states, as well as a quick transition to an active state from standby.A transition time from a standby to an active state can be essentially instantaneous and may be similar to the propagation time of control signals in the memory system. For example, a fast transition from a standby state may be approximately 1 ns or less. Such a transition may be one or more orders of magnitude faster than the read cycle time for the memory system (e.g., 0.01–0.1 times the length of a read cycle time). Waking up from a sleep state or turning on a device may be considered fast if it occurs on the order of microseconds (e.g., 1–10 µs), since certain circuit elements may be able to be loaded from an inactive state. In some alternative embodiments, other durations may be used to indicate a fast transition from a standby to an active state and a wake-up from a sleep state.

[0016] In some embodiments, control circuits operate with low current in a standby state but provide essentially instantaneous transitions from the standby state to an active operating state, particularly when a read instruction is received. In one embodiment, the control circuits comprise a standby state detector and a start generator. A standby state detector can operate to determine when to begin or end a standby state based on the receipt of read instructions from the storage system. The standby state detector can operate in conjunction with a start generator, which provides additional current when the storage system is powered on or wakes from a sleep state to control the circuits, thereby generating analog signals for read operations.The system can operate with low standby power when it is not in an active state.

[0017] Fig. Figure 1 is a block diagram illustrating a non-volatile storage system according to one embodiment. The computer system 100 can a processing device 104 include those that go beyond the address bus 106 , data bus 108 and control bus 110 with the non-volatile storage system 102 is coupled. In some embodiments, the computer system can 100 a programmable system-on-a-chip (PSoC) device or a similar programmable system. The components of the computer system 100 The descriptions have been simplified for illustrative purposes and are not intended as a complete description. In particular, details of the processing equipment are not described. 104 , address decoder 114 , address driver 116 , control circuits 120, write control circuits 136 , data reading circuits 118 and reading control circuit arrangement 124 not described in detail herein. In some embodiments, the computer system 100 fewer or additional components than in Fig. 1. This will be illustrated. For example, the computer system can include... 100 It may include one or more additional memory components, such as RAM or ROM, may include various input or output ports or devices, or may include other components that are provided by the computer system. 100 be used.

[0018] The power supply 150 is with the non-volatile storage system 102 , also simply referred to as a "storage system", are coupled. The power supply 150 Can an external power supply be connected to the storage system? 102 be and can be from the storage system 102They can be used to supply bias currents and voltages to provide power to a storage array. 112 to generate the signal needed to read from or write to non-volatile memory. The power supply 150 Furthermore, electricity can be supplied to the processing device. 104 or other components of the computer system 100 provide.

[0019] The processing device 104 can reside on a common substrate, such as an integrated circuit (IC) die substrate, a multi-chip module substrate, or the like. Alternatively, the components of the processing device can 104 It may be one or more integrated circuits and / or discrete components. In a single exemplary embodiment, the processing device is 104 the Programmable System-on-a-Chip processing device (PSoC) ®-processing device), developed by Cypress Semiconductor Corporation, San Jose, California. Alternatively, the processing device can be used. 104 one or more other processing devices, such as a microprocessor or central processing unit, a controller, a special processor, a digital signal processor (“DSP”), an application-specific integrated circuit (“ASIC”), a free programmable gate array (“FPGA”) or the like.

[0020] The storage system 102 includes a storage array 112 , which can be organized as rows and columns of non-volatile memory cells. The memory array 112 can be used with the address drivers 116 They can be coupled via multiple select lines and read lines. For example, each row of the memory array can have one select line and one read line. The address drivers 116can drive storage locations that correspond to addresses provided via the address bus 106 be received. The address decoders 114 They may, for example, include a row decoder, a column decoder, and a sector decoder to decode the addresses provided by the processing device. 104 be received.

[0021] The address drivers 116 can be configured to be the first row of a memory array 112 For a program operation, a selection is made by applying a voltage to a first select line in the first row, and a second row of the memory array is deselected by applying a different voltage to a second select line in the second row. The address drivers 116They can further be configured to select a memory cell in the first row for programming by applying a voltage to a first bit line in a first column, and to inhibit an unselected memory cell in the first row from programming by applying a different voltage to a second bit line in a second column. The read control circuit arrangement 124 , in particular the standby control circuit arrangement 126 , can be configured to apply a bias current to analog read circuits to match the input from the address drivers 116 to control the power supplied during reading operations and during standby mode.

[0022] The storage array 112 can also be used with data reading circuits 118 They must be coupled via multiple bit lines. The data reading circuits 118Column multiplexers and read amplifiers can be included. The column multiplexers can select the memory columns that the read amplifiers should access during a read operation. For example, the column multiplexers can access multiple column lines in the memory array. 112 provide a system to enable read amplifiers to read multibit words from it. The storage system 102 Furthermore, a control circuit arrangement may be used. 120 include signals from the processing device 104 to receive, and sends signals to the reading control circuit arrangement. 124 and write control circuit arrangement 136 The reading control circuit arrangement 124 and write control circuit arrangement 136 This allows control of read and write operations to the memory array. 112 Provide. For example, the write control circuit arrangement can 136the control of data writing circuits 140 provide and can provide the reading control circuit arrangement 124 the control of analog reading circuits 128 Provide the write control circuit arrangement. 136 can drivers of the write path circuits of the memory array 112 Provide current and voltage supply. For example, the write control circuit arrangement can 136 Analog and digital circuits are included to create data writing circuits. 140 a high voltage for writing data to the memory array 112 to provide. The analog reading circuits 128 provide drivers of the read path circuits of the memory array 112 bias currents and the data reading circuits 118 Control signals are ready. The reading circuit arrangement. 124 includes a standby control circuit arrangement 126 , to control standby and active operation of the storage system 102to generate and control. The standby control circuit arrangement. 126 It can provide bias currents and protection voltages for level converters in the read path of the memory circuit for word line and column drivers.

[0023] Data that is stored on the storage array 112 written or from the memory array 112 can be read by the processing device 104 via a data bus 108 to the storage system 102 be transferred. The storage system 102 can handle data input / output circuits 130 include processing the data that is being processed by the storage system 102 to the processing device 104 or are passed from it. The data input / output circuits can, for example, include one or more data buffers to control the communication between the processing device and the storage array. 112 include.

[0024] The storage system 102 can be a storage device configured to store data values ​​in various low-current and non-volatile contexts. Accordingly, storage systems, such as the one disclosed here, can be like the storage system 102 , can be implemented in such a way that they have a relatively small footprint, which can be manufactured using advanced processing nodes, such as a 65 nm node or lower. Furthermore, the storage system can 102 As explained in more detail below, memory cells comprise various storage cells to store data values. These memory cells can be implemented with a common source line to reduce the overall footprint of each memory cell.

[0025] The storage array 112 can include one or more memory sectors, such as sector A 131 to Sector N 132Each sector can contain any number of rows and columns of memory cells, for example, 4096 columns and 256 rows. Rows can contain multiple horizontally arranged memory cells. Columns can contain multiple vertically arranged memory cells.

[0026] The storage array 112 can also be used for data reading circuits 118 They are used to couple a column of memory cells in a sector with read amplifiers during a read operation. For example, the data read circuits can 118 for column 0 of sector A 131 They can be used as switches to couple the memory cells of column 0 of sector A with read amplifiers during a read operation.

[0027] It should be recognized that the terms "rows" and "columns" of a memory array are used for illustrative purposes rather than for delimitation. In one embodiment, rows are arranged horizontally in the conventional manner, and columns are arranged vertically in the conventional manner. In another embodiment, the rows and columns of the memory array can be 112 be arranged in any orientation.

[0028] In one embodiment, a memory cell can be a two-transistor (2T) memory cell. In a 2T cell, one transistor can be a storage transistor, while another transistor can be a pass transistor. In other implementations, the memory cell can comprise a different number of transistors, such as a single storage transistor (1T).

[0029] The storage array 112A storage array implemented using charge-capture storage transistors can be called a charge-capture storage device. Charge-capture storage transistors can be implemented using transistors and gate structures that include a charge-capture layer. The charge-capture layer can be an insulator used to trap charge. The charge-capture layer can be programmed to store data based on voltages applied to the storage array. 112 can be created or received from it. This is how a storage array can be used. 112Memory arrays consist of various different memory cells arranged in rows and columns, and each memory cell can be capable of storing at least one data value (e.g., bits). Voltages can be applied to each of the memory cells to program the memory cell (e.g., program operation – storing a logical "1"), to erase the memory cell (e.g., erase operation – storing a logical "0"), or to read the memory cell (e.g., read operation).

[0030] In a single embodiment, charge-trapping storage transistors can be implemented using different materials. One example of a charge-trapping storage transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor. A storage array implemented using SONOS-type transistors can be referred to as a SONOS storage device. In a SONOS-type transistor, the charge-trapping layer of the storage transistor can be a nitride layer, such as a layer of silicon nitride. Alternatively, the charge-trapping layer can also include other charge-trapping materials, such as silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminum oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxynitride, hafnium zirconium oxide, lanthanum oxide, or a high-k layer.The charge-trapping layer can be configured to reversibly trap or retain carriers or holes injected from a channel of the storage transistor and can have one or more electrical characteristics that can be reversibly changed, modified, or altered based on the voltages applied to the memory cell. In another embodiment, different types of charge-trapping storage transistors can be used.

[0031] Fig. Figure 2 is a block diagram illustrating a standby control circuit arrangement according to an embodiment that uses read path circuits. 290 is coupled. The standby control circuit arrangement can be a bias control circuit arrangement. 210 include those with voltage drivers 270 (e.g., low-voltage and high-voltage drivers), a variable frequency oscillator 260, to provide the voltage boost for read path circuits 290 to control, and one or more analog drivers 280 is coupled. The standby control circuit arrangement can also include a standby generator. 220 , a wake-up generator 230 and a logical element 235 include determining whether a standby state, wake state or power-on state has been detected.

[0032] The read path circuits 290 These represent various circuits used to read from a memory array. The read path circuits can, for example, be data read circuits. 118 , including column multiplexers and read amplifiers, as well as data input / output circuits 130 , address decoder 114 , address driver 116 or other elements of a storage system, such as with regard to Fig. 1 described, to include reading from a storage location. The in Fig. The two additional elements shown illustrate different control and driver circuits for the read path circuits. 290 For example, the voltage drivers can 270 , distributed analog drivers 280 and the voltage doubler 250 Driver circuits of the read path circuits 290 be and the bias control circuit arrangement 210 can be control circuits for one or more of the driver circuits.

[0033] The standby generator 220 It can detect whether a standby state is present in the storage system. For example, the standby generator can include a standby detection circuit. The standby generator 220 It can accept clock inputs, an activation input, and a read input. The read input can indicate when a read instruction is being executed by the memory system. The standby generator 220It can determine whether a certain amount of time has elapsed since the last read request to the storage system. The standby generator 220For example, it may include standby detection circuitry to determine when the storage system has entered a standby state or when a standby state should be entered. If a threshold time interval has elapsed since the last read instruction, the standby generator may produce an output indicating that a standby state is present. For example, in some embodiments, the standby generator may generate a logic high in response to determining that no read instruction has been received for a specified number of clock cycles (for example, 3, 4, 5, 10, or any number of cycles). In some embodiments, a low logic high may indicate a standby state, and a high logic high may indicate an active state. After the control circuitry receives a read instruction and an associated clock signal, the standby generator 220its output changes to indicate that it is in an active mode. An exemplary embodiment of a standby generator is described below with reference to Fig. 3 discussed.

[0034] The wake-up generator 230 can the read path circuits 290 The wake-up generator provides additional power in response to waking from sleep mode or powering on the storage system. 230 This can reduce the time required for the initial charging of capacitors and other circuit elements of the read circuitry in the read path when the memory system is powered on or wakes from sleep mode. For example, during sleep, various circuit elements of the memory system may not remain in a charged state. To wake from sleep, the read path circuitry can be... 290 from the wake-up generator 230An increased current is provided. A similar process can occur when the memory system is powered on, as various elements of the memory system may not be loaded into operating states. The wake-up generator therefore provides an increased current to the read path circuits in response to waking from a sleep state or powering on the memory system.

[0035] In addition to the wake-up generator, the bias control circuit arrangement can also provide a higher current to reduce the wake-up or turn-on time for the storage system. Therefore, the logic element 235 A logic output of the wake-up generator is provided. The output of the wake-up generator is therefore used to ensure that the read path circuits 290Sufficient power is provided during wake-up in addition to the active modes. In some embodiments, the standby control circuitry may not include a wake-up generator. For example, certain embodiments of a memory system may provide limited standby power and a fast transition for the duration of the transition to an active mode from standby, but may not require fast power-on or fast transitions from sleep mode. In such applications, a standby generator may be required. 220 in the standby control circuit arrangement without the use of a wake-up generator 230 be provided. If this is the case, in some embodiments the standby generator is coupled with the bias control circuit arrangement and may not use an intervening logic element. 235 .

[0036] The logical element 235determines whether the memory system is currently in wake-up mode, start-up mode or active mode, and if the memory system is operating in one of these modes, produces an output to the bias control circuit arrangement. 210 , the frequency divider 265 and regulator 240 (e.g., a low-dropout switching regulator or the like) to indicate that the memory system will operate in an active mode, thereby enabling the read path circuits 290 An increased power supply is provided. As in Fig. As shown in 2, the logical element 235 shown as a NAND gate that receives an input from the standby generator 220 and from the wake-up generator 230 Accepted. The input from the wake-up generator can be inverted, so that a high logic value is associated with the wake-up generator not operating, and a low logic value is associated with the wake-up generator being operational. The logical element235 Therefore, it will produce a logic low output if the standby generator has a logic high value and the inverted output of the wake-up generator has a logic high value. In other states, the output of the logic element will be 235 exhibit a high logical value. As such, the logical element can 235 generate a logical low output if the standby generator 220 This indicates that the memory system is in a standby state and the wake-up generator is not operating. A logic low output from the NAND gate is therefore sent to the bias control circuitry. 210 , the frequency divider 265 and the voltage regulator 240 to indicate whether the logical element is operating in standby mode and in active mode. 235 It has a high logical value. In various embodiments, the logical element can 235with a different logical element. For example, the logical element could be an AND gate, and a logic high output would indicate to the coupled circuits that they are operating in standby mode. Other implementations using AND, NAND, NOR, and OR gates are also possible. Fig. 2 will be the logical output of the wake-up generator. 230 in front of the circuit element 235 In some embodiments, the wake-up generator can produce a logic output separate from the driver output, which is inverted. In such embodiments, the inversion occurs before the logic element. 235 Not required. In some embodiments, the logic high and logic low values ​​can be determined by one or both of the standby generator and wake-up generator. 230 can be reversed and can be a different logical element. 235can be used to determine whether the storage system is in an active, wake-up, or startup mode.

[0037] The bias control circuit arrangement 210 Provides bias currents or control signal voltages to bring the storage system from a standby state to an active state. The bias control circuit arrangement 210 For example, a variable frequency oscillator 260 provide a bias current to control the oscillation frequency of a voltage doubler 250 The bias control circuit arrangement is provided. 210 can also be used with one or more distributed analog drivers 280 Provide a bit line limit voltage. In some embodiments, the bias control circuit arrangement can 210 the voltage drivers 270It can also provide a protective voltage. In some embodiments, the bias control circuit arrangement can distribute bias currents and voltages to fewer or additional components than in Fig. 2 shown, adjust. In some embodiments, the bias control circuit arrangement can be adjusted. 210 The voltage drivers may not provide a protective voltage.

[0038] The bias control circuit arrangement can include multiple current mirrors to provide bias currents in different operating states. For example, the bias control circuit arrangement can provide a first set of current mirrors that supply standby bias currents and a second set of current mirrors that supply active bias currents. An exemplary embodiment of a bias control circuit arrangement is described in Fig. Figure 4 illustrates this and is discussed further below.

[0039] The voltage doubler 250 can work to configure the read path circuits 290 To provide a boost voltage. The power supply for the memory system may, for example, operate at a low voltage (e.g., 1.2 volts), but various components of the memory system may operate at a higher voltage (e.g., 2.4 volts). Therefore, a voltage doubler circuit can be provided to supply a higher voltage to read path circuits. 290to generate. In some embodiments, the boost voltage is provided to address drivers to drive sections of the voltage array according to an address received from a processing device. The voltage doubler can draw a significant current during active operation of the memory system, but can drive lower-current read path circuits during standby operation. The low current can, for example, operate at a level to charge a filter capacitor to raise the voltage level to read path circuits. 290 to maintain, but not with a current to power the read path circuits 290 as in active operation. The voltage doubler 250 Can an input voltage from a voltage regulator 240 and a control signal for switching the frequency oscillator 260 and frequency divider 265 receive.

[0040] The voltage doubler 250During standby operation, the storage system can receive a lower oscillation frequency than during active operation. This lower frequency results in slower switching of the circuits in the voltage doubler. 250 and therefore consumes less power than when operating at higher frequencies. A variable frequency oscillator 260 For example, it can operate in active mode at a frequency of approximately 50 MHz. During active operation, the frequency divider 165 active and the voltage doubler becomes 250 switched according to this frequency. In standby mode, the bias current is applied to the variable frequency oscillator. 260 The frequency is reduced, resulting in a lower output frequency. Continuing from the example above, the frequency can be reduced from 50 MHz to approximately 8 MHz. The frequency can be further reduced using a frequency divider. 265The frequency can be further reduced. For example, the 8 MHz output can be reduced by a factor of 8 to approximately 1 MHz using the frequency divider. In some embodiments, the control circuit arrangement may not include a frequency divider. 265 , but can only be done on the variable frequency oscillator 260 They operate based on this principle. In some embodiments, a fixed frequency oscillator can be used, and the frequency can be adjusted using only a frequency divider. 265 be reduced.

[0041] The distributed analog drivers 280A – 280n work to improve the read path circuits 290 to provide driver voltages and currents. In some embodiments, the read path circuits can 290 Driver voltages and currents from a single analog driver instead of multiple distributed drivers, as in Fig. 2 shown, received. The distributed analog drivers 280A – 280ncan connect the current output to the read path circuits 290 reduce in response to bias currents and bias voltages applied by the bias control circuit arrangement 210 received. The bias control circuit arrangement can, for example, supply a lower current than the bit line limit voltage to the analog drivers in standby mode. The distributed analog drivers 280A – 280n They can therefore provide enough current to maintain the charge on one or more capacitors or other elements to enable fast switching to active operation from standby, but cannot supply additional current to the read path circuits. 290 provide.

[0042] Similarly, the protective voltage and the voltage drivers can 270is provided with a lower current to reduce power consumption by the drivers, which power the read path circuits 290 feed. The voltage drivers 270 They can act as voltage level converters to transform a low-voltage control signal into a higher voltage in order to drive memory cells in the memory array during a read operation. The protection voltage supplied to the voltage drivers 270 The provided protection voltage can prevent certain overvoltage conditions from damaging one or more circuits in the storage system. During standby operation, the protection voltage can be provided at a low current to maintain the protection voltage level supplied to the voltage drivers. 270 is supplied. The current of the protection voltage can be increased during active operation of the storage system to drive the voltage drivers. 270to protect against potential overvoltage events.

[0043] Fig. Figure 3A illustrates a block diagram of a standby detection circuit arrangement for a standby generator. The circuit arrangement can, for example, be used as a standby generator. 220 implemented as in the exemplary embodiment of Fig. 2. As discussed above, the standby generator generates a signal to indicate a standby state of the memory system. In some embodiments, the standby generator determines that the memory system is in a standby state in response to an elapsed time since the previous read instruction. The standby generator may include two parallel paths for both rising and falling edges of the clock signal. The standby generator may be connected to a flip-flop with one input of a read signal and one input of a clock signal. 310A logic high read signal can be provided to the standby generator when the memory system is not performing a read operation. For example, if the memory system is performing write operations, the read signal might be a logic low. When the standby generator receives a logic low read signal, it can provide a logic low output, indicating an active state. This allows the circuitry to operate at an active current level, as may be required by other operations performed by the memory system. For example, the oscillator might operate at an active current level during write operations, so the standby generator provides an indication that it is operating in active mode when no read operations are being performed. A high read signal can precede an active clock signal in response to a read instruction to the memory system.The control circuit arrangement can cause the memory system to switch to active mode in response to pulses at the clock signal. In some embodiments, the flip-flop can... 310 It will be a d-type flip-flop. The flip-flop 310 It outputs a signal from the rising and falling edges of the input signal to a series of circuit components for conditioning the signal. In particular, the signal passes through triggers. 330A – 330B and buffer 340A – 340B through. The triggers 330 In some embodiments, they can be Schmitt triggers. The triggers remove noise from the signal to produce consistent high and low logic levels. The buffers 340 hold the trigger output for use by logic circuits 350 The logic circuits 350determine whether the signals indicate that the storage system is in a standby state, and a logical output at the buffer. 360 produce, which, as with reference to Fig. 2. It is distributed as discussed above.

[0044] In some embodiments, the logic circuits determine 350 The logic circuit can, for example, maintain the most recent set of signals and determine that the memory system is in an active state if one of the signals is a logic high. In some embodiments, this can be implemented by monitoring the intermediate storage locations. 340Received signals are sent through a series of cascaded flip-flops on each clock cycle, and a logical OR operation is performed on the flip-flop outputs. This functions similarly to a shift register to maintain a memory of the most recent signals received by the standby generator. Therefore, if any of the most recent read input values ​​are logically high, the standby generator will indicate that the memory system is in an active state; otherwise, it will indicate that it is in a standby state. For example, to determine whether there has been a read operation in the previous three clock cycles, the read signal can be fed into the three cascaded flip-flops.In such a configuration, the most recent signal is on the first flip-flop, the signal before that is on the second flip-flop, and the signal two clock cycles before that is on the third flip-flop. The output of the three flip-flops can be passed to an OR gate to determine if any of the outputs indicate a read instruction. If none of the flip-flops indicates a logic high, which represents a read instruction, then no read instruction has been issued for three clock cycles. In such circumstances, the logic can provide an indication to enter or remain in standby mode. In other situations, the logic can provide an indication to enter or remain in active mode.

[0045] Fig. Figure 3B is an exemplary embodiment of a timing diagram for signals input to a standby generator and for the output of the standby generator. In the example of Fig. 3B indicates that the "Read" input is ready for a read operation once a clock signal is present. The standby generator can provide a "Standby" output with a logic high when the memory system is in standby mode and a logic low when the memory system is in active mode. At the beginning of the timing diagram, the Read input was inactive, and the Standby generator outputs a logic low, indicating that the memory system is in an active state. The Standby output can be provided as a logic low to allow circuitry to operate the memory device in the active state for other operations. At time A, the Read input transitions from a logic low to a logic high, indicating that the memory system is ready for a read instruction.Since the standby generator has not received a clock input, it instantly changes its standby output to a high logical value to indicate a standby state. At time B, the clock is activated for a read instruction from the memory system. The standby generator instantly changes its standby output to a low logical value to indicate an active state. During the time period in which the read instruction is processed, the clock cycles, and the standby generator maintains an output indicating the active state. At time C, the clock is deactivated, and no read instruction occurs, but the standby generator maintains the active state. At time D, the standby generator determines that no read has occurred for a predetermined duration and outputs a signal indicating that the memory system is in a standby state.The standby state ends at time E when the clock signal is applied to the standby generator. The standby generator provides a standby output with a logic low value, indicating that the storage system is in an active mode.

[0046] In the example of Fig. 3B The time between C and D can be determined based on the system clock. For example, the time can be based on a fixed number of running clock cycles that indicate no read operation before the start of a standby mode. In some embodiments, the standby generator can wait three clock cycles, indicating that no read operation has occurred, before a standby state is output. For example, if a clock signal lasts approximately 30 ns, the time between C and D on the timing diagram can be approximately 100 ns. In some embodiments, the time can be shorter or longer than shown. Fig. 3B will be shown. Furthermore, Fig. 3B is not necessarily drawn to scale.

[0047] Fig. Figure 4 is a block diagram of the bias control circuit arrangement used in one embodiment. The bias control circuit arrangement can provide a standby mode current mirror. 410 , an active mode power mirror 420 , a Vlim generator 430 , to generate a bit line limit voltage, and a voltage generator 440 (referred to as a Vprot generator) to generate a protection voltage for one or more voltage drivers. The standby mode current mirror 410 and active mode power mirror 420 can receive an input from the standby generator output. The active-mode current mirror 420 It can use the inverted standby input to determine its operating mode.

[0048] The standby mode power mirror 410and active mode power mirror 420 They can provide outputs to the same circuits with different currents. For example, the current mirrors can provide a current for the bit line limit voltage (Ilim), a protection voltage (Iprot), a bias current for the variable oscillator (Ibias), and a current for reference voltages (Iref). In some embodiments, the currents from the standby mode current mirror can be... 410 be considerably smaller than those measured by the active mode current mirror 420 are generated. The standby currents can be, for example, 10 times smaller or even smaller than those of the active currents. In some embodiments, the bias current during active mode can be approximately 3 µA, while the bias currents during standby mode can be approximately 300 nA. In some embodiments, the standby current mirror 410 or the active mode power mirror 420Different currents are generated for each of the outputs. For example, the bit line limit current, the protection current, and the bias current cannot be the same value.

[0049] The Vlim generator 430 and the protective voltage generator 440 They generate voltages for use in the storage system. The output of the Vlim generator 430 This can be a driver bias voltage and a voltage limit output, as shown, for use by the distributed analog drivers. The current supplied by the current mirrors therefore determines the current of the voltages provided to the analog drivers. The voltage supplied by the Vprot generator 440 The generated protection current can be used by the high-voltage and low-voltage drivers that operate the read path circuitry of the storage system. Similar to the Vlim generator. 430 can the output of the Vprot generator 440a constant voltage, but the current level provided at that voltage can increase based on whether the standby mode current level is 410 or the active mode power mirror 420 works. In some embodiments, the standby mode power mirror works. 410 in active operating mode and standby operating mode, and the active mode power level is displayed. 420 the only one that, as determined by the standby generator, is used in an active state.

[0050] Fig. Figure 5 is a block diagram showing the operation of the distributed analog drivers used in one embodiment. The distributed analog drivers can be associated with different sectors of the memory system. For example, there can be one driver for each sector, or each driver can be coupled to a subset of sectors of the memory system. In some embodiments, there can be more than one analog driver associated with specific memory sectors. Fig. Figure 5 shows a PMOS-controlled power source. 510 and a PMOS trailing arm 520 The PMOS-controlled power source 510 receives a driver bias input and the PMOS follower 520 receives a bit line input threshold voltage. These voltages can be, for example, as in Fig. The output voltage Vlim can be generated as described in section 4. The output voltage Vlim can be essentially constant during both active and standby operation of the memory system. However, the current Vlim can be higher during an active state of the memory system compared to its standby state. During standby operation, the current can be adjusted, for example, to maintain the charge of a filter capacitor. 530 maintained. Therefore, the transition to active mode from standby mode is fast, as the capacitors in the circuit are charged and the increased current provided by the bias control circuits supplies power to the storage system without delay.

[0051] Fig. Figure 6 is a block diagram illustrating a standby control circuit arrangement according to an embodiment that uses read path circuits. 290 is coupled. The embodiment in Fig. 6 works similarly to the one in Fig. 2, but instead of a voltage doubler, the control circuit arrangement uses a voltage booster. 650 , to provide a boost voltage for the read path circuits 290 to generate.

[0052] Fig. 7 is a block diagram that shows a voltage booster 700 shows one embodiment in which it is used. The voltage booster contains a comparator. 730 This determines whether the supply voltage is higher than a reference voltage. If the supply voltage is higher than the reference voltage, the voltage booster will provide the supply voltage to the read path circuits. If the supply voltage is lower than the reference voltage, the voltage booster will supply a voltage from a charging pump. 720 provide. For example, the output of the comparator will be provided. 730 , as in Fig. 7 shown, provided to a multiplexer that provides the V supply as Vboost if the output of the comparator 730 indicates that the supply voltage is greater than the reference voltage, and otherwise sets the output of the charging pump. 720 ready.

[0053] The charging pump 720 can add the supply voltage to a core voltage supplied by a core voltage buffer. 710 is received. The charging pump's clock signal is linked to the core voltage. This generates the voltage of the supply voltage plus the core voltage, which is sent to a multiplexer. 740 from the charging pump 720The charge pump therefore generates at least a minimum sufficient voltage to supply the storage system for proper operation. In some embodiments, the reference voltage for comparison is, for example, 2.5 V. The multiplexer will therefore provide the supply voltage if it is 2 V, or the supply voltage plus the core voltage if the supply voltage is less than 2.5 V. Furthermore, the charge pump provides a maximum voltage for the core voltage plus the supply voltage. Limiting the maximum voltage can prevent damage to the storage circuits from potential overvoltage effects. Similarly, with reference to… Fig. 2 described operation of the voltage doubler can be carried out by the charging pump during 720Current used during standby mode is reduced by lowering the frequency provided by the variable frequency generator and frequency divider. In some embodiments, instead of a voltage doubler or charge pump, the control circuit arrangement uses a pulsed voltage supply for the boost voltage, or it may use a single voltage level at the storage system, so that no boost voltage is used by the circuit arrangement.

[0054] Although described here generally in relation to detecting a standby state of a memory system, the standby control circuit arrangement can be used in other applications. For example, a circuit with low-power standby requirements and a fast transition to active mode can use similar circuitry. For instance, a system resources subsystem (SRSS) control operation of a system on a chip can benefit from a low-power standby mode of control circuitry during periods of inactivity, but can start up quickly when the chip is used again. The start-up time can, for example, be essentially instantaneous.

[0055] Fig. Figure 8 is a flowchart of the processes for transitioning into and out of standby mode according to one embodiment. Starting in block 810The standby control circuit arrangement detects a standby state of a non-volatile memory system. The control circuit arrangement can, for example, use the standby generator to detect the state, as with reference to... Fig. 2, Fig. 3A and Fig. Detect as described in 3B. Detecting a standby state in block 810 This may also include determining that the storage system is not in a wake-up state from a sleep state or a start-up state from when the device was switched on.

[0056] Continuing with block 820 The standby control circuit arrangement reduces bias current at driver circuits of the non-volatile memory system. Currents at variable oscillators, analog driver circuits, and voltage drivers, for example, can be reduced by the bias control circuit arrangement, as described with reference to Fig. 2 and Fig. As described in section 4, after the bias currents have been reduced, the memory system can be considered to be in standby mode. The current consumed by the memory system is lower in standby mode than in active mode, when the memory is being accessed. In standby mode, the current to the read path circuitry can be minimal, resulting in trickle charging of capacitors in the read path and the filter capacitor to maintain voltage levels.

[0057] In standby mode, the standby generator maintains a display standby mode until a read instruction is detected. In the block 830 A read instruction to the non-volatile memory system is detected. The control circuit arrangement can, for example, determine the state using the standby generator, as with reference to... Fig. 2, Fig. 3A and Fig. Detect as described in 3B. When the read instruction is detected, the standby generator can change its output to signal the bias control circuitry to increase bias currents and provide additional current to the memory system's read paths.

[0058] In the block 840 The current control circuit arrangement increases the bias currents at driver circuits of the non-volatile memory system. The bias currents can be increased by additional current mirrors to output additional current to driver circuits of the memory system. In some embodiments, the Fig. The process described in section 8 may be carried out in a different order. Furthermore, the control of current and electricity consumption by the storage system may include fewer or additional processes than shown in the flowchart of [reference missing]. Fig. 8 shown.

[0059] Embodiments of the present invention comprise various processes described herein. These processes can be carried out by hardware components, software, firmware, or a combination thereof.

[0060] Although the operations of the procedure are shown and described here in a specific order, the order of any procedure can be changed so that certain operations may be performed in reverse order or so that certain operations may be performed, at least partially, concurrently with other operations. In another embodiment, instructions or sub-operations of separate operations may be performed in an intermittent and / or alternating manner. The terms "first," "second," "third," "fourth," etc., as used here, are employed as labels to distinguish between different elements and do not necessarily have an ordinal meaning according to their numerical designation.

[0061] The above description presents numerous specific details, such as examples of specific systems, components, methods, and so on, to provide an understanding of several embodiments of the present invention. However, it may be apparent to a person skilled in the art that at least some embodiments of the present invention can be carried out without these specific details. In other cases, well-known components or methods are not described in detail or are presented in a simple block diagram format so as not to unnecessarily complicate the understanding of the present invention. The specific details presented are therefore merely exemplary. Particular embodiments may differ from these exemplary details and still be provided for within the scope of protection of the present invention.

Claims

[1] A device comprising the following: a non-volatile storage system that includes a variety of drivers; and a standby control circuit coupled to the non-volatile memory system, wherein the standby control circuit includes the following: a standby detection circuit to detect a standby state; an awakening detection circuit to detect a waking state; and a bias control circuit coupled with the multiple drivers, the standby detection circuit, and the wake-up detection circuit, wherein the bias control circuit will control bias currents supplied to the plurality of drivers with respect to the standby state, the awake state or both. [2] Device according to claim 1, wherein the bias control circuit comprises: a first current mirror coupled to the standby detection circuit; and a second current mirror coupled to the standby detection circuit; the second current mirror operates in response to receiving an output from the standby detection circuit indicating that the non-volatile memory system is in an active mode. [3] Device according to claim 1, wherein the standby control circuit further comprises: a frequency oscillator coupled to an output of the bias control circuit; and a voltage doubler coupled to the frequency oscillator, wherein the voltage doubler will increase the current to the non-volatile storage system in response to an increased frequency from the frequency oscillator. [4] Device according to claim 1, wherein the standby control circuit further comprises: a first distributed analog driver coupled to a first sector of the non-volatile memory system; and a second distributed analog driver coupled to a second sector of the non-volatile memory system, wherein the first distributed analog driver and the second distributed analog driver are coupled to the bias control circuit. [5] Device according to claim 1, wherein the standby control circuit provides an indication that the device is in a standby mode if no read request is present for at least three clock cycles of the non-volatile memory system. [6] Device according to claim 1, wherein the non-volatile storage system includes a charge capture storage device. [7] Device according to claim 1, wherein the non-volatile storage system comprises a silicon oxide nitride oxide silicon storage device (SONOS storage device). [8] A procedure that includes the following: Detecting a standby operating state of a non-volatile storage system; Detect that the non-volatile memory system is not in a wake-up mode; and reduce the bias currents supplied to the drivers of the non-volatile memory system in response to the detection of the standby operating state. [9] Method according to claim 8, wherein reducing the bias currents provided by the driver circuits includes: Reducing an initial bias current supplied to a frequency oscillator; Reducing a second bias current supplied to the distributed analog drivers; and Reducing a third bias current supplied to the voltage drivers of read path circuits of the non-volatile memory system. [10] The method according to claim 8, further comprising: Detecting a read instruction that accesses data from the non-volatile storage system; and Increasing the bias currents supplied to the drivers of the non-volatile memory system in response to the detection of the read instruction. [11] Method according to claim 10, wherein increasing the bias currents supplied to the drivers of the non-volatile memory system includes increasing a frequency bias current to a frequency oscillator to increase a frequency of an output of the frequency oscillator, wherein increasing the frequency from the frequency oscillator increases the current supplied to the read path circuits of the non-volatile memory system. [12] Method according to claim 10, wherein increasing the bias currents to driver circuits of the non-volatile memory system includes increasing the current to an analog driver of the non-volatile memory system. [13] Method according to claim 8, further comprising: detecting an instruction to wake up from a sleep state; and increasing the bias currents at driver circuits of the non-volatile memory system in response to the detection of the instruction to wake up from the sleep state. [14] Method according to claim 8, wherein the non-volatile storage system includes a charge capture storage device. [15] Method according to claim 8, wherein the non-volatile storage system comprises a silicon oxide nitride oxide silicon storage device (SONOS storage device). [16] A system that includes the following: a non-volatile storage system that includes a variety of drivers; and a standby control circuit coupled to the non-volatile memory system, wherein the standby control circuit includes the following: a standby detection circuit to detect that the non-volatile memory system is in a standby state; and a bias control circuit coupled with the standby detection circuit to provide bias currents to the plurality of drivers of the non-volatile memory system in a standby mode in response to a determination that the non-volatile memory system is in a standby state. [17] System according to claim 16, wherein the system further includes a wake-up detection circuit to detect that the non-volatile memory system is in a wake-up mode, wherein the bias control circuit of the plurality of drivers of the non-volatile memory system in an active mode provides bias currents in response to the detection that the non-volatile memory system is in a waking state. [18] System according to claim 16, wherein the system further comprises: a first distributed analog driver coupled to a first sector of the non-volatile memory system; and a second distributed analog driver coupled to a second sector of the non-volatile memory system, wherein the first distributed analog driver and the second distributed analog system are coupled to the bias control circuit. [19] System according to claim 16, wherein the non-volatile storage system includes a charge capture storage device. [20] System according to claim 16, wherein the non-volatile storage system comprises a silicon oxide nitride oxide silicon storage device (SONOS storage device).

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