Semiconductor memory device

Abstract

The present application provides a semiconductor memory device, although configured to be able to carry out the correction of the duty cycle of the switching signal, but still can inhibit the enlargement. The semiconductor memory device (2) has: comparator (51), generates and outputs the signal (RE_in) which is switched synchronously with the reading enable signal (RE) from the outside; and correction circuit (60), adjusts the duty cycle of the signal (RE_in). The correction circuit (60) has the variable current source (61) connected with the first output part (513) of the comparator (51), and the variable current source (62) connected with the second output part (514) of the comparator (51), by adjusting the size of the current output from the current source (61, 62), to adjust the duty cycle of the signal ( / RE_c, RE_c).

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-058234 (filed on March 31, 2022). This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] For example, semiconductor memory devices such as NAND flash memory output read data based on signals sent from the memory controller. When outputting read data, the semiconductor memory device also outputs a switching signal indicating the output timing. Summary of the Invention

[0005] According to the disclosed embodiments, a semiconductor memory device is provided that is configured to both modify the duty cycle of switching signals and suppress large-scale development.

[0006] The semiconductor memory device of the embodiment includes: a receiving unit for receiving a first switching signal from an external source; a first comparator for generating and outputting a second switching signal that switches synchronously with the first switching signal; an adjustment unit for adjusting the duty cycle of the second switching signal; and a transmitting unit for transmitting the second switching signal with the adjusted duty cycle, or a switching signal generated based on the second switching signal, to an external source. The second switching signal output from the first comparator includes a third switching signal and a fourth switching signal that is a complementary signal to the third switching signal. The first comparator has: a first input unit for inputting the first switching signal; a second input unit for inputting a reference signal; a first output unit for outputting a third switching signal that switches according to the magnitude relationship between the first switching signal and the reference signal; and a second output unit for outputting the fourth switching signal. The adjustment unit has a variable current source connected to at least one of the first input unit, the second input unit, the first output unit, and the second output unit, and adjusts the duty cycle of the second switching signal by adjusting the magnitude of the current output from the current source. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a configuration example of the memory system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating a configuration example of the memory system according to the first embodiment.

[0009] Figure 3 This is a block diagram illustrating the configuration of the semiconductor memory device according to the first embodiment.

[0010] Figure 4 It is an equivalent circuit diagram representing the structure of a memory cell array.

[0011] Figure 5 It is a cross-sectional view showing the structure of the memory cell array.

[0012] Figure 6 This is a diagram showing the circuit configuration of a sense amplifier group.

[0013] Figure 7 This is a diagram illustrating an example of the threshold distribution of a memory cell transistor.

[0014] Figure 8 It is a graph showing the potential changes of each wiring during a write operation.

[0015] Figure 9 It is a graph showing the potential changes of each wiring during the readout operation.

[0016] Figure 10 This is a diagram illustrating an example of the time variation of signals transmitted and received between the semiconductor memory device and the memory controller in the comparative example.

[0017] Figure 11 (A) and (B) are diagrams used to illustrate the duty cycle of the switching signal.

[0018] Figure 12 This is a diagram schematically illustrating a portion of the configuration of the semiconductor memory device according to the first embodiment.

[0019] Figure 13 This is a diagram showing the configuration of the receiving circuit and the correction circuit in the semiconductor memory device of the first embodiment.

[0020] Figure 14 This is a diagram representing an example of a correction code.

[0021] Figure 15 This is a diagram illustrating an example of a switching signal.

[0022] Figure 16 This is a diagram illustrating an example of a switching signal.

[0023] Figure 17 This is a diagram illustrating an example of a switching signal.

[0024] Figure 18 This diagram illustrates the configuration of the receiving circuit and the correction circuit in the semiconductor memory device of the second embodiment.

[0025] Figure 19 This diagram illustrates the configuration of the receiving circuit and the correction circuit in the semiconductor memory device of the third embodiment.

[0026] Figure 20 This diagram illustrates the configuration of the receiving circuit and the correction circuit in the semiconductor memory device of the fourth embodiment.

[0027] Figure 21 This diagram illustrates the configuration of the receiving circuit and the correction circuit included in the semiconductor memory device of the fifth embodiment.

[0028] Figure 22 This diagram illustrates the configuration of the receiving circuit and the correction circuit in the semiconductor memory device of the sixth embodiment.

[0029] Figure 23 This diagram illustrates the configuration of the receiving circuit and the correction circuit in the semiconductor memory device of the seventh embodiment.

[0030] Figure 24 This is a diagram showing the configuration of the receiving circuit and the correction circuit of the comparative example semiconductor memory device. Detailed Implementation

[0031] Hereinafter, this embodiment will be described with reference to the accompanying drawings. For ease of understanding, the same reference numerals will be used for the same constituent elements in each drawing, and repeated descriptions will be omitted.

[0032] The first embodiment will be described. The semiconductor memory device 2 in this embodiment is a non-volatile memory device configured as a NAND flash memory. Figure 1 The diagram below shows an example of the configuration of a memory system including a semiconductor memory device 2. The memory system includes a memory controller 1 and a semiconductor memory device 2.

[0033] Furthermore, in practical memory systems, such as Figure 2 As shown, multiple semiconductor memory devices 2 are provided relative to one memory controller 1. Figure 1 The diagram shows only one of the multiple semiconductor memory devices 2 present. The specific configuration of the semiconductor memory device 2 will be described below.

[0034] This memory system can be connected to a host device (not shown). The host device could be, for example, a personal computer, a mobile terminal, or other electronic device. The memory controller 1 controls the writing of data to the semiconductor memory device 2 based on write requests from the host. Furthermore, the memory controller 1 controls the reading of data from the semiconductor memory device 2 based on read requests from the host.

[0035] The memory controller 1 and the semiconductor storage device 2 transmit and receive the following signals: chip enable signal / CE, ready-to-work signal R / B, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, RE, write protection signal / WP, data signal DQ<7:0>, data strobe signal DQS, and / DQS.

[0036] The chip enable signal / CE is used to enable the semiconductor memory device 2. The ready / busy signal R / B is used to indicate whether the semiconductor memory device 2 is in a ready state or a busy state. "Ready state" means that it is accepting commands from the outside. "Busy state" means that it is not accepting commands from the outside.

[0037] like Figure 2 As shown, the chip enable signal / CE is individually sent to each of the multiple semiconductor memory devices 2. Figure 2 In this context, for example, " / CE0" is appended with a number to the end to distinguish the various chip enable signals / CE from one another.

[0038] Similarly, a ready-to-work signal R / B is sent individually from each of the multiple semiconductor memory devices 2. Figure 2 In this context, a number is appended to the end, such as "R / B0", to distinguish the various ready-to-work signals R / B from one another.

[0039] Signals other than the chip enable signal / CE and the ready / busy signal R / B (such as the instruction latch enable signal CLE) are transmitted and received between the memory controller 1 and the semiconductor memory devices 2 via a signal line common to multiple semiconductor memory devices 2. The memory controller 1 uses an individual chip enable signal / CE to identify the semiconductor memory device 2 as the communication target.

[0040] The instruction latch enable signal CLE indicates that signals DQ<7:0> represent instructions. The address latch enable signal ALE indicates that signals DQ<7:0> represent addresses. The write enable signal / WE is used to fetch received signals into the semiconductor memory device 2, and it takes effect whenever instructions, addresses, and data are received through the memory controller 1. The memory controller 1 instructs the semiconductor memory device 2 to fetch signals DQ<7:0> while the signal / WE is at a "L" level.

[0041] The read enable signal / RE is used to enable the memory controller 1 to read data from the semiconductor memory device 2. Signal RE is the complementary signal to signal / RE. These signals are used, for example, to control the timing of the operation of the semiconductor memory device 2 when outputting signal DQ<7:0>. The write protect signal / WP is used to instruct the semiconductor memory device 2 to prohibit data writing and erasure. Signals DQ<7:0> are the entities of data transmitted and received between the semiconductor memory device 2 and the memory controller 1, including instructions, addresses, and data. The data strobe signal DQS is used to control the timing of the input and output of signal DQ<7:0>. Signal / DQS is the complementary signal to signal DQS.

[0042] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0043] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. Furthermore, the host interface 13 sends user data read from the semiconductor storage device 2, responses from the processor 12, etc., to the host.

[0044] The memory interface 15 controls the processes of writing user data to the semiconductor storage device 2 and reading user data from the semiconductor storage device 2 according to the instructions of the processor 12.

[0045] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit), an MPU (Microprocessor Unit), or the like. Upon receiving a request from the host via host interface 13, processor 12 performs control according to that request. For example, based on a request from the host, processor 12 instructs memory interface 15 to write user data and parity data to semiconductor storage device 2. Furthermore, based on a request from the host, processor 12 instructs memory interface 15 to read user data and parity data from semiconductor storage device 2.

[0046] The processor 12 determines the storage area (memory region) on the semiconductor memory device 2 for the user data stored in RAM 11. The user data is stored in RAM 11 via the internal bus 16. The processor 12 determines the memory region for data in page units (page data) as write units. Hereinafter, the user data stored in one page of the semiconductor memory device 2 will also be referred to as "group data". Group data is generally encoded and stored in the semiconductor memory device 2 in the form of code words. Encoding is not mandatory in this embodiment. The memory controller 1 may also store group data in the semiconductor memory device 2 without encoding, but... Figure 1 The diagram illustrates an encoding configuration as an example. When the memory controller 1 does not perform encoding, the page data and the group data are identical. Furthermore, a codeword can be generated from one group of data, or from segmented data obtained by dividing the group data. Alternatively, multiple groups of data can be used to generate a single codeword.

[0047] Processor 12 determines the memory region of semiconductor storage device 2 as the write destination for each group of data. Physical addresses are allocated to the memory regions of semiconductor storage device 2. Processor 12 uses physical addresses to manage the memory regions as write destinations for groups of data. Processor 12 specifies the determined memory region (physical address) to instruct memory interface 15 to write user data to semiconductor storage device 2. Processor 12 manages the mapping between logical addresses (host-managed logical addresses) and physical addresses of user data. Upon receiving a read request containing a logical address from the host, processor 12 specifies the physical address corresponding to the logical address and instructs memory interface 15 to read the user data.

[0048] ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Furthermore, ECC circuit 14 decodes the codewords read from semiconductor memory device 2. ECC circuit 14 detects and corrects errors in the data using, for example, a checksum assigned to the user data.

[0049] RAM 11 temporarily stores user data received from the host before storing it in the semiconductor storage device 2, or temporarily stores data read from the semiconductor storage device 2 before sending it to the host. RAM 11 is, for example, a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0050] Figure 1The diagram shows an example configuration where the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Furthermore, the ECC circuit 14 can also be integrated into the semiconductor memory device 2. Figure 1 The specific composition and configuration of the elements shown are not particularly limited.

[0051] In the event that a write request is received from the host Figure 1 The memory system operates as follows: Processor 12 temporarily stores data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and inputs the code word to memory interface 15. Memory interface 15 writes the input code word to semiconductor memory device 2.

[0052] When a read request is received from the host Figure 1 The memory system operates as follows: The memory interface 15 inputs the codewords read from the semiconductor memory device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codewords and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0053] The configuration of semiconductor memory device 2 will be described. For example... Figure 3 As shown, the semiconductor memory device 2 includes two planar circuits PL1 and PL2, an input / output circuit 21, a logic control circuit 22, a sequencer 41, a register 42, a voltage generation circuit 43, an input / output pad group 31, a logic control pad group 32, and a power input terminal group 33.

[0054] Plane PL1 includes a memory cell array 110, a sense amplifier 120, and a line decoder 130. Plane PL2 includes a memory cell array 210, a sense amplifier 220, and a line decoder 230. The configurations of plane PL1 and plane PL2 are identical. That is, the configurations of memory cell array 110 and memory cell array 210 are identical, the configurations of sense amplifier 120 and sense amplifier 220 are identical, and the configurations of line decoder 130 and line decoder 230 are identical. The number of planes disposed on the semiconductor memory device 2 can be two as in this embodiment, but it can also be one, or three or more.

[0055] Memory cell arrays 110 and 210 are the data storage portions. Each of memory cell arrays 110 and 210 includes multiple memory cell transistors associated with word lines and bit lines. Their specific configuration will be described below.

[0056] Input / output circuit 21 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with memory controller 1. Input / output circuit 21 transfers the instruction and address contained in signal DQ<7:0> to register 42. Furthermore, input / output circuit 21 transmits and receives write data and read data with sense amplifier 120 and sense amplifier 220. Input / output circuit 21 includes input circuitry (not shown) and output circuitry 80 (…). Figure 3 (See diagram below for reference) Figure 12 Both of these, the input circuit receives instructions from the memory controller 1, and the output circuit 80 outputs data to the memory controller 1.

[0057] The logic control circuit 22 receives the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP from the memory controller 1. Furthermore, the logic control circuit 22 transmits the ready-to-work signal R / B to the memory controller 1 to notify the external system of the status of the semiconductor memory device 2.

[0058] Both the input / output circuit 21 and the logic control circuit 22 are configured to input / output signals with the memory controller 1. That is, the input / output circuit 21 and the logic control circuit 22 serve as an interface circuit for the semiconductor memory device 2.

[0059] The sequencer 41 controls the operation of various parts such as plane PL1, PL2, and voltage generation circuit 43 according to the control signals input from memory controller 1 to semiconductor memory device 2. The sequencer 41 is the part that controls the operation of various parts such as logic control circuit 22, memory cell array 110, 210, etc., and is equivalent to the "control unit" of semiconductor memory device 2.

[0060] Register 42 is the part that temporarily stores instructions and addresses. Register 42 also serves as the part that stores status information representing the status of each plane PL1, PL2. According to the request from the memory controller 1, the status information is output to the memory controller 1 from the input / output circuit 21 in the form of status signals.

[0061] The voltage generation circuit 43 generates the voltages required for data write, read, and erase operations in the memory cell arrays 110 and 210 according to instructions from the sequencer 41. These voltages include, for example, the voltages applied to the word line WL (VPGM, VPASS_PGM, VPASS_READ) and the voltage applied to the bit line BL. The voltage generation circuit 43 can individually apply voltages to each word line WL, bit line BL, etc., in a manner in which planes PL1 and PL2 can operate in parallel.

[0062] The input / output pad group 31 is a portion provided with multiple terminals (pads) for transmitting and receiving signals between the memory controller 1 and the input / output circuit 21. Each terminal is individually provided corresponding to the signals DQ<7:0> and the data strobe signals DQS and / DQS.

[0063] The logic control pad group 32 is a portion provided with multiple terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the logic control circuit 22. Each terminal is individually configured corresponding to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protection signal / WP, and ready busy signal R / B.

[0064] The power input terminal group 33 is a portion provided with multiple terminals for receiving the applied voltages required for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltages Vcc, VccQ, Vpp, and the ground voltage Vss.

[0065] The power supply voltage Vcc is the circuit power supply voltage supplied externally as the operating power source, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is the voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0066] When writing or erasing data to the memory cell arrays 110 and 210, a high voltage of approximately 20V (VPGM) is required. In this case, compared to boosting the approximately 3.3V power supply voltage Vcc using the boost circuit of voltage generation circuit 43, boosting the approximately 12V power supply voltage Vpp allows for high-speed and low-power generation of the required voltage. On the other hand, if the semiconductor memory device 2 is used in an environment where a high voltage cannot be supplied, the power supply voltage Vpp may not be supplied. Even without supplying the power supply voltage Vpp, the semiconductor memory device 2 can perform various operations as long as the power supply voltage Vcc is supplied. That is, the power supply voltage Vcc is the standard power supply supplied to the semiconductor memory device 2, while the power supply voltage Vpp is an additional, arbitrary power supply supplied, for example, depending on the usage environment.

[0067] The configurations of planes PL1 and PL2 will be explained. Furthermore, as mentioned above, the configurations of plane PL1 and plane PL2 are identical. Therefore, only the configuration of plane PL1 will be explained below; the configuration of plane PL2 will be omitted from the illustrations and explanations.

[0068] Figure 4 The diagram shows the configuration of a memory cell array 110 disposed on plane PL1 as an equivalent circuit diagram. The memory cell array 110 is composed of multiple blocks BLK, but... Figure 4 The diagram only shows one block BLK from these blocks. The composition of the other block BLKs in the storage cell array 110 is also similar. Figure 4 same.

[0069] like Figure 4 As shown, block BLK contains, for example, four string groups SU (SU0 to SU3). Furthermore, each string group SU contains multiple NAND strings NS. Each NAND string NS contains, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2.

[0070] Furthermore, the number of memory cell transistors MT is not limited to 8; for example, it can be 32, 48, 64, or 96. For instance, to improve disconnection characteristics, select transistors ST1 and ST2 are composed of multiple transistors instead of a single transistor. Moreover, dummy cell transistors can also be provided between the memory cell transistor MT and the select transistors ST1 and ST2.

[0071] The memory cell transistor MT is configured in series between the select transistor ST1 and the select transistor ST2. The memory cell transistor MT7 on one side is connected to the source of the select transistor ST1, and the memory cell transistor MT0 on the other side is connected to the drain of the select transistor ST2.

[0072] The gates of the select transistors ST1 for each string group SU0 to SU3 are all connected to the select gate lines SGD0 to SGD3. The gates of the select transistor ST2 are all connected to the same select gate line SGS across multiple string groups SU within the same block BLK. The gates of the memory cell transistors MT0 to MT7 within the same block BLK are all connected to the word lines WL0 to WL7. That is, the word lines WL0 to WL7 and the select gate line SGS are shared across multiple string groups SU0 to SU3 within the same block BLK, while the select gate line SGD is individually configured for each string group SU0 to SU3, even within the same block BLK.

[0073] The memory cell array 110 has m bit lines BL (BL0, BL1, ..., BL(m-1)). "m" is an integer representing the number of NAND strings NS contained in a string group SU. In each NAND string NS, the drain of the select transistor ST1 is connected to the corresponding bit line BL. The source of the select transistor ST2 is connected to the source line SL. The source lines SL are commonly connected to the sources of the multiple select transistors ST2 in block BLK.

[0074] Data stored in multiple memory cell transistors MT within the same block BLK is erased all at once. Conversely, data is read from and written to multiple memory cell transistors MT connected to one word line WL and belonging to one string group SU all at once. Each memory cell can store 3 bits of data, including the upper order bit, the middle order bit, and the lower order bit.

[0075] That is, the semiconductor memory device 2 of this embodiment uses a TLC (Triple Level Cell) method, in which one memory cell transistor MT stores 3 bits of data, as the data writing method to the memory cell transistor MT. Alternatively, an MLC (Multi Level Cell) method, in which one memory cell transistor MT stores 2 bits of data, may be used as the data writing method to the memory cell transistor MT. The number of bits of data stored in one memory cell transistor MT is not particularly limited.

[0076] Additionally, in the following description, the collection of one bit of data stored in multiple memory cell transistors MT that are connected to one word line WL and belong to one string group SU is called a "page". Figure 4 In this context, one of the sets containing the plurality of memory cell transistors T is designated with the symbol "MG".

[0077] In the case where 3 bits of data are stored in one memory cell transistor MT as described in this embodiment, a set of multiple memory cell transistors MT connected to a common word line WL within a single string group SU can store 3 pages of data. Hereinafter, the page containing the set of lower-order bits will be referred to as the "lower-order page," and the data on the lower-order page will also be referred to as "lower-order page data." Similarly, the page containing the set of middle-order bits will be referred to as the "middle-order page," and the data on the middle-order page will also be referred to as "middle-order page data." The page containing the set of upper-order bits will be referred to as the "upper-order page," and the data on the upper-order page will also be referred to as "upper-order page data."

[0078] Figure 5 The diagram shows a schematic cross-sectional view of the memory cell array 110 and its surroundings. As shown, in the memory cell array 110, multiple NAND strings NS are formed above the conductive layer 320. The conductive layer 320 is also called the embedded source line (BSL), which is equivalent to... Figure 4 The source line SL.

[0079] Above the conductor layer 320, the stacked layer includes multiple wiring layers 333 that function as select gate line (SGS), multiple wiring layers 332 that function as word line (WL), and multiple wiring layers 331 that function as select gate line (SGD). An insulating layer (not shown) is disposed between each of the wiring layers 333, 332, and 331 of the stacked layer.

[0080] Multiple memory vias 334 are formed in the memory cell array 110. Each memory via 334 is a hole that penetrates the wiring layers 333, 332, 331 and an insulating layer (not shown) located between them in the vertical direction, reaching the conductor layer 320. A barrier insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side of each memory via 334, and a conductive pillar 338 is embedded inside it. The conductive pillar 338 may contain, for example, polysilicon, and functions as a channel forming area when the memory cell transistors MT and select transistors ST1 and ST2 contained in the NAND string NS are activated. Thus, a pillar-shaped structure comprising the barrier insulating film 335, the charge storage layer 336, the gate insulating film 337, and the conductive pillar 338 is formed inside the memory via 334.

[0081] The portions of the pillars formed inside the memory holes 334 that intersect with the stacked wiring layers 333, 332, and 331 function as transistors. Among these transistors, the portion intersecting with wiring layer 331 functions as a select transistor ST1. The portion intersecting with wiring layer 332 functions as memory cell transistors MT (MT0 to MT7). The portion intersecting with wiring layer 333 functions as a select transistor ST2. With this configuration, the pillars formed inside each memory hole 334 serve as references... Figure 4 The NAND string NS is explained below. The conductive pillar 338 located inside the pillar is the part that functions as a channel for the memory cell transistor MT, the selection transistors ST1 and ST2.

[0082] A wiring layer that functions as a bit line BL is formed above the conductor post 338. At the upper end of the conductor post 338, a contact plug 339 is formed to connect the conductor post 338 and the bit line BL.

[0083] and Figure 5 The configuration shown is the same along the configuration. Figure 5 There are multiple [items] arranged along the depth direction of the paper. [This is due to] the [various] [arrange Figure 5 A set of multiple NAND strings NS arranged in a row along the depth direction of the paper forms a string group SU.

[0084] In the semiconductor memory device 2 of this embodiment, a peripheral circuit PER is provided on the lower side of the memory cell array 110, that is, at a position between the memory cell array 110 and the semiconductor substrate 300. The peripheral circuit PER is a circuit provided to realize data writing operations, reading operations, and erasing operations in the memory cell array 110. Figure 3 The sensor amplifier 120, line decoder 130, and voltage generation circuit 43 shown are part of the peripheral circuit PER. The peripheral circuit PER includes various transistors, RC (resistor-capacitor) circuits, etc. Figure 5 In the example shown, the transistor TR formed on the semiconductor substrate 300 is electrically connected to the bit line BL located on the upper side of the memory cell array 110 via a contact 924.

[0085] Alternatively, instead of this configuration, the memory cell array 110 can be directly disposed on the semiconductor substrate 300. In this case, the p-type well region of the semiconductor substrate 300 functions as the source line SL. Furthermore, the peripheral circuit PER is disposed along the surface of the semiconductor substrate 300 at a position adjacent to the memory cell array 110.

[0086] return Figure 3 Continuing the explanation. As mentioned above, in addition to the memory cell array 110, the plane PL1 also includes a sense amplifier 120 and a line decoder 130.

[0087] The sense amplifier 120 is a circuit used to adjust the voltage applied to the bit line BL, or to read out the voltage of the bit line BL and convert it into data. When reading data, the sense amplifier 120 acquires the read data read from the memory cell transistor MT to the bit line BL and transmits the acquired read data to the input / output circuit 21. When writing data, the sense amplifier 120 transmits the write data written via the bit line BL to the memory cell transistor MT.

[0088] The line decoder 130 is a circuit (not shown) configured to apply voltage to each word line WL. The line decoder 130 receives a block address and a line address from register 42, selects the corresponding block BLK based on the block address, and selects the corresponding word line WL based on the line address. The line decoder 130 switches the switch group by applying a voltage from voltage generation circuit 43 to the selected word line WL.

[0089] Figure 6 The diagram shows an example of the configuration of the sense amplifier 120. The sense amplifier 120 includes multiple sense amplifier groups SAU that are associated with each of the multiple bit lines BL. Figure 6 The detailed circuit configuration of one of the sense amplifier groups SAU is extracted from the data.

[0090] like Figure 6 As shown, the sense amplifier group SAU includes a sense amplifier section SA and latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS to enable them to send and receive data.

[0091] The sensing amplifier section SA, for example, senses the data read to the corresponding bit line BL during the readout operation and determines whether the read data is "0" or "1". The sensing amplifier section SA includes, for example, a transistor TR1 as a p-channel MOS (Metal Oxide Semiconductor) transistor, transistors TR2 to TR9 as n-channel MOS transistors, and a capacitor C10.

[0092] One end of transistor TR1 is connected to the power supply line, and the other end is connected to transistor TR2. The gate of transistor TR1 is connected to node INV in the latch circuit SDL. One end of transistor TR2 is connected to transistor TR1, and the other end is connected to node COM. The gate input signal for transistor TR2 is BLX. One end of transistor TR3 is connected to node COM, and the other end is connected to transistor TR4. The gate input signal for transistor TR3 is BLC. Transistor TR4 is a high-voltage MOS transistor. One end of transistor TR4 is connected to transistor TR3. The other end of transistor TR4 is connected to the corresponding bit line BL. The gate input signal for transistor TR4 is BLS.

[0093] Transistor TR5 is connected to node COM at one end and to node SRC at the other end. The gate of transistor TR5 is connected to node INV. Transistor TR6 is connected between transistors TR1 and TR2 at one end, and to node SEN at the other end. The gate input signal for transistor TR6 is HLL. Transistor TR7 is connected to node SEN at one end and to node COM at the other end. The gate input signal for transistor TR7 is XXL.

[0094] One end of transistor TR8 is grounded, and the other end is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end is connected to the bus LBUS. The STB signal is input to the gate of transistor TR9. One end of capacitor C10 is connected to node SEN. The clock CLK is input to the other end of capacitor C10.

[0095] Signals BLX, BLC, BLS, HLL, XXL, and STB are generated, for example, by sequencer 41. Furthermore, an internal power supply voltage, such as Vdd, of the semiconductor memory device 2 is applied to the power supply line connected to one end of transistor TR1, and a ground voltage, such as Vss, of the semiconductor memory device 2 is applied to node SRC.

[0096] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily store the read data. The latch circuit XDL is connected to the input / output circuit 21 and is used to sense the input / output of data between the sense amplifier bank SAU and the input / output circuit 21. The read data becomes in a state where it can be output from the input / output circuit 21 to the memory controller 1 by being held in the latch circuit XDL. For example, after storing the data read by the sense amplifier bank SAU in any one of the latch circuits ADL, BDL, and CDL, it is transferred to the latch circuit XDL and output from the latch circuit XDL to the input / output circuit 21. Further, for example, the data input from the memory controller 1 to the input / output circuit 21 is transferred from the input / output circuit 21 to the latch circuit XDL and then transferred from the latch circuit XDL to any one of the latch circuits ADL, BDL, and CDL.

[0097] The latch circuit SDL includes, for example, inverters IV11 and IV12, and transistors TR13 and TR14 which are n-channel MOS transistors. The input node of the inverter IV11 is connected to the node LAT. The output node of the inverter IV11 is connected to the node INV. The input node of the inverter IV12 is connected to the node INV. The output node of the inverter IV12 is connected to the node LAT. One end of the transistor TR13 is connected to the node INV, and the other end of the transistor TR13 is connected to the bus LBUS. The signal STI is input to the gate of the transistor TR13. One end of the transistor TR14 is connected to the node LAT, and the other end of the transistor TR14 is connected to the bus LBUS. The signal STL is input to the gate of the transistor TR14. For example, the data stored in the node LAT corresponds to the data stored in the latch circuit SDL. Further, the data stored in the node INV corresponds to the inverted data of the data stored in the node LAT. The circuit configurations of the latch circuits ADL, BDL, CDL, and XDL are the same as that of the latch circuit SDL, for example, and thus the description thereof is omitted.

[0098] Figure 7 is a diagram schematically showing the threshold distribution etc. of the memory cell transistor MT. The Figure 7 middle diagram shows the correspondence between the threshold voltage (horizontal axis) of the memory cell transistor MT and the number of memory cell transistors MT (vertical axis).

[0099] In the case of adopting the TLC method as in the present embodiment, multiple memory cell transistors MT form eight threshold distributions as shown in the Figure 7 middle diagram. These eight threshold distributions (write levels) are referred to as "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level in the order of increasing threshold voltage.

[0100] The Figure 7 The table above shows an example of the data allocated to each of the threshold voltage levels. As shown in the table, different 3-bit data are allocated, for example, to the “ER” level, “A” level, “B” level, “C” level, “D” level, “E” level, “F” level, and “G” level.

[0101] “ER” level: “111” (“Lower order / Middle order / Upper order”)

[0102] "A" level: "011"

[0103] "B" level: "001"

[0104] "C" level: "000"

[0105] "D" level: "010"

[0106] "E" level: 110

[0107] "F" level: 100

[0108] "G" level: 101

[0109] Thus, the threshold voltage of the memory cell transistor MT in this embodiment can be one of eight pre-set candidate levels, and data is allocated as described above corresponding to each candidate level.

[0110] Verification voltages used during the write operation are set between two adjacent pairs of threshold distributions. Specifically, verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set corresponding to the "A", "B", "C", "D", "E", "F", and "G" levels, respectively.

[0111] The verification voltage VfyA is set between the maximum threshold voltage in the "ER" level and the minimum threshold voltage in the "A" level. When the verification voltage VfyA is applied to the word line WL, the memory cell transistor MT connected to the word line WL with a threshold voltage in the "ER" level is turned on, and the memory cell transistor MT with a threshold voltage in the threshold distribution above the "A" level is turned off.

[0112] Other verification voltages VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set in the same manner as verification voltage VfyA. Verification voltage VfyB is set between the "A" level and the "B" level, verification voltage VfyC is set between the "B" level and the "C" level, verification voltage VfyD is set between the "C" level and the "D" level, verification voltage VfyE is set between the "D" level and the "E" level, verification voltage VfyF is set between the "E" level and the "F" level, and verification voltage VfyG is set between the "F" level and the "G" level.

[0113] For example, the verification voltage VfyA can be set to 0.8V, VfyB to 1.6V, VfyC to 2.4V, VfyD to 3.1V, VfyE to 3.8V, VfyF to 4.6V, and VfyG to 5.6V. However, this is not a limitation; the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG can be appropriately set in stages within the range of 0V to 7.0V.

[0114] Furthermore, readout voltages used in the readout operation are set between adjacent threshold distributions. "Readout voltage" refers to the voltage applied to the word line WL, i.e., the select word line, connected to the memory cell transistor MT that is being read, during the readout operation. During the readout operation, data is determined based on whether the threshold voltage of the memory cell transistor MT that is being read is higher than the applied readout voltage.

[0115] like Figure 7 As illustrated in the lower section of the diagram, specifically, the read voltage VrA used to determine whether the threshold voltage of the memory cell transistor MT is contained within the "ER" level or within a level above the "A" level is set between the maximum threshold voltage in the "ER" level and the minimum threshold voltage in the "A" level.

[0116] Other readout voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same manner as readout voltage VrA. Readout voltage VrB is set between the "A" level and the "B" level, readout voltage VrC is set between the "B" level and the "C" level, readout voltage VrD is set between the "C" level and the "D" level, readout voltage VrE is set between the "D" level and the "E" level, readout voltage VrF is set between the "E" level and the "F" level, and readout voltage VrG is set between the "F" level and the "G" level.

[0117] Furthermore, the read pass voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (e.g., "G" level). The memory cell transistor MT, whose gate is subject to the read pass voltage VPASS_READ, is turned on regardless of the data stored.

[0118] Additionally, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are, for example, set to be higher than the readout voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG, respectively. That is, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set near the lower edge of the threshold distributions for levels "A," "B," "C," "D," "E," "F," and "G," respectively.

[0119] When applying the data allocation described above, during the readout operation, the lower-order page data (lower-order page data) can be determined using the readout results of readout voltages VrA and VrE. The middle-order page data (middle-order page data) can be determined using the readout results of readout voltages VrB, VrD, and VrF. The upper-order page data (upper-order page data) can be determined using the readout results of readout voltages VrC and VrG. Thus, the lower-order page data, middle-order page data, and upper-order page data are determined through 2, 3, and 2 readout operations respectively, hence this data allocation is called "2-3-2 code".

[0120] Furthermore, the data allocation described above is merely an example, and actual data allocation is not limited to this. For example, 2 or more bits of data can be stored in a single memory cell transistor MT. Additionally, the number of threshold distributions for data allocation (i.e., the number of "candidate levels") can be 7 or fewer, or 9 or more. For example, "1-3-3 code" or "1-2-4 code" can be used instead of "2-3-2 code". Furthermore, the allocation of lower-order bits / middle-order bits / upper-order bits can be changed, for example. More specifically, for example, in "2-3-2 code", data can be allocated as follows: lower-order page data is determined by the readout results of readout voltages VrC and VrB; middle-order page data is determined by the readout results of readout voltages VrB, VrD, and VrF; and upper-order page data is determined by the readout results of readout voltages VrA and VrE. That is, the allocation of lower-order bits and upper-order bits can be interchanged, for example. In this case, data is allocated according to each level of the threshold voltage in the following manner.

[0121] “ER” level: “111” (“Lower order / Middle order / Upper order”)

[0122] Level "A": 110

[0123] "B" level: 100

[0124] "C" level: "000"

[0125] "D" level: "010"

[0126] "E" level: "011"

[0127] "F" level: "001"

[0128] "G" level: 101

[0129] The write operation performed in the semiconductor memory device 2 will be described. The write operation includes a programming operation and a verification operation. The "programming operation" refers to the operation of changing the threshold voltage of a portion of the memory cell transistor MT by injecting electrons into the charge storage layer 336 of that memory cell transistor MT. The "verification operation" refers to the operation of determining whether the threshold voltage of the memory cell transistor MT has reached a target level by reading data after the programming operation. A memory cell transistor MT whose threshold voltage reaches the target level is subsequently disabled from writing. The "target level" referred to here is a specific candidate level set as the target level from the eight candidate levels.

[0130] During the write operation, the above programming and verification actions are repeated. As a result, the threshold voltage of the memory cell transistor MT rises to the target level.

[0131] Hereinafter, the word line WL connected to the memory cell transistor MT that is the object of a write operation (i.e., the object that causes a change in the threshold voltage) among the multiple word lines WL will also be called a "select word line". Furthermore, the word line WL connected to the memory cell transistor MT that is not the object of a write operation will also be called a "non-select word line". The memory cell transistor MT that is the object of a write operation will also be called a "select memory transistor".

[0132] Hereinafter, the string group SU that is the object of the write operation among multiple string groups SU will also be referred to as the "selected string group". In addition, the string group SU that is not the object of the write operation will also be referred to as the "non-selected string group".

[0133] Hereinafter, the conductive pillars 338 of each NAND string NS contained in the selected string group, i.e., each channel in the selected string group, will also be referred to as "selection channels". In addition, the conductive pillars 338 of each NAND string NS contained in the non-selection string group, i.e., each channel in the non-selection string group, will also be referred to as "non-selection channels".

[0134] Hereinafter, the bit line BL connected to the select memory transistor will also be referred to as the "select bit line". In addition, the bit line BL not connected to the select memory transistor will also be referred to as the "non-select bit line".

[0135] The programming actions will be explained below. The following example illustrates the case where the object of the programming action is plane PL1, but the same applies to the case of plane PL2. Figure 8 This indicates the potential changes of each bit line during programming. During programming, the sensing amplifier 120 changes the potential of each bit line BL in response to the programming data. For the bit line BL connected to the memory cell transistor MT that is being programmed (which should raise the threshold voltage), a voltage such as ground Vss (0V) is applied as the "L" level. For the bit line BL connected to the memory cell transistor MT that is not being programmed (which should maintain the threshold voltage), a voltage such as 2.5V is applied as the "H" level. The former bit line BL... Figure 8 The latter is denoted as "BL(0)". The bit line BL is in... Figure 8 It is denoted as "BL(1)".

[0136] The line decoder 130 selects any block BLK as the target of the write operation, and thus selects any string group SU. More specifically, the voltage generation circuit 43 applies, for example, 5V to the select gate line SGD (selected select gate line SGDsel) in the selected string group SU via the line decoder 130. As a result, the select transistor ST1 is turned on. On the other hand, the voltage generation circuit 43 applies, for example, a voltage Vss to the select gate line SGS via the line decoder 130. As a result, the select transistor ST2 is turned off.

[0137] Furthermore, a voltage of, for example, 5V is applied from the voltage generation circuit 43 to the selection gate line SGD (selection gate line SGDusel) of the non-selection string group SU in the selection block BLK via the line decoder 130. This turns on the selection transistor ST1. Additionally, the selection gate line SGS is commonly connected to the string groups SU contained in each block BLK. Therefore, the selection transistor ST2 in the non-selection string group SU is also turned off.

[0138] Furthermore, voltage Vss is applied, for example, to the select gate line SGD and select gate line SGS in the non-selection block BLK via the voltage generation circuit 43 and the line decoder 130. As a result, select transistors ST1 and ST2 are turned off.

[0139] The source line SL is set to a potential higher than the selected gate line SGS. This potential is, for example, 1V.

[0140] Subsequently, the potential of the selection gate line SGDsel in the selection block BLK is set to, for example, 2.5V. This potential is such that it turns on the selection transistor ST1 corresponding to the bit line BL(0), which is given 0V in the example, but turns off the selection transistor ST1 corresponding to the bit line BL(1), which is given 2.5V. Thus, in the selection string group SU, the selection transistor ST1 corresponding to the bit line BL(0) is turned on, and the selection transistor ST1 corresponding to the bit line BL(1), which is given 2.5V, is turned off. On the other hand, the potential of the non-selection gate line SGDusel is set to, for example, voltage Vss. Thus, in the non-selection string group SU, regardless of the potentials of the bit lines BL(0) and BL(1), the selection transistor ST1 is turned off.

[0141] Furthermore, the line decoder 130 selects any word line WL as the target for a write operation within the selection block BLK. From the voltage generation circuit 43, via the line decoder 130, a voltage such as VPGM is applied to the word line WL (selected word line WLsel) that is the target for the write operation. On the other hand, from the voltage generation circuit 43, via the line decoder 130, a voltage such as VPASS_PGM is applied to other word lines WL (non-selected word lines WLusel). The voltage VPGM is a high voltage used to inject electrons into the charge storage layer 336 through tunneling. The voltage VPASS_PGM is a voltage that turns on the memory cell transistor MT connected to the word line WL, but does not change the threshold voltage. VPGM is a voltage higher than VPASS_PGM.

[0142] In the NAND string NS corresponding to the bit line BL(0) which is being programmed, the selection transistor ST1 is turned on. Therefore, the channel potential of the memory cell transistor MT connected to the selection word line WLsel is 0V. The potential difference between the control gate and the channel increases, resulting in the injection of electrons into the charge storage layer 336, thus raising the threshold voltage of the memory cell transistor MT.

[0143] In the NAND string NS corresponding to the bit line BL(1) which is not a programming target, the selection transistor ST1 is in the off state. Therefore, the channel of the memory cell transistor MT connected to the selection word line WLsel is electrically floating, and the channel potential rises to near the voltage VPGM through capacitive coupling with word lines WL, etc. The potential difference between the control gate and the channel becomes smaller, and as a result, no electrons are injected into the charge storage layer 336, thus maintaining the threshold voltage of the memory cell transistor MT. More precisely, the degree of change in the threshold voltage is not such that the threshold distribution level shifts to a higher distribution.

[0144] The readout action will be explained below. The following example describes the case where the object of the readout action is plane PL1, but the same applies to plane PL2. The verification action performed after the programming action is the same as the readout action described below. Figure 9 This indicates the potential changes of each wiring during a read operation. During a read operation, the NAND string NS containing the memory cell transistor MT that is the object of the read operation is selected. Alternatively, the string group SU containing the page that is the object of the read operation is selected.

[0145] First, from the voltage generation circuit 43 via the row decoder 130, an example of 5V is applied to the selected gate line SGDsel, the non-selected gate line SGDusel, and the selected gate line SGS. This turns on the selected transistors ST1 and ST2 contained in the selected block BLK. Furthermore, from the voltage generation circuit 43 via the row decoder 130, an example of a read pass voltage VPASS_READ is applied to the selected word line WLsel and the non-selected word line. The read pass voltage VPASS_READ is a voltage that turns on the memory cell transistor MT regardless of its threshold voltage and does not cause the threshold voltage to change. Therefore, current is conducted in all NAND strings NS contained in the selected block BLK, regardless of whether it is the selected string group SU or the non-selected string group SU.

[0146] Next, from the voltage generation circuit 43 via the line decoder 130, a read voltage Vr, such as VrA, is applied to the word line WL (select word line WLsel) connected to the memory cell transistor MT, which is the target of the read operation. A read pass voltage VPASS_READ is applied to the other word lines (non-select word lines WLusel).

[0147] Furthermore, while maintaining the voltage applied to the selected gate line SGDsel and the selected gate line SGS, a voltage, for example, Vss, is applied from the voltage generation circuit 43 to the non-selected selected gate line SGDusel via the line decoder 130. As a result, the selected transistor ST1 included in the selected string group SU remains in the ON state, but the selected transistor ST1 included in the non-selected string group SU becomes ON. Additionally, regardless of whether it is the selected string group SU or the non-selected string group SU, the selected transistor ST2 included in the selected block BLK becomes ON.

[0148] Therefore, in the NAND strings NS contained in the non-select string group SU, at least the select transistor ST1 is in the off state, and thus no current path is formed. On the other hand, in the NAND strings NS contained in the select string group SU, a current path is formed or not formed depending on the relationship between the read voltage Vr applied to the select word line WLsel and the threshold voltage of the memory cell transistor MT.

[0149] The sense amplifier 120 applies a voltage to the bit line BL, which is connected to the selected NAND string NS. In this state, the sense amplifier 120 performs data readout based on the value of the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT, which is the target of the readout operation, is higher than the readout voltage applied to the memory cell transistor MT. Alternatively, data readout may be performed not based on the value of the current flowing through the bit line BL, but based on the time change of the potential in the bit line BL. In the latter case, the bit line BL is pre-charged to a predetermined potential.

[0150] The verification operation described above is performed in the same manner as the read operation described above. In the verification operation, a verification voltage, such as VfyA, is applied from the voltage generation circuit 43 to the word line WL connected to the memory cell transistor MT, which is the object of verification, via the line decoder 130.

[0151] Additionally, the application of a 5V voltage to the selection gate line SGDsel and the non-selection selection gate line SGDusel during the initial stage of the programming operation described above is sometimes omitted. Similarly, the application of a 5V voltage to the non-selection selection gate line SGDusel and the application of the read pass voltage VPASS_READ to the selection word line WLsel during the initial stage of the read operation (verification operation) described above is sometimes omitted.

[0152] The specific signal flow between the semiconductor storage device 2 and the memory controller 1 during the read operation will be explained. The following explanation will focus on the case where the read operation is performed on plane PL1, but the same applies to plane PL2.

[0153] Figure 10 The text shows examples of various signals transmitted and received between the semiconductor storage device 2 and the memory controller 1 in the configuration of this embodiment.

[0154] During a read operation, the memory controller 1 sequentially inputs signals including "05h", multiple "ADD", and "E0h" to the semiconductor storage device 2 as signals DQ<7:0>. "05h" is the instruction used to execute the read operation of data from the memory cell array 110. "ADD" is the signal specifying the address as the data read source. "E0h" is the instruction used to start the read operation.

[0155] Figure 10In the diagram, the timing of the input of "E0h" to the semiconductor memory device 2 is shown as time t0. At time t1, after a predetermined period from time t0, the memory controller 1 begins to switch between the read enable signals / RE and RE. As described above, the read enable signals / RE and RE are signals used by the memory controller 1 to read data from the semiconductor memory device 2, and they are input to the input / output pad group 31 of the semiconductor memory device 2. After time t1, the read enable signal / RE alternates between H level and L level.

[0156] The read enable signal RE, input from the external memory controller 1 to the semiconductor memory device 2, is equivalent to the "first switching signal" in this embodiment. Another read enable signal / RE is equivalent to the "reference signal" in this embodiment. However, these definitions are for convenience; the read enable signal / RE can also be considered equivalent to the "first switching signal," and the read enable signal RE can also be considered equivalent to the "reference signal." The logic control circuit 22 described above has the function of receiving both the read enable signals / RE and RE, and therefore is equivalent to the "receiving unit" in this embodiment.

[0157] Whenever the read enable signal / RE switches between H and L levels, the semiconductor memory device 2 outputs new data as the signal DQ<7:0>, and switches the data strobe signal DQS between H and L levels. In this way, the semiconductor memory device 2 performs high-speed data output corresponding to the rising and falling of the data strobe signal DQS, and is also known as "DDR SDRAMs" (Double data rate synchronous DRAMs).

[0158] Figure 10 In this diagram, the data output as signals DQ<7:0> are denoted as "D". Furthermore, the timing of outputting the initial data and switching the data strobe signal DQS is denoted as time t2. Figure 10 The dashed arrows in the diagram represent the correspondence between the switching of the read enable signal / RE input from the memory controller 1 and the switching of the data strobe signal DQS output from the semiconductor memory device 2.

[0159] As explained below, the data strobe signal DQS is a signal generated inside the semiconductor memory device 2 based on the read enable signal / RE, RE input from the memory controller 1, and it switches at approximately the same period as the read enable signal / RE, RE.

[0160] Furthermore, the output of read data from the semiconductor memory device 2 is performed by dividing a single data into even data containing an even number of bits and odd data containing an odd number of bits, and then outputting them alternately. Figure 10In the diagram, each data point marked "D" is output as either an even number or an odd number.

[0161] After acquiring one read data, memory controller 1 acquires the next read data in the timing sequence following the switching of the data strobe signal DQS. For example, memory controller 1 acquires read data in each of the timing sequences that are in the middle of the alternation of the data strobe signal DQS. In this way, memory controller 1 can acquire read data in each timing sequence synchronized with the switching of the data strobe signal DQS.

[0162] To achieve the acquisition of the read data, it is preferable that the ratio of the length of the period when the data strobe signal DQS is at the H level to the length of the period when it is at the L level, i.e., the duty cycle, is a preset fixed ratio (e.g., 50%).

[0163] Figure 11 (A) shows an example of a data strobe signal DQS that alternates between H and L levels. The single-point link in the figure represents the transition between H and L levels. Figure 11 In (A), the period during which the data strobe signal DQS exceeds the intermediate level is denoted as "TM1", and the period during which the data strobe signal DQS is below the intermediate level is denoted as "TM2". Figure 11 In example (A), the lengths of TM1 and TM2 are equal, and the duty cycle is 50%. Alternatively, the target value for the duty cycle can also be as follows: Figure 11 (A) is typically 50%, but may also be a different value than 50%.

[0164] Alternatively, the definition of duty cycle can differ from the above. For example, the period from when the data strobe signal DQS starts to rise until it starts to fall can be defined as TM1, and the period from when the data strobe signal DQS starts to fall until it starts to rise again can be defined as TM2, and the ratio of the two can be defined as the duty cycle.

[0165] The data strobe signal DQS is generated based on the read enable signal / RE and RE from the memory controller 1, as described above. Therefore, when the target value of the duty cycle of the data strobe signal DQS is 50%, it is preferable that the duty cycle of the read enable signal / RE, etc., from which it originates, is also 50%.

[0166] However, even assuming the duty cycle of the read enable signal / RE, etc., is 50% when it is sent from the memory controller 1, the duty cycle may sometimes change compared to the initial value until the signal reaches the semiconductor memory device 2. In this case, the duty cycle of the generated data strobe signal DQS will also become a value different from 50%.

[0167] Furthermore, the duty cycle may change further during the process of generating the data strobe signal DQS inside the semiconductor memory device 2 until the signal is output from the logic control pad group 32. Figure 11 (B) shows an example where the duty cycle of the data strobe signal DQS is less than 50% due to the various reasons mentioned above, i.e., an example where TM1 is shorter than TM2.

[0168] Therefore, the semiconductor memory device 2 of this embodiment includes a circuit that is used to correct the duty cycle of the data strobe signal DQS inside the semiconductor memory device 2 so that it is close to a target value (e.g., 50%).

[0169] Figure 12 schematic depiction Figure 3 This is a component of the semiconductor memory device 2 shown. For example... Figure 12 As shown, the logic control circuit 22 has a receiving circuit 50 and a correction circuit 60.

[0170] The receiving circuit 50 is a component that receives the read enable signals / RE and RE, and generates and outputs signals / RE_in and RE_in based on these signals. The signal / RE_in is a signal that is at level H when the read enable signal / RE is higher than the read enable signal RE, and at level L otherwise. The signal RE_in is a complementary signal to signal / RE_in. Signals / RE_in and RE_in can be referred to as signals that switch synchronously with the read enable signals / RE and RE (first switching signals), and are equivalent to the "second switching signal" in this embodiment. Among these signals, signal RE_in is also equivalent to the "third switching signal" in this embodiment, and signal / RE_in is also equivalent to the "fourth switching signal" in this embodiment. The specific configuration of the receiving circuit 50 used to generate signals RE_in and / RE_in will be described below.

[0171] The correction circuit 60 corrects the duty cycle of each of the signals / RE_in and RE_in and outputs the corrected signals / RE_c and RE_c to the output control circuit 70 described below. In other words, the correction circuit 60 is the part that adjusts the duty cycle of the signals / RE_in and RE_in, which are the second switching signals, and corresponds to the "adjustment unit" in this embodiment. The specific configuration and correction method of the correction circuit 60 will be described below.

[0172] like Figure 12 As shown, the input / output circuit 21 includes an output control circuit 70, an output circuit 80, and a detection circuit 90.

[0173] The output control circuit 70 generates signals / DQS_in and DQS_in based on signals / RE_c and RE_c. Signal / DQS_in is a switching signal that switches synchronously with signal / RE_c. Signal DQS_in is a complementary signal to signal / DQS_in and also switches synchronously with signal RE_c. Signal / DQS_in can also be the same as signal / RE_c, and signal DQS_in can also be the same as signal RE_c. The duty cycle of each of signals / DQS_in and DQS_in is approximately the same as the duty cycle of each of signals / RE_c and RE_c (i.e., the corrected duty cycle).

[0174] Output circuit 80 generates data strobe signals / DQS and DQS based on signals / DQS_in and DQS_in. Data strobe signal / DQS is a switching signal that switches synchronously with signal / DQS_in. Data strobe signal DQS is a complementary signal to data strobe signal / DQS and switches synchronously with signal DQS_in. Data strobe signal / DQS can also be the same signal as signal / DQS_in, and data strobe signal DQS can also be the same signal as signal DQS_in. The duty cycle of each of the data strobe signals / DQS and DQS is approximately the same as the duty cycle of each of signals / DQS_in and DQS_in (i.e., the modified duty cycle).

[0175] The data strobe signal / DQS, DQS can be referred to as a signal generated based on the second switching signal whose duty cycle is adjusted by the correction circuit 60. The data strobe signal / DQS, DQS can also be the second switching signal itself after the duty cycle is adjusted by the correction circuit 60. The input / output circuit 21 has the function of transmitting the data strobe signal / DQS, DQS to the outside, and therefore corresponds to the "transmission unit" in this embodiment.

[0176] As described above, the read enable signals / RE and RE input to the semiconductor memory device 2 pass sequentially through the receiving circuit 50, the correction circuit 60, the output control circuit 70, and the output circuit 80, and are finally output to the memory controller 1 as data strobe signals / DQS and DQS. During this process, the duty cycle of the signals is corrected in the correction circuit 60.

[0177] The detection circuit 90 is configured to generate a signal corresponding to the duty cycle of the input signal DQS_in and output this signal to the sequencer 41. The "signal corresponding to the duty cycle of the signal DQS_in" can be a binary signal indicating whether the duty cycle of the signal DQS_in is greater than a target value, or it can be a signal obtained by quantifying the duty cycle of the signal DQS_in using a specified resolution. Furthermore, the signal input to the detection circuit 90 may not be the signal DQS_in but rather the signal / DQS_in. Various known configurations can be used for the detection circuit 90, therefore, specific illustrations and descriptions are omitted.

[0178] After receiving the signal corresponding to the duty cycle of signal DQS_in from detection circuit 90, sequencer 41 generates the signal required for correcting the duty cycle and outputs this signal to correction circuit 60. Hereinafter, this signal will also be referred to as the "correction code". Correction circuit 60 corrects the duty cycles of signals / RE_in and RE_in according to the correction code input from sequencer 41.

[0179] Thus, in the semiconductor memory device 2, a correction code is generated based on the duty cycle of the signal DQS_in, located near the output side in the transmission path of the signal that is the source of the data strobe signal / DQS, DQS, and this correction code is fed back to correct the duty cycle of the signal / RE_in, etc. This allows the duty cycle of the data strobe signal / DQS, DQS to approach a predetermined target value.

[0180] refer to Figure 13 The specific configuration of the receiving circuit 50 will be described below. As shown in the figure, the receiving circuit 50 includes a comparator 51. The comparator 51 includes a first input section 511, a second input section 512, a first output section 513, and a second output section 514.

[0181] The first input section 511 is the part that receives the read enable signal RE as the first switching signal. The signal line SL1, which is used to send the read enable signal RE from the input / output pad group 31, is connected to the first input section 511.

[0182] The second input section 512 is the part that provides a read enable signal / RE as an input reference signal. The signal line SL2, which is used to send the read enable signal / RE from the input / output pad group 31, is connected to the second input section 512.

[0183] The first output section 513 is the part that outputs the signal RE_in as the third switching signal. The signal line SL3, which is used to send the signal RE_in to the output control circuit 70, is connected to the first output section 513.

[0184] The second output section 514 is the part that outputs the signal / RE_in as the fourth switching signal. The signal line SL4, which is used to send the signal / RE_in to the output control circuit 70, is connected to the first output section 513.

[0185] When the input read enable signal RE (first switching signal) is higher than the read enable signal / RE (reference signal), comparator 51 sets the signal / RE_in (fourth switching signal) to H level and outputs it from the second output unit 514, and sets the signal RE_in (third switching signal) to L level and outputs it from the first output unit 513. Otherwise, comparator 51 sets the signal / RE_in (fourth switching signal) to L level and outputs it from the second output unit 514, and sets the signal RE_in (third switching signal) to H level and outputs it from the first output unit 513. The comparator 51 operating in this manner can be configured using well-known structures, therefore, its specific illustrations and descriptions are omitted.

[0186] Both RE_in (the third switching signal) and signal / RE_in (the fourth switching signal) can be referred to as signals that are switched according to the magnitude relationship between the first switching signal and the reference signal. The comparator 51 configured above is equivalent to the "first comparator" in this embodiment.

[0187] Then, refer to Figure 13 The specific configuration of the correction circuit 60 is explained below. As shown in the figure, the correction circuit 60 has current sources 61 and 62.

[0188] The current source 61 is a variable current source electrically connected to the first output unit 513. Specifically, the current source 61 is connected between the signal line SL3 and the ground line Vss, and is configured to adjust the magnitude of the current flowing to the ground line Vss side. The magnitude of the current output from the current source 61, that is, the magnitude of the current fed into the signal line SL3 through the current source 61, is adjusted by a correction code (CODE_RE) sent from the sequencer 41.

[0189] The correction code is, for example, Figure 14 The 3-bit digital signals shown in each row. Sequencer 41, through... Figure 14 The correction code shown in any of the rows a to h is sent to the current source 61 to adjust the magnitude of the current fed into the signal line SL3 through the current source 61. Figure 14 In the example, the current is minimum when the correction code of line a is sent, and maximum when the correction code of line h is sent.

[0190] The current source 61 in this embodiment is formed by connecting three current sources (not shown) with different current values ​​in parallel. It is configured to individually switch the on / off state of each current source based on the values ​​of the upper, middle, and lower orders of the correction code. For example, when the correction code of line g is transmitted, the current sources corresponding to the upper and middle orders are turned on, and the current source corresponding to the lower order is turned off. This method enables the transmission of current sources corresponding to the upper and middle orders. Figure 14 The correction codes for each line are used to adjust the magnitude of the current fed into the signal line SL3 through the current source 61 in stages.

[0191] Current source 62 is a variable current source electrically connected to the second output unit 514. Specifically, current source 62 is connected between signal line SL4 and ground line Vss, configured to adjust the magnitude of the current flowing to the ground line Vss side. The magnitude of the current output from current source 62, that is, the magnitude of the current fed into signal line SL4 through current source 62, is adjusted by a correction code (CODE_ / RE) sent from sequencer 41. This correction code is related to... Figure 14 The correction code (CODE_RE) shown is the same, but it is sent from the sequencer 41 as a signal independent of the correction code sent to the current source 61. The configuration of the current source 62 is the same as that of the current source 61.

[0192] The sequencer 41 can individually adjust the magnitude of the current fed from the signal line SL3 through the current source 61 and the magnitude of the current fed from the signal line SL4 through the current source 62. At this time, the sequencer 41 can change the duty cycle of each of the signals / RE_c and RE_c by making the magnitudes of the currents fed from each current source 61 and 62 different.

[0193] Explain the reasons. Figure 15 The upper paragraph shows an example of reading the enable signal / RE and the time variation of RE. Figure 15 The following paragraph shows an example of the time variation of signals / RE_c and RE_c generated by correcting signals / RE_in and RE_in generated according to the read enable signals / RE and RE using correction circuit 60.

[0194] Figure 15 In the diagram, the period during which the read enable signal / RE exceeds the middle level is designated as "TM11", and the period during which the read enable signal / RE is below the middle level is designated as "TM12". Furthermore, the period during which the signal RE_c exceeds the middle level is designated as "TM21", and the period during which the signal RE_c is below the middle level is designated as "TM22".

[0195] Figure 15In the example, the read enable signal / RE input from memory controller 1 has a duty cycle of 50% as the target, and the lengths of TM11 and TM12 are equal. Assuming no signal distortion is caused by the circuitry containing comparator 51, the duty cycle of the output signals / RE_c and RE_c is also 50% as the target. Specifically, TM21 has approximately the same length as TM11, and TM22 has approximately the same length as TM12, resulting in the lengths of TM21 and TM22 being equal.

[0196] Figure 15 In the example, sequencer 41 sends the same correction code to current source 61 and current source 62 (e.g., Figure 4 (The correction code shown in row d). The current fed through current source 61 is equal to the current fed through current source 62, and no correction is performed using correction circuit 60. As a result, the lengths of TM21 and TM22 remain equal.

[0197] Figure 16 China through and Figure 15 Another example of reading the time variation of the enable signal / RE, etc., is represented using the same method. This example is also similar to... Figure 15 Similarly, the read enable signal / RE input from memory controller 1 has a duty cycle of 50% as the target, and the lengths of TM11 and TM12 are equal.

[0198] Figure 16 In this example, sequencer 41 sends different correction codes to current source 61 and current source 62. Specifically, it sends correction codes to current source 61. Figure 4 The correction code shown in line e is sent to current source 62. Figure 4 The correction code shown in line c. That is, to make the current fed from current source 61 more than... Figure 15 On the one hand, the situation increases, and on the other hand, the current fed from the current source 62 is compared with... Figure 15 The number of such cases has decreased.

[0199] In this case, such as Figure 16 As shown, TM21 is shorter than TM11, and TM22 is longer than TM12. As a result, TM21 is shorter than TM22, and the duty cycle of the signal RE_c is less than 50%. Based on this, the duty cycle of the data strobe signal DQS is also less than 50%.

[0200] Figure 17 In China, through cooperation with Figure 15 , Figure 16 This is yet another example of using the same method to represent the time variation of the read-emitter signal / RE, etc. This example also uses... Figure 15Similarly, the read enable signal / RE input from memory controller 1 has a duty cycle of 50% as the target, and the lengths of TM11 and TM12 are equal.

[0201] Figure 17 In this example, sequencer 41 sends different correction codes to current source 61 and current source 62. Specifically, it sends correction codes to current source 61. Figure 4 The correction code shown in line c is sent to current source 62. Figure 4 The correction code shown in line e. That is, to make the current fed from current source 61 more than... Figure 15 On the one hand, this reduces the likelihood of such situations, and on the other hand, it makes the current fed from the current source 62 more than... Figure 15 The number of cases is increasing.

[0202] In this case, such as Figure 17 As shown, TM21 is longer than TM11, and TM22 is shorter than TM12. As a result, TM21 is longer than TM22, and the duty cycle of the signal RE_c is greater than 50%. Based on this, the duty cycle of the data strobe signal DQS is also greater than 50%.

[0203] In summary, the sequencer 41 can individually adjust the magnitude of the current fed from the current source 61 and the current source 62 using a correction code, thereby changing the duty cycle of the signal RE_c, the data strobe signal DQS, etc.

[0204] Therefore, in this embodiment, the sequencer 41 adjusts the correction codes sent to the current source 61 and the current source 62 in such a way that the duty cycle shown by the signal received from the detection circuit 90 is close to the target value (e.g., 50%). Furthermore, the correspondence between the signal received by the sequencer 41 from the detection circuit 90 and the correction codes sent from the sequencer 41 to the current source 61 and the current source 62 can be appropriately set according to, for example, a pre-made diagram.

[0205] Additionally, as observed Figure 13 As is understood, both signals RE_in and RE_c are transmitted via signal line SL3, and therefore are essentially the same signal. However, for ease of explanation, the signal output from sequencer 41 will be designated as signal RE_in, and the signal output from correction circuit 60 to the subsequent stage will be designated as signal RE_c. The same applies to signals / RE_in and / RE_c transmitted via signal line SL4.

[0206] Furthermore, the configuration of the correction circuit 60, used to adjust the duty cycle of signals such as RE_c, is also considered. Figure 24The comparative example shown is configured as follows. The correction circuit 60 of this comparative example has four converters, INV1, INV2, INV3, and INV4, connected in series. Each converter has a PMOS transistor TR11 and an NMOS transistor TR12. Converter INV1 has a variable current source 65 that supplies current from the power line Vdd to the transistor TR11 side, and a variable current source 66 that supplies current from the transistor TR12 to the ground line Vss side. The magnitude of the current output from each current source 65 and 66 is individually adjusted by a correction code sent from the sequencer 41.

[0207] The gates of transistors TR11 and TR12 in converter INV1 are input with signal RE_in via signal line SL3. Sequencer 41 adjusts the rise time of the switching signal output from converter INV1 by sending a correction code to current source 65. Furthermore, sequencer 41 adjusts the fall time of the switching signal output from converter INV2 by sending a correction code to current source 66. Converters INV3 and INV4 function as waveform shaping circuits. The corrected signal RE_c is output from the final stage INV4. With this configuration, sequencer 41 can adjust the duty cycle of the signal RE_c output from converter INV4.

[0208] In addition, in this comparative example, signal line SL4 is also equipped with a connection to... Figure 24 The same correction circuit 60 is used to adjust the duty cycle of the signal / RE_c.

[0209] In this comparative example, multiple transistors such as TR11 must be formed in the correction circuit 60, thus increasing the area occupied by the correction circuit 60 in the semiconductor memory device 2 and making the semiconductor memory device 2 larger. In addition, this also leads to an increase in the current consumption of the correction circuit 60.

[0210] In contrast, in the correction circuit 60 of this embodiment, current sources 61 and 62 are only provided on the signal lines connected to comparator 51, without the need for additional transistors. Therefore, the enlargement of the semiconductor memory device 2 can be suppressed. Furthermore, since current sources 61 and 62 apply current to the signal output from comparator 51, i.e., the signal at a relatively low amplification stage, the output current is suppressed to a small level. As a result, power consumption can also be reduced.

[0211] In addition, this embodiment ( Figure 13In this configuration, current source 61 is connected to signal line SL3, and current source 62 is connected to signal line SL4. Alternatively, the current source can be connected to either signal line SL3 or signal line SL4. Even with this configuration, the duty cycle of signals such as RE_c and data strobe signal DQS can be changed by adjusting the current output from the current source.

[0212] refer to Figure 18 The second embodiment will be described. In this embodiment, the configuration of the current source differs from that in the first embodiment.

[0213] In this embodiment, a current source 63, having the same configuration as the current source 61, is connected between the signal line SL3 and the power supply line Vdd, and is configured to adjust the magnitude of the current flowing to the signal line SL3. The magnitude of the current output from the current source 63, that is, the magnitude of the current fed into the signal line SL3 through the current source 63, is adjusted by a correction code (CODE_RE) sent from the sequencer 41.

[0214] Similarly, in this embodiment, a current source 64 having the same configuration as current source 62 is connected between signal line SL4 and power supply line Vdd, configured to adjust the magnitude of the current flowing to signal line SL4. The magnitude of the current output from current source 64, that is, the magnitude of the current fed into signal line SL4 through current source 64, is adjusted by a correction code (CODE_ / RE) sent from sequencer 41.

[0215] Even with this configuration, the sequencer 41 can individually adjust the magnitude of the current fed from each current source 63 and current source 64 to change the duty cycle of the signal RE_c, the data strobe signal DQS, etc.

[0216] In this embodiment, current source 63 is connected to signal line SL3, and current source 64 is connected to signal line SL4. Alternatively, the current source can be connected to only one of signal lines SL3 and SL4. Even with this configuration, the duty cycle of signals such as RE_c and data strobe signal DQS can be changed by adjusting the current output from the current source.

[0217] refer to Figure 19 The third embodiment will be described. In this embodiment, the number and arrangement of current sources differ from those in the first embodiment.

[0218] In this embodiment, a method similar to that in the first embodiment is provided. Figure 13 The same current sources 61, 62, and the same as those in the second embodiment ( Figure 18The same current sources 63 and 64 are used. The sequencer 41 can individually adjust the magnitude of the current output from each of these current sources. Even in this configuration, it achieves the same effect as in the first and second embodiments.

[0219] refer to Figure 20 The fourth embodiment will be described. For example... Figure 20 As shown, in this embodiment, a comparator 53 is provided in the signal lines SL3 and SL4 at a position further back than the correction circuit 60.

[0220] The configuration of comparator 53 is the same as that of comparator 51. Comparator 53 has a first input section 531, a second input section 532, a first output section 533, and a second output section 534.

[0221] Signal line SL3 is connected to the first input section 531, and signal line SL4 is connected to the second input section 532. The end of signal line SL5, which extends to the output control circuit 70, is connected to the first output section 533, and the end of signal line SL6, which extends to the output control circuit 70, is connected to the second output section 534.

[0222] When the input signal RE_in is higher than the signal / RE_in, comparator 53 sets the signal / RE_c to H level and outputs it from the second output unit 534, and sets the signal RE_c to L level and outputs it from the first output unit 533. Otherwise, comparator 53 sets the signal / RE_c to L level and outputs it from the second output unit 534, and sets the signal RE_c to H level and outputs it from the first output unit 533.

[0223] Comparator 53, as described above, provides input signals RE_in (third switching signal) and / RE_in (fourth switching signal). In this embodiment, current sources 61 and 62 are connected midway to the signal lines SL3 and SL4 that connect comparator 51 and comparator 53. Comparator 53 corresponds to the "second comparator" in this embodiment. Even with this comparator 53 configuration, it performs the same effects as described in the first embodiment, etc. Alternatively, it can be configured as in the second embodiment (…). Figure 18 ), third implementation method ( Figure 19 The configuration of comparator 53 is set.

[0224] refer to Figure 21 The fifth embodiment will be described. For example... Figure 21 As shown, in this embodiment, the receiving circuit 50 is provided with two comparators 51 and 52, which are connected in series.

[0225] The configuration of comparator 52 is the same as that of comparator 51. Comparator 52 has a first input section 521, a second input section 522, a first output section 523, and a second output section 524.

[0226] The signal line extending from the first output section 513 is connected to the first input section 521, and the signal line extending from the second output section 514 is connected to the second input section 522. The end of the signal line SL3 extending to the correction circuit 60 and the output control circuit 70 is connected to the first output section 523, and the end of the signal line SL4 extending to the correction circuit 60 and the output control circuit 70 is connected to the second output section 524. Thus, even if the receiving circuit 50 has a configuration with multiple comparators, it achieves the same effect as described in the first embodiment, etc. The receiving circuit 50 may have three or more comparators. Furthermore, the configuration of the receiving circuit 50 having multiple comparators may also be combined in the second embodiment (…). Figure 18 ), third implementation method ( Figure 19 ), and the fourth embodiment ( Figure 20 In the composition of ).

[0227] refer to Figure 22 The sixth embodiment will be described. In this embodiment, a signal VREF with a fixed input voltage is used as a reference signal input to the second input section 512 of the comparator 51. The signal VREF is, for example, a signal at an intermediate level between H and L levels, and is generated internally within the semiconductor memory device 2, specifically in the voltage generation circuit 43. Even in this configuration, it achieves the same effect as described in the first embodiment. In the embodiments described above, as in this embodiment, a signal with a fixed voltage can also be used as a reference signal.

[0228] refer to Figure 23 The seventh embodiment will be described. For example... Figure 23 As shown, in this embodiment, the read enable signal / RE and RE are first input to the correction circuit 60, and the signal corrected by the correction circuit 60 is input to the comparator 51 of the receiving circuit 50. That is, it becomes the first embodiment ( Figure 13 The receiving circuit 50 and the correction circuit 60 are interchanged. Even in this configuration, it achieves the same effect as described in the first embodiment.

[0229] In this embodiment, current source 61 is connected to signal line SL1, and current source 62 is connected to signal line SL2. Alternatively, a configuration may be adopted in which a current source is connected only to either signal line SL1 or signal line SL2. Even with this configuration, the duty cycle of signals such as RE_c and data strobe signal DQS can be changed by adjusting the current output from the current source.

[0230] As shown in the above embodiments, the variable current source 61, etc., can be connected to at least any one of the first input section 511, the second input section 512, the first output section 513, and the second output section 514 of the comparator 51.

[0231] The embodiments described above have been illustrated with reference to specific examples. However, the present invention is not limited to these specific examples. Any modifications made by those skilled in the art to these specific examples, as long as they possess the features of the present invention, are also included within the scope of the present invention. The elements, configurations, conditions, shapes, etc., of each specific example should not be limited to the examples and can be appropriately modified. The elements of each specific example can be appropriately combined as long as they do not create technical contradictions.

[0232] [Explanation of Symbols]

[0233] 2 Semiconductor memory devices

[0234] 31 Input / output pad group

[0235] 51 comparator

[0236] 511 First Input Section

[0237] 512 Second Input Section

[0238] 513 First Output Section

[0239] 514 Second Output Section

[0240] 60 Correction Circuit

[0241] 61, 62 Current sources.

Claims

1. A semiconductor memory device comprising: The receiving unit receives the first switching signal from the outside; The first comparator generates and outputs a second switching signal that switches synchronously with the first switching signal; The adjustment unit adjusts the duty cycle of the second switching signal; and The transmitting unit transmits the second switching signal with the duty cycle adjusted, or the switching signal generated based on the second switching signal, to the outside. The second switching signal output from the first comparator includes a third switching signal and a fourth switching signal that is a complementary signal to the third switching signal. The first comparator has: The first input section is used to input the first switching signal; The second input section is for inputting reference signals; The first output unit outputs the third switching signal, which is switched according to the magnitude relationship between the first switching signal and the reference signal; and The second output unit outputs the fourth switching signal; The adjustment unit has a variable current source. The variable current source is connected to at least one of the first input section, the second input section, the first output section, and the second output section. The duty cycle of the second switching signal is adjusted by adjusting the magnitude of the current output from the current source.

2. The semiconductor memory device according to claim 1, wherein the reference signal is a signal input from the outside as a complementary signal to the first switching signal.

3. The semiconductor memory device according to claim 1, wherein the reference signal is a signal with a fixed voltage.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein the current source is connected to at least one of the first output section and the second output section.

5. The semiconductor memory device according to claim 4, further comprising a second comparator, The second comparator is provided with inputs to the third switching signal and the fourth switching signal. The current source is connected to the signal line that connects the first comparator and the second comparator.

6. The semiconductor memory device of claim 1, wherein the current source causes a change in the magnitude of the current flowing between the power supply line and the signal line connected to the first comparator.

7. The semiconductor memory device of claim 1, wherein the current source causes a change in the magnitude of the current flowing between the ground line and the signal line connected to the first comparator.

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