Non-volatile memory device

Abstract

A nonvolatile memory device includes a first cell region, a second cell region, and a peripheral circuit region. The first cell region includes a first normal bit line and a first redundant bit line. The second cell region is disposed above the first cell region in a vertical direction and includes a second normal bit line and a second redundant bit line. The peripheral circuit region is disposed below the first cell region in the vertical direction and includes a page buffer circuit and a page buffer decoder. The page buffer circuit includes a page buffer connected to the first normal bit line, the second normal bit line, the first redundant bit line, and the second redundant bit line. The page buffer decoder is configured to integrate a defective bit line occurring among the first normal bit line and the second normal bit line and replace the defective bit line with the first redundant bit line and the second redundant bit line.

Description

Technical Field

[0001] This application relates to non-volatile memory devices. Background Technology

[0002] Semiconductor memory devices may include a large number of memory cells for storing data. If at least one of the memory cells becomes defective during mass production of the memory device, the yield of the memory device can be improved by performing repair on the defective cells. To repair the defective cells, the memory device may have redundant memory cells in spare areas and replace the defective cells with the redundant memory cells. Summary of the Invention

[0003] Some aspects of this disclosure provide a non-volatile memory device capable of efficiently performing column repair.

[0004] According to some embodiments of this disclosure, a non-volatile memory device includes: a first cell region, a second cell region, and a peripheral circuit region. The first cell region includes a plurality of first normal bit lines and a plurality of first redundant bit lines. The second cell region is vertically disposed above the first cell region and includes a plurality of second normal bit lines and a plurality of second redundant bit lines. The peripheral circuit region is vertically disposed below the first cell region and includes a page buffer circuit and a page buffer decoder. The page buffer circuit includes a plurality of page buffers connected to the plurality of first normal bit lines, the plurality of second normal bit lines, the plurality of first redundant bit lines, and the plurality of second redundant bit lines. The page buffer decoder is configured to integrate defective bit lines appearing among the plurality of first normal bit lines and the plurality of second normal bit lines, and replace the defective bit lines with the plurality of first redundant bit lines and the plurality of second redundant bit lines.

[0005] According to some embodiments of this disclosure, a non-volatile memory device includes: a first cell region including a plurality of first normal bit lines and a plurality of first redundant bit lines; a second cell region disposed vertically above the first cell region and including a plurality of second normal bit lines and a plurality of second redundant bit lines; and a peripheral circuit region including a page buffer circuit and a page buffer decoder. The page buffer circuit includes a plurality of page buffers connected to the plurality of first normal bit lines, the plurality of second normal bit lines, the plurality of first redundant bit lines, and the plurality of second redundant bit lines. The page buffer decoder is configured to integrate defective bit lines appearing among the plurality of first normal bit lines and the plurality of second normal bit lines, and replace the defective bit lines with the plurality of first redundant bit lines and the plurality of second redundant bit lines.

[0006] According to some embodiments of this disclosure, a non-volatile memory device includes a plurality of cell regions and a peripheral circuit region stacked in a vertical direction. Each cell region includes a plurality of normal bit lines and a plurality of redundant bit lines. The peripheral circuit region includes a page buffer decoder configured to replace at least some of the defective bit lines that appear among the plurality of normal bit lines in one of the cell regions with redundant bit lines included in other cell regions of the plurality of cell regions.

[0007] Therefore, compared to non-volatile memory devices lacking the features described herein, some embodiments of the non-volatile memory devices described herein can provide improved repair performance and yield, for example, by utilizing defective bit lines integrated within multiple cell regions to perform column repair. Furthermore, in some embodiments, the non-volatile memory devices can reduce repair resources and the size of the non-volatile memory devices compared to non-volatile memory devices lacking the features described herein. Attached Figure Description

[0008] Figure 1 This is a perspective view showing an example of a non-volatile memory device.

[0009] Figure 2 This is a diagram illustrating an example layout of a page buffer circuit and a page buffer decoder included in a non-volatile memory device.

[0010] Figure 3 and Figure 4 This is a diagram illustrating an example of integrated column repair for non-volatile memory devices.

[0011] Figure 5 This is a diagram illustrating an example layout of a page buffer circuit and a page buffer decoder included in a non-volatile memory device.

[0012] Figure 6 This is a diagram illustrating an example of column repair information for a non-volatile memory device.

[0013] Figure 7 It is shown that... Figure 6 The column repair information corresponding to Figure 5 A timing diagram illustrating an example of the operation of the page buffer decoder.

[0014] Figure 8 This is a block diagram illustrating an example of a storage device.

[0015] Figure 9 This is a block diagram illustrating an example of a memory controller included in a storage device.

[0016] Figure 10 This is a block diagram illustrating an example of a non-volatile memory device.

[0017] Figure 11 This is a block diagram illustrating an example of a storage device.

[0018] Figure 12 This is a block diagram illustrating an example of a memory cell array included in a non-volatile memory device.

[0019] Figure 13 This is a circuit diagram showing an example of an equivalent circuit of a memory block included in a memory cell array.

[0020] Figure 14 and Figure 15 This is a diagram illustrating an example of the connection of bit lines and page buffers in a non-volatile memory device.

[0021] Figure 16 This is a cross-sectional view showing an example of a vertical structure of a non-volatile memory device.

[0022] Figure 17 This is a diagram illustrating an example of the intersection area between the bit lines and input-output contacts of a non-volatile memory device.

[0023] Figure 18 This is a circuit diagram illustrating an example of a page buffer included in a non-volatile memory device.

[0024] Figure 19 and Figure 20 This is a diagram illustrating an example of a dual-drive word line (DDWL) structure for a non-volatile memory device.

[0025] Figure 21 It is shown that... Figure 20 A diagram showing an example configuration corresponding to the DDWL structure.

[0026] Figure 22 This is a diagram illustrating an example of a channel transistor circuit.

[0027] Figure 23 This is a perspective view showing an example of a non-volatile memory device.

[0028] Figure 24 It is shown Figure 23 An example illustration of integrated column repair of a non-volatile memory device.

[0029] Figure 25 It is shown that it includes Figure 23 A block diagram of an example page buffer circuit and page buffer decoder in a non-volatile memory device.

[0030] Figure 26This is a perspective view showing an example of a non-volatile memory device.

[0031] Figure 27 This is a block diagram illustrating an example of a data center including storage devices.

[0032] Figure 28 This is a cross-sectional view showing an example of a non-volatile memory device.

[0033] Figure 29 This is a diagram illustrating an example of the manufacturing process for a non-volatile memory device.

[0034] Figure 30 This is a cross-sectional view showing an example of a semiconductor package including a non-volatile memory device. Detailed Implementation

[0035] In the accompanying drawings, the same reference numerals always denote the same elements, and repeated descriptions may be omitted.

[0036] In the following text, two directions parallel to and intersecting each other on the upper surface of the semiconductor substrate are defined as the first direction D1 and the second direction D2, respectively, and a direction substantially perpendicular to the upper surface of the semiconductor substrate is defined as the third direction D3. For example, the first direction D1 and the second direction D2 may intersect each other substantially perpendicularly. The first direction D1 may be referred to as the first horizontal direction or row direction, the second direction D2 may be referred to as the second horizontal direction or column direction, and the third direction D3 may be referred to as the vertical direction. The directions indicated by arrows in the figures and their opposite directions are described as the same direction. The above definitions of directions are the same in all subsequent figures.

[0037] During the repair of defective cells, according to column repair, the column line associated with the defective cell (i.e., the bit line) can be replaced with the column line associated with the redundant memory cell (i.e., column repair can be performed by mapping (or converting) the column address corresponding to the column line associated with the defective cell to the column address corresponding to the column line associated with the redundant memory cell). As the number of redundant memory cells and redundant bit lines used for column repair increases, the chip area of ​​the memory device can be increased.

[0038] Some aspects of this disclosure provide improved efficiency for column repair operations.

[0039] Figure 1 This is a perspective view illustrating an example of a non-volatile memory device. (Refer to...) Figure 1 The non-volatile memory device 300 may include a first cell region CREG1, a second cell region CREG2, and a peripheral circuit region PREG. In some embodiments, the first cell region CREG1, the second cell region CREG2, and the peripheral circuit region PREG may be stacked in the vertical direction D3. For example, as Figure 1 As shown, the second unit region CREG2 can be disposed above the first unit region CREG1 in the vertical direction D3, and the peripheral circuit region PREG can be disposed below the first unit region CREG1 in the vertical direction D3.

[0040] For ease of explanation and description, the case of stacking two unit regions CREG1 and CREG2 in the vertical direction D3 will be described, but the device structure within the scope of this disclosure is not limited to this. For example, as shown in reference Figure 30 The described non-volatile memory device may include three or more stacked cell regions, and integrated column repair may be applied to all vertically stacked cell regions. One or more cell regions may be located between the peripheral circuitry region PREG and the first cell region CREG1, and / or one or more cell regions may be located between the first cell region CREG1 and the second cell region CREG2.

[0041] The first unit region CREG1 may include multiple first bit lines BL, and the second unit region CREG2 may include multiple second bit lines BU. The first bit lines BL of the first unit region CREG1 may include multiple first normal bit lines (or end bit lines) NBLL and multiple first redundant bit lines RBLL. The second bit lines BU of the second unit region CREG2 may include multiple second normal bit lines NBLU and multiple second redundant bit lines RBLU.

[0042] Multiple first normal bit lines NBLL, multiple first redundant bit lines RBLL, multiple second normal bit lines NBLU, and multiple second redundant bit lines RBLU may be arranged in a first horizontal direction D1 (e.g., spaced apart from each other in the first horizontal direction D1) and extend in a second horizontal direction D2 perpendicular to the first horizontal direction D1.

[0043] The peripheral circuitry area PREG may include the page buffer circuit PGBF and the page buffer decoder PBD.

[0044] The page buffer circuit PGBF may include multiple page buffers connected to multiple first normal bit lines NBLL, multiple second normal bit lines NBLU, multiple first redundant bit lines RBLL, and multiple second redundant bit lines RBLU. See below for reference. Figure 5 , Figure 14 and Figure 15 As described, a bit line and a page buffer can be connected one-to-one.

[0045] exist Figure 1 For clarity, only bit lines BL and BU, page buffer circuit PGBF, and page buffer decoder PBD are shown; other components are omitted. (Refer to...) Figure 28Further described, the first cell region CREG1 and the second cell region CREG2 may each include NAND strings, multiple word lines, and / or source lines, etc. Additionally, as referenced... Figure 10 As further described, the peripheral circuit region PREG may include various components.

[0046] The Page Buffer Decoder (PBD) can integrate defective bit lines appearing in multiple first normal bit lines (NBLL) and multiple second normal bit lines (NBLU), and replace the defective bit lines with multiple first redundant bit lines (RBLL) and multiple second redundant bit lines (RBLU). (See reference...) Figures 3 to 7 This integrated column repair of defect bit lines in the first unit region CREG1 and the second unit region CREG2 is described in more detail.

[0047] Figure 2 This is a diagram illustrating an example layout of a page buffer circuit and a page buffer decoder included in a non-volatile memory device. (Refer to...) Figure 1 The page buffer decoder (PBD) can be configured to extend along the first horizontal direction D1. For example... Figure 2 As shown, the first page buffer circuit PGBFL, including page buffers connected to the first normal bit line NBLL and the first redundant bit line RBLL, can be configured to be adjacent to the first side of the page buffer decoder PBD in the second horizontal direction D2. The second page buffer circuit PGBFU, including page buffers connected to the second normal bit line NBLU and the second redundant bit line RBLU, can be configured to be adjacent to the second side of the page buffer decoder PBD in the second horizontal direction D2. For example, the first side can be opposite the second side. In this way, by setting the page buffers corresponding to the first unit region CREG1 and the page buffers corresponding to the second unit region CREG2 to be adjacent to the two sides of the page buffer decoder PBD respectively, the integrated column repair can be effectively achieved.

[0048] Figure 3 and Figure 4 This is a diagram illustrating the integrated column repair of a non-volatile memory device. Figure 3 and Figure 4 In this context, the normal region ANM represents the region containing normal bit lines, and the redundant region ARD represents the region containing redundant bit lines.

[0049] Reference Figure 3The Page Buffer Decoder (PBD) can perform column repair by integrating the first cell region (CREG1) and the second cell region (CREG2) for defective bit lines BUa and BUB that appear in the second cell region (CREG2). For example, defective bit line BUB in the second cell region (CREG2) can be replaced by redundant bit line BUC in the second cell region (CREG2), and defective bit line BUA in the second cell region (CREG2) can be replaced by redundant bit line BLd in the first cell region (CREG1).

[0050] Reference Figure 4 The Page Buffer Decoder (PBD) can perform column repair by integrating the first cell region CREG1 and the second cell region CREG2 for defective bit lines BLe and BLf that appear in the first cell region CREG1. For example, the defective bit line BLf in the first cell region CREG1 can be replaced by the redundant bit line Blg in the first cell region CREG1, and the defective bit line BLe in the first cell region CREG1 can be replaced by the redundant bit line BUh in the second cell region CREG2.

[0051] In this way, the Page Buffer Decoder (PBD) can be used to perform column repair by integrating the first cell region CREG1 and the second cell region CREG2. For example, a defective bit line appearing among multiple first normal bit lines NBLL can be replaced by a first redundant bit line RBLL and a second redundant bit line RBLU. Furthermore, a defective bit line appearing among multiple second normal bit lines NBLU can be replaced by a first redundant bit line RBLL and a second redundant bit line RBLU.

[0052] Now refer to Figures 5 to 7 This section will describe examples of the configurations and operations used to implement integrated column repair.

[0053] Figure 5 This is a diagram illustrating an example layout of a page buffer circuit and a page buffer decoder included in a non-volatile memory device.

[0054] Figure 5 The diagram shows the page buffer decoder PBD, the first page buffer circuit PGBFL, and the second page buffer circuit PGBFU, all located in the peripheral circuit region PREG. (See reference...) Figure 2 As described, the first page buffer circuit PGBFL and the second page buffer circuit PGBFU can be configured to be adjacent to both sides on the first horizontal direction D1 of the page buffer decoder PBD, respectively. Figure 5 The example shown is an allocation of two redundant bit lines to eight normal bit lines, but the bit line configuration is not limited to this. The first number of normal bit lines, the second number of redundant bit lines, and / or the ratio of the first number to the second number can be determined differently.

[0055] Reference Figure 5 The page buffer decoder (PBD) may include control logic circuit CLG, first switch circuit SW1, second switch circuit SW2 and third switch circuit SW3.

[0056] The control logic circuit CLG can generate a first enable signal EN1, a second enable signal EN2, and a third enable signal EN3 based on the column address C_ADDR and the column repair information CRI. The control logic circuit CLG may include storage circuitry (such as fuse circuitry, latch circuitry) for storing the column repair information CRI. See below for further details. Figure 6 and Figure 7 This describes the operation of the column repair information (CRI) and the control logic circuit (CLG).

[0057] The first switching circuit SW1 is connected to the page buffers corresponding to the first normal bit lines BL1 to BL8 (NBLL) of the first unit region CREG1. The second switching circuit SW2 is connected to the page buffers corresponding to the second normal bit lines BU1 to BU8 (NBLU) of the second unit region CREG2. The third switching circuit SW3 is connected to the page buffers corresponding to the first redundant bit lines BL9 and BL10 (RBLL) of the first unit region CREG1 and the page buffers corresponding to the second redundant bit lines BU9 and BU10 (RBLU) of the second unit region CREG2.

[0058] The first switching circuit SW1 controls the connection between the page buffer PB, which is connected to multiple first normal bit lines NBLL, and the input-output line WOR, based on the first enable signal EN1. The second switching circuit SW2 controls the connection between the page buffer PB, which is connected to multiple second normal bit lines NBLU, and the input-output line WOR, based on the second enable signal EN2. The third switching circuit SW3 controls the connection between the first redundant bit line RBLL, the second redundant bit line RBLU, and the input-output line WOR, based on the third enable signal EN3.

[0059] Figure 6 This is a diagram illustrating an example of column repair information for a non-volatile memory device.

[0060] Reference Figure 6 The column repair information (CRI) may include the mapping between the column address of the defective bit line (i.e., the defective column address FLAD) and the column address of the redundant bit line that replaces the defective bit line (i.e., the repair column address RPAD).

[0061] For example, such as Figure 6As shown, three defective bit lines BL2, BL5, and BL8 may appear in the first normal bit lines BL1 to BL8 of the first unit region CREG1, and one defective bit line BU4 may appear in the second normal bit lines BU1 to BU8 of the second unit region CREG2. In this case, the first normal bit line BL2 can be replaced by the first redundant bit line BL9, the first normal bit line BL5 can be replaced by the first redundant bit line BL10, the first normal bit line BL8 can be replaced by the second redundant bit line BU9, and the second normal bit line BU4 can be replaced by the second redundant bit line BU10. The column repair information CRI may include such a mapping relationship of column address ADD.

[0062] Figure 7 It is shown that... Figure 6 The column repair information corresponding to Figure 5 The timing diagram of the operation of the page buffer decoder. Figure 7 Showing with Figure 5 The configuration corresponds to the read operation and Figure 6 The column repair information CRI. In Figure 7 In this context, the unit period Tc corresponds to the time it takes for data to be output from a page buffer.

[0063] Reference Figure 5 , Figure 6 and Figure 7 The page buffer decoder (PBD) generates a first enable signal EN1 based on column repair information from defective bit lines BL2, BL5, and BL8 among multiple first normal bit lines BL1 to BL8. In response to the activation of the first enable signal EN1, the first switching circuit SW1 outputs a first switching signal OUT1, including data bits DL1, DL3, DL4, BL6, and DL7 from the first normal bit lines BL1, BL3, BL4, BL6, and BL7, to the input-output line WOR. During the deactivation period of the first enable signal EN1, the first switching circuit SW1 can mask the data bits DL2, DL5, and DL8 output from the first normal bit lines BL2, BL5, and BL8 corresponding to the defective bit lines.

[0064] The page buffer decoder (PBD) generates a second enable signal EN2 based on column repair information of the defective bit line BU4, which appears among the multiple second normal bit lines BU1 to BU8. In response to the activation of the second enable signal EN2, the second switching circuit SW2 outputs a second switching signal OUT2, including data bits DU1, DU2, DU3, DU5, BU6, BU7, and DU8 output from the second normal bit lines BU1, BU2, BU3, BU5, BU6, BU7, and BU8, to the input-output line WOR. During the deactivation period of the second enable signal EN2, the second switching circuit SW2 can mask the data bit DU4 output from the second normal bit line BU4 corresponding to the defective bit line.

[0065] The page buffer decoder (PBD) generates a third enable signal EN3 based on column repair information for defective bit lines BL2, BL5, and BL8 appearing among the multiple first normal bit lines BL1 to BL8, and column repair information for defective bit line BU4 appearing among the multiple second normal bit lines BU1 to BU8. In response to the activation of the third enable signal EN3, the third switching circuit SW3 outputs a third switching signal OUT3, including data bits DL9 and DL10 output from the first redundant bit lines BL9 and BL10, and data bits DU9 and DU10 output from the second redundant bit lines BU9 and BU10, to the input-output line WOR.

[0066] The data output signal DO output via the input-output line WOR may include the data bits DL9, DL10, DU9 and DU10 of the redundant bit lines BL9, BL10, BU9 and BU10, instead of the data bits DL2, DL5, DL8 and DU4 of the defective bit lines BL2, BL5, BL8 and BU4.

[0067] Therefore, a merged column repair can be performed, in which the defective bit lines BL2, BL5, BL8 and BU4 of the first cell region CREG1 and the second cell region CREG2 are merged and replaced with redundant bit lines BL9, BL10, BU9 and BU10 of the first cell region CREG1 and the second cell region CREG2.

[0068] In this way, the non-volatile memory device 300 can perform column repair by merging defective bit lines arising from multiple cell regions CREG1 and CREG2, thereby improving repair performance and increasing the yield of the non-volatile memory device 300. Furthermore, for the same repair performance, the consumption of repair resources can be reduced, and the size of the non-volatile memory device 300 can be reduced.

[0069] Figure 8 This is a block diagram illustrating an example of a storage device. (See reference...) Figure 8 The storage device 10 may include a memory controller (or storage controller) 100 and at least one non-volatile memory device 300. Figure 8 The storage device 10 shown may include a flash-based data storage medium, such as a memory card, USB memory, SSD, etc.

[0070] The non-volatile memory device 300 can perform erase, write, or read operations under the control of the memory controller 100. The non-volatile memory device 300 receives commands CMD (such as read and write commands) and addresses ADDR (such as read and write addresses) from the memory controller 100 via input and output lines, and transmits and receives data DATA for read or write operations (or programming operations) with the memory controller 100. Furthermore, the non-volatile memory device 300 can receive control signals CTRL via control lines, and can receive power PWR from the memory controller 100.

[0071] The memory controller 100 can control access to the non-volatile memory device 300 based on a request REQ received from an external host device.

[0072] As described above, the non-volatile memory device 300 may include multiple cell regions, and the memory device 10 may perform integrated column repair on the multiple cell regions.

[0073] Figure 9 This is a block diagram illustrating an example of a memory controller included in a storage device. (See reference...) Figure 9 The memory controller or storage controller 100 may include a processor 110, a buffer memory (BUFF) 140, a DRAM controller 130, a host interface (HIF) 120, an error correction code (ECC) engine 170, a memory interface (MIF) 150, an advanced encryption standard (AES) engine 180, and an internal bus 160 for electrical connection components.

[0074] Processor 110 can control the operation of memory controller 100 in response to commands received from an external host device via host interface 120. For example, processor 110 can control the memory system (e.g., Figure 8 The operation of the storage device 10 in the memory can be controlled by firmware to drive the memory system and control the individual components.

[0075] The buffer memory 140 may store instructions and data executed and processed by the processor 110. For example, the buffer memory 140 may be implemented as a volatile memory (such as SRAM, DRAM, etc.).

[0076] The ECC engine 170 for error correction can use error correction codes (such as Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, Turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC)) and coding modulations (such as trellis-coded modulation (TCM), block-coded modulation (BCM), Hamming codes, etc.) to perform ECC encoding and ECC decoding.

[0077] Host interface 120 provides a physical connection between the host device and storage controller 100 (i.e., host interface 120 can provide an interface connection with storage controller 100 in a bus format corresponding to the bus format of the host device). In some embodiments, the bus format of the host device may be SCSI or SAS. In some embodiments, the bus format of the host device may be USB, Peripheral Component Interconnect Fast (PCIe), ATA, PATA, SATA, NVMe, etc.

[0078] Memory interface 150 can be used with non-volatile memory devices (e.g., Figure 8 The memory interface 150 can exchange data with the non-volatile memory device 300. The memory interface 150 can transfer write data to the non-volatile memory device 300 and receive read data from the non-volatile memory device 300. For example, the memory interface 150 can utilize standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0079] The AES engine 180 can use a symmetric key algorithm to perform at least one of encryption and decryption operations on data input to the storage controller 100. Although not shown in detail, the AES engine 180 may include an encryption module and a decryption module. The encryption module and the decryption module may be implemented as separate modules or as a single module.

[0080] Processor 110 can access external DRAM 80 via DRAM controller 130. Processor 110 can control DRAM controller 130, memory interface 150 and host interface 120 to transfer user data stored in external DRAM 80 to non-volatile memory device 300 or external host device.

[0081] Figure 10 This is a block diagram illustrating an example of a non-volatile memory device. (See reference...) Figure 10The non-volatile memory device 300 may include a memory cell array 500, a page buffer circuit (PGBF) 510, a page buffer decoder (PBD) 515, a data input-output (I / O) circuit 520, an address decoder 530, a control circuit 550, and a voltage generator 560. (Refer to the following...) Figure 28 and Figure 29 As described, in some embodiments, the cell region CREG and the peripheral circuit region PREG may be formed and disposed in different wafers. Furthermore, in some embodiments, the cell region CREG may include multiple cell regions disposed in different wafers.

[0082] The memory cell array 500 can be coupled to the address decoder 530 via the string select line SSL, word line WL, and ground select line GSL. Furthermore, the memory cell array 500 can be coupled to the page buffer circuitry 510 via the bit line BL. The memory cell array 500 may include memory cells coupled to the word line WL and the bit line BL. In some embodiments, the memory cell array 500 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (e.g., a vertical structure). In this case, the memory cell array 500 may include vertically oriented cell strings (e.g., NAND strings) such that at least one memory cell is vertically stacked with another memory cell.

[0083] Control circuitry 550 can receive command (signal) CMD and address (signal) ADDR from the memory controller. Therefore, control circuitry 550 can control erase, program, and read operations of the non-volatile memory device 1000 in response to (or based on) at least one of the command signal CMD and the address signal ADDR. Erasing operations may include performing a series of erase cycles. Programming operations may include performing a series of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations and data recovery read operations.

[0084] For example, control circuit 550 can generate a control signal CTL for controlling the operation of voltage generator 560. Control circuit 550 can also generate a page buffer control signal PBC for controlling page buffer circuit 510 based on command signal CMD, and generate block address B_ADDR, row address R_ADDR, and column address C_ADDR based on address signal ADDR. Control circuit 550 can provide block address B_ADDR and row address R_ADDR to address decoder 530, and provide column address C_ADDR to data I / O circuit 520.

[0085] Address decoder 530 can be integrated into memory cell array 500 via serial select line SSL, word line WL, and ground select line GSL. During programming or reading operations, address decoder 530 can determine or select one of the word lines WL as the selected word line based on row address R_ADDR, and determine the remaining word lines WL other than the selected word line as unselected word lines.

[0086] During programming or reading operations, the address decoder 530 can determine one of the string select lines SSL as the selected string select line based on the row address R_ADDR, and determine the remaining string select lines SSL as unselected string select lines.

[0087] Voltage generator 560 can generate the word line voltage VWL required for the operation of the memory cell array 500 of the non-volatile memory device 1000 based on the control signal CTL. Voltage generator 560 can obtain the voltage from the memory controller (such as...) Figure 8 The memory controller 100 receives power PWR. The word line voltage VWL can be applied to the word line WL via the address decoder 530.

[0088] For example, during an erase operation, voltage generator 560 may apply an erase voltage to the wells and / or common-source lines of the memory block, and apply an erase permission voltage (e.g., ground voltage) to all or a portion of the word lines of the memory block based on the erase address. During an erase verification operation, voltage generator 560 may apply an erase verification voltage simultaneously to all word lines of the memory block, or sequentially (e.g., one by one) to the word lines.

[0089] For example, during programming operations, voltage generator 560 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line. Furthermore, during programming verification operations, voltage generator 560 can apply a programming verification voltage to the selected word line and a verification pass voltage to the unselected word line.

[0090] During a normal read operation, voltage generator 560 can apply a read voltage to the selected word line and can apply a read pass voltage to the unselected word line. During a data recovery read operation, voltage generator 560 can apply a read voltage to the word line adjacent to the selected word line and can apply a recovery read voltage to the selected word line.

[0091] Page buffer circuitry 510 can be coupled to memory cell array 500 via bit line BL. Page buffer circuitry 510 may include multiple buffers. In some embodiments, each buffer may be connected to a single bit line. In some embodiments, each buffer may be connected to two or more bit lines. Page buffer circuitry 510 may temporarily store data to be programmed into selected pages of memory cell array 500 or data read from selected pages of memory cell array 500.

[0092] Page buffer decoder 515 can control the connection between page buffer circuit 510 and data line DL based on the row address R_ADDR provided from control circuit 550 and the column repair information stored therein. Page buffer decoder 515 can perform integrated column repair as described above.

[0093] Data I / O circuit 520 can be coupled to page buffer circuit 510 via data line DL. During programming operations, data I / O circuit 520 can receive programming data DATA from memory controller and provide programming data DATA to page buffer circuit 510 based on column address C_ADDR received from control circuit 550. During read operations, data I / O circuit 520 can provide read data DATA that has been read from memory cell array 500 and stored in page buffer circuit 510 to memory controller based on column address C_ADDR received from control circuit 550.

[0094] Furthermore, the page buffer circuit 510 and the data I / O circuit 520 can (e.g., without transferring data to a source outside the non-volatile memory device 1000, such as a memory controller) read data from a first region of the memory cell array 500 and write the read data to a second region of the memory cell array 500. For example, the page buffer circuit 510 and the data I / O circuit 520 can perform a copy-back operation.

[0095] Figure 11 This is a block diagram illustrating an example of a storage device. (See reference...) Figure 11 The storage device 600 may include a non-volatile memory device 610 and a memory controller 100. The storage device 600 may support multiple channels CH1, CH2, ..., CHm, and the non-volatile memory device 610 may be connected to the memory controller 100 via multiple channels CH1 to CHm. For example, the storage device 600 may be implemented as general-purpose flash memory (UFS), a solid-state drive (SSD), etc. The storage device 600 may be connected to... Figure 8 The storage device 10 corresponds to this.

[0096] The non-volatile memory device 610 may include a plurality of non-volatile memories NVM11, NVM12, ..., NVM1n, NVM21, NVM22, ..., NVM2n, NVMm1, NVMm2, ..., NVMmn. Here, n and m may each be an integer greater than 0. Each of the non-volatile memories NVM11 to NVMmn can be connected to one of the plurality of channels CH1 to CHm through its corresponding path. For example, non-volatile memories NVM11 to NVM1n can be connected to the first channel CH1 through paths W11, W12, ..., W1n, non-volatile memories NVM21 to NVM2n can be connected to the second channel CH2 through paths W21, W22, ..., W2n, and non-volatile memories NVMm1 to NVMmn can be connected to the m-th channel CHm through paths Wm1, Wm2, ..., Wmn. In some implementations, each of the non-volatile memories NVM11 to NVMmn may be implemented as a memory cell operable according to individual commands from the memory controller 100. For example, each of the non-volatile memories NVM11 to NVMmn may be implemented as a chip or a die, but the implementation is not limited thereto.

[0097] The memory controller 100 can send signals to and receive signals from the non-volatile memory device 610 via multiple channels CH1 to CHm. For example, the memory controller 100 can send commands CMDa, CMDb, ..., CMDm, addresses ADDRa, ADDRb, ..., ADDRm, and data DATAa, DATAb, ..., DATAm to the non-volatile memory device 610 via channels CH1 to CHm, or it can receive data DATAa to DATAm from the non-volatile memory device 610 via channels CH1 to CHm.

[0098] The memory controller 100 can use one of the corresponding channels CH1 to CHm to select one of the non-volatile memories NVM11 to NVM1n connected to one of the corresponding channels CH1 to CHm, and can send signals to and receive signals from the selected non-volatile memory. For example, the memory controller 100 can select non-volatile memory NVM11 from non-volatile memories NVM11 to NVM1n connected to the first channel CH1. The memory controller 100 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory NVM11 through the first channel CH1, or can receive data DATAa from the selected non-volatile memory NVM11 through the first channel CH1.

[0099] The memory controller 100 can send signals to and receive signals from the non-volatile memory device 610 in parallel through different channels. For example, the memory controller 100 can send command CMDb to the non-volatile memory device 610 through the first channel CH1 while simultaneously sending command CMDb to the non-volatile memory device 610 through the second channel CH2. For example, the memory controller 100 can receive data DATAa from the non-volatile memory device 610 through the first channel CH1 while simultaneously receiving data DATAb from the non-volatile memory device 610 through the second channel CH2.

[0100] The memory controller 100 controls all operations of the non-volatile memory device 610. The memory controller 100 can send signals to channels CH1 to CHm and can control each of the non-volatile memories NVM11 to NVM1n connected to channels CH1 to CHm. For example, the memory controller 100 can send command CMDa and address ADDRa to the first channel CH1 and can control the selection of one of the non-volatile memories NVM11 to NVM1n.

[0101] Each of the non-volatile memories NVM11 to NVMmn can operate under the control of the memory controller 100. For example, the non-volatile memory NVM11 can be programmed with data DATAa based on the command CMDa, address ADDRa, and data DATAa provided from the memory controller 100 via the first channel CH1. For example, the non-volatile memory NVM21 can read data DATAb based on the command CMDb and address ADDRb provided from the memory controller 100 via the second channel CH2, and can send the read data DATAb to the memory controller 100 via the second channel CH2.

[0102] although Figure 11 An example is shown of a non-volatile memory device 610 communicating with a memory controller 100 via m channels and including n non-volatile memories corresponding to each channel. However, the channel configuration is not limited to this, and the number of channels and the number of non-volatile memories connected to a channel can be changed differently.

[0103] Figure 12 This illustrates the inclusion of non-volatile memory devices (e.g., Figure 10 A block diagram of an example memory cell array in a non-volatile memory device, and Figure 13 This illustrates the inclusion of memory cell arrays (e.g., Figure 12 The circuit diagram of the equivalent circuit of the memory block in the memory cell array.

[0104] Reference Figure 12 The memory cell array 500 may include memory blocks BLK1 to BLKz. In some embodiments, memory blocks BLK1 to BLKz may be... Figure 10 The address decoder 530 selects the memory block BLK corresponding to the block address from memory blocks BLK1 to BLKz.

[0105] Figure 13 The memory block BLKi can be formed on the substrate in a three-dimensional structure (e.g., a vertical structure). For example, the NAND strings or cell strings included in the memory block BLKi can be arranged in a vertical direction D3 perpendicular to the upper surface of the substrate.

[0106] Reference Figure 13 The memory block BLKi may include cell strings or NAND strings NS11 to NS33 coupled between bit lines BL1, BL2 and BL3 and the common source line CSL. Each NAND string may include multiple memory cells stacked on the vertical direction D3, and multiple word lines may be stacked on the vertical direction D3.

[0107] Each of the NAND strings NS11 to NS33 may include a string select transistor SST, memory cells MC1 to MC8, and a ground select transistor GST. Figure 13 In the diagram, each of the NAND strings NS11 to NS33 is shown as comprising eight memory cells MC1 to MC8. However, the number of memory cells is not limited to this. In some embodiments, each of the NAND strings NS11 to NS33 may include any number of memory cells.

[0108] Each string select transistor (SST) can be connected to a corresponding string select line (e.g., one of SSL1 through SSL3). Memory cells MC1 through MC8 can be connected to corresponding gate lines GTL1 through GTL8, respectively. Gate lines GTL1 through GTL8 can be word lines. A portion of gate lines GTL1 through GTL8 can be dummy word lines. Each ground select transistor (GST) can be connected to a corresponding ground select line (e.g., one of GSL1 through GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3). Each ground select transistor (GST) can be connected to the common-source line CSL.

[0109] Word lines of the same height (each of gate lines GTL1 to GTL8) can be connected together. Ground select lines GSL1 to GSL3 and serial select lines SSL1 to SSL3 can be separated. Figure 13In the diagram, memory block BLKi is shown as being coupled to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, the connection configuration is not limited to this. Each memory block in memory cell array 500 can be coupled to any number of word lines and any number of bit lines.

[0110] Figure 14 and Figure 15 This is a diagram illustrating an example of the connection of bit lines and page buffers in a non-volatile memory device. Figure 14 An example of a configuration is shown in which the first normal bit lines BL1 to BL20 (NBLL) and the first redundant bit lines BL21 to BL24 (RBLL) located in the first unit region CREG1 are connected to the page buffer PB of the first page buffer circuit PGBFL, which is set to be adjacent to one side of the page buffer decoder PBD in the second horizontal direction D2. Figure 15 An example of a configuration is shown in which the page buffer PB of the second page buffer circuit PGBFU, which is set to be adjacent to the page buffer decoder PBD on the other side of the second horizontal direction D2, is connected to the second normal bit lines BU1 to BU20 (NBLU) and the second redundant bit lines BU21 to BU24 (RBLU) set in the second cell region CREG1.

[0111] like Figure 14 and Figure 15 As shown, a page buffer PB can be connected to a corresponding bit line. In some cases, if the length of each page buffer PB in the first horizontal direction D1 is greater than the spacing between two adjacent bit lines, it is not possible or difficult to arrange the page buffer PB included in each of the first page buffer circuit PGBFL and the second page buffer circuit PGBFU as a single line in the first horizontal direction D1. For ease of connection, as... Figure 14 and Figure 15 As shown, the page buffer PB can be arranged as two or more lines, and the bit lines and the page buffer PB can be connected in a zigzag pattern.

[0112] like Figure 14 and Figure 15As shown, multiple first normal bit lines NBLL and multiple first redundant bit lines RBLL can be arranged to overlap with multiple second normal bit lines NBLU and multiple second redundant bit lines RBLU in the vertical direction D3. For example, the multiple first normal bit lines NBLL and multiple first redundant bit lines RBLL included in the first unit region CREG1 can be disconnected from or not connected to the multiple second normal bit lines NBLU and multiple second redundant bit lines RBLU included in the second unit region CREG2. For example, the first unit region CREG1 and the second unit region CREG2 can be manufactured using the same manufacturing process with the same structure to facilitate mass production.

[0113] Figure 16 This is a cross-sectional view showing an example of a vertical structure of a non-volatile memory device.

[0114] Reference Figure 16 The non-volatile memory device 400 may include a peripheral circuit region PREG, a first cell region CREG1, and a second cell region CREG2, which are sequentially stacked in the vertical direction D3. A first memory cell array 411a may be disposed within the first cell region CREG1, and a second memory cell array 411b may be disposed within the second cell region CREG2. A first page buffer circuit PGBFL 412, a page buffer decoder PBD 413, and a second page buffer circuit PGBFU 414 may be disposed within the peripheral circuit region PREG.

[0115] The peripheral circuit region PREG and the first cell region CREG1 can be attached to each other at the first bonding interface IF1 via low-level bonding pads BPL1, BPL2, BPL3, and BPL4, and the first cell region CREG1 and the second cell region CREG2 can be attached to each other at the second bonding interface IF2 via high-level bonding pads BPU1 and BPU2. From a planar perspective, the low-level bonding pads BPL1, BPL2, BPL3, and BPL4, as well as the high-level bonding pads BPU1 and BPU2, can be disposed in bonding pad regions within the memory cell arrays 411a and 411b. In some embodiments, the bonding pad regions in the non-volatile memory device 400 can be disposed in multiple regions.

[0116] The first memory cell array 411a in the first cell region CREG1 is connected to the low-level bit line BL_a via bit line contact 415a, and the low-level bit line BL_a is electrically connected to the low-level bonding pads BPL1 and BPL2 via connection via 416a. The low-level bit line BL_a corresponds to the first bit line BL described above. The second memory cell array 411b in the second cell region CREG2 is connected to the high-level bit line BL_b via bit line contact 415b, and the high-level bit line BL_b is electrically connected to the high-level bonding pads BPU1 and BPU2 via connection via 416b. The high-level bit line BL_b corresponds to the second bit line BU described above.

[0117] The first cell region CREG1 may further include input-output contacts IOMC, which can penetrate a portion of the first memory cell array 411a to electrically connect low-level bonding pads BPL3 and BPL4 to high-level bonding pads BPU1 and BPU2. Low-level bonding pads BPL1 and BPL2 can be electrically connected to the first page buffer circuit PGBFL via vias 417 and wiring layers 418 disposed within the peripheral circuit region PREG. Low-level bonding pads BPL3 and BPL4 can be electrically connected to the second page buffer circuit PGBFU via vias 417 and wiring layers 418 disposed within the peripheral circuit region PREG.

[0118] In some embodiments, the first memory cell array 411a in the first cell region CREG1 can store m bits per cell, and the second memory cell array 411b in the second cell region CREG2 can store n bits per cell, where n may be different from or equal to m. In some embodiments, both the first memory cell array 411a and the second memory cell array 411b can be single-level cell memories storing 1 bit per cell. In some embodiments, both the first memory cell array 411a and the second memory cell array 411b can be multi-level cell memories storing two bits per cell. In some embodiments, both the first memory cell array 411a and the second memory cell array 411b can be three-level cell memories storing 3 bits per cell. In some embodiments, the first memory cell array 411a can be a multi-level cell memory, and the second memory cell array 411b can be a single-level cell memory. In some embodiments, the first memory cell array 411a can be a three-level cell memory, and the second memory cell array 411b can be either a multi-level cell memory or a single-level cell memory. In some embodiments, the first memory cell array 411a may be a single-level cell memory, and the second memory cell array 411b may be a multi-level cell memory. In some embodiments, the first memory cell array 411a may be a multi-level cell memory or a single-level cell memory, and the second memory cell array 411b may be a three-level cell memory.

[0119] Figure 17 It is shown Figure 16 An example diagram of the intersection region (e.g., the intersection region CRS) of the bit lines and input-output contacts of a non-volatile memory device.

[0120] For reference Figure 14 and Figure 15 As described, multiple first normal bit lines NBLL and multiple first redundant bit lines RBLL can be arranged to overlap with multiple second normal bit lines NBLU and multiple second redundant bit lines RBLU in the vertical direction D3.

[0121] In this case, multiple second normal bit lines NBLU and multiple second redundant bit lines RBLU, including those in the second cell region CREG2, can be accessed via a vertical conductive path through the first cell region (e.g., Figure 16 The input-output contact (IOMC) in the circuit is connected to the page buffer PB included in the peripheral circuit area PREG.

[0122] like Figure 17As shown, each bit line BL in the plurality of second normal bit lines NBLU and the plurality of second redundant bit lines RBLU can be divided into two segments BLS1 and BLS2 in the intersecting region CRS traversed by the vertical conductive path IOMC. The two segments BLS1 and BLS2 can be connected to each other by a detour conductive path DPH formed spaced apart from the vertical conductive path IOMC. For example, the detour conductive path DPH may include a conductive pattern MPT formed in a conductive layer and a vertical contact VC connecting the conductive pattern MPT to segments BLS1 and BLS2.

[0123] Thus, when the first bit line BL of the first cell region CREG1 includes a circuitous conductive path, the bit line defect rate of the first cell region CREG1 can be greater than that of the second cell region CREG2. In this case, the yield of the non-volatile memory device can be improved by replacing the defective bit lines in the first cell region CREG1 with redundant bit lines in the second cell region CREG2 according to the integrated column repair.

[0124] Figure 18 This is a circuit diagram illustrating an example of a page buffer included in a non-volatile memory device. (Refer to...) Figure 18 The page buffer PB may include a high-voltage unit HVU, a main unit MU, and a cache unit CU.

[0125] The high-voltage cell HVU may include a bit line selection transistor TR_hv connected to the bit line BL and driven by the bit line selection signal BLSLT. The bit line selection transistor TR_hv may be implemented as a high-voltage transistor to reduce the effects of high voltages (e.g., erase voltages), and therefore, the bit line selection transistor TR_hv may be located in a different well region from the main cell MU.

[0126] The cache unit (CU) may include a cache latch (C-LATCH) CL, and the cache latch CL may be connected to data input and output (I / O) lines. Therefore, the cache unit (CU) may be configured to be adjacent to the data I / O lines. For example, the main unit (MU) and the cache unit (CU) may be spaced apart from each other. The cache unit (CU) may also include a first transistor (NM1). The first transistor (NM1) may be driven according to a cache monitoring signal (MON_C).

[0127] The master unit MU may include the master transistor within the page buffer PB. For example, the master unit MU may include a sense latch (S-LATCH) SL, a force latch (F-LATCH) FL, a high-order latch (M-LATCH) ML, and a low-order latch (L-LATCH) LL. The sense latch SL may store data stored in the memory cell or a sensed result of the threshold voltage of the memory cell during a read operation or a program verification operation. The sense latch SL may also be used to apply a programming bit line voltage or a programming inhibit voltage to the bit line BL during a programming operation. The force latch FL may be used to improve the threshold voltage distribution during a programming operation. For example, the force latch FL stores force data. The force data may be initially set to "1" and then inverted to "0" when the threshold voltage of the memory cell enters a force region below the target region. The force data may be used to control the bit line voltage and form a narrower programming threshold voltage distribution during a programming execution operation.

[0128] The high-order latch ML, low-order latch LL, and cache latch CL can be used to store externally input data during programming operations. When 3 bits of data are programmed into a memory cell, the 3 bits of data can be stored in the high-order latch ML, low-order latch LL, and cache latch CL, respectively. However, the storage configuration is not limited to this, and the 3 bits of data received through the cache latch CL can be stored in the forced latch FL, high-order latch ML, and low-order latch LL, respectively. The high-order latch ML, low-order latch LL, and cache latch CL can retain the stored data until the programming of the memory cell is complete. In addition, the cache latch CL can receive data read from the memory cell from the sensing latch SL during read operations and output the data to the outside via the data input-output line.

[0129] The main unit MU may also include second transistors NM2 to fifth transistors NM5. Second transistor NM2 may be connected between sensing node SO and sensing latch SL, and can be driven by sensing monitoring signal MON_S. Third transistor NM3 may be connected between sensing node SO and forced latch FL, and can be driven by forced monitoring signal MON_F. Fourth transistor NM4 may be connected between sensing node SO and high-order latch ML, and can be driven by high-order monitoring signal MON_M. Fifth transistor NM5 may be connected between sensing node SO and low-order latch LL, and can be driven by low-order monitoring signal MON_L.

[0130] The main unit MU may also include a sixth transistor NM6 and a seventh transistor NM7 connected in series between the bit line selection transistor TV_hv and the sensing node SO. The sixth transistor NM6 can be driven by the bit line cutoff signal BLSHF, and the seventh transistor NM7 can be driven by the bit line connection control signal CLBLK. The main unit MU may also include an eighth transistor NM8 connected to the sensing node SO. The eighth transistor NM8 may be referred to as the "channel transistor" and can be driven by the channel control signal SO_PASS.

[0131] Figure 19 and Figure 20 This is a diagram illustrating an example of a dual-drive word line (DDWL) structure for a non-volatile memory device.

[0132] Reference Figure 19 and Figure 20 The first unit region CREG1 may include multiple first word lines WLL1 to WLL3, and the second unit region CREG2 may include multiple second word lines WLU1 to WLU3.

[0133] The row addresses of multiple first word lines WLL1 to WLL3 ( Figure 10 The first selected word line (R_ADDR) and the second selected word line corresponding to the row address of multiple second word lines WLU1 to WLU3 can be enabled simultaneously.

[0134] In some implementations, such as Figure 19 As shown, the first selected word line and the second selected word line can be electrically connected via a conductive path. For example, the first word line WLL1 can be connected to the second word line WLU1 via a conductive path VPH1, the first word line WLL2 can be connected to the second word line WLU2 via a conductive path VPH2, and the first word line WLL3 can be connected to the second word line WLU3 via a conductive path VPH3.

[0135] In some implementations, such as Figure 20 As shown, by the address decoder (ADEC) (e.g., Figure 10 (530) Multiple drive signals SI generated based on row address R_ADDR can be jointly applied to multiple first word lines WLL1 to WLL3 and multiple second word lines WLU1 to WLU3. The multiple drive signals SI may include multiple string select signals SS, multiple word line drive signals S0 to S63 and multiple ground select signals GS.

[0136] Figure 21 It is shown that... Figure 20 A diagram illustrating an example configuration corresponding to the DDWL structure, and Figure 22 It is shown Figure 21 A diagram illustrating an example of a channel transistor circuit.

[0137] Figure 21 An example of a row decoder and channel transistor circuitry included in a non-volatile memory device is shown. For ease of illustration and description, in Figure 21 The diagram shows two sub-memory blocks SMB11 and SMB12 of the first unit region CREG1, two sub-memory blocks SMB21 and SMB22 of the second unit region CREG2, and the corresponding address decoder and channel transistor circuits. However, the embodiments within the scope of this disclosure are not limited to a specific number of memory blocks.

[0138] Reference Figure 21 The aforementioned address decoder may include a drive signal decoder SIDEC and a first decoder BDEC1 and a second decoder BDEC2 corresponding to sub-memory blocks SMB11, SMB12, SMB21 and SMB22. The channel transistor circuit may include a first channel transistor block PTB1 and a second channel transistor block PTB2 corresponding to sub-memory blocks SMB11, SMB12, SMB21 and SMB22.

[0139] The drive signal decoder SIDEC can generate multiple drive signals SI based on the row address R_ADDR. The drive signal decoder SIDEC can determine the voltage level of the multiple drive signals SI and their corresponding programming, reading, and erasing operations, respectively.

[0140] According to the DDWL structure, a sub-memory block of the first cell region CREG1 and a sub-memory block of the second cell region CREG2 can be selected simultaneously, and the two selected sub-memory blocks can correspond to a memory block as the unit of the erase operation. For example, two sub-memory blocks SMB11 and SMB21 can correspond to the first memory block, and two sub-memory blocks SMB12 and SMB22 can correspond to the second memory block. For ease of illustration and description, an example of a memory cell array including two memory blocks is described, but the number of memory blocks can vary.

[0141] Reference Figure 21 and Figure 22 The first decoder BDEC1 and the second decoder BDEC2 can generate a block selection signal based on the block address B_ADDR to determine a selected memory block among the first memory blocks SMB11 and SMB21 and the second memory blocks SMB12 and SMB22.

[0142] The first decoder BDEC1 can generate a first block selection signal BLKWL1 corresponding to the first memory blocks SMB11 and SMB21, and the second decoder BDEC2 can generate a second block selection signal BLKWL2 corresponding to the second memory blocks SMB12 and SMB22.

[0143] The first channel transistor block PTB1 and the second channel transistor block PTB2 can control the transfer of multiple drive signals SI to the corresponding memory blocks based on the block selection signal provided by the corresponding block decoder.

[0144] The first channel transistor block PTB1 can control the transmission of multiple drive signals SI to the first memory blocks SMB11 and SMB21 based on the block selection signal BLKWL1 provided from the first decoder BDEC1. The second channel transistor block PTB2 can control the transmission of multiple drive signals SI to the second memory blocks SMB12 and SMB22 based on the block selection signal BLKWL2 provided from the second decoder BDEC2.

[0145] When the first memory blocks SMB11 and SMB21 are selected, the block selection signal BLKWL1 provided from the first block decoder BDEC1 can be activated. Therefore, all channel transistors PTR, including those in the first channel transistor block PTB1, are turned on. At this time, multiple drive signals SI, including the ground selection signal GS, the string selection signal SS, and the word line drive signals S0 to S63, are passed to the first memory blocks SMB11 and SMB21. The multiple drive signals GS, SS, and S0 to S63 can be provided to each of the selected transistors in the first memory blocks SMB11 and SMB21, as well as the gate of the memory cell (i.e., the word line).

[0146] When the second memory blocks SMB12 and SMB22 are selected, the block selection signal BLKWL2 provided from the second block decoder BDEC2 is activated. Therefore, all channel transistors PTR in the second channel transistor block PTB2 are turned on. At this time, multiple drive signals SI, including the ground selection signal GS, the string selection signal SS, and the word line drive signals S0 to S63, are passed to the second memory blocks SMB12 and SMB22. The multiple drive signals GS, SS, and S0 to S63 can be provided to each of the selected transistors in the second memory blocks SMB12 and SMB22, as well as the gate of the memory cell (i.e., the word line).

[0147] In this way, multiple word line drive signals S0 to S63 generated based on the row address R_ADDR can be provided to multiple first word lines of the first unit region CREG1 and multiple second word lines of the second unit region CREG2.

[0148] In reference Figures 19 to 22In the described DDWL structure, the sum of the first number of multiple first endpoint lines NBLL in the first unit region CREG1 and the second number of multiple second endpoint lines NBLU in the second unit region CREG2 is equal to the number of bits in the page, which serves as the unit for read and write operations. For example, if the number of bits in the page, which serves as the unit for read and write operations, is 2N, then the first number of multiple first normal bit lines NBLL and the second number of multiple second normal bit lines NBLU are both N.

[0149] Figure 23 This is a perspective view illustrating an example of a non-volatile memory device. (Refer to...) Figure 23 The non-volatile memory device 301 may include a first cell region CREG1, a second cell region CREG2, and a peripheral circuit region PREG. In some embodiments, the first cell region CREG1, the second cell region CREG2, and the peripheral circuit region PREG may be stacked in the vertical direction D3. For example, as Figure 23 As shown, the second unit region CREG2 can be disposed above the first unit region CREG1 in the vertical direction D3, and the peripheral circuit region PREG can be disposed below the first unit region CREG1 in the vertical direction D3.

[0150] For ease of explanation and description, the case of stacking two element regions CREG1 and CREG2 in the vertical direction D3 will be described, but the arrangement is not limited to this. For example, see below for reference. Figure 30 The described non-volatile memory device may include three or more stacked cell regions, and integrated column repair may be applied to all stacked cell regions in the vertical direction.

[0151] The first unit region CREG1 may include multiple first bit lines BL, and the second unit region CREG2 may include multiple second bit lines BU. The first bit lines BL of the first unit region CREG1 may include multiple first normal bit lines NBLL and multiple first redundant bit lines RBLL. The second bit lines BU of the second unit region CREG2 may include multiple second normal bit lines NBLU and multiple second redundant bit lines RBLU.

[0152] The first bit line BL of the first unit region CREG1 can be grouped into a first bit line group BG1 and a second bit line group BG2. The first bit line group BG1 includes a portion of multiple first normal bit lines NBLL and a portion of multiple first redundant bit lines RBLL. The second bit line group BG2 includes the remaining portions of multiple first normal bit lines NBLL and the remaining portions of multiple first redundant bit lines RBLL.

[0153] The second bit line BU of the second unit region CREG2 can be grouped into a third bit line group BG3 and a fourth bit line group BG4. The third bit line group BG3 includes a portion of multiple second normal bit lines NBLU and a portion of multiple second redundant bit lines RBLU. The fourth bit line group BG4 includes other portions of multiple second normal bit lines NBLU and other portions of multiple second redundant bit lines RBLU.

[0154] Figure 23 The diagram shows, but is not limited to, bit lines in each cell region being grouped into two bit line groups. For example, bit lines in each cell region may be grouped into three or more bit line groups.

[0155] The page buffer circuit PGBF described above may include a first page buffer circuit PGBF1 and a second page buffer circuit PGBF2, and the page buffer decoder PBD described above may include a first page buffer decoder PBD1 that controls the page buffer of the first page buffer circuit PGBF1 and a second page buffer decoder PBD2 that controls the page buffer of the second page buffer circuit PGBF2.

[0156] The first page buffer circuit PGBF1 may include page buffers associated with the first normal bit line NBLL and the first redundant bit line RBLL of the first bit line group BG1, and the second normal bit line NBLU and the second redundant bit line RBLU of the third bit line group BG3. The second page buffer circuit PGBF2 may include page buffers associated with the first normal bit line NBLL and the first redundant bit line RBLL of the second bit line group BG2, and the second normal bit line NBLU and the second redundant bit line RBLU of the fourth bit line group BG4.

[0157] Figure 24 It is shown Figure 23 An example illustration of integrated column repair of a non-volatile memory device.

[0158] exist Figure 24 In the diagram, normal regions ANM1 and ANM2 represent regions with normal bit lines, and redundant regions ARD1 and ARD2 represent regions with redundant bit lines.

[0159] Reference Figure 24The first page buffer decoder PBD1 can integrate defective bit lines appearing in the first normal bit line NBLL of the first bit line group BG1 and the second normal bit line NBLU of the third bit line group BG3, and replace the defective bit lines with the first redundant bit line RBLL of the first bit line group BG1 and the second redundant bit line RBLU of the third bit line group BG3. For example, a defective bit line BLa appearing in the first normal bit line NBLL of the first bit line group BG1 in the first unit region CREG1 can be replaced by one of the first redundant bit line BLb of the first bit line group BG1 and the second redundant bit line BUB of the third bit line group BG3, and / or a defective bit line BUa appearing in the second normal bit line NBLU of the third bit line group BG3 can be replaced by one of the first redundant bit line BLb of the first bit line group BG1 and the second redundant bit line BUB of the third bit line group BG3.

[0160] The second-page buffer decoder PBD2 can integrate defective bit lines appearing in the first normal bit line NBLL of the second bit line group BG2 and the second normal bit line NBLU of the fourth bit line group BG4, and replace the defective bit lines with the first redundant bit line RBLL of the second bit line group BG2 and the second redundant bit line RBLU of the fourth bit line group BG4. For example, a defective bit line Blc appearing in the first normal bit line NBLL of the second bit line group BG2 in the first unit region CREG1 can be replaced by one of the first redundant bit line BLd of the second bit line group BG2 and the second redundant bit line BUd of the fourth bit line group BG4, and / or a defective bit line BUc appearing in the second normal bit line of the fourth bit line group BG4 can be replaced by one of the first redundant bit line BLd of the second bit line group BG2 and the second redundant bit line BUd of the fourth bit line group BG4.

[0161] Figure 25 It is shown that it includes Figure 23 A block diagram of an example page buffer circuit and page buffer decoder in a non-volatile memory device.

[0162] Reference Figure 25 The page buffer decoder PBD may include a first page buffer decoder PBD1 and a second page buffer decoder PBD2. The first page buffer decoder PBD1 may be connected to page buffer circuits PGBF1L and PGBF1U. Page buffer circuit PGBF1L includes page buffers connected to the first normal bit line NBLL and the first redundant bit line RBLL of the first bit line group BG1. Page buffer circuit PGBF1U includes page buffers connected to the second normal bit line NBLU and the second redundant bit line RBLU of the third bit line group BG3. The two page buffer circuits PGBF1L and PGBF1U are connected to... Figure 23 The first page buffer circuit PGBF1 corresponds to this.

[0163] The second page buffer decoder PBD2 can be connected to page buffer circuits PGBF2L and PGBF2U. Page buffer circuit PGBF2L includes page buffers connected to the first normal bit line NBLL and the first redundant bit line RBLL of the second bit line group BG2. Page buffer circuit PGBF2U includes page buffers connected to the second normal bit line NBLU and the second redundant bit line RBLU of the fourth bit line group BG4. The two page buffer circuits PGBF2L and PGBF2U are connected to... Figure 23 The second page buffer circuit PGBF2 corresponds to this.

[0164] In some implementations, each of the first page buffer decoder PBD1 and the second page buffer decoder PBD2 may include, as referenced Figure 5 The control logic circuit CLG, the first switching circuit SW1, the second switching circuit SW2, and the third switching circuit SW3 are described.

[0165] The first page buffer decoder PBD1 can output the data output signal DO1 by performing integrated column repair on the first bit group BG1 of the first unit region CREG1 and the third bit group BG3 of the second unit region CREG2 based on the column address C_ADDR and the first column repair information CRI1 stored in the first page buffer decoder PBD1. The first column repair information CRI1 may include integrated information about defective bit lines appearing in the first normal bit line NBLL of the first bit group BG1 and defective bit lines appearing in the second normal bit line NBLU of the third bit group BG3.

[0166] The second page buffer decoder PBD2 can output the data output signal DO2 by performing integrated column repair on the second bit line group BG2 of the first unit region CREG1 and the fourth bit line group BG4 of the second unit region CREG2 based on the column address C_ADDR and the second column repair information CRI2 stored in the second page buffer decoder PBD2. The second column repair information CRI2 may include integrated information about defective bit lines appearing in the first normal bit line NBLL of the second bit line group BG2 and defective bit lines appearing in the second normal bit line NBLU of the fourth bit line group BG4.

[0167] Figure 26 This is a perspective view showing an example of a non-volatile memory device.

[0168] Reference Figure 26 The non-volatile memory device 302 may include a first cell region CREG1, a second cell region CREG2, and a peripheral circuit region PREG. In the following text, the terms related to CREG and PREG will be omitted. Figure 1 Redundant description.

[0169] like Figure 26 As shown, the first unit region CREG1 and the second unit region CREG2 can be positioned above the peripheral circuit region PREG in the vertical direction D3. Multiple first normal bit lines NBLL, multiple first redundant bit lines RBLL, multiple second normal bit lines NBLU, and multiple second redundant bit lines RBLU can be arranged in the first horizontal direction D1 and extend in the second horizontal direction D2, which is perpendicular to the first horizontal direction D1. The first unit region CREG1 and the second unit region CREG2 can be arranged in the second horizontal direction D2.

[0170] As described above, the page buffer decoder PBD can be configured to extend in the first horizontal direction D1. A first page buffer circuit PGBFL, including page buffers connected to the first normal bit line NBLL and the first redundant bit line RBLL, can be configured to be adjacent to a first side of the page buffer decoder PBD in the second horizontal direction D2. A second page buffer circuit PGBFU, including page buffers connected to the second normal bit line NBLU and the second redundant bit line RBLU, can be configured to be adjacent to a second side of the page buffer decoder PBD in the second horizontal direction D2.

[0171] Page Buffer Decoder (PBD) can perform integrated column repair, which integrates defective bit lines appearing from multiple first normal bit lines (NBLL) and multiple second normal bit lines (NBLU), and replaces the defective bit lines appearing from multiple first redundant bit lines (RBLL) and multiple second redundant bit lines (RBLU) with multiple first redundant bit lines (RBLL) and multiple second redundant bit lines (RBLU).

[0172] Figure 27 This is a block diagram illustrating an example of a data center including storage devices. In some implementations, Figure 27 At least one NVM has as about Figures 1 to 26 The structure described.

[0173] Reference Figure 27 A Data Center 4000 can collect various types of data and provide services, and is also known as a data storage center. For example, a Data Center 4000 could be a system configured to operate search engines and databases, or a computing system used by a company (such as a bank) or government agency. Figure 27 As shown, data center 4000 may include application servers 50_1 to 50_n and storage servers 60_1 to 60_m (where each of m and n is an integer greater than 1). The number n of application servers 50_1 to 50_n and the number m of storage servers 60_1 to 60_m may be chosen differently. In some embodiments, the number n of application servers 50_1 to 50_n may be different from the number m of storage servers 60_1 to 60_m.

[0174] Application servers 50_1 to 50_n may include any one or any combination of processors 51_1 to 51_n, memory 52_1 to 52_n, switches 53_1 to 53_n, network interface controllers (NICs) 54_1 to 54_n, and storage devices 55_1 to 55_n. Processors 51_1 to 51_n may control all operations of application servers 50_1 to 50_n, access memory 52_1 to 52_n, and execute instructions and / or data loaded in memory 52_1 to 52_n. Non-limiting examples of memory 52_1 to 52_n may include dual data rate synchronous dynamic random access memory (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVDIIMM).

[0175] The number of processors and memory included in application servers 50_1 to 50_n can be selected differently. In some embodiments, processors 51_1 to 51_n and memory 52_1 to 52_n can provide processor-memory pairs. In some embodiments, the number of processors 51_1 to 51_n may differ from the number of memory 52_1 to 52_n. Processors 51_1 to 51_n may include single-core processors or multi-core processors. In some embodiments, such as Figure 27 As shown by the dashed lines, storage devices 55_1 to 55_n can be omitted from application servers 50_1 to 50_n. The number of storage devices 55_1 to 55_n included in application servers 50_1 to 50_n can be selected differently. Processors 51_1 to 51_n, memories 52_1 to 52_n, switches 53_1 to 53_n, NICs 54_1 to 54_n, and / or storage devices 55_1 to 55_n can communicate with each other via the links described above with reference to the accompanying drawings.

[0176] Storage servers 60_1 to 60_m may include any one or any combination of processors 61_1 to 61_m, memory 62_1 to 62_m, switches 63_1 to 63_m, network interface controllers (NICs) 64_1 to 64_m, and storage devices 65_1 to 65_m. Processors 61_1 to 61_m and memory 62_1 to 62_m may operate similarly to processors 51_1 to 51_n and memory 52_1 to 52_n of application servers 50_1 to 50_n described above.

[0177] Application servers 50_1 to 50_n can communicate with storage servers 60_1 to 60_m via network 70. In some implementations, network 70 can be implemented using Fibre Channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission. Optical switches providing high performance and high availability can be used as FC. Depending on the access method of network 70, storage servers 60_1 to 60_m can be configured as file storage devices, block storage devices, or object storage devices.

[0178] In some implementations, network 70 may be a storage-only network (such as a Storage Area Network (SAN)). For example, the SAN may be an FC-SAN, which can be implemented using an FC network and the FC protocol (FCP). In another case, the SAN may be an Internet Protocol (IP)-SAN, which uses a Transmission Control Protocol / Internet Protocol (TCP / IP) network and is implemented according to a SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In some implementations, network 70 may be a general-purpose network (such as a TCP / IP network). For example, network 70 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), or Non-Volatile Memory Fast (NVMe) over a Structured Module (NVMe-oF).

[0179] The main focus will be on describing application server 50_1 and storage server 60_1. However, it should be noted that the description of application server 50_1 can also be applied to other application servers (e.g., 50_n), and the description of storage server 60_1 can also be applied to other storage servers (e.g., 60_m).

[0180] Application server 50_1 can store data requested by users or clients in one of storage servers 60_1 to 60_m via network 70. In some implementations, application server 50_1 can retrieve data requested by users or clients from one of storage servers 60_1 to 60_m via network 70. For example, application server 50_1 can be implemented using a web server or a database management system (DBMS).

[0181] Application server 50_1 can access, via network 70, the memory 52_n and / or storage device 55_n included in another application server 50_n, and / or via network 70, the memory 62_1 to 62_m and / or storage device 65_1 to 65_m included in storage servers 60_1 to 60_m. Therefore, application server 50_1 can perform various operations on data stored in application servers 50_1 to 50_n and / or storage servers 60_1 to 60_m. For example, application server 50_1 can execute instructions for migrating or copying data between application servers 50_1 to 50_n and / or storage servers 60_1 to 60_m. In this case, data can be migrated from the memory 62_1 to 62_m of storage servers 60_1 to 60_m or directly from the storage devices 65_1 to 65_m of storage servers 60_1 to 60_m to the memory 52_1 to 52_n of application servers 50_1 to 50_n. In some implementations, the data migrated via network 70 may be encrypted data for security or privacy purposes.

[0182] In storage server 60_1, interface IF provides the physical connection between processor 61_1 and controller CTRL', and between NIC 64_1 and controller CTRL'. For example, interface IF can be implemented using the Direct Attach Storage (DAS) method, in which storage device 65_1 is directly connected to a dedicated cable. For example, interface IF can be implemented using various interface methods such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCIe, NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded MMC (eMMC), UFS, Embedded UFS (eUFS), and / or Compact Flash (CF) card interface.

[0183] In storage server 60_1, switch 63_1 can selectively connect processor 61_1 to storage device 65_1 or selectively connect NIC 64_1 to storage device 65_1 based on the control of processor 61_1.

[0184] In some embodiments, the network interface controller (NIC) 64_1 may include a network interface card and a network adapter. NIC 64_1 can connect to network 70 via a wired interface, wireless interface, Bluetooth interface, or optical interface. NIC 64_1 may include internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to processor 61_1 and / or switch 63_1 via the host bus interface. In some embodiments, NIC 64_1 may be integrated with any one or any combination of processor 61_1, switch 63_1, and storage device 65_1.

[0185] In application servers 50_1 to 50_n or storage servers 60_1 to 60_m, processors 51_1 to 51_m and 61_1 to 61_n can send commands to storage devices 55_1 to 55_n and 65_1 to 65_m or memories 52_1 to 52_n and 62_1 to 62_m, and program or read data. In this case, the data can be data whose errors have been corrected by an error correction code (ECC) engine. The data can be data processed using Data Bus Inversion (DBI) or Data Masking (DM), and includes Cyclic Redundancy Check (CRC) information. The data can be encrypted data for security or privacy purposes.

[0186] In response to a read command received from processors 51_1 to 51_m and 61_1 to 61_n, storage devices 55_1 to 55_n and 65_1 to 65_m can send control signals and command / address signals to the non-volatile memory device (e.g., a NAND flash memory device) NVM. Therefore, when data is read from the non-volatile memory device NVM, a read enable signal can be input as a data output control signal to output data to the DQ bus. A data strobe signal can be generated using the read enable signal. Command and address signals can be latched based on the rising or falling edge of the write enable signal.

[0187] The controller CTRL' controls all operations of storage device 65_1. In some embodiments, the controller CTRL' may include static RAM (SRAM). The controller CTRL' may write data to the non-volatile memory device NVM in response to a write command, or read data from the non-volatile memory device NVM in response to a read command. For example, write and / or read commands may be generated based on requests provided from a host (e.g., processor 61_1 of storage server 60_1, processor 61_m of another storage server 60_m, or processors 51_1 to 51_n of application servers 50_1 to 50_n). The buffer BUF may temporarily store (or buffer) data to be written to or read from the non-volatile memory device NVM. In some embodiments, the buffer BUF may include DRAM. The buffer BUF may store metadata. The metadata may represent user data or data generated by the controller CTRL' to manage the non-volatile memory device NVM. Storage device 65_1 may include a security element (SE) for security or privacy.

[0188] Figure 28 This is a cross-sectional view showing an example of a non-volatile memory device.

[0189] Reference Figure 28 The memory device (or semiconductor device) 5000 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell region and a lower chip including a peripheral circuit region PREG can be fabricated separately. The at least one upper chip and the lower chip can then be connected to each other by a bonding method to realize the C2C structure. For example, the bonding method may refer to a method of electrically connecting and / or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, if the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Optionally or additionally, the bonding metal pattern may be formed of other metals, including but not limited to aluminum (Al) or tungsten (W).

[0190] The memory device 5000 may include at least one on-chip containing cell regions. For example, such as Figure 28As shown, the memory device 5000 may include two upper chips. However, the number of upper chips is not limited to this. In the case where the memory device 5000 includes two upper chips, a first upper chip that may include a first cell region CREG1, a second upper chip that may include a second cell region CREG2, and a lower chip that may include a peripheral circuit region PREG can be manufactured separately. Subsequently, for example, the first upper chip, the second upper chip, and the lower chip can be connected to each other by a bonding method to manufacture the memory device 5000. In some embodiments, the first upper chip can be flipped and then connected to the lower chip by a bonding method, and the second upper chip can also be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first and second upper chips will be defined based on each of the first and second upper chips before it is flipped. For example, in Figure 28 In this configuration, the upper portion of the lower chip may refer to an upper portion defined based on the +Z-axis direction, and the upper portion of each of the first and second upper chips may refer to an upper portion defined based on the -Z-axis direction. However, the configuration is not limited in this respect. For example, in some embodiments, one of the first and second upper chips may be flipped and then connected to the corresponding chip by a bonding method.

[0191] Each of the peripheral circuit region PREG, the first cell region CREG1, and the second cell region CREG2 of the memory device 5000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0192] The peripheral circuit region PREG may include a first substrate 5210 and a plurality of circuit elements (e.g., first circuit element 5220a, second circuit element 5220b, and third circuit element 5220c) formed on the first substrate 5210. An interlayer insulating layer 5215 including one or more insulating layers may be disposed on the plurality of circuit elements 5220a, 5220b, and 5220c, and a plurality of metal wires electrically connected to the plurality of circuit elements 5220a, 5220b, and 5220c may be disposed in the interlayer insulating layer 5215. For example, the plurality of metal wires may include first metal wires 5230a, 5230b, and 5230c connected to the plurality of circuit elements 5220a, 5230b, and 5220c, and second metal wires 5240a, 5240b, and 5240c formed on the first metal wires 5230a, 5230b, and 5230c. The plurality of metal wires may be formed of at least one of a variety of conductive materials. In some embodiments, the first metal lines 5230a, 5230b and 5230c may be formed of tungsten, which has a relatively high resistivity, and the second metal lines 5240a, 5240b and 5240c may be formed of copper, which has a relatively low resistivity.

[0193] First metal lines 5230a, 5230b, and 5230c and second metal lines 5240a, 5240b, and 5240c are shown and described. However, embodiments are not limited in this respect. For example, in some embodiments, one or more additional metal lines may be further formed on the second metal lines 5240a, 5240b, and 5240c. In this case, the second metal lines 5240a, 5240b, and 5240c may be formed of aluminum, and at least a portion of the additional metal lines formed on the second metal lines 5240a, 5240b, and 5240c may be formed of copper having a lower resistivity than the aluminum of the second metal lines 5240a, 5240b, and 5240c.

[0194] An interlayer insulating layer 5215 may be disposed on a first substrate 5210 and may include an insulating material (such as silicon oxide and / or silicon nitride).

[0195] Each of the first cell region CREG1 and the second cell region CREG2 may include at least one memory block. The first cell region CREG1 may include a second substrate 5310 and a common source line 5320. Multiple word lines 5330 (e.g., 5331 to 5338) may be stacked on the second substrate 5310 in a direction perpendicular to the top surface of the second substrate 5310 (e.g., the Z-axis direction). Serial select lines and ground select lines may be disposed above and below the word lines 5330, and multiple word lines 5330 may be disposed between the serial select lines and the ground select lines. Optionally or additionally, the second cell region CREG2 may include a third substrate 5410 and a common source line 5420, and multiple word lines 5430 (e.g., 5431 to 5438) may be stacked on the third substrate 5410 in a direction perpendicular to the top surface of the third substrate 5410 (e.g., the Z-axis direction). Each of the second substrate 5310 and the third substrate 5410 may be formed of at least one of various materials, such as, but not limited to, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Multiple channel structures CH may be formed in each of the first unit region CREG1 and the second unit region CREG2.

[0196] In some embodiments, such as region "A1" as an alternative embodiment to region "A", a channel structure CH may be disposed in a bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 5310 to penetrate word line 5330, serial select line, and ground select line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to a first metal line 5350c and a second metal line 5360c in the bit line bonding region BLBA. For example, the second metal line 5360c may be a bit line and may be connected to the channel structure CH via the first metal line 5350c. The bit line 5360c may extend in a first direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 5310.

[0197] In some embodiments, such as region "A2" which is an alternative embodiment of region "A", the channel structure CH may include a lower channel LCH and an upper channel UCH that can be connected to each other. For example, the channel structure CH may be formed by a process for forming the lower channel LCH and a process for forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 5310 to penetrate the common source line 5320 and the lower word lines 5331 and 5332. The lower channel LCH may include a data storage layer, a channel layer, and a filler insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 5333 to 5338. The upper channel UCH may include a data storage layer, a channel layer, and a filler insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 5350c and the second metal line 5360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The memory device 5000 may include channels with improved width uniformity due to the lower channel (LCH) and upper channel (UCH) formed by sequentially performed processes.

[0198] When the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in region "A2", the word lines located near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, word lines 5332 and 5333 adjacent to the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Optionally or additionally, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The voltage level applied to the dummy word lines may be different from the voltage level applied to the general word lines, thus it is feasible to reduce the impact of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device.

[0199] In some embodiments, in region "A2", the number of lower word lines 5331 and 5332 penetrated by the lower channel LCH may be less than the number of upper word lines 5333 to 5338 penetrated by the upper channel UCH. However, the word line configuration is not limited in this respect. For example, in some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. Optionally or additionally, the structural features and connection relationships of the channel structure CH disposed in the second unit region CREG2 may be substantially the same as those of the channel structure CH disposed in the first unit region CREG1. For example, the channel structure CH disposed in the second unit region CREG2 may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer may be electrically connected to the first metal line 5450c and the second metal line 5460c in the bit line bonding region BLBA.

[0200] In the bit line bonding region BLBA, a first through electrode THV1 may be disposed in the first cell region CREG1, and a second through electrode THV2 may be disposed in the second cell region CREG2. For example... Figure 28 As shown, the first through electrode THV1 can penetrate the common source line 5320 and multiple word lines 5330. In some embodiments, the first through electrode THV1 can also penetrate the second substrate 5310. The first through electrode THV1 may include a conductive material. Optionally or additionally, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0201] In some embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected to each other via a first through metal pattern 5372d and a second through metal pattern 5472d. The first through metal pattern 5372d can be formed at the bottom of a first upper chip including a first cell region CREG1, and the second through metal pattern 5472d can be formed at the top of a second upper chip including a second cell region CREG2. The first through electrode THV1 can be electrically connected to a first metal line 5350c and a second metal line 5360c. A lower via 5371d can be formed between the first through electrode THV1 and the first through metal pattern 5372d, and an upper via 5471d can be formed between the second through electrode THV2 and the second through metal pattern 5472d. The first through metal pattern 5372d and the second through metal pattern 5472d can be connected to each other by a bonding method.

[0202] In some embodiments, in the bit line bonding region BLBA, an upper metal pattern 5252 may be formed in the uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern 5392 having the same shape as the upper metal pattern 5252 may be formed in the uppermost metal layer of the first cell region CREG1. The upper metal pattern 5392 of the first cell region CREG1 and the upper metal pattern 5252 of the peripheral circuit region PREG may be electrically connected to each other by a bonding method. In the bit line bonding region BLBA, a bit line 5360c may be electrically connected to a page buffer included in the peripheral circuit region PERI. For example, a portion of the circuit element 5220c of the peripheral circuit region PREG may constitute a page buffer, and the bit line 5360c may be electrically connected to the circuit element 5220c constituting the page buffer via the upper bonding metal pattern 5370c of the first cell region CREG1 and the upper bonding metal pattern 5270c of the peripheral circuit region PERI.

[0203] Continue to refer to Figure 28 In the word line bonding area WLBA, the word line 5330 of the first cell region CREG1 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 5310 and may be connected to a plurality of cell contact plugs 5340 (e.g., 5341 to 5347). A first metal line 5350b and a second metal line 5360b may be sequentially connected to the cell contact plugs 5340 connected to the word line 5330. In the word line bonding area WLBA, the cell contact plugs 5340 may be connected to the peripheral circuit region PREG via the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PERI.

[0204] Cell contact plug 5340 can be electrically connected to a line decoder included in the peripheral circuitry region PERI. For example, a portion of the circuit elements 5220b in the peripheral circuitry region PREG can constitute a line decoder, and cell contact plug 5340 can be electrically connected to the circuit elements 5220b constituting the line decoder via the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuitry region PERI. In some embodiments, the operating voltage of the circuit elements 5220b constituting the line decoder can be different from the operating voltage of the circuit elements 5220c constituting the page buffer. For example, the operating voltage of the circuit elements 5220c constituting the page buffer can be greater than the operating voltage of the circuit elements 5220b constituting the line decoder.

[0205] In some embodiments, in the word line bonding area WLBA, the word line 5430 of the second cell region CREG2 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 5410 and may be connected to a plurality of cell contact plugs 5440 (e.g., 5441 to 5447). The cell contact plugs 5440 may be connected to the peripheral circuitry region PREG via the upper metal pattern of the second cell region CREG2 and the lower metal pattern, upper metal pattern, and cell contact plug 5348 of the first cell region CREG1.

[0206] In the word line bonding region WLBA, an upper bonding metal pattern 5370b may be formed in the first cell region CREG1, and an upper bonding metal pattern 5270b may be formed in the peripheral circuit region PERI. The upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG may be electrically connected to each other by a bonding method. The upper bonding metal patterns 5370b and 5270b may be formed of at least one metal, including but not limited to aluminum, copper, and tungsten.

[0207] In the external pad bonding region PA, a lower metal pattern 5371e may be formed in the lower part of the first unit region CREG1, and an upper metal pattern 5472a may be formed in the upper part of the second unit region CREG2. The lower metal pattern 5371e of the first unit region CREG1 and the upper metal pattern 5472a of the second unit region CREG2 may be connected to each other in the external pad bonding region PA by a bonding method. In some embodiments, the upper metal pattern 5372a may be formed in the upper part of the first unit region CREG1, and the upper metal pattern 5272a may be formed in the upper part of the peripheral circuit region PERI. The upper metal pattern 5372a of the first unit region CREG1 and the upper metal pattern 5272a of the peripheral circuit region PREG may be connected to each other by a bonding method.

[0208] Common source electrode contact plugs 5380 and 5480 may be disposed in the external pad bonding region PA. Common source electrode contact plugs 5380 and 5480 may be formed of a conductive material (such as a metal, a metal compound, and / or doped polysilicon). Common source electrode contact plug 5380 of the first unit region CREG1 may be electrically connected to common source electrode 5320, and common source electrode contact plug 5480 of the second unit region CREG2 may be electrically connected to common source electrode 5420. First metal wire 5350a and second metal wire 5360a may be sequentially stacked on common source electrode contact plug 5380 of the first unit region CREG1, and first metal wire 5450a and second metal wire 5460a may be sequentially stacked on common source electrode contact plug 5480 of the second unit region CREG2.

[0209] Input-output pads 5205, 5405, and 5406 can be positioned within the external pad mating area PA. For example... Figure 28 As shown, a lower insulating layer 5201 may cover the bottom surface of the first substrate 5210, and a first input-output pad 5205 may be formed on the lower insulating layer 5201. The first input-output pad 5205 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via a first input-output contact plug 5203, and may be separated from the first substrate 5210 via the lower insulating layer 5201. Optionally or additionally, a side insulating layer may be disposed between the first input-output contact plug 5203 and the first substrate 5210 to electrically isolate the first input-output contact plug 5203 from the first substrate 5210.

[0210] An upper insulating layer 5401 covering the top surface of the third substrate 5410 may be formed on the third substrate 5410. A second input-output pad 5405 and / or a third input-output pad 5406 may be disposed on the upper insulating layer 5401. The second input-output pad 5405 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via second input-output contact plugs 5403 and 5303, and the third input-output pad 5406 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG via third input-output contact plugs 5404 and 5304.

[0211] In some embodiments, the third substrate 5410 may not be located in the region where the input-output contact plug is provided. For example, as shown in region "B", the third input-output contact plug 5404 may be separated from the third substrate 5410 in a direction parallel to the top surface of the third substrate 5410 and may penetrate the interlayer insulation layer 5415 of the second cell region CREG2 to connect to the third input-output pad 5406. In this case, the third input-output contact plug 5404 may be formed by at least one of various processes.

[0212] In some implementations, as shown in region "B1" as an alternative embodiment of region "B", the third input-output contact plug 5404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input-output contact plug 5404 may gradually increase (e.g., widen) toward the upper insulating layer 5401. In other words, the diameter of the channel structure CH described in region "A1" may gradually decrease (e.g., narrow) toward the upper insulating layer 5401, but the diameter of the third input-output contact plug 5404 may gradually increase toward the upper insulating layer 5401. For example, the third input-output contact plug 5404 may be formed after the second unit region CREG2 and the first unit region CREG1 are joined together by a joining method.

[0213] In some implementations, such as region "B2" as an alternative embodiment of region "B", the third input-output contact plug 5404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input-output contact plug 5404 may gradually decrease (e.g., narrow) toward the upper insulating layer 5401. In other words, like the channel structure CH, the diameter of the third input-output contact plug 5404 may gradually decrease (e.g., narrow) toward the upper insulating layer 5401. For example, the third input-output contact plug 5404 may be formed together with the unit contact plug 5440 before the second unit region CREG2 and the first unit region CREG1 are engaged with each other.

[0214] In some embodiments, the input-output contact plug may be stacked with the third substrate 5410. For example, as shown in region “C”, the second input-output contact plug 5403 may penetrate the interlayer insulation layer 5415 of the second unit region CREG2 in a third direction (e.g., the Z-axis direction) and be electrically connected to the second input-output pad 5405 through the third substrate 5410. In this case, the connection structure of the second input-output contact plug 5403 and the second input-output pad 5405 can be implemented by various methods.

[0215] In some embodiments, as shown in region "C1" as an alternative embodiment of region "C", the opening 5408 may be formed to penetrate the third substrate 5410, and the second input-output contact plug 5403 may be directly connected to the second input-output pad 5405 through the opening 5408 formed in the third substrate 5410. In this case, as shown in region "C1", the diameter of the second input-output contact plug 5403 may gradually increase (e.g., widen) toward the second input-output pad 5405. However, the size is not limited in this respect. For example, in some embodiments, the diameter of the second input-output contact plug 5403 may gradually decrease (e.g., narrower) toward the second input-output pad 5405.

[0216] In some embodiments, as shown in region "C2" as an alternative embodiment of region "C", an opening 5408 penetrating the third substrate 5410 may be formed, and a contact 5407 may be formed in the opening 5408. One end of the contact 5407 may be connected to the second input-output pad 5405, and the other end of the contact 5407 may be connected to the second input-output contact plug 5403. Thus, the second input-output contact plug 5403 can be electrically connected to the second input-output pad 5405 through the contact 5407 in the opening 5408. In this case, as shown in region "C2", the diameter of the contact 5407 may gradually increase (e.g., widen) toward the second input-output pad 5405, and the diameter of the second input-output contact plug 5403 may gradually decrease (e.g., narrow) toward the second input-output pad 5405. For example, a second input-output contact plug 5403 may be formed together with the unit contact plug 5440 before the second unit region CREG2 and the first unit region CREG1 are engaged with each other, and a contact 5407 may be formed after the second unit region CREG2 and the first unit region CREG1 are engaged with each other.

[0217] In some embodiments shown in region "C3" as an alternative embodiment of region "C", the stop member 5409 may also be formed on the bottom end of the opening 5408 of the third substrate 5410, compared to region "C2". The stop member 5409 may be a metal wire formed in the same layer as the common source line 5420. Optionally or additionally, the stop member 5409 may be a metal wire formed in the same layer as at least one of the word lines 5430. The second input-output contact plug 5403 may be electrically connected to the second input-output pad 5405 via the contact 5407 and the stop member 5409.

[0218] Similar to the second input-output contact plug 5403 and the third input-output contact plug 5404 of the second unit region CREG2, the diameter of each of the second input-output contact plug 5303 and the third input-output contact plug 5304 of the first unit region CREG1 may gradually decrease (e.g., narrow) and / or gradually increase (e.g., widen) towards the lower metal pattern 5371e.

[0219] In some embodiments, a slit 5411 may be formed in the third substrate 5410. For example, the slit 5411 may be formed at a specific location in the outer pad engagement region PA. For example, as shown in region “D”, when viewed in a plan view, the slit 5411 may be located between the second input-output pad 5405 and the cell contact plug 5440. Optionally or additionally, when viewed in a plan view, the second input-output pad 5405 may be located between the slit 5411 and the cell contact plug 5440.

[0220] In some embodiments, such as region "D1" as an alternative embodiment of region "D", the slit 5411 may be formed to penetrate the third substrate 5410. For example, the slit 5411 may be used to prevent the third substrate 5410 from developing minute cracks when the opening 5408 is formed. However, the embodiments are not limited in this respect. For example, in some embodiments, the slit 5411 may be formed to a depth of about 60% to about 70% of the thickness of the third substrate 5410.

[0221] In some implementations, such as region "D2" as an alternative embodiment of region "D", conductive material 5412 may be formed in slit 5411. For example, conductive material 5412 may be used to release leakage current that occurs when driving circuit elements in the external pad bonding region PA to the outside. In this case, conductive material 5412 may be connected to an external ground wire.

[0222] In some embodiments, such as region "D3" as an alternative embodiment of region "D", insulating material 5413 may be formed in slit 5411. For example, insulating material 5413 may be used to electrically isolate the second input-output pad 5405 and the second input-output contact plug 5403 disposed in the outer pad bonding region PA from the word line bonding region WLBA. Since insulating material 5413 is formed in slit 5411, it is feasible to prevent the voltage supplied through the second input-output pad 5405 from affecting the metal layer disposed on the third substrate 5410 in the word line bonding region WLBA.

[0223] In some embodiments, the first input-output pads to the third input-output pads 5205, 5405, and 5406 may be selectively formed. For example, the memory device 5000 may be implemented to include only the first input-output pad 5205 disposed on the first substrate 5210, only the second input-output pad 5405 disposed on the third substrate 5410, and / or only the third input-output pad 5406 disposed on the upper insulating layer 5401.

[0224] In some embodiments, at least one of the second substrate 5310 of the first unit region CREG1 and the third substrate 5410 of the second unit region CREG2 may be used as a sacrificial substrate and may be completely and / or partially removed before and / or after the bonding process. After removing the substrate, additional layers may be stacked. For example, the second substrate 5310 of the first unit region CREG1 may be removed before and / or after the bonding process of the peripheral circuit region PREG and the first unit region CREG1. Subsequently, an insulating layer or a conductive layer for connection may be formed covering the top surface of the common source line 5320. Similarly, the third substrate 5410 of the second unit region CREG2 may be removed before and / or after the bonding process of the first unit region CREG1 and the second unit region CREG2, and subsequently, an upper insulating layer 5401 or a conductive layer for connection may be formed covering the top surface of the common source line 5420.

[0225] Figure 29 This is an illustration of an example of a manufacturing process for a non-volatile memory device.

[0226] Reference Figure 29 Integrated circuits can be formed on the first wafer WF1, the second wafer WF2, and the third wafer WF3. A memory cell array including the first cell region CREG1 and the second cell region CREG2 described above can be formed on the first wafer WF1 and the second wafer WF2, and peripheral circuits can be formed on the third wafer WF3. When integrated circuits are formed on the first wafer WF1, the second wafer WF2, and the third wafer WF3, the first wafer WF1, the second wafer WF2, and the third wafer WF3 can be bonded together by a bonding method. The bonded wafers WF1, WF2, and WF3 can be diced into multiple chips, and each chip corresponds to a semiconductor device 5000 including stacked semiconductor dies SD1, SD2, and SD3. The diced portion of the first wafer WF1 corresponds to the first semiconductor die SD1, the diced portion of the second wafer WF2 corresponds to the second semiconductor die SD2, and the diced portion of the third wafer WF3 corresponds to the third semiconductor die SD3. Figure 28 The non-volatile memory device 5000 can be based on Figure 29 It is manufactured using advanced manufacturing processes.

[0227] Figure 30 This is a cross-sectional view showing an example of a semiconductor package including a non-volatile memory device.

[0228] Reference Figure 30In the semiconductor package 2000, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a body portion 2120, a package top pad disposed on the top surface of the body portion 2120, a package bottom pad (or lower pad) 2125 disposed on or exposed through the bottom surface of the body portion 2120, and internal wiring 2135 within the body portion 2120 electrically connecting the package top pad to the package bottom pad 2125.

[0229] Multiple pads 2125 can be connected to multiple wiring patterns on the main substrate via multiple conductive bumps 2800.

[0230] A packaging substrate 2100 may be disposed beneath a stacked structure 2200 including a peripheral circuit semiconductor chip 2010 and a plurality of memory semiconductor chips 2021, 2022, 2023, and 2024. The peripheral circuit semiconductor chip 2010 may have a peripheral circuit region PREG as described above, and each of the plurality of memory semiconductor chips 2021, 2022, 2023, and 2024 may have a cell region. A molding layer 2500 may be formed to cover the stacked structure 2200 and the packaging substrate 2100.

[0231] The peripheral circuit semiconductor chip 2010 may be provided with the page buffer circuit and page buffer decoder as described above. The buffer decoder can perform integrated column repair, which shares redundant bit lines of at least two of the multiple memory semiconductor chips 2021, 2022, 2023 and 2024.

[0232] As described above, non-volatile memory devices can provide improved repair performance and yield by performing column repair using defective bit lines integrated across multiple cell regions. Non-volatile memory devices can reduce repair resources and the size of the non-volatile memory device itself.

[0233] The memory devices described herein can be applied to any electronic device and system, including non-volatile memory devices. For example, the disclosed memory devices may include memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), universal flash storage (UFS), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital televisions, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, data centers, automotive driving systems, and the like.

[0234] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims. Specific features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from the combination may be removed from the combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

[0235] The foregoing is illustrative of various examples. Although these examples have been described, those skilled in the art will readily understand that many modifications are possible without substantially departing from the scope of this disclosure.

Claims

1. A non-volatile memory device, comprising: The first unit region includes multiple first normal bit lines and multiple first redundant bit lines; The second unit region is located vertically above the first unit region and includes multiple second normal bit lines and multiple second redundant bit lines; as well as The peripheral circuit area is vertically positioned below the first unit area and includes a page buffer circuit and a page buffer decoder. The page buffer circuit includes multiple page buffers connected to the plurality of first normal bit lines, the plurality of second normal bit lines, the plurality of first redundant bit lines, and the plurality of second redundant bit lines. The page buffer decoder is configured to integrate defective bit lines from the plurality of first normal bit lines and the plurality of second normal bit lines, and replace the defective bit lines with redundant bit lines from the plurality of first redundant bit lines and the plurality of second redundant bit lines.

2. The non-volatile memory device according to claim 1, wherein, The page buffer decoder is configured to perform at least one of the following operations: replacing defective bit lines in the plurality of first normal bit lines with redundant bit lines in the plurality of second redundant bit lines, and replacing defective bit lines in the plurality of second normal bit lines with redundant bit lines in the plurality of first redundant bit lines.

3. The non-volatile memory device according to claim 1, wherein, The page buffer decoder includes: A first switching circuit is configured to control the connection between an input-output line and a page buffer connected to the plurality of first normal bit lines based on a first column of repair information corresponding to one or more defective bit lines among the plurality of first normal bit lines. A second switching circuit is configured to control the connection between an input-output line and a page buffer connected to the plurality of second normal bit lines based on a second column of repair information corresponding to one or more defective bit lines among the plurality of second normal bit lines; and The third switching circuit is configured to control the connection between the input-output line and the plurality of first redundant bit lines and the plurality of second redundant bit lines based on a first column of repair information corresponding to one or more defective bit lines among the plurality of first normal bit lines and a second column of repair information corresponding to one or more defective bit lines among the plurality of second normal bit lines.

4. The non-volatile memory device according to claim 1, wherein, The first unit area includes multiple first word lines, the second unit area includes multiple second word lines, and the peripheral circuit area includes a circuit system configured to simultaneously enable the following: The first selected word line corresponds to the row address of the plurality of first word lines, and The second selected word line corresponds to the row address of the plurality of second word lines.

5. The non-volatile memory device according to claim 4, wherein, The plurality of first word lines and the plurality of second word lines are connected to each other through conductive paths.

6. The non-volatile memory device according to claim 4, wherein, The peripheral circuit region includes a circuit system configured to apply multiple word line drive signals jointly to the multiple first word lines and the multiple second word lines.

7. The non-volatile memory device according to claim 1, wherein, The sum of the number of the plurality of first normal bit lines and the number of the plurality of second normal bit lines is equal to the number of bits in a page, which serves as the unit for read and write operations.

8. The non-volatile memory device according to claim 1, wherein, The plurality of first normal bit lines, the plurality of first redundant bit lines, the plurality of second normal bit lines, and the plurality of second redundant bit lines are spaced apart in a first horizontal direction and extend in a second horizontal direction perpendicular to the first horizontal direction. The page buffer decoder extends in the first horizontal direction. The page buffers connected to the plurality of first normal bit lines and the plurality of first redundant bit lines are arranged adjacent to the first side of the page buffer decoder in the second horizontal direction, and The page buffer connected to the plurality of second normal bit lines and the plurality of second redundant bit lines is arranged to be adjacent to the second side of the page buffer decoder in the second horizontal direction, with the second side opposite to the first side.

9. The non-volatile memory device according to claim 1, wherein, The bit lines of the first unit region are grouped into a first bit line group and a second bit line group. The first bit line group includes a first portion of the plurality of first normal bit lines and a first portion of the plurality of first redundant bit lines. The second bit line group includes a second portion of the plurality of first normal bit lines and a second portion of the plurality of first redundant bit lines. The bit lines in the second unit region are grouped into a third bit line group and a fourth bit line group. The third bit line group includes the first part of the plurality of second normal bit lines and the first part of the plurality of second redundant bit lines. The fourth bit line group includes the second part of the plurality of second normal bit lines and the second part of the plurality of second redundant bit lines.

10. The non-volatile memory device according to claim 9, wherein, The page buffer decoder includes: The first page buffer decoder is configured to control page buffers connected to the first normal bit line and the first redundant bit line of the first bit line group and the second normal bit line and the second redundant bit line of the third bit line group; and The second page buffer decoder is configured to control page buffers connected to the first normal bit line and the first redundant bit line of the second bit line group and the second normal bit line and the second redundant bit line of the fourth bit line group.

11. The non-volatile memory device according to claim 10, wherein, The first page buffer decoder is configured to integrate the first normal bit line from the first normal bit line of the first bit line group and the first defective bit line from the second normal bit line of the third bit line group, and replace the first defective bit line with the first redundant bit line of the first bit line group and the second redundant bit line of the third bit line group. The second page buffer decoder is configured to integrate the second defective bit line in the first normal bit line of the second bit line group and the second normal bit line of the fourth bit line group, and replace the second defective bit line with the first redundant bit line of the second bit line group and the second redundant bit line of the fourth bit line group.

12. The non-volatile memory device according to claim 10, wherein, The first page buffer decoder is configured to perform at least one of the following operations: replacing defective bit lines in the first normal bit lines of the first bit line group with first redundant bit lines of the first bit line group and second redundant bit lines of the third bit line group; and replacing defective bit lines in the second normal bit lines of the third bit line group with first redundant bit lines of the first bit line group and second redundant bit lines of the third bit line group. The second page buffer decoder is configured to perform at least one of the following operations: replacing defective bit lines in the first normal bit lines of the second bit line group with first redundant bit lines of the second bit line group and second redundant bit lines of the fourth bit line group, and replacing defective bit lines in the second normal bit lines of the fourth bit line group with first redundant bit lines of the second bit line group and second redundant bit lines of the fourth bit line group.

13. The non-volatile memory device according to claim 10, wherein, The first page buffer decoder is configured to store integrated information about defective bit lines in the first normal bit lines of the first bit line group and defective bit lines in the second normal bit lines of the third bit line group, and The second page buffer decoder is configured to store integrated information about defective bit lines in the first normal bit lines of the second bit line group and defective bit lines in the second normal bit lines of the fourth bit line group.

14. The non-volatile memory device according to claim 1, wherein, The plurality of first normal bit lines and the plurality of first redundant bit lines are arranged to overlap with the plurality of second normal bit lines and the plurality of second redundant bit lines in the vertical direction.

15. The non-volatile memory device according to claim 14, wherein, The plurality of second normal bit lines and the plurality of second redundant bit lines included in the second cell region are connected to the page buffer included in the peripheral circuit region via a vertical conductive path penetrating the first cell region, and Each of the plurality of second normal bit lines and the plurality of second redundant bit lines is cut into two segments in the intersection region traversed by the corresponding vertical conductive path, and the two segments are connected to each other by a detour conductive path spaced apart from the vertical conductive path.

16. The non-volatile memory device according to any one of claims 1 to 15, in, The plurality of first normal bit lines and the plurality of first redundant bit lines included in the first unit region are disconnected from the plurality of second normal bit lines and the plurality of second redundant bit lines included in the second unit region.

17. A non-volatile memory device, comprising: The first unit region includes multiple first normal bit lines and multiple first redundant bit lines; The second unit region includes multiple second normal bit lines and multiple second redundant bit lines; as well as The peripheral circuitry area includes the page buffer circuitry and the page buffer decoder. The page buffer circuit includes multiple page buffers connected to the plurality of first normal bit lines, the plurality of second normal bit lines, the plurality of first redundant bit lines, and the plurality of second redundant bit lines. The page buffer decoder is configured to integrate defective bit lines from the plurality of first normal bit lines and the plurality of second normal bit lines, and replace the defective bit lines with redundant bit lines from the plurality of first redundant bit lines and the plurality of second redundant bit lines.

18. The non-volatile memory device according to claim 17, wherein, The second unit area is positioned vertically above the first unit area.

19. The non-volatile memory device according to claim 17 or 18, wherein, The first and second unit regions are positioned vertically above the peripheral circuit region. The plurality of first normal bit lines, the plurality of first redundant bit lines, the plurality of second normal bit lines, and the plurality of second redundant bit lines are spaced apart in a first horizontal direction and extend in a second horizontal direction perpendicular to the first horizontal direction. The first unit region and the second unit region are separated in the second horizontal direction.

20. A non-volatile memory device, comprising: Multiple unit areas and peripheral circuit areas are stacked vertically. Each of the multiple unit regions includes multiple normal bit lines and multiple redundant bit lines, and The peripheral circuit region includes a page buffer decoder, which is configured to replace defective bit lines in a plurality of first normal bit lines in a first unit region with redundant bit lines in a second unit region included in the plurality of unit regions.

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