Microelectronic unit using vertically stacked units

Abstract

Microelectronic unit (100; 200; 300) having a plurality of layers, wherein the microelectronic unit has: a first pair of transistors (110; 210a, 210b; 217a, 217b; 310a, 310b) stacked vertically and connected in series, both transistors of the first pair being of the same type; and a second pair of transistors (116; 215, 216; 315, 316) connected in parallel, wherein the second pair of transistors is of a different type than the first pair of transistors, wherein a gate of a transistor (217a; 210a; 310a) of the first pair of transistors and gates of the second pair of transistors are arranged exclusively in the same layer of the microelectronic unit, wherein the first pair of transistors and the second pair of transistors are arranged essentially perpendicular to the majority of layers, wherein the gate of one transistor (210a; 217a; 310a) of the first pair of transistors and the gate of one transistor (116; 216; 316) of the second pair of transistors are connected to each other and correspond to a first input (171; 371) of the microelectronic unit, wherein the gate of another transistor (210b; 217b; 310b) of the first pair of transistors and the gate of another transistor (215; 315) of the second pair of transistors are connected to each other and correspond to a second input (172; 372) of the microelectronic unit, wherein the gate of the other transistor of the first pair of transistors and the gate of the other transistor of the second pair of transistors are arranged in different layers of the microelectronic unit, the microelectronic unit further comprising: power supply traces (191; 291; 391, 392) arranged in a first layer of the microelectronic unit, wherein one of the power supply traces is connected to an end of the first pair of vertically stacked transistors and another of the power supply traces is connected to power supply terminal ends of the transistors of the second pair of transistors, and a second layer in which the signal connection conductors (181; 281;381) are arranged, wherein the first pair of vertically stacked transistors and the second pair of transistors are arranged between the first layer and the second layer, wherein a vertical conducting element (143) extends from a conducting element (153) in an upward direction to the second layer, the conducting element (153) being formed in a layer in which the gate of one transistor (210a; 217a; 310a) of the first pair and the gate of one transistor of the second pair are formed.;

Description

BACKGROUND

[0001] The present disclosure relates to a microelectronic unit for integrated circuits and a method for its manufacture.

[0002] Integrated circuits typically contain several adjacent layers that are deposited and structured sequentially. Power supply traces are provided to supply current to the cells of the integrated circuit. These cells can be static random access memory (SRAM) cells for storing data and logic cells for executing combinational logic functions, for example, using NAND gates and NOR gates. Signal lines are provided for transmitting data, such as the result of a Boolean operation or data to be stored in a cell (e.g., an SRAM cell). The cells of the integrated circuit contain field-effect transistors (FETs), each comprising a drain region, a source region, and a gate region.Typically, FETs are implemented in the lowest layers of the integrated circuit. The layers containing the signal lines and power supply traces are provided in the layers above the FETs.

[0003] Vertical interconnect access contacts (VIAs) are provided to connect the drain, source, and gate regions of the FETs to the signal lines and power supply tracks. Each VIA establishes contact between surface-mount capacitors and resistors and the corresponding regions of the FETs, signal lines, and power supply rails. Furthermore, each VIA occupies a portion of the surface area required to fabricate the integrated circuit. Therefore, there may be a need to reduce the number of VIAs required to manufacture an integrated circuit.

[0004] Furthermore, the individual VIAs may require alignment with the source areas and gates of the FETs, as well as the signal lines and power supply traces. There may also be a need to facilitate the fabrication of vertical structures for connecting conductors that extend across different layers of the integrated circuit.

[0005] US Patent 9,653,457 B2 describes stacked components and circuits formed by stacked components. According to some embodiments, a semiconductor post extends vertically from a substrate. A first source / drain region is located within the semiconductor post. A first gate electrode layer surrounds the semiconductor post laterally and is located vertically above the first source / drain region. A first gate dielectric layer is located between the first gate electrode layer and the semiconductor post. A second source / drain region is located within the semiconductor post and vertically above the first gate electrode layer. The second source / drain region is connected to a power supply node. A second gate electrode layer surrounds the semiconductor post laterally and is located vertically above the second source / drain region.A second gate dielectric layer is positioned between the second gate electrode layer and the semiconductor post. A third source / drain region is located within the semiconductor post and lies vertically above the second gate electrode layer.

[0006] JP 2007-250 652 A demonstrates the provision of an energy-saving fluid dryer that can be started efficiently. In the fluid dryer, a partition wall, which separates a predetermined area from one feed opening side of a drying chamber from another area, is erected on a distribution plate, and gas for drying can be supplied individually to each area separated by the partition wall.

[0007] US 2018 / 0122793A1 provides a circuit comprising an SRAM cell with a set of vertical nanowire transistor columns. Each element of the set comprises one vertical nanowire transistor, and at least one element of the set is a vertical nanowire transistor column comprising two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, with a first column comprising two n-type vertical nanowire transistors, a second column comprising two n-type vertical nanowire transistors, a third column comprising one p-type vertical nanowire transistor, and a fourth column comprising one p-type vertical nanowire transistor. EDA tools for such circuits are also provided. SUMMARY

[0008] The following description also includes embodiments and examples that do not exhibit all the features of the subject matter defined in claim 1. Such embodiments serve solely for technical explanation and are not part of the claimed subject matter.

[0009] The invention relates to an object having the features of claim 1 and a method having the features of claim 5.

[0010] By providing a microelectronic unit and the method according to the independent claims, alternatives to the prior art are provided. Advantageous embodiments are described in the dependent claims.

[0011] Further features disclosed in the description are described below using exemplary embodiments:

[0012] According to one embodiment, an integrated circuit is provided which contains several adjacent layers, wherein the integrated circuit contains a plurality of vertical structures, the vertical structures extending in a vertical direction that is substantially perpendicular to the layers of the integrated circuit, wherein the vertical structures include at least one vertical connecting element and at least one vertical channel region, and wherein the vertical structures are arranged above nodes of a regular virtual two-dimensional grid. There may be nodes of the grid above which no vertical structure is provided. The regularity of the grid facilitates the fabrication of the integrated circuit.

[0013] According to one embodiment, an integrated circuit is provided. The integrated circuit contains several adjacent layers, each containing a stack of one or more field-effect transistors (FETs) (e.g., a first FET and a second FET). The FETs each contain a channel region. The channel regions of the FETs in the stack are electrically connected in series. The stack extends in a vertical direction that is substantially perpendicular to the layers (e.g., layers of the integrated circuit). The first FET and the second FET are of the same type.

[0014] According to one embodiment, the two opposite ends of the stack correspond to a power supply end and a signal end. The power supply end is connected to a power supply trace of the integrated circuit. The signal end is connected to signal lines of the integrated circuit.

[0015] According to one embodiment, the FETs of the stack are of the same type, wherein the channel regions of the FET of the stack are electrically connected in series, wherein the two opposite ends of the stack correspond to a power supply terminal end and a signal end, and wherein the power supply terminal end is connected to a power supply trace of the integrated circuit.

[0016] According to one embodiment, different cell types (i.e., cells for performing Boolean operations or for storing data) require two FETs of the same type connected in series. Stacking two FETs extending in a vertical direction simplifies wiring connections and trace routing within and between the functional cells. This allows for a higher cell density within the integrated circuit.

[0017] According to one embodiment, the power supply track can be provided as a hidden conductive layer in a substrate of the integrated circuit. In particular, the power supply track can be formed as a heavily doped semiconductor region. The heavily doped semiconductor region can be formed by an ion implantation process. Alternatively, the heavily doped semiconductor region can be formed by a diffusion process. The low-resistance power supply track can be formed by various process options (e.g., combined methods).

[0018] According to one embodiment, the channel areas of the FETs of the stack are provided in layers between the layer comprising the power supply track of the integrated circuit and layers comprising signal lines of the integrated circuit.

[0019] By separating the layer(s) containing signal lines from the layer(s) containing the power supply traces, the complexity of the conductor routing in the integrated circuit can be significantly reduced. In particular, the number of via contacts and the conductor lengths can be reduced. This can result in a higher unit density of the integrated circuit and / or reduced power consumption.

[0020] According to one embodiment, the stack can be formed by epitaxy on the heavily doped semiconductor region that forms the power supply pathway. The dopant concentration can be varied during epitaxy.

[0021] According to a non-inventive embodiment, the channel regions of the FETs in the stack are horizontal channels in which charge carriers move in a direction parallel to the layers of the integrated circuit when the FETs are in a conducting state. The stack can contain two conventional planar FETs arranged one above the other, with the source region of one of the conventional planar FETs electrically connected to the drain region of the other. Alternatively, the stack can contain two FinFETs connected in series via a source-drain connection. The fins of the FinFETs can be arranged parallel or perpendicular to each other.

[0022] According to one embodiment, the first FET and / or the second FET contain more than one vertical channel region. By providing more than one vertical channel, the FET can be more easily adapted to different electrical requirements. The vertical channel regions can have substantially the same dimensions to improve process stability during the fabrication of the integrated circuit. "Substantially the same dimensions" can refer to dimensions that vary solely due to unavoidable variations during the manufacturing of the integrated circuit. The characteristics of a FET in the integrated circuit can be tuned by selecting the number of vertical channel regions. For example, one FET can contain twice as many vertical channel regions as another if it is required to deliver twice the current. In this way, the dimensions of the FETs can be quantized.

[0023] According to one embodiment, the vertical channel region has a cross-section with a longitudinal axis and a transverse axis, wherein the longitudinal axis and the transverse axis are of substantially the same length. For example, the vertical channel region can have a circular cross-section. A circular cross-section can result from exposure errors at the corners of the square when using a mask with square features. According to one embodiment, the vertical channel region can have a hexagonal cross-section. For example, the vertical channel region can be formed using a semiconductor with a hexagonal crystal structure. According to another embodiment, the vertical channel region can also have a triangular cross-section. The triangle can be an equilateral triangle.Using a vertical channel area with a cross-section whose longitudinal axis and transverse axis are essentially the same length can lead to FETs with a particularly narrow channel.

[0024] According to one embodiment, the vertical channel region can be formed by epitaxial growth in a direction perpendicular to the layers. Epitaxial growth allows the length (e.g., vertical length) of the vertical channel region to be precisely defined. In particular, the lengths of vertical channel regions of different FETs provided in the same layer of the integrated circuit can be formed such that they are essentially the same. Variations in channel lengths caused by structuring processes, for example, using extreme ultraviolet (EUV) lithography, can be avoided.

[0025] According to one embodiment, the longitudinal axis is longer than the transverse axis. For example, the vertical channel section can have a rectangular or elliptical cross-section. Vertical channel sections with an elongated cross-section, whose longitudinal axis is longer and whose transverse axis is shorter, or vice versa, allow for a wider channel for a given cross-sectional area.

[0026] According to one embodiment, the longitudinal axis of the elongated cross-section is essentially perpendicular to a longitudinal direction of the power supply path. Such an arrangement allows for the optimization of the use of the area above the power supply path while simultaneously providing narrow quantized channels.

[0027] According to one embodiment, the stack includes a common nanowire. The nanowire contains the channel regions of the multiple FETs. A region positioned between the channel region of the first FET and the channel region of the second FET can simultaneously form the source / drain region of the first FET and the drain / source region of the second FET.

[0028] According to one embodiment, the first FET and / or the second FET is a gate-all-around FET. By providing a gate-all-around configuration for the channel region of the first / second FET, the electrical properties of the FET can be improved. Interface effects at the interfaces of the gate extending parallel to the channel region can be avoided.

[0029] According to one embodiment, the integrated circuit includes a second stack of two FETs. The two FETs of the second stack are of the same type. The two FETs of the second stack are of a different type than the first and second FETs. One power supply terminal of the second stack is connected to a different power supply track.

[0030] According to one embodiment, the integrated circuit includes an SRAM cell. The SRAM cell contains a memory element and an access FET. The memory element includes a first inverter, which has a first inverter FET connected to a power supply track. The first inverter FET is the first FET in the stack. The access FET is the second FET in the stack. The access FET is electrically connected to a bit line.

[0031] According to one embodiment, the proposed SRAM cell can require fewer vias than a conventional SRAM cell. Therefore, the proposed SRAM cell can have a smaller footprint, and the density of SRAM cells in the integrated circuit can be increased. Furthermore, the traces connecting the elements of the proposed SRAM cell can be shorter, thus reducing the power consumption of the integrated circuit due to trace capacitance. The bit line can be considered the signal line of the integrated circuit.

[0032] According to one embodiment, the integrated circuit contains two mirror-symmetric SRAM cells. By providing mirror-symmetric SRAM cells, an increased SRAM cell density can be achieved in the integrated circuit.

[0033] According to one embodiment, the mirror-symmetrical SRAM cells can use the same power supply track. By having the mirror-symmetrical SRAM cells use the same power supply track, a wider power supply track can be provided. This results in fewer voltage fluctuations along the power supply track.

[0034] According to one embodiment, the integrated circuit includes a logic cell. The logic cell contains the stack and a second pair of FETs. The second pair of FETs is of a different type than the first and second FETs. The two FETs of the second pair are electrically connected in parallel. The two FETs of the second pair form different vertical structures than the stack.

[0035] In one embodiment, a gate of one FET in the stack and a gate of a FET in the second pair are connected and correspond to a first input of the logic cell. The gate of the FET in the stack and the gate of the FET in the second pair extend in the same layer within the layer structure of the integrated circuit. In another embodiment, the gate of the FET in the stack and the gate of the FET in the second pair can be formed from a single component.

[0036] In one embodiment, the gate of one FET in the stack and the gate of one FET in the second pair are connected and correspond to a second input of the logic cell. The gate of one FET in the stack and the gate of one FET in the second pair extend across different layers of the integrated circuit's layered structure.

[0037] According to one embodiment, the power supply traces extend in at least one layer located at a first end of the stack and / or vertical structure. Signal connection conductors extend in a layer located at a second, opposite end of the stack or vertical structure.

[0038] According to one embodiment, the logic cell is a NAND gate or a NOR gate.

[0039] According to one embodiment, the integrated circuit contains more than one cell selected from the group of SRAM cells and logic cells described herein, wherein the selected cells share at least one power supply track.

[0040] According to one embodiment, the selected cells jointly use the VDD power supply track or the ground power supply track and use a different power supply track for the further voltage.

[0041] According to one embodiment, the selected cells share both power supply pathways.

[0042] According to one embodiment, there can be nodes of the grid where no vertical structure is provided. The uniformity of the grid can facilitate the fabrication of the integrated circuit.

[0043] According to one embodiment, the longitudinal distance between two nodes of the grid in a longitudinal direction is equal to the transverse distance between two nodes of the grid in a transverse direction, wherein the longitudinal direction is perpendicular to the transverse direction. In particular, the grid can correspond to a checkerboard pattern.

[0044] According to one embodiment, the longitudinal distance between two nodes of the grid differs from the transverse distance between two nodes in a transverse direction, with the longitudinal direction being perpendicular to the transverse direction. This allows for better isolation between two power supply lines for providing different voltages when the power supply lines extend along a longitudinal or transverse direction of the grid. In particular, the different longitudinal and transverse distances can reduce the magnitude of leakage currents and / or unintended capacitances.

[0045] According to one embodiment, the grid has a hexagonal pattern. A hexagonal pattern allows for a particularly high density of the vertical structures.

[0046] One embodiment may include a microelectronic unit. The microelectronic unit may contain a first pair of transistors stacked vertically and connected in series. Both transistors of the first pair are of the same type. The microelectronic unit may also contain a second pair of transistors connected in parallel. The type of the second pair of transistors differs from that of the first pair. The first and second pairs of transistors are arranged substantially perpendicular to the majority of the layers.

[0047] One embodiment may include a microelectronic unit. The microelectronic unit may contain a first pair of transistors stacked vertically and connected in series. Both transistors of the first pair are of the same type. The microelectronic unit may contain a second pair of transistors connected in parallel. The type of the second pair of transistors differs from that of the first pair. The first and second pairs of transistors are arranged substantially perpendicular to the majority of the layers. A gate of one transistor of the first pair and a gate of one transistor of the second pair are connected together and correspond to a first input of the microelectronic unit.The gate of one transistor of the first pair of transistors and the gate of one transistor of the second pair of transistors are located in the same layer of the microelectronic unit. A gate of one transistor of the first pair of transistors and a gate of one transistor of the second pair of transistors are connected together and correspond to a second input of the microelectronic unit. The gate of one transistor of the first pair of transistors and the gate of one transistor of the second pair of transistors are located in different layers of the microelectronic unit.

[0048] One embodiment may include a method for forming a microelectronic unit. The method may include forming a first pair of transistors that are vertically stacked and connected in series. Both transistors of the first pair are of the same type. The method may include forming a second pair of transistors that are connected in parallel. The type of the second pair of transistors is different from that of the first pair of transistors. The first pair of transistors and the second pair of transistors are formed substantially perpendicular to the majority of the layers.

[0049] One embodiment may include a method for forming a microelectronic unit. The method may include forming a first pair of transistors that are vertically stacked and connected in series. Both transistors of the first pair are of the same type. The method may include forming a second pair of transistors that are connected in parallel. The type of the second pair of transistors is different from that of the first pair. The first pair of transistors and the second pair of transistors are formed substantially perpendicular to the majority of the layers. A gate of a transistor of the first pair of transistors and a gate of a transistor of the second pair of transistors are connected together and correspond to a first input of the microelectronic unit.The gate of one transistor from the first pair of transistors and the gate of one transistor from the second pair of transistors are located in the same layer of the microelectronic unit. The gate of one transistor from the first pair of transistors and the gate of one transistor from the second pair of transistors are connected and correspond to a second input of the microelectronic unit. The gate of one transistor from the first pair of transistors and the gate of one transistor from the second pair of transistors are located in different layers of the microelectronic unit.

[0050] In particular, a method for fabricating an integrated circuit is provided, which has several adjacent layers with any one of the features mentioned above. Regarding the advantageous effects of the proposed method, reference is made to the description of the embodiment of the integrated circuit described in this disclosure.

[0051] Additional features and benefits are achieved through the techniques disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The above, as well as other tasks, features and advantages of the disclosure, will become clear from the following detailed description in conjunction with the accompanying drawings, wherein: the Fig. 1a to 6a show circuit diagrams with elements of a NAND gate; the Fig. 1b to 6b the physical structure of the in the Fig. The elements shown in 1a to 6a are shown; Fig. 7a shows a circuit diagram of a balanced NAND gate; Fig. 7b the physical structure of the balanced NAND gate of Fig. 7a shows; Fig. 7c shows vertical structures of nodes of a grid; Fig. 7d the grid of Fig. 7c illustrated in more detail; the Fig. Sections 8a to 13a show circuit diagrams with elements of a NOR gate; the Fig. 8b to 13b the physical structure of the in the Fig. The elements shown in sections 8a to 13a are shown; the Fig. Figures 14a to 20a show circuit diagrams with elements of an SRAM cell that does not have all the essential features of the invention; the Fig. 14b to 20b the physical structure of the in the Fig. The elements shown in sections 14a to 20a are shown; the Fig. 21 to Fig. 22 show the physical structure of a first array of SRAM cells; Fig. 23 shows the physical structure of a second array of SRAM cells, which does not have all the features essential to the invention; Fig. 24 shows the physical structure of a third array of SRAM cells, which does not have all the features essential to the invention; Fig. 25 vertical structures of nodes of a grid are shown; and Fig. Shows 26 nodes of another grid. DETAILED DESCRIPTION

[0053] Details of generally known features and techniques may be omitted from the description in order to avoid unnecessarily obscuring the presented embodiments.

[0054] References in the description to "a particular embodiment," "an embodiment," "an exemplary embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or property, but that not every embodiment necessarily includes that particular feature, structure, or property. Furthermore, such expressions do not necessarily refer to one and the same embodiment. When a particular feature, structure, or property is described in connection with an embodiment, it is also assumed that the person skilled in the art, based on their knowledge, would apply such a feature, structure, or property in connection with other embodiments, even if this is not explicitly stated.

[0055] For the purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "above," "below," and their derivatives shall refer to the disclosed structures and methods as depicted in the figures. The terms "overlying," "above," "on top," "arranged on," or "arranged above" mean that a first element, for example, a first structure, is located on top of a second element, for example, a second structure, with intermediate elements, for example, an intermediate structure, potentially located between the first and second elements. The term "direct contact" means that a first element, for example, a first structure, and a second element, for example, a second structure, are connected to each other at the interface between the two elements without any intervening conductive, insulating, or semiconductor layers.

[0056] In order to avoid obscuring the representation of embodiments of the present disclosure, certain process steps or operations known in the art may be combined for illustrative purposes in the following detailed description and may not be described in detail in some cases. In other cases, some process steps or operations known in the art may not be described at all. It should be clear that the following description focuses primarily on the individual features or elements of different embodiments of the present disclosure. Although some components of the structure may be mentioned in the singular in this description, it should be noted that more than one component may be shown in the figures.

[0057] The terms “essentially”, “essentially similar”, “approximately”, or any other terms used to denote functionally equivalent correspondences apply to cases where the difference in length, height, or orientation does not represent a practical difference between the exact specification (e.g., the expression without the essentially similar expression) and the essentially similar deviations. According to one embodiment, the term “essentially” (and its derivatives) denotes a difference due to a generally accepted machining or manufacturing tolerance for similar units, for example, up to 10% deviation from the value or up to 10° angular deviation.

[0058] In the semiconductor industry, lithographic limitations can pose a problem when miniaturizing integrated circuits. Potential issues include the impact of power supply system resistance on performance, reliability due to electromigration at lower layers, reduced trace connectivity due to trace resources being allocated to power and ground lines, and lithographic problems resulting from uneven traces.

[0059] One solution to the limitations of lithography is to miniaturize circuits and build the units in a vertical dimension (i.e., in a third dimension). To miniaturize circuits, contact layers can be embedded below (i.e., opposite the conductor stack) the active area, providing power and ground connections. For example, ground (GND) is located below the area of ​​an n-channel FET (nFET), and voltage source (VSS) is located below the area of ​​a p-channel FET (pFET). An advantage can be gained by supplying the power and ground connections from opposite ends of the conductor stack.Potential advantages include optimized density, lack of electromigration, more space for signal lines, unrestricted access to signal pins, provision of uniform spacing on lower metal and via (VIA) layers, and fewer vias.

[0060] An additional advantage is that interference between the signal lines and the power supply traces of the integrated circuit is avoided. This can lead to greater flexibility in the arrangement of the logic cells of the integrated circuit.

[0061] The Fig. Figures 1a to 6a show elements in the circuit diagram of a NAND gate, and the Fig. Figures 1b to 6b show the corresponding elements of a physical structure of an integrated circuit 100, which contains several adjacent layers. For better understanding, the integrated circuit 100 is shown with an increasing number of elements, and in some of the figures, some elements are hidden behind other elements (i.e., they can be seen from other angles that are not necessarily shown in every figure). Fig. 1a to 6a correspond to the following in terms of the electrical circuit diagrams: Fig. 1b to 6b. The following description refers primarily to those in the Fig. The physical structure shown in 1b to 6b is referenced.

[0062] According to the Fig. In 1a / b, the integrated circuit 100 contains a stack 110 consisting of a first field-effect transistor (FET) 110a and a second FET 110b. Both FETs 110a and 110b each contain a channel region. The channel region of the first FET 110a is covered by a gate dielectric 112 and a gate 113. The channel regions of the FETs 110a and 110b of the stack 110 are electrically connected in series. The stack 110 extends in a direction V that is substantially perpendicular to the layers of the integrated circuit 100. The two FETs 110a and 110b and the stack are of the same type. For example, both FETs in stack 110 can be n-channel FETs (nFETs) or both FETs in stack 110 can be p-channel FETs (pFETs). The two opposite ends of stack 110 containing FETs 110a and 110b correspond to a power supply terminal 111 and a signal terminal 114, respectively.

[0063] The terms “essentially”, “essentially similar”, “approximately”, or any other terms used to denote functionally equivalent correspondences apply to cases where the difference in length, height, or orientation does not represent a practical difference between the exact specification (e.g., the expression without the essentially similar expression) and the essentially similar deviations. According to one embodiment, the term “essentially” (and its derivatives) denotes a difference due to a generally accepted machining or manufacturing tolerance for similar units, for example, up to 10% deviation from the value or up to 10° angular deviation.

[0064] The channel regions of stack 110 (i.e., the channel regions of the first FET 110a and the second FET 110b) can be vertical channel regions. Vertical channel regions can be those in which charge carriers in a conducting state of the first FET 110a and / or the second FET 110b move in a direction substantially perpendicular to the layers of the integrated circuit 100.

[0065] The first FET 110a and the second FET 110b can contain more than one vertical channel region. In the Fig. In the embodiment shown in Figure 1b, the stack 110 is shown as a single column with a circular cross-section. However, the stack 110 can contain a bundle of vertical columns, the channel regions each being covered by a gate dielectric and the gate dielectrics being surrounded by a common gate.

[0066] Cross-sections of vertical channel areas can have a longitudinal axis C Land a transverse axis C T have. In Fig. 1b shows that the longitudinal axis C L and the transverse axis C T have essentially the same length. In the Fig. In the embodiment shown in 1b, the cross-sections are approximately circular. Further cross-sections with a longitudinal axis C L and a transverse axis C T They can have square, hexagonal and / or triangular cross-sections of approximately the same length.

[0067] Alternatively, vertical channel sections can have an elongated cross-section, with the longitudinal axis C L longer than the transverse axis C T For example, the cross-section can have a rectangular or elliptical shape.

[0068] Stack 110 can contain a common nanowire, where the common nanowire contains the channel regions of FETs 110a and 110b. However, stack 110 can have a shape other than that of a nanowire.

[0069] During a Fig. In the embodiment shown in Figure 1b, both the first FET 110a and the second FET 110b are gate-all-around FETs. The gates of FETs 110a and 110b completely surround the channel regions of FETs 110a and 110b. This improves the electrical properties of FETs 110a and 110b.

[0070] Furthermore, the integrated circuit 100 contains a second pair of FETs 115 and 116, which can be configured as vertical structures distinct from the stack 110. FET 115 can also be configured as a vertical structure that differs from that of FET 116. Thus, the stack 110, FET 115, and FET 116 can form three distinct columns extending in the direction V. The lower ends of FETs 115 and 116 can be considered the power supply terminals.

[0071] In the Fig. Figures 1a to 1b show that the gate 113 of the first FET 110a and the gate of the FET 116 can be provided in the same layer of the integrated circuit 100.

[0072] According to the Fig. In 2a / 2b, the gate 113 of the first FET and the gate of FET 116 can be electrically connected to a conductive element 153. The conductive element 153 can be provided in the same layer as the gate 113 of the first FET 110a and the gate of FET 116. Specifically, the gate 113 of the first FET 110a, the conductive element 153, and the gate of FET 116 can be formed from a single piece of the same material. Alternatively, the gate 113 of the first FET 110a and the gate of FET 116 can be formed from different materials. For example, the material of the gate of the first FET 110a and the gate of FET 116 can be chosen such that a specific threshold voltage of the first FET 110a and FET 116 is achieved. The material of the conductive element 153 can be chosen to have a particularly low resistance.

[0073] According to the Fig. In 3a / 3b, the gate of FET 115 can be connected to the gate of the second FET 110b by conductive elements 151 and 152. Therefore, the integrated circuit 100 can contain a conductive element 151 located in the same layer as the gate of the second FET 110b. The conductive element 151 and the gate of the second FET 110b can be formed as a single unit. This simplifies the fabrication of the integrated circuit 100. They can also be formed from different materials, as explained above with respect to the gate 113 and the conductive element 153. Another conductive element 152 can be provided in the same layer as the gate of FET 115. This layer can correspond to the layer in which the gate 113 of the first FET 110a, the gate of FET 116, and the conductive element 153 are formed. The gate of FET 115 and the conducting element 152 can be formed from a single piece.They can also be made of different materials, as explained above with regard to gate 113 and conductive element 153. The vertical conductive element 142 can electrically connect conductive element 151 to conductive element 152.

[0074] In this description, the vertical conductive elements of the integrated circuits can be made of a metal. Metals can have particularly high conductivity. Furthermore, metals can facilitate heat dissipation within the integrated circuit, thus preventing localized overheating. Alternatively, the vertical conductive elements of the integrated circuit can be made of a semiconductor material. These elements can be made of the same semiconductor material as a source region, channel region, or drain region of a FET within the integrated circuit. Using the same semiconductor material for both the vertical conductive elements and the FETs prevents contamination of the FETs with materials that could degrade their electrical properties.Furthermore, it would be possible to use the same process for forming the vertical conductive elements and the vertical channel regions of the FETs. The physical dimensions (e.g., cross-section, width, length, or height) of the vertical conductive elements and the FETs can be identical. Structuring during the fabrication of the integrated circuit can be simplified by reducing the number of features with differing dimensions.

[0075] According to the Fig. 4a / 4b The integrated circuit 100 can contain an internal connecting element 160 for connecting the FET 115 and the FET 116. The internal connecting element 160 can extend within a single layer of the integrated circuit 100. Charge carriers can move within the internal connecting element 160 substantially parallel to the layers of the integrated circuit 100. The internal connecting element 160 electrically connects the top ends of the FETs 115 and 116.

[0076] The internal interconnects of the integrated circuits disclosed in this description can be made of a metal. Alternatively, the internal interconnects of the integrated circuit can be made of a semiconductor material. In particular, the internal interconnects of the integrated circuit can be made of the same semiconductor material as the source and / or drain regions of the FETs of the integrated circuit. This avoids contact resistances between the source and / or drain regions of the FETs of the integrated circuit and the internal interconnects.

[0077] The integrated circuit 100 contains a vertical conductive element 143 and may contain a vertical conductive element 144. The vertical conductive element 143 may be electrically connected to the conductive element 153. The vertical conductive element 143 may extend upwards from the conductive element 153. The vertical conductive element 144 may be electrically connected to the inner connecting element 160. The vertical conductive element 144 may extend upwards from the inner connecting element 160.

[0078] According to the Fig. 5a / 5b the vertical conductive element 143 can be electrically connected to a first input 171 of the integrated circuit 100. Thus, a gate of the FET 110a ( Fig. 1 to Fig. 2) of the stack 110 ( Fig. 1 to Fig. 2) and a gate of FET 116 ( Fig. 1, Fig. 2 to Fig. 3) connected to each other and can correspond to a first input 171 of the integrated circuit 100.

[0079] Furthermore, the gate of FET 110b extends ( Fig. 1 to Fig. 2) and the gate of FET 115 ( Fig. 1 to Fig. 2) in different layers in the integrated circuit 100. The gate of the second FET 110b and the gate of the FET 115 are connected to each other via the conductive element 151, the vertical conductive element 142 and the conductive element 152, and also via another vertical conductive element 141 ( Fig. 4) connected to a second input 172 of the integrated circuit 100. One end of the stack 110 can correspond to a signal end 114. The signal end 114 of the stack 110 can be connected to an output 181 of the integrated circuit 100. Through the vertical conductive element 144 ( Fig. 4) can an electrical connection be made from the inner connecting element 160 ( Fig. 4) to the output 181 of the integrated circuit 100.

[0080] According to the Fig. 6a / 6b, the power supply connection end 111 of the stack 110 can be connected to a power supply track 191 of the integrated circuit 100. Both a power supply connection end of the FET 115 ( Fig. 1 to Fig. 2) as well as a power supply connection end of the FET 116 ( Fig. 1 to Fig. 2) can be connected to another power supply line 192. Power supply line 191 and power supply line 192 can be provided parallel to each other.

[0081] The electrically interconnected elements of the integrated circuit 100 can be considered a logic cell, in particular a NAND gate 100 with inputs 171 and 172 and an output 181. The inputs 171 and 172 and the output 181 can be considered signal lines of the integrated circuit. Above the input and output layers shown, there may be further local and global conductor connection layers.

[0082] In the integrated circuit 100 (i.e., in the Fig. Figures 1b to 6b) show that the channel regions of the FETs 110a, 110b, 115, 116 of the integrated circuit 100 can be located between a layer containing the signal lines 171, 172, 181 and a layer containing the power supply lines 191, 192. This avoids interference between the signal lines and the power supply lines. In this way, greater flexibility is possible when arranging the logic cells of the integrated circuit.

[0083] By using FETs with vertical channel regions to form the integrated circuit of the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. 6. The need for additional vertical connecting elements can be reduced, since some electrical connections between the different layers of the integrated circuit are already provided by the vertical channel areas.

[0084] Power supply track 191 can provide a ground voltage GND, and power supply track 192 can provide a voltage VDD above GND for operating the integrated circuit 100. FETs 110a and 110b of stack 110 can be nFETs, and FETs 115 and 116 can be pFETs.

[0085] The FETs of the disclosed integrated circuits can be arranged at regular intervals along the longitudinal direction of the power supply traces. The spacing between the FETs along the longitudinal direction of the power supply traces and the spacing between the FETs in a direction perpendicular to the longitudinal direction of the power supply traces can be equal. Such a regular arrangement of the FETs enables reliable fabrication of the integrated circuit. Furthermore, a regular arrangement of FETs can optimize the FET density of the integrated circuit.

[0086] The Fig. Figures 7a to 7d show an integrated circuit 200, which corresponds to the integrated circuit 100 described above. Fig. Figure 7a is a circuit diagram of a balanced NAND gate, Fig. Figure 7b shows the physical structure of the balanced NAND gate. Fig. Figure 7c shows vertical structures on nodes of a grid, and Fig. 7d explained Fig. 7c closer.

[0087] According to the Fig. 7a, Fig. 7b contains an integrated circuit 200 comprising several adjacent layers according to an embodiment of the present invention. The integrated circuit 200 corresponds to the integrated circuit 100 described above. In addition to a stack 210 containing a first FET 210a and a second FET 210b, corresponding to the first stack 110 of the integrated circuit 100, the integrated circuit 200 contains a further stack 217 containing a third FET 217a and a fourth FET 217b.

[0088] Power supply terminals 211 and 218 of the two stacks 210 and 217 can be connected to a power supply track 291. Signal terminals 214 and 219 of the two stacks 210 and 217 can be connected to an output 281 of the integrated circuit 200. Furthermore, the gate of the first FET 210a, the gate of the third FET 217a, and a connecting element 253 can extend in the same layer of the integrated circuit. In particular, the gate of the first FET 210a, the gate of the third FET 217a, and the connecting element 253 can be formed as a single unit. The gate of the second FET 210b and the gate of the fourth FET 217b, together with a connecting element 251, can also extend in a single layer.

[0089] The resistance of a stack of two FETs can be greater than the resistance of a vertical structure that may contain only a single FET. Therefore, by providing an additional stack 217 connected in parallel to the stack 211, an integrated circuit 200 with better balanced characteristics compared to the integrated circuit 100 can be created. In particular, the impedance at the output 281 of the integrated circuit 200 can be lower, depending on the voltage supplied at the output 281 of the integrated circuit 200.

[0090] The Fig. 7c and Fig. Figure 7d illustrates that the vertical structures of the integrated circuit 200, in particular the vertical structures 241, 210, 217 of the integrated circuit 200, are arranged above node N of a regular virtual two-dimensional lattice G. The lattice G has translational symmetry. Furthermore, the lattice G has rotational symmetry, since a rotation of the lattice by 90° results in exactly the same lattice. The longitudinal spacing G L The distance between two nodes of the grid in a longitudinal direction is equal to the transverse distance G. T between two nodes of the grid in a transverse direction, with the longitudinal direction being perpendicular to the transverse direction.

[0091] The Fig. Figures 8a to 13a show elements of the circuit diagram of a NOR logic gate, and the Fig. Figures 8b to 13b show the corresponding elements of a physical structure of an integrated circuit 300, which contains several adjacent layers. The integrated circuit 300 is shown with an increasing number of elements. Fig. 8a to 13a correspond to the following in terms of the electrical circuit diagrams. Fig. 8b to 13b. The following description refers primarily to those in the Fig. Reference is made to the physical structure shown in sections 8b to 13b.

[0092] According to Fig. In 8b, the integrated circuit 300 contains a stack 310. The stack 310 contains a first field-effect transistor (FET) 310a and a second FET 310b. The first FET 310a has a channel region covered by a gate dielectric 312 and a gate 313. A channel region of the second FET 310b is electrically connected in series with the channel region of the first FET 310a. The first FET 310a and the second FET 310b are stacked one above the other in a direction V that is substantially perpendicular to the layers of the integrated circuit 300. The two FETs 310a and 310b are of the same type. For example, both FETs in stack 310 can be p-channel FETs (pFETs), or both FETs 310a and 310b can be n-channel FETs (nFETs). One end of stack 310 can be considered the power supply end 311, and the other end on the opposite side can be considered the signal end 314.

[0093] Charge carriers can move in the channel regions of the first FET 310a and the second FET 310b (i.e., in the channel regions of the stack 310) in a direction that is essentially perpendicular to the layers of the integrated circuit 300 when the channels are open (i.e., in a conducting state of the first FET 310a and the second FET 310b). Thus, the channel regions can be considered vertical channel regions.

[0094] According to Fig. Figure 8b shows the stack as a column. The cross-section of the column is a circle. According to an alternative embodiment, the stack 310 can contain several columns, each having a vertical channel region. The vertical channel regions can each be covered by a gate dielectric (e.g., a gate oxide), and the gate dielectrics can be surrounded by a common gate. Typically, the columns have the same cross-section to facilitate the fabrication of the integrated circuit. It is also conceivable that the columns have different cross-sections to allow for finer tuning of the electrical properties of the FETs.

[0095] The vertical channel sections can have cross-sections with a longitudinal axis C. L and a transverse axis C T have. The Fig. Figures 8b to 13b show that the longitudinal axis C L as long as the transverse axis C TThis can be the case with cross-sections with approximately the same longitudinal axis C. L and transverse axis C T These could be, for example, circles, squares, triangles and hexagons.

[0096] According to one embodiment, the longitudinal axis C L the cross-section of the vertical channel areas is longer than the transverse axis C T Such a cross-section can be described as an elongated cross-section. Rectangles or ellipses can be examples of elongated cross-sections.

[0097] The stack 310 can be formed from a common nanowire, wherein the common nanowire contains the channel regions of the FETs 310a and 310b of the stack. According to other embodiments, the shape of the stack 310 can be different from a nanowire.

[0098] At the gate that goes into the Fig. The FETs shown in Figures 8b to 13b, particularly the first FET 310a and the second FET 310b, may be gate-all-around FETs. The gates of these FETs are completely surrounded by the channel regions of the FETs.

[0099] According to Fig. In the integrated circuit 300, a second pair of FETs 315 and 316 is provided (8b). FET 315 and FET 316 can be formed as separate vertical structures within the integrated circuit 310. FETs 315 and 316 can each also be formed as separate vertical structures within the stack 310. A single layer of the integrated circuit 300 contains both the gate 313 of the first FET 310a and the gate of FET 316.

[0100] Fig. Figure 9b shows that a conducting element 351, which is provided in the same layer as the (in the Fig. Gate 313 of the (in the) (shown in 8a to 13a, 8b) Fig. 8a, Fig. The first FET 310a (shown in Figure 8b) and the gate of FET 316 are included, and the gate 313 of the first FET 310a and the gate of FET 316 can be electrically connected. The gate 313 of the first FET 310a, the conductive element 351, and the gate of FET 316 can be formed from a single piece.

[0101] The gate of the (in the Fig. 8a, Fig. The second FET 310b (shown in Figure 8b) is provided in a different layer of the integrated circuit 300 than the gate of FET 315. Fig. Figure 10b shows that the gate of FET 310b is electrically connected to the gate of FET 315. The electrical connection can be established by the illustrated conductive element 353, the vertical conductive element 344, and the conductive element 352. The conductive element 353 and the gate of FET 315 can be formed as a single unit. Alternatively or additionally, the gate of FET 310b and the conductive element 352 can also be formed as a single unit.

[0102] In Fig. Figure 11b shows that an internal connecting element 360 can provide an electrical connection between FET 315 and FET 316. The internal connecting element 360 is provided in a single layer of the integrated circuit 300. Electrical currents can flow in the internal connecting element essentially parallel to the layers of the integrated circuit 300. In particular, the internal connecting element 360 can connect the upper ends of FETs 315 and 316. The lower ends of FETs 315 and 316 can be considered as power supply terminals.

[0103] Fig. Figure 12b shows a vertical conductive element 343, which electrically connects the inner connecting element 360 to an output 381 of the integrated circuit 300. The output 381 is also electrically connected to the signal end 314 of the stack 310.

[0104] A vertical conductive element 341 electrically connects the conductive element 351 to an input 372 of the integrated circuit 300. Another vertical conductive element 342 provides an electrical connection between the conductive element 352 and another input 371 of the integrated circuit 300.

[0105] According to Fig. 13b the power supply terminal end of stack 310 is connected to a power supply track 392, and the power supply terminal ends of FETs 315 and 316 are connected to another power supply track 391.

[0106] Power supply track 391 can provide a ground voltage GND, and power supply track 392 can provide a voltage above GND VDD to operate the integrated circuit 300. (In the) Fig. 8a, Fig. 8b shown) FETs 310a, 310b of stack 310 may be pFETs and FETs 315 and 316 may be nFETs.

[0107] The electrically interconnected elements of the integrated circuit 300 correspond to a logic cell, in particular a NOR gate.

[0108] The physical structure of the NOR gate 300 can be mirror-symmetrical to the physical structure of the NAND gate 100, with the two power supply tracks 191 (shown in the Fig. 6a, Fig. 6b) and Fig. 391 provide a ground voltage GND, with the power supply traces 192 (shown in the Fig. 6a, Fig. 6b) and Fig. 392 provide a voltage VDD above GND and wherein the type of FETs 110a, 110b (shown in the Fig. 1 to 2a and 1 to 2b), 115 (shown in the Fig. 1a to 6a, 1b to 2b) and 116 (shown in the Fig. 1a to 5a, 1b to 5b) is opposite to the type of FETs 310a, 310b or 315, 316 respectively.

[0109] An integrated circuit can contain a sub-circuit corresponding to integrated circuit 100 and a sub-circuit corresponding to integrated circuit 300, which share power supply tracks 191 / 391 and 192 / 392. This can be an example of an integrated circuit containing several adjacent layers, wherein the integrated circuit contains a (first) stack 110 of two FETs of the same type and a second stack 310 of two FETs of the same type, which is different from the type of FETs in the (first) stack 110, wherein one power supply terminal end of the (first) stack 110 is connected to a power supply track 191 / 391 and one power supply terminal end of the second stack 310 is connected to another power supply track 192 / 392.

[0110] Starting with NAND and NOR gates, shown as examples of logic cells, several combinations of p- and n-channel stacks, as well as p- and n-channel individual units, can be constructed with p-channels above or below VDD lines and n-channels above or below GND lines. Using multiple variations of p- and n-channel stacks and units, the units can be interconnected to achieve the desired function using the connection elements shown in the NAND and NOR examples.

[0111] The Fig. Figures 14a to 20a show elements of the circuit diagram of an SRAM cell, and the Fig. Figures 14b to 20b show the corresponding elements of a physical structure of an integrated circuit 400, which contains several adjacent layers. For better understanding, the integrated circuit 300 with an increasing number of elements is shown. Fig. 14a to 20a correspond to the following in terms of the electrical circuit diagrams. Fig. 14b to 20b. The following description focuses primarily on the points in the Fig. Reference is made to the physical structure shown in sections 14b to 20b.

[0112] According to the Fig. 14b to 20b have elements of a physical structure of an integrated circuit 400, a layered structure. In particular, in the Fig. 14b to 20b elements of an SRAM 400 cell are shown. The integrated circuit 400 is equipped with one of Fig. The increasing number of elements shown is shown from 14b to 20b. Fig. 14a to 20a correspond to the following in terms of the electrical circuit diagrams. Fig. 14b to 20b. The following description focuses on the physical structure of the 400 integrated circuit, and the electrical circuit diagrams are provided mainly for a better understanding of the function of the corresponding elements.

[0113] According to Fig. Figure 14b shows that the integrated circuit 400 comprises a (first) stack 410 of a first field-effect transistor (FET) 410a and a second FET 410b. The first FET 410a and the second FET 410b each contain a channel region. The channel regions of the first FET 410a and the second FET 410b are electrically connected in series. The (first) stack 410 extends in a vertical direction V, which is substantially perpendicular to the layers. The first FET 410a and the second FET 410b of the stack 410 are of the same type. The two opposite ends of the stack 410 correspond to a power supply terminal 411 and a signal terminal 414.

[0114] The integrated circuit 400 can correspond to an SRAM cell 400. The SRAM cell 400 contains a Fig. Storage element 470 shown in 20a. The (in Fig. (20a shown) storage element 470 contains a (in Fig. (shown in Figure 20a) the first inverter 471, which contains a first inverter FET 410a. The first inverter FET 410a is the first FET 410a of the (first) stack 410 in Fig. 14b shown and with a (in the Fig. 20a, Fig. 20b connected to the power supply track 491 shown. The SRAM cell 400 also contains an access FET 410b, which is electrically connected to a (in the Fig. 20a, Fig. The bit line 481 (shown in Figure 20b) is connected. The access FET 410b is the second FET 410b of the (first) stack 410 in Fig. 14b shown.

[0115] According to Fig. In Figure 14b, the integrated circuit / SRAM cell 400 contains a second stack 415, which can contain two FETs 415a and 415b. The channel regions of the two FETs 415a and 415b are electrically connected in series. In particular, a source region of one of the two FETs 415a and 415b can correspond to a drain region of the other of the two FETs 415a and 415b. A lower end of the stack 415 can be referred to as the power supply end and an upper end of the stack 415 as the signal end of the stack 415.

[0116] The channel areas of the (first) stack 410 and the second stack 415 are divided into two layers between the layer that contains the (in the Fig. 20a, Fig. 20b) contains the power supply trace, and is provided to the layers containing signal lines, in particular bit line 481 and bit line 482 of the integrated circuit 400 of Fig. 20b. Bitline 482 can also be referred to as complementary bitline 482, since bitlines 481 and 482 were designed to transmit complementary data. By separating the layer containing the gates of FETs 410a and 415a and the layer containing the gates of FETs 410b and 415b from the layer containing the power supply traces 491 and 492 and the layer containing bitlines 481 and 482, the complexity of the trace routing in the integrated circuit 400 can be significantly reduced. In particular, fewer VIA contacts may be required to manufacture the integrated circuit, and shorter interconnects may suffice. This can increase the unit density of an integrated circuit. Furthermore, the power consumption caused by trace capacitances can be reduced.

[0117] In the canal areas of the in Fig. The stacks 410 and 415 shown in Figure 14b are vertical channel regions. In vertical channel regions, the charge carriers in a conducting state of the corresponding FETs can move in a direction that is essentially perpendicular to the layers of the integrated circuit 400.

[0118] The in Fig. The first inverter 471 shown in 20a further includes a second inverter FET 417, which contains a gate. The second inverter FET 417 is of a different type than the one shown in the Fig. (14 to 17a, 14 to 20a) the first inverter FET 410a, which contains a gate. One end of the second inverter FET 417 is connected to another power supply track 492. The second inverter 472 also contains two FETs, namely the (shown in the Fig. (shown in Figures 14 to 17a and 14 to 20b) FET 415a and FET 416. FET 416 is in Fig. 14b is hidden behind stack 410. Stack 410, stack 415, FET 417, and stack 416 can be arranged in the corners of a rectangle in plan view. In particular, stack 410, stack 415, FET 417, and FET 416 can be provided in the corners of a square.

[0119] According to Fig. In Figure 15b, the gate 413 of the first inverter FET 410a and the gate of the second inverter FET 417 are electrically connected in series by a conductive element 451, which extends in a single layer of the integrated circuit 400. In particular, the gate of the first inverter FET 410a, the gate of the second inverter FET 417, and the conductive element 451 can be formed from a single piece to facilitate the fabrication of the integrated circuit 400.

[0120] Accordingly, a conductive element 452 is provided, which connects the gate of FET 415a and the gate of FET 416. The conductive element 452 extends in a single layer of the integrated circuit 400. The gate of FET 415a, the gate of FET 416, and the conductive element 452 are also formed from a single piece.

[0121] During a session in the Fig. In the embodiment shown in Figures 14b to 20b, the first inverter FET 410a and the access FET 410b are n-channel FETs (nFETs), and the second inverter FET 417 is a p-channel FET (pFET). Accordingly, FETs 415a and 415b are nFETs, and FET 416 is a pFET. For given physical dimensions, nFETs can have higher conductivity. The use of FETs of the higher conductivity type can be particularly advantageous when the FETs are connected in series to reduce the power consumption of the integrated circuit. However, embodiments are conceivable in which the first inverter FET and the access FET are pFETs, and the second inverter FET is an n-channel FET. This can be advantageous in an integrated circuit with inverse logic.

[0122] The Fig. 16b and Fig. Figure 17b shows that the integrated circuit 400 contains an intermediate layer. The intermediate layer is located between the first gate layer, which contains the gate 413 of the first inverter FET 410a, and a second gate layer, which contains the gate of the access FET 410b. The (in Fig. (20a shown) storage element 470 contains a (in Fig. (20a shown) second inverter 472. The second inverter 472 is formed from the FET 415a and the FET 416.

[0123] The second inverter 472 is connected to the (in) by two cross-coupling conductors. Fig. The first inverter 471 (shown in 20a) is cross-coupled. Fig. 17b shows that a cross-coupling conductor (in the Fig. (shown in 16 to 20a) the conducting element and the (in the Fig. The vertical conducting element 441 (shown in Figures 16 to 20a) provides a connection between the upper end of FET 415a and the (shown in the Fig. The other cross-coupling conductor contains the conducting element 461 and a (behind the conducting element 461 in Fig. 17b hidden) further vertical conductive element 442, which connects the conductive element 461 to the conductive element 452. Thus, the two cross-coupling conductors contain a section 461, 462 that extends within the intermediate layer.

[0124] According to Fig. In section 18b, the access FET 410b contains a gate, the gate being connected to a word line 453. The gate of FET 415b can also be connected to the word line 453. The word line 453 can extend in the same layer as the gate of the access FET 410b. In particular, the word line 453 and the access FET 410a of the SRAM cell 400 can be formed as a single unit. This further reduces the complexity of manufacturing the integrated circuit 400.

[0125] Fig. Figure 19b shows that the signal ends of stacks 410 and 415 are connected to corresponding bit lines 482 and 481.

[0126] The power supply connection ends of stacks 410, 415 are according to Fig. 20b is connected to the power supply track 491 and the power supply connection ends of FETs 416 and 417 are connected to the power supply track 492.

[0127] During the Fig. In the embodiment shown in 13b to 20b, the width of the word line 453 in a direction P perpendicular to the longitudinal direction of the power supply path 491 is T only slightly smaller than the gate of the access FET 410b. In other embodiments, a wider word line 453 can be provided, which also extends above the FETs 416 and 417. The word line 453 can electrically connect the access FETs of a plurality of SRAM cells arranged in one direction P. LThe power supply lines 491 and 492 are provided along the power supply lines. Thus, the word line 453 enables parallel writing or reading of data to / from a plurality of SRAM cells. For this purpose, the word line 453 can extend parallel to the power supply line 491. A wider word line 453 allows more SRAM cells to be addressed.

[0128] The bit line 481 extends perpendicularly to the power supply line 491. The bit line 481 can connect multiple SRAM cells arranged in a direction P transverse to the longitudinal direction of the power supply line 391. L The other bit line 482 can be provided in parallel with bit line 481.

[0129] The word line 453, the bit line 481 / 482, and the power supply line 481 / 482 can be provided in different layers of the integrated circuit 400. This allows for a larger two-dimensional array of SRAM cells without the need for special bridging structures to isolate intersecting word / bit lines.

[0130] According to a study in the Fig. 21 and Fig. In the embodiment shown in Figure 22, an integrated circuit 500 with several adjacent layers can be provided, containing mirror-symmetric SRAM cells 501 and 502. The SRAM cells 501 and 502 can correspond to the SRAM cell of the integrated circuit 300. The plane of symmetry of the two mirror-symmetric SRAM cells 501 and 502 can extend perpendicular to the layers of the integrated circuit 500 and parallel to the power supply tracks 591, 592, 593. The two mirror-symmetric SRAM cells 501 and 502 can share a power supply track 591.

[0131] For example, the two mirror-symmetrical SRAM cells 501 and 502 can share the power supply track 591, which is connected to the stacks of SRAM cells 501 and 502.

[0132] Furthermore, the two mirror-symmetrical SRAM cells 501 and 502 (the SRAM cell 503 is in Fig. 21 (only partially shown) share a power supply track 593, which is connected to the second inverter FETs of the SRAM cells 501 and 503.

[0133] This allows wider power supply traces 591, 592, 593 to be used for driving the SRAM cells. This reduces voltage fluctuations during read / write operations of SRAM cells connected to a common word line. Furthermore, the spacing between the SRAM cells in the longitudinal direction P can be reduced. L the power supply lines 591, 592 running transversely in the direction of P T will be reduced.

[0134] The integrated circuit 500 contains a pair of two additional SRAM cells 504, 505. This pair of additional SRAM cells 504, 505 represents an extended version of the pair of SRAM cells 501, 502. An array of SRAM cells can be formed by providing even more SRAM cells along the power supply traces 591, 592, 593 and further providing mirror-symmetrical SRAM cells in a direction perpendicular to the power supply traces 591, 592, 593.

[0135] Fig. Figure 22 shows that word line 553 can be used to address SRAM cells 501 and 504. Similarly, word line 554 can be used to address SRAM cells 502 and 505. Word line 553 can only extend along the vertical structures containing two FETs, and not above the vertical structures containing only one FET. The SRAM cells can be read / written using bit line 581, a complementary bit line 582, a bit line 583, and a complementary bit line 584. Thus, an integrated circuit with alternating and complementary bit lines can be provided.

[0136] Fig. Figure 23 shows another integrated circuit 600, which is similar to the one in the Fig. 21 and Fig. The integrated circuit shown in Figure 22 is very similar to the 500. Features 684, 683, 682, 681, 603, 693, 604, 605, 601, 691, 602, and 692 correspond to those shown in Figure 22. Fig. 22 shown) features 584, 583, 582, 581, 503, 593, 504, 505, 501, 591, 502 and 592. However, word lines 653 and 654 differ from those (in Fig. (22 shown) word lines 553 and 554. In particular, word lines 653 and 654 extend above the vertical structures that contain only one FET. As a result of the wider word lines 653 and 654, more SRAM cells can be addressed.

[0137] Fig. Figure 24 shows a further integrated circuit 700. The integrated circuit with its features 703, 793, 704, 705, 701, 791, 702, 792 essentially corresponds to the one in Fig. The integrated circuit 500 shown in Figure 21. The SRAM cells 704 and 705 are not simply extended versions, but mirror-symmetrical versions of the SRAM cells 701 and 702. This enables a configuration in which two bit lines are followed by two complementary bit lines, which in turn are followed by two more bit lines.

[0138] Fig. Figure 25 illustrates another integrated circuit 800 containing several adjacent layers. The integrated circuit includes vertical structures extending in a vertical direction V that is essentially perpendicular to the layer of the integrated circuit. The vertical structures include a vertical connector 841, a stack 810 with two FETs, each containing a vertical channel region, and a FET also containing a vertical channel region.

[0139] The vertical structures 841, 810, 817 are arranged above node N of a regular virtual two-dimensional lattice G. The lattice G has translational symmetry. The longitudinal distance G L The distance between two nodes of the grid in a longitudinal direction is determined by the transverse distance G. T The distance G between two nodes of the grid differs in a longitudinal direction, where the longitudinal direction is perpendicular to the transverse direction. However, other embodiments may stipulate that the distance G L between two nodes in a longitudinal direction equal to the transverse distance G T between two nodes of the grid in a transverse direction.

[0140] Fig. Figure 26 shows another regular two-dimensional lattice G with nodes N, above which vertical structures can be arranged. The lattice G has a hexagonal structure.

[0141] The various elements of the integrated circuit can be embedded in an electrically insulating material. For example, the "open" spaces can be filled with a semiconductor oxide.

[0142] In the embodiments shown in the figures of the application, the power supply traces are located below and the signal lines above the channel regions of the FETs. However, a mirror-image arrangement is also conceivable, in which the signal lines are located below and the power supply traces above the channel regions of the FETs.

[0143] The integrated circuit can contain one stack of two FETs of the same type and another stack of two FETs of the same type, but different from the first stack. Specifically, one stack can be a NAND gate and the other a NOR gate. The two stacks can be arranged as vertical structures on different power supply traces.

Claims

[1] Microelectronic unit (100; 200; 300) having a plurality of layers, wherein the microelectronic unit has: a first pair of transistors (110; 210a, 210b; 217a, 217b; 310a, 310b) stacked vertically and connected in series, both transistors of the first pair being of the same type; and a second pair of transistors (116; 215, 216; 315, 316) connected in parallel, wherein the second pair of transistors is of a different type than the first pair of transistors, wherein a gate of a transistor (217a; 210a; 310a) of the first pair of transistors and gates of the second pair of transistors are arranged exclusively in the same layer of the microelectronic unit, wherein the first pair of transistors and the second pair of transistors are arranged essentially perpendicular to the majority of layers, wherein the gate of one transistor (210a; 217a; 310a) of the first pair of transistors and the gate of one transistor (116; 216; 316) of the second pair of transistors are connected to each other and correspond to a first input (171; 371) of the microelectronic unit, wherein the gate of another transistor (210b; 217b; 310b) of the first pair of transistors and the gate of another transistor (215; 315) of the second pair of transistors are connected to each other and correspond to a second input (172; 372) of the microelectronic unit, wherein the gate of the other transistor of the first pair of transistors and the gate of the other transistor of the second pair of transistors are arranged in different layers of the microelectronic unit, the microelectronic unit further comprising: power supply traces (191; 291; 391, 392) arranged in a first layer of the microelectronic unit, wherein one of the power supply traces is connected to an end of the first pair of vertically stacked transistors and another of the power supply traces is connected to power supply terminal ends of the transistors of the second pair of transistors, and a second layer in which the signal connection conductors (181; 281;381) are arranged, wherein the first pair of vertically stacked transistors and the second pair of transistors are arranged between the first layer and the second layer, wherein a vertical conducting element (143) extends from a conducting element (153) in an upward direction to the second layer, the conducting element (153) being formed in a layer in which the gate of one transistor (210a; 217a; 310a) of the first pair and the gate of one transistor of the second pair are formed.; [2] Microelectronic unit according to claim 1, further comprising: an internal connecting element (192; 360) arranged in a single layer and connecting the second pair of transistors. [3] Microelectronic unit according to any of the preceding claims, wherein the microelectronic unit is a NAND gate (100; 200) or a NOR gate (300). [4] Microelectronic unit according to one of the preceding claims, wherein the power supply tracks comprise a VDD power supply track and a ground power supply track. [5] Method for forming a microelectronic unit (100; 200; 300) having a plurality of layers, the method comprising: forming a first pair of transistors (110; 210a, 210b; 217a, 217b; 310a, 310b) stacked vertically and connected in series, wherein both transistors of the first pair are of the same type; and forming a second pair of transistors (116; 215, 216; 315, 316) connected in parallel, wherein the second pair of transistors is of a different type than the first pair of transistors, wherein a gate of one transistor (217a; 210a; 310a) of the first pair of transistors and gates of the second pair of transistors are arranged exclusively in the same layer of the microelectronic unit, wherein the first pair of transistors and the second pair of transistors are formed substantially perpendicular to the plurality of layers, wherein the gate of one transistor (210a; 217a;310a) of the first pair of transistors and a gate of a transistor (116; 216; 316) of the second pair of transistors are connected together and correspond to a first input (171; 371) of the microelectronic unit, wherein a gate of another transistor (210b; 217b; 310b) of the first pair of transistors and a gate of a transistor (215; 315) of the second pair of transistors are connected together and correspond to a second input (172; 372) of the microelectronic unit, wherein the gate of the other transistor of the first pair of transistors and the gate of the other transistor of the second pair of transistors are arranged in different layers of the microelectronic unit, the method further comprising: forming power supply traces (191; 291;391, 392), which are arranged in a first layer of the microelectronic unit, wherein one end of the first pair of vertically stacked transistors is arranged at one of the power supply traces when forming the first pair of vertically stacked transistors and power supply terminal ends of the transistors of the second pair of transistors are arranged at another of the power supply traces when forming the second pair of transistors, and forming signal interconnect conductors (181; 281;381), which are arranged in a second layer of the microelectronic unit and at an opposite end of the first pair of vertically stacked transistors, wherein the first pair of vertically stacked transistors and the second pair of transistors are arranged between the first layer and the second layer, forming a vertical conducting element (143) extending upwards from a conducting element (153) to the second layer, the conducting element (153) being formed in a layer in which the gate of one transistor (210a; 217a; 310a) of the first pair and the gate of one transistor of the second pair are formed.; [6] Method according to claim 5, further comprising: forming an inner connecting element (192; 360) arranged in a single layer and connecting the second pair of transistors together. [7] Method according to one of claims 5 or 6, wherein the microelectronic unit is a NAND gate (100; 200) or a NOR gate (300). [8] Method according to claim 5, wherein the power supply tracks comprise a VDD power supply track and a ground power supply track.

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