Multilayer ceramic capacitor with ultra-wideband performance and manufacturing process

Abstract

Multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136) and wherein the capacitor (100) comprises a top surface (18) and a bottom surface (20) opposite the top surface (18) in the Z-direction (136), wherein the multilayer broadband ceramic capacitor (100) comprises: a monolithic body comprising a multitude of dielectric layers stacked in the Z direction (136); a multitude of active electrodes (106, 108) arranged within the monolithic body; a first outer terminal (118) located along the first end (119), wherein the first outer terminal (118) comprises a bottom part (138) extending along the bottom surface (20) of the capacitor (100); a second outer terminal (120) located along the second end (121), wherein the second outer terminal (120) comprises a bottom part (140) extending along the bottom surface (20) of the capacitor (100), wherein the bottom part (138) of the first outer terminal (118) and the bottom part (140) of the second outer terminal (120) are spaced apart longitudinally (132) by a bottom-outer terminal distance (142); a lower shielding electrode (22) which is arranged within the monolithic body between the plurality of active electrodes (106, 108) and the bottom surface (20) of the capacitor (100), wherein the lower shielding electrode (22) is spaced apart from the bottom surface (20) of the capacitor by a lower shielding-bottom distance (63); where: the lower shield-ground distance (63) is in a range of about 3 µm to about 100 µm; the lower shielding electrode (22, 24) is connected to the first outer terminal (118); the lower shielding electrode (22, 24) has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the lower shielding electrode (22, 24) has a second longitudinal edge (30) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) relative to the first longitudinal edge (28); the capacitor has a length (21) in the longitudinal direction (132) between the first end (119) and the second end (121) of the capacitor and the ratio of the capacitor length (21) to the lower outer connection distance (142) is less than approximately 4.

Description

Background of the invention

[0001] The diversity of modern technical applications creates a need for efficient electronic components and the integrated circuits in which they are used. Capacitors are a fundamental component used for filtering, coupling, bypassing, and other aspects of such modern applications, which include wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many others. A dramatic increase in the speed and packing density of integrated circuits necessitates advances in coupling capacitor technology. When high-capacitance coupling capacitors are subjected to the high clock frequencies of many current applications, performance characteristics become increasingly critical. Because capacitors are fundamental to such a wide range of applications, their precision and efficiency are essential.Many specific aspects of capacitor design are therefore the focus for improving their performance characteristics.

[0002] US 2010 / 0039749A1 discloses a device and a method for the cost-effective realization of one or more secondary capacitors in a monolithic body that already contains a first, larger capacitor, in order to create ultra-wideband structures. Alternating electrode layers are provided with arm sections that enclose portions of adjacent electrode layers to generate additional coupling effects within the capacitor structure, thereby creating multiple additional equivalent capacitor structures within the device.

[0003] US 2012 / 0297596A1 discloses a method for manufacturing a ceramic multilayer component for forming a ceramic capacitor body from electrode layers and dielectric layers. A first and a second external terminal are attached to opposite ends of the ceramic capacitor body. The ceramic capacitor body is coated to increase the breakdown voltage. The electrode layers include active electrode layers that are alternately configured such that a first end of the active electrodes extends inward from one end of the ceramic capacitor body, and a next inner active electrode extends inward from an opposite end of the ceramic capacitor body. The active electrode layer includes side shields to provide additional shielding.

[0004] US 2018 / 0374646A1 discloses a multilayer ceramic coupling capacitor with low insertion loss over a broadband frequency range. The ceramic multilayer capacitor (MLCC) comprises a body with a top and bottom surface, a first and second opposite end, and an electrode and dielectric layer. The MLCC also includes a first and second terminal attached to the ends and main block layer electrodes within the body, which are alternately configured such that a first main electrode is electrically connected to the first terminal and extends inward from one end, and a next main electrode is electrically connected to the second terminal and extends inward from an opposite end. Brief description of the invention

[0005] According to the invention, a multilayer broadband ceramic capacitor is provided, having a first end and a second end spaced longitudinally from the first end. The longitudinal direction is perpendicular to a lateral direction, and the lateral direction and the longitudinal direction are each perpendicular to a Z-direction. The capacitor comprises a top face and a bottom face, the latter oriented in the Z-direction opposite to the top face. The multilayer broadband ceramic capacitor comprises a monolithic body containing a plurality of dielectric layers stacked in the Z-direction. A plurality of active electrodes is arranged within the monolithic body. A first outer terminal is located along the first end. The first outer terminal includes a bottom portion extending along the bottom face of the capacitor.A second outer terminal is located along the second end. The second outer terminal includes a base portion that extends along the bottom surface of the capacitor. The base portion of the first outer terminal and the base portion of the second outer terminal are longitudinally spaced apart by a lower-outer-terminal distance. The capacitor includes a lower shielding electrode located within the monolithic body between the plurality of active electrodes and the bottom surface of the capacitor. The lower shielding electrode is spaced from the bottom surface of the capacitor by a lower-shield-ground distance. Furthermore, the lower shielding electrode is connected to the first outer terminal, the lower shielding electrode having a first longitudinal edge that is oriented laterally and faces away from the first outer terminal.The lower shielding electrode also has a second longitudinal edge, which is oriented in the lateral direction and faces away from the first outer terminal, wherein the second longitudinal edge is offset in the longitudinal direction by a shielding electrode offset distance relative to the first longitudinal edge.

[0006] In another embodiment, the distance between the lower shield and the ground is in a range of approximately 3 µm to approximately 100 µm. In this embodiment, the capacitor has a longitudinal length between its first and second ends. The ratio of the capacitor length to the distance between the lower and outer terminals is less than approximately 4 in this embodiment.

[0007] The invention also discloses a method for forming a multilayer broadband ceramic capacitor. The capacitor has a first end and a second end, the latter being spaced from the first end in a longitudinal direction perpendicular to a lateral direction. The lateral direction and the longitudinal direction each run perpendicular to a Z-direction. The capacitor comprises a top surface and a bottom surface, the latter oriented opposite the top surface in the Z-direction.The method comprises the following: the formation of a plurality of active electrodes on a plurality of active electrode layers; the formation of a bottom shielding electrode on a shielding electrode layer; the stacking of the plurality of active electrode layers, the shielding electrode layer, and a plurality of dielectric layers to form a monolithic body; the formation of a first outer terminal at a first end of the monolithic body, the first outer terminal comprising a base portion extending along the bottom surface of the capacitor; and the formation of a second outer terminal at a second end of the monolithic body. The second outer terminal comprises a base portion extending along the bottom surface of the capacitor.The base portion of the first outer terminal and the base portion of the second outer terminal are longitudinally spaced apart by a bottom-outer terminal distance. The capacitor may include a bottom shield electrode located within the monolithic body between the plurality of active electrodes and the base of the capacitor. The bottom shield electrode is spaced from the base of the capacitor by a bottom-shield-base distance. The bottom-shield-base distance is in the range of approximately 3 µm to approximately 100 µm. The capacitor has a longitudinal length between its first end and its second end. The ratio of the capacitor length to the bottom-outer terminal distance is less than approximately 4. Brief description of the drawings

[0008] A full and instructive disclosure of the present invention, including the best way to implement it for the person skilled in the art, is set out in particular in the remainder of the description; this includes a reference to the accompanying drawings, and the following applies: Fig. 1A shows a top view of an embodiment of an active electrode layer according to aspects of the present disclosure; Fig. Figure 1B shows a perspective view of alternating electrode layers, as shown in Fig. 1A is shown to be configured according to aspects of the present disclosure; Fig. 1C shows a top view of the embodiment of the active electrode layer of Fig. 1A, in which several capacitive areas are formed according to aspects of the present revelation; Fig.Figure 1D shows a top view of the embodiment of a shielding electrode layer in which several capacitive areas are formed according to aspects of the present disclosure; Fig. Figure 1E shows a side cross-sectional view of an embodiment of a capacitor comprising several regions in which active electrode layers are configured as described in the Fig. 1A to 1C is shown, and a shielding electrode layer is configured as shown in Fig. 1C is shown, according to aspects of the present revelation; Fig. Figure 2A shows a top view of another embodiment of an active electrode layer according to aspects of the present disclosure; Fig. 2B shows a top view of the embodiment of the active electrode layer of Fig. 2A, in which several capacitive areas are formed according to aspects of the present revelation; Fig.Figure 2C shows a perspective view of alternating electrode layers, as seen in Fig. 2A is shown to be configured according to aspects of the present disclosure; Fig. 3A is a side cross-sectional view of another embodiment of a capacitor comprising multiple regions in which active electrode layers are configured as described in the Fig. 2A to 2C is shown, and a shielding electrode layer is configured as shown in Fig. 1D is shown, according to aspects of the present revelation; Fig. 3B shows another embodiment of a capacitor according to aspects of the present disclosure; Fig. Figure 4 shows a schematic representation of a circuit of the embodiment of a capacitor, which is located in the Fig. 1A to 1E is shown, with multiple capacitive areas; Fig.Figure 5 shows a schematic representation of a circuit of the embodiment of a capacitor, which is located in the Fig. 2A to 2C is shown, with several capacitive areas; Fig. Figure 6 shows a side cross-sectional view of an embodiment of a capacitor of the present invention; Fig. Figures 7A to 7D show top views of the armature electrodes, shielding electrodes, and active electrodes of the capacitor. Fig. 6 according to an embodiment of the present invention; The Fig. Figures 8A to 8D show top views of additional embodiments of active electrode layers according to certain embodiments of the present invention; Fig. 9 shows the capacitor of Fig. 1E in the second orientation; and Fig.Figure 10 shows a representative insertion loss characteristic measured for a multilayer ceramic of eight multilayer ceramic capacitors that were manufactured. Detailed description of preferred embodiments

[0009] The person skilled in the art should be aware that the present discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0010] In general terms, the present invention relates to a multilayer ceramic capacitor. The capacitor contains alternating dielectric layers and electrode layers within a single monolithic body. The capacitor comprises a first outer terminal located along a first end of the capacitor and a second outer terminal located along a second end of the capacitor. The first outer terminal comprises a base portion extending along the bottom surface of the capacitor, and the second outer terminal also comprises a base portion extending along the bottom surface of the capacitor. The base portion of the first outer terminal and the base portion of the second outer terminal are spaced apart longitudinally by a bottom-outer terminal distance.The ratio of the length of the capacitor between the first and second ends to the lower outer terminal distance can be less than about 3, in some embodiments less than about 2.75, in some embodiments less than about 2.5, in some embodiments less than about 2.25, in some embodiments less than about 2, in some embodiments less than about 1.75, in some embodiments less than about 1.5 and in some embodiments less than about 1.25.

[0011] The capacitor includes a bottom shielding electrode. The bottom shielding electrode is located between a plurality of active electrodes and the base of the capacitor. The bottom shielding-to-base distance is defined as the distance between the shielding electrodes and the base of the capacitor. If multiple shielding electrode layers are present, the bottom shielding-to-base distance can be defined as the distance between the lowest of the shielding electrode layers and the base. The bottom shielding-to-base distance is in the range of approximately 3 µm to approximately 100 µm, and in some embodiments may be from approximately 4 µm to approximately 75 µm, from approximately 5 µm to approximately 60 µm, and from approximately 8 µm to approximately 30 µm.

[0012] The inventors have discovered that such a configuration can provide a multilayer ceramic capacitor with low insertion loss over a wide frequency range. Generally, insertion loss is the power loss through the capacitor and can be measured using any method commonly known in engineering.

[0013] The shielding electrodes can be arranged within the monolithic body in a variety of configurations, which may exhibit different insertion loss characteristics. According to the invention, at least one shielding electrode is located between an active electrode region and a bottom surface of the capacitor. A dielectric region free of shielding electrodes can be located between the active electrode region and an upper surface of the capacitor, as described below, for example, with respect to Fig.1E is described. In such embodiments, the capacitor may have an insertion loss that is greater than approximately -0.5 dB from approximately 1 GHz to approximately 40 GHz, greater than approximately -0.4 dB in some embodiments, greater than approximately -0.35 dB in some embodiments, and greater than approximately -0.3 dB in some embodiments. In some embodiments, the capacitor may have an insertion loss that is greater than approximately -0.4 dB at approximately 10 GHz, greater than approximately -0.35 dB at approximately 10 GHz in some embodiments, greater than approximately -0.3 dB in some embodiments, and greater than approximately -0.25 dB at approximately 10 GHz in some embodiments. The capacitor may have an insertion loss that is greater than about -0.4 dB at about 20 GHz, greater than about -0.35 dB in some embodiments at about 20 GHz, and greater than about -0.3 dB in some embodiments at about 20 GHz.The capacitor can have an insertion loss that is greater than approximately -0.4 dB at approximately 30 GHz, greater than approximately -0.35 dB in some embodiments, greater than approximately -0.3 dB in some embodiments, and greater than approximately -0.25 dB in some embodiments. The capacitor can have an insertion loss that is greater than approximately -0.4 dB at approximately 40 GHz, greater than approximately -0.35 dB in some embodiments, greater than approximately -0.3 dB in some embodiments, and greater than approximately -0.25 dB in some embodiments.

[0014] In some embodiments, the multilayer broadband ceramic capacitor can have an insertion loss that is in the range of about -0.05 dB to about -0.4 dB from about 5 GHz to about 20 GHz, in some embodiments in the range of about -0.05 dB to about -0.3 dB from about 10 GHz to about 20 GHz, in some embodiments from about 20 GHz to about 30 GHz from about -0.05 dB to about -0.3 dB and in some embodiments from about 30 GHz to about 40 GHz from about -0.05 dB to about -0.3 dB.

[0015] According to the invention, at least one or more lower shielding electrodes are arranged between the active electrode region and the base surface of the capacitor. One or more upper shielding electrodes can be arranged between the active electrode region and the upper surface of the capacitor, as is shown below, for example, with regard to Fig.3B is described. In such embodiments, the insertion loss may be approximately -0.3 dB or more, such as approximately -0.28 dB or more, such as approximately -0.25 dB or more, such as approximately -0.23 dB or more, when measured over a frequency range from 4 GHz to 10 GHz.

[0016] In such embodiments, the insertion loss may be approximately -0.4 dB or more, such as -0.38 dB or more, such as -0.35 dB or more, such as -0.34 dB or more, when measured over a frequency range from 13 GHz to 20 GHz.

[0017] In such embodiments, the insertion loss may be approximately -0.45 dB or more, such as -0.4 dB or more, such as -0.38 dB or more, such as -0.35 dB or more, such as -0.32 dB or more, when measured over a frequency range from 23 GHz to 30 GHz.

[0018] In such embodiments, the insertion loss may be approximately -0.55 dB or more, such as -0.5 dB or more, such as -0.48 dB or more, such as -0.45 dB or more, such as -0.43 dB or more, when measured over a frequency range from 33 GHz to 40 GHz.

[0019] In some embodiments, the ratio of the capacitor thickness to the lower shield-ground distance can be greater than approximately 3, in some embodiments greater than approximately 5, in some embodiments greater than approximately 10, in some embodiments greater than approximately 15, in some embodiments greater than approximately 20, and in some embodiments greater than approximately 40. The ratio of the capacitor thickness to the lower shield-ground distance can range from approximately 10 to approximately 100, in some embodiments from approximately 20 to approximately 80, and in some embodiments from approximately 30 to approximately 50.

[0020] A top-outer terminal gap can also exist between the first outer terminal and the second outer terminal. Specifically, the first outer terminal can include a top section extending along the upper surface of the capacitor. The top section of the first outer terminal and the top section of the second outer terminal can be longitudinally spaced apart by a top-outer terminal gap. The top-outer terminal gap can be approximately equal to the bottom-outer terminal gap.In some embodiments, the ratio of the length of the capacitor between the first end and the second end of the capacitor to the top-outer terminal distance may be less than about 4, in some embodiments less than about 3.5, in some embodiments less than about 3.25, in some embodiments less than about 3, in some embodiments less than about 2.75, in some embodiments less than about 2.5, in some embodiments less than about 2.25, in some embodiments less than about 2, in some embodiments less than about 1.75, in some embodiments less than about 1.5, in some embodiments less than about 1.25 and in some embodiments less than about 1.1.

[0021] The monolithic body of the capacitor may include a dielectric material exposed between the base of the first outer terminal and the base of the second outer terminal along the base surface of the capacitor.

[0022] According to the invention, the capacitor comprises an upper shielding electrode located between the plurality of active electrodes and the upper surface of the capacitor. The upper shielding electrode can be spaced a certain distance (upper-shield-top distance) from the upper surface of the capacitor. The ratio of the upper-shield-top distance to the lower-shield-bottom distance is between approximately 0.8 and approximately 1.2, in some embodiments approximately 0.9 to approximately 1.1, in some embodiments approximately 0.95 to approximately 1.05, and in some embodiments approximately 0.98 to approximately 1.02.

[0023] The ratio of the capacitor thickness to the lower shield-ground distance can be greater than about 2, in some embodiments greater than about 3, in some embodiments greater than about 5, in some embodiments greater than about 10, in some embodiments greater than about 15, in some embodiments greater than about 20 and in some embodiments greater than about 40.

[0024] An additional lower shielding electrode can be approximately aligned with the lower shielding electrode in the Z-direction. The lower shielding electrode is connected to the first outer terminal, and the additional lower shielding electrode is connected to the second outer terminal.

[0025] The shielding electrodes can have a variety of shapes. For example, in some embodiments, the lower shielding electrode can define a step feature between two longitudinal edges. The lower shielding electrode has a first longitudinal edge and a second longitudinal edge, each oriented laterally and facing away from the first outer terminal. The second longitudinal edge is offset longitudinally from the first longitudinal edge by a shielding electrode offset distance. However, in some embodiments, one or more of the shielding electrodes can be rectangular without any step features. Furthermore, one or more of the shielding electrodes (e.g., the lower shielding electrode(s) and / or the upper shielding electrode(s)) can be symmetrical laterally about a longitudinal center line extending in the longitudinal direction.

[0026] The additional lower shielding electrode, which is connected to the second outer terminal and approximately aligned with the lower shielding electrode in the Z-direction, may also have a step feature. A first longitudinal edge is oriented laterally and faces away from the second outer terminal, and a second longitudinal edge is oriented laterally and faces away from the second outer terminal. The second longitudinal edge is offset longitudinally from the first longitudinal edge by approximately the shielding electrode offset distance.

[0027] A first shielding gap can be formed longitudinally between the first longitudinal edge of the first shielding electrode and the first longitudinal edge of the second shielding electrode. The capacitor can have a length in the longitudinal direction between its first end and its second end. The ratio of the capacitor length to the first shielding gap can be greater than approximately 2, in some embodiments greater than approximately 3, in some embodiments greater than approximately 4, in some embodiments greater than approximately 5, in some embodiments greater than approximately 10, in some embodiments greater than approximately 15, in some embodiments greater than approximately 20, and in some embodiments greater than approximately 50.

[0028] A second shielding gap can be formed longitudinally between the second longitudinal edge of the lower shielding electrode and the second longitudinal edge of the additional lower shielding electrode. The ratio of the capacitor length to the second shielding gap can be greater than approximately 2, in some embodiments greater than approximately 3, in some embodiments greater than approximately 4, in some embodiments greater than approximately 5, in some embodiments greater than approximately 10, in some embodiments greater than approximately 15, in some embodiments greater than approximately 20, and in some embodiments greater than approximately 50.

[0029] The first shielding gap distance and / or the second shielding gap distance can be in a range of about 10 µm to about 200 µm, in some embodiments from about 20 µm to about 150 µm and in some embodiments from about 30 µm to about 80 µm.

[0030] The shielding electrode offset distance can be in a range of approximately 75 µm to approximately 300 µm, in some embodiments from approximately 100 µm to approximately 250 µm and in some embodiments from approximately 125 µm to approximately 175 µm.

[0031] The multilayer broadband ceramic capacitor can have a capacitor thickness in the Z-direction between the top and bottom surfaces. The ratio of the capacitor thickness to the thickness of the upper shielding electrode region in the Z-direction can range from approximately 2.0 to approximately 20, in some embodiments from approximately 2.2 to approximately 10, in some embodiments from approximately 2.5 to approximately 7, in some embodiments from approximately 2.7 to approximately 6, and in some embodiments from approximately 3 to approximately 5. The ratio of the capacitor thickness to the thickness of the lower shielding electrode region in the Z-direction can range from approximately 2.1 to approximately 20, in some embodiments from approximately 2.2 to approximately 10, in some embodiments from approximately 2.5 to approximately 7, in some embodiments from approximately 2.7 to approximately 6, and in some embodiments from approximately 3 to approximately 5.

[0032] The ratio of the capacitor thickness to the thickness of the area of ​​the active electrodes can be in a range of about 1.1 to about 20, in some embodiments about 1.5 to about 15, in some embodiments about 1.7 to about 12, in some embodiments about 2 to about 10 and in some embodiments about 3 to about 7.

[0033] The capacitor can comprise multiple electrode regions stacked in a vertical Z-direction. These multiple electrode regions can include a dielectric region, an active electrode region, and a shielding electrode region. The active electrode region can comprise multiple active electrode layers. The shielding electrode region can include at least one shielding electrode. The active electrode region can be located in the Z-direction between the dielectric region and the shielding electrode region.

[0034] The dielectric region can extend from the active electrode region to an upper surface of the multilayer broadband ceramic capacitor. The dielectric region can be free of active electrodes and / or shielding electrodes. For example, the dielectric region can be free of electrode layers extending from one end of the capacitor over more than 25% of the capacitor's length, in some embodiments more than 20% of the capacitor's length, in some embodiments more than 15% of the capacitor's length, in some embodiments more than 10% of the capacitor's length, in some embodiments more than 5% of the capacitor's length, and in some embodiments more than 2% of the capacitor's length. For example, in some embodiments, the dielectric region can include one or more floating electrodes and / or dummy electrode tabs.In other embodiments, however, the dielectric region can be free of all electrode layers. In some embodiments, the multilayer broadband ceramic capacitor can be free of shielding electrodes above a plurality of active electrode layers in the Z-direction. In some embodiments, the multilayer broadband ceramic capacitor can be free of shielding electrodes above a bottommost electrode layer of the plurality of active electrode layers in the Z-direction.

[0035] The multilayer broadband ceramic capacitor can have a capacitor thickness in the Z-direction between the top and bottom surfaces. The dielectric region can have a thickness in the Z-direction. The ratio of the capacitor thickness to the thickness of the dielectric region can range from approximately 1.1 to approximately 20, in some embodiments from approximately 1.5 to approximately 10, and in some embodiments from approximately 1.7 to approximately 5.

[0036] Aspects of the present disclosure relate to a multilayer broadband capacitor having orientation-sensitive insertion loss characteristics. For example, in the first orientation, the capacitor may have a first insertion loss value at a test frequency greater than about 2 GHz, and a second insertion loss value in a second orientation at approximately the test frequency that differs from the first insertion loss value by at least about 0.3 dB, in some embodiments at least about 0.4 dB, and in some embodiments at least about 0.5 dB. In the second orientation, the capacitor may be rotated by 90 degrees or more about the longitudinal direction 132 relative to the first orientation. For example, in some embodiments, the capacitor in the second orientation may be rotated by 180 degrees about the longitudinal direction relative to the first orientation.In other embodiments, the capacitor in the second orientation can be rotated by 90 degrees around the longitudinal direction relative to the first orientation.

[0037] The test frequency can be in a range of approximately 10 GHz to approximately 20 GHz, in some embodiments approximately 10 GHz to approximately 30 GHz and in some embodiments approximately 10 GHz to approximately 40 GHz. I. Exemplary embodiments

[0038] If we look at the Fig. Turning to 1A-1E, an embodiment of a multilayer ceramic capacitor 100 is disclosed. Fig.Figure 1E is a simplified side view of the multilayer capacitor 100 mounted on a mounting surface 101, such as a printed circuit board or a substrate. The multilayer capacitor 100 can comprise a plurality of electrode regions 10 stacked in the Z-direction 136. The plurality of electrode regions 10 can include a dielectric region 12, an active electrode region 14, and a shielding electrode region 16. The active electrode region 14 can be located in the Z-direction 136 between the dielectric region 12 and the shielding electrode region 16. The dielectric region 12 can extend from the active electrode region 14 to an upper surface 18 of the multilayer broadband ceramic capacitor 100. The capacitor 100 can include a bottom surface 20 opposite the upper surface 18 in the Z-direction 136.

[0039] The electrode regions 10 can comprise a variety of dielectric layers. Some of these dielectric layers can include electrode layers formed on them. In general, the thickness of the dielectric and electrode layers is not restricted and can be any desired thickness depending on the performance characteristics of the capacitor. For example, the thickness of the electrode layers can be approximately 500 nm or more, such as 1 µm or more, 2 µm or more, 3 µm or more, 4 µm or more, up to approximately 10 µm or less, 5 µm or less, 4 µm or less, 3 µm or less, or 2 µm or less. For example, the electrode layers can have a thickness of approximately 1 µm to approximately 2 µm. Furthermore, in one embodiment, the thickness of the dielectric layer can be defined according to the thickness of the electrode layers mentioned above.Furthermore, it should be noted that this thickness of the dielectric layers may also apply to the layers between the active electrode layers and / or the shielding electrode layers, if they are present and as defined here.

[0040] In general, the present invention provides a multilayer capacitor with an electrode having a unique configuration which offers various benefits and advantages. In this regard, it should be understood that the materials used in the construction of the capacitor are not limited and can be any materials generally used in the art, and can be formed using any method generally used in the art.

[0041] In general, the dielectric layers are typically formed from a material that has a relatively high dielectric constant (K), such as about 10 to about 40000, in some embodiments about 50 to about 30000 and in some embodiments about 100 to about 20000.

[0042] In this respect, the dielectric material can be a ceramic. The ceramic can be provided in a variety of forms, such as a wafer (e.g., pre-fired), or as a dielectric material that is fired within the device itself.

[0043] Specific examples of materials with high dielectric constants include NPO (COG) (up to about 100), X7R (about 3000 to about 7000), X7S, Z5U, and / or Y5V. It should be understood that the materials mentioned above are described according to their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and as such, they should be recognized by those skilled in the art. For example, such a material may include a ceramic. Such materials may include a perovskite, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconatit titanate, barium strontium zirconatit titanate, barium calcium zirconatit titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconatit titanate, lead anthanasia zirconatit titanate), sodium bismuth titanate, etc.In a particular embodiment, for example, barium strontium titanate (“BSTO”) of the formula Ba. x Sr 1-x TiO3 can be used, where x = 0 to 1, in some embodiments approximately 0.15 to approximately 0.65, and in some embodiments approximately 0.25 to approximately 0.6. Other suitable perovskites include, for example, Ba x Approx 1-x TiO3, where x is approximately 0.2 to approximately 0.8 and in some embodiments approximately 0.4 to approximately 0.6, Pb x Zr 1-x TiO3 (“PZT”), where x is in the range of about 0.05 to about 0.4, lead anthanizirconium titanate (“PLZT”), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Further complex perovskites can include A[B1 1 / 3 B2 2 / 3 ]O3 materials, where A = Ba x Sr 1-x is (x can be a value from 0 to 1); B1 = Mg y Zn 1-yis (y can be a value from 0 to 1); B2 = Ta z Note 1-z is (z can be a value from 0 to 1). In a particular embodiment, the dielectric layers can comprise a titanate.

[0044] The electrode layers can be formed from a variety of materials, as is known in engineering. The electrode layers can consist of a metal, such as a conductive metal. The materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as sputtered layers of chromium, nickel, and gold, can also be suitable. The electrodes can also be formed from a low-resistance material, such as silver, copper, gold, aluminum, palladium, etc. In a particular embodiment, the electrode layers can comprise nickel or an alloy thereof.

[0045] If we turn again to Fig.Referring to 1E, in some embodiments the dielectric region 12 may be free of electrode layers extending from a first end 119 or a second end 120 of the capacitor 100 over more than approximately 25% of the length 21 of the capacitor 100. For example, in such embodiments the dielectric region 12 may comprise one or more floating electrodes and / or dummy electrode tabs. In other embodiments, however, the dielectric region 12 may be free of all electrode layers. In some embodiments the multilayer broadband ceramic capacitor 100 may be free of shielding electrodes 22, 24 above a plurality of active electrode layers 102, 104 in the Z-direction 136.In some embodiments, the multilayer broadband ceramic capacitor 100 can be free of shielding electrodes 22, 24 above a lowest electrode layer 19 of the plurality of active electrode layers 102, 104 in the Z-direction 136.

[0046] The multitude of active electrode layers 102, 104 can be arranged within the active electrode region 14. Each active electrode layer 102, 104 can comprise one or more active electrodes, as shown below, for example, with regard to the Fig. 1A to 1C is described. For example, in some embodiments, each active electrode layer 102, 104 can comprise a third electrode 106 and a second electrode 108.

[0047] The shielding electrode area 16 can comprise one or more shielding electrodes, as shown below, for example, in relation to Fig.1D is described. For example, the shielding electrode area 16 can include a first shielding electrode 22, which is arranged within a monolithic body of the capacitor 100. The first shielding electrode 22 can run parallel to the longitudinal direction 132. The first shielding electrode 22 can be connected to the first outer terminal 118. The shielding electrode area 16 can include a second shielding electrode 24, which can be connected to the second outer terminal 120. The second shielding electrode 24 can be aligned approximately with the first shielding electrode 22 in the Z-direction 136.

[0048] The first outer terminal 118 can be connected to the first electrode 106 of a first electrode layer 102 and to a second (counter) electrode 108 of the second electrode layer 104. The second outer terminal 120 can be connected to the first electrode 106 of the second electrode layer 104 and to the second (counter) electrode 108 of the first electrode layer 102.

[0049] The first outer terminal 118 can include a base section 138 extending along the base surface 20 of the capacitor 100. The second outer terminal 120 can include a base section 140 extending along the base surface 20 of the capacitor 100. The base section 138 of the first outer terminal 118 and the base section 140 of the second outer terminal 120 can be spaced apart longitudinally 132 by a base-to-outer-terminal distance 142. The ratio of the capacitor length 21 to the base-to-outer-terminal distance 142 can be less than approximately 4.

[0050] The first outer terminal 118 can include an upper part 144 extending along the upper surface 18 of the capacitor 100. The second outer terminal 120 can include an upper part 146 extending along the upper surface 18 of the capacitor 100. The upper part 144 of the first outer terminal 118 can be spaced longitudinally 132 apart from the outer terminal 148 by a distance approximately equal to the bottom-to-outer-terminal distance 142.

[0051] The dielectric material of the monolithic body of the capacitor 100 can be exposed along the base surface 20 of the capacitor 100 between the base part 138 of the first outer terminal 118 and the base part 140 of the second outer terminal 120. Likewise, the dielectric material of the monolithic body of the capacitor 100 can be exposed between the upper part 144 of the first outer terminal 118 and the upper part 146 of the second outer terminal 120.

[0052] In general, with regard to the embodiments discussed here, the external terminals can be made of a variety of different metals, as is known in the art. The external terminals can be made of a single metal, such as a conductive metal. The materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and so on, as well as various combinations thereof. In one particular embodiment, the external terminals can comprise copper or an alloy thereof.

[0053] The external connections can be formed using any method generally known in engineering. These include techniques such as sputtering, painting, printing, electroless deposition or copper refining (FCT), electroplating, plasma deposition, blowing agent spraying / airbrushing, and so on.

[0054] In one embodiment, the outer terminals can be designed to be relatively thick. For example, such terminals can be formed by depositing a thick film strip of metal onto exposed parts of electrode layers (e.g., by immersing the capacitor in a liquid outer terminal material). Such a metal can be in a glass matrix and can include silver or copper. As an example, such a strip can be printed and fired onto the capacitor. Subsequently, additional metal deposition layers (e.g., nickel, tin, solder, etc.) can be created over the terminal strip so that the capacitor can be soldered onto a substrate. Such an application of thick film strips can be achieved using any method generally known in the art (e.g.,by means of a connecting machine and a pressure wheel for transferring a metal-loaded paste over the exposed electrode layers).

[0055] The thickly deposited outer terminals can have an average thickness of approximately 150 µm or less, such as approximately 125 µm or less, such as approximately 100 µm or less, such as approximately 80 µm or less. The thickly deposited outer terminals can have an average thickness of approximately 25 µm or more, such as approximately 35 µm or more, such as approximately 50 µm or more, such as approximately 75 µm or more. For example, the thickly deposited outer terminals can have an average thickness of approximately 25 µm to approximately 150 µm, such as from approximately 35 µm to approximately 125 µm, such as from approximately 50 µm to approximately 100 µm.

[0056] In another embodiment, the outer terminals can be configured such that the outer terminal is a thin-film deposition of a metal. Such a thin-film deposition can be formed by depositing a conductive material, such as a conductive metal, onto an exposed portion of an electrode layer. For example, a leading edge of an electrode layer can be exposed to allow the formation of a coated terminal.

[0057] The thinly deposited outer connections can have an average thickness of approximately 50 µm or less, such as approximately 40 µm or less, such as approximately 30 µm or less, such as approximately 25 µm or less. The thinly deposited outer connections can have an average thickness of approximately 5 µm or more, such as approximately 10 µm or more, such as approximately 15 µm or more. For example, the outer connections can have an average thickness of approximately 5 µm to approximately 50 µm, such as from approximately 10 µm to approximately 40 µm, such as from approximately 15 µm to approximately 30 µm, such as from approximately 15 µm to approximately 25 µm.

[0058] In general, the outer terminal can include a deposited terminal. For example, the outer terminal can include an electroplated terminal, a electroless deposited terminal, or a combination thereof. For example, an electroplated terminal can be formed by electrolytic deposition. An electroless deposited terminal can be formed by electroless deposition.

[0059] If multiple layers form the outer terminal, the outer terminal can include an electroplated terminal and an electroless deposited terminal. For example, electroless deposition can be used first to deposit an initial layer of material. Then, the deposition technique can be switched to an electrochemical deposition system, which allows for faster material build-up.

[0060] When the deposited terminals are formed using one of the two deposition methods, a leading edge of the terminal tabs of the electrode layers, which protrudes from the main body of the capacitor, is exposed to a deposition solution. In one embodiment, the capacitor can be immersed in the deposition solution during this exposure.

[0061] The deposition solution contains a conductive material, such as a conductive metal, and is used to form the deposited terminal. Such a conductive material can be one of the materials mentioned previously or one commonly known in the trade. For example, the deposition solution can be a nickel sulfamate bath solution or another nickel solution, so that the deposited layer and the outer terminal comprise nickel. Alternatively, the deposition solution can also be a copper acid bath or another suitable copper solution, so that the deposited layer and the outer terminal comprise copper.

[0062] Furthermore, it should be noted that the deposition solution may also include other additives, as is generally known in the art. For example, the additives may include other organic additives and media that can support the deposition process. Additives may also be used to adjust the deposition solution to a desired pH value. In one embodiment, resistance-reducing additives may be included in the solutions to promote complete coverage of the deposit and adhesion of the deposit materials to the capacitor and the exposed leading edges of the terminal tabs.

[0063] The capacitor can be treated, submerged, or immersed in the deposition solution for a predetermined period of time. This exposure time is not necessarily limited, but it can be long enough to allow sufficient deposition material to form the coated terminal. In this respect, the time should be sufficient to allow the formation of a permanent bond between the desired exposed, adjacent leading edges of terminal tabs of a given polarity of the respective electrode layers within a set of alternating dielectric and electrode layers.

[0064] In general, the difference between electroplating and electroless plating is that electroplating uses an electrical bias voltage, as when using an external current source. The electroplated solution can typically withstand a high current density range, for example, ten to fifteen amperes per foot. 2 (rated at 9.4 volts). A connection can be formed with a negative connection to the capacitor, requiring the formation of the deposited terminals and a positive connection to a solid material (e.g., copper in copper plating solution) in the same deposition solution. That is, the capacitor is biased to a polarity opposite to that of the deposition solution. Using this method, the conductive material of the deposition solution is attracted to the metal of the exposed leading edge of the electrode layer terminals.

[0065] Several pretreatment steps can be employed before immersing or treating the capacitor in a deposition solution. Such steps can be performed for various purposes, including catalyzing, accelerating, and / or improving the adhesion of the deposition materials to the leading edges of the terminal tabs.

[0066] Furthermore, an initial cleaning step can be employed prior to deposition or any other pretreatment steps. Such a step can be used to remove any oxide adhesion that forms on the exposed terminals of the electrode layers. This cleaning step can be particularly helpful in aiding the removal of nickel oxide adhesion when the internal electrodes or other conductive elements are made of nickel. Component cleaning can be performed by full immersion in a pre-cleaning bath, such as one containing an acid cleaner. In one embodiment, the immersion can be carried out for a predetermined time, on the order of about 10 minutes. Alternatively, cleaning can be performed by chemical polishing or harperization steps.

[0067] Furthermore, a step can be performed to activate the exposed metallic leading edges of the electrode layer tabs to facilitate the deposition of the conductive materials. Activation can be achieved by immersion in palladium salts, photostructured metal-organic palladium precursors (via mask or laser), screen-printed or inkjet-deposited palladium compounds, or electrophoretic palladium deposition. It should be noted that palladium-based activation is currently disclosed only as one example of activation solutions, which often work well in conjunction with activation for exposed tab parts made of nickel or an alloy thereof. However, it should be understood that other activation solutions can also be used.

[0068] Furthermore, instead of or in addition to the activation step mentioned above, the activating dopant can be introduced into the conductive material when the capacitor's electrode layers are formed. For example, if the electrode layer comprises nickel and the activating dopant comprises palladium, the palladium dopant can be introduced into the nickel ink or composition forming the electrode layers. This can eliminate the need for the palladium activation step. It should also be noted that some of the activation methods described above, such as metal-organic precursors, are also suitable for co-deposition with glass formers for increased adhesion to the generally ceramic body of the capacitor.When activation steps are performed as described above, traces of the activator material often remain on the exposed conductive parts before and after the connection deposition.

[0069] Additionally, post-treatment steps can be employed after deposition. Such steps can be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or tempering) step can be used after the deposition step. This heating can be carried out by burning, laser treatment, UV irradiation, microwave irradiation, arc welding, etc.

[0070] As already mentioned, the outer connection can comprise at least one deposit layer. In one embodiment, the outer connection can comprise only one deposit layer. However, it should be understood that the outer connections can comprise a plurality of deposit layers. For example, the outer connections can comprise a first deposit layer and a second deposit layer. Furthermore, the outer connections can also comprise a third deposit layer. The materials of these deposit layers can be any of those mentioned above and any materials generally known in the art.

[0071] For example, a deposit layer, such as a first deposit layer, can comprise copper or an alloy thereof. Another deposit layer, such as a second deposit layer, can comprise nickel or an alloy thereof. Another deposit layer, such as a third deposit layer, can comprise tin, lead, gold, or a combination thereof, such as an alloy. Alternatively, an initial deposit layer can comprise nickel, followed by deposit layers of tin or gold. In another embodiment, an initial deposit layer of copper can be formed, followed by a nickel layer.

[0072] In one embodiment, the initial or first deposition layer can consist of a conductive metal (e.g., copper). This area can then be covered with a second layer containing a polymeric resistive material for sealing. The area can then be polished to selectively remove the polymeric resistive material and subsequently metallized again with a third layer containing a conductive metallic material (e.g., copper).

[0073] The second layer mentioned above, located above the initial deposition layer, can correspond to a solder barrier layer, for example, a nickel solder barrier layer. In some embodiments, the aforementioned layer can be formed by electroplating an additional layer of metal (e.g., nickel) over an initial electroless deposited or electroplated layer (e.g., deposited copper). Other exemplary materials for the aforementioned solder barrier layer are nickel-phosphorus, gold, and silver. A third layer on the aforementioned solder barrier layer can, in some embodiments, correspond to a conductive layer, such as deposited Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable deposited solder metal.

[0074] Furthermore, a deposit layer can be formed, followed by an electroplating step to obtain a resistance alloy or a metal alloy with higher resistance, for example, an electroless deposited Ni-P alloy over such a deposit. However, it should be understood that it is possible to use any metal coating, as the person skilled in the art will understand from the present complete disclosure.

[0075] It should be understood that each of the above-mentioned steps can be performed as a batch process, such as drum deposition, fluidized bed deposition, and / or flow deposition finishing processes, all of which are well-known in engineering. Such batch processes allow for the simultaneous processing of multiple components, resulting in an efficient and rapid finishing process. This is a significant advantage over conventional finishing methods, such as thick-film terminal printing, which requires individual processing of each component.

[0076] As described here, the formation of the outer terminals is generally determined by the position of the exposed leading edges of the electrode layer terminal tabs. Such phenomena can be described as "self-determining" because the formation of the outer metallized terminals is determined by the configuration of the exposed conductive metal of the electrode layers at selected peripheral locations on the capacitor. In some embodiments, the capacitor may include dummy tabs to provide exposed conductive metal along portions of the monolithic body of the capacitor that do not include other electrodes (e.g., active or shielding electrodes).

[0077] It should be noted that additional techniques for forming capacitor terminals may also fall within the scope of this technology. Exemplary alternatives include, but are not limited to, the formation of terminals by deposition, magnetism, masking, electrophoresis / electrostatics, sputtering, vacuum deposition, printing, or other techniques for forming conductive thick and thin films.

[0078] Fig. Figure 1A shows a top view of an embodiment of an active electrode configuration for one or more electrodes in the active electrode region 14 according to aspects of the present disclosure. In particular, the active electrode region 14 can comprise first electrode layers 102 and second electrode layer 104 in an alternating arrangement, as is shown, for example, below with respect to Fig. 1B is described. If we look at Fig.Referring to 1A, each electrode layer 102, 104 can comprise a third electrode 106 and a second electrode 108. The first electrode 106 can have a base part 114 extending along a longitudinal edge of the first electrode 106 in the lateral direction 134. The first electrode 106 can have a pair of electrode arms 110 extending from a base part 114 in the longitudinal direction 132. The second electrode 108 can have a base part 114 extending along a longitudinal edge of the second electrode 108 in the lateral direction 134. The second electrode 108 can have a pair of electrode arms 110 extending from the base part 114 in the longitudinal direction 132.

[0079] The electrode arm or arms 110 of the first electrode 106 can be substantially longitudinally aligned with respect to the electrode arm or arms 110 of the second electrode 108. An arm gap or arm gaps 226 can be defined in the longitudinal direction 132 between the aligned electrode arms 110 of the first and the second electrode 106, 108.

[0080] A central edge gap 23a can be defined in the lateral direction 134 between the central part 112 of the first electrode and the second electrode arm 110. A central end gap 23b can be defined in the longitudinal direction 132 between the central part 112 of the first electrode 106 and the base part 114 of the second electrode 108. In some embodiments, the central edge gap 23a can be approximately equal to the central end gap 23b.

[0081] The central part 112 of the first electrode 106 can have a first width 27 at a first location and a second width 29 at a second location, which is larger than the first width 27. The first location of the first width 27 can be offset in the longitudinal direction 132 relative to the second location of the second width. Such a configuration makes it possible to establish an overlapping area between central parts 112 of adjacent electrodes in the Z-direction 136 without changing the central edge gap distance 23.

[0082] In Fig. 1B A plurality of first electrode layers 102 and a plurality of second electrode layers 104 can be present in an alternating mirrored configuration. As shown, the central parts 112 of the respective electrode layers overlap at least partially. Fig.Figure 1B shows a total of four electrode layers; however, it should be noted that any number of electrode layers can be used to obtain the desired capacity for the intended application.

[0083] According to Fig. In 1C, several capacitive regions can form between the first electrode 106 and the second electrode 108. For example, in some embodiments, a central capacitive region 122 can form between the middle part 112 of the first electrode 106 and the base part 114 and / or the arms 128 of the second electrode 108. In some embodiments, a capacitive region 124 of the arm gap 226 can form within the arm gap between the electrode arms 110 of the first electrode 106 and the second electrode 108.

[0084] Fig. Figure 1D shows a shielding electrode layer 26 located within the shielding electrode area 16 (in Fig.(1E shown) within the monolithic body of the capacitor 100. According to the above note, the first shielding electrode 22 can be parallel to the longitudinal direction 132 (e.g., parallel to the one shown in Fig. The first shielding electrode 22 can have a first longitudinal edge 28, which is aligned in the lateral direction 134 and extends from the first outer terminal 118 (in Fig. 1E) and is facing away from the first end 119. The first shielding electrode 22 may have a second longitudinal edge 30, which is oriented in the lateral direction 134 and is separated from the first outer terminal (in Fig. (1E shown) and is facing away from the first end 119. The second longitudinal edge 30 can be offset in the longitudinal direction 132 by a shielding electrode offset distance 32 relative to the first longitudinal edge 28.

[0085] The second shielding electrode 24 can be connected to the second outer terminal 120 (in Fig. 1E) and the second end 121. The second shielding electrode 24 can be connected in the Z-direction 136 (in Fig. (shown in Figure 1E) with the first shielding electrode 22 being approximately aligned. The second shielding electrode 24 can have a similar configuration to the first shielding electrode 22. For example, the second shielding electrode 24 can have a first longitudinal edge 28 that is aligned in the lateral direction 134 and is connected to the second outer terminal 120 (in Figure 1E). Fig. 1E) and is turned away from the second end 121. The second shielding electrode 24 can have a second longitudinal edge 30, which is oriented in the lateral direction 134 and is faced away from the second outer terminal 120 (in Fig.(1E shown) and the second end 121 is turned away. The second longitudinal edge 30 of the second shielding electrode 24 can be offset in the longitudinal direction 132 by the shielding electrode offset distance 32 relative to the first longitudinal edge 28 of the second shielding electrode 24.

[0086] A first capacitive shielding area 34 can be formed between the first longitudinal edges 28 of the first and second shielding electrodes 22, 24. A second capacitive shielding area 36 can be formed between the second longitudinal edges 30 of the first and second shielding electrodes 22, 24. In some embodiments, the width 38 of the first longitudinal edge 28 in the lateral direction 134 can be smaller than the width 40 of the first shielding electrode 22 in the lateral direction 134.

[0087] A first shielding gap 42 can be formed in the longitudinal direction 132 between the first longitudinal edge 28 of the first shielding electrode 22 and the first longitudinal edge 28 of the second shielding electrode 24. A second shielding gap 44 can be formed in the longitudinal direction 132 between the second lateral edge 30 of the first shielding electrode 22 and the second lateral edge 30 of the second shielding electrode 22.

[0088] In some embodiments, a third shielding gap 46 can be formed between a third longitudinal edge 48 of the first shielding electrode 22 and a third longitudinal edge 48 of the second shielding electrode 24. A third capacitive shielding area 51 can be formed between the third longitudinal edges 48 of the first and second shielding electrodes 119, 121. In some embodiments, the third shielding gap 46 can be approximately equal to the second shielding gap 44, so that the third capacitive shielding area 51 can have essentially the same size and shape as the second capacitive shielding area 36. For example, in some embodiments, the first shielding electrode 22 and / or the second shielding electrode 24 can be symmetrical about a longitudinal center line 50 extending in the longitudinal direction 132.

[0089] In other embodiments, however, the third shielding gap 46 can be larger or smaller than the second shielding gap 44, so that the third capacitive area 51 has a different size and / or shape than the second capacitive area 36 and produces a different capacitance than the second capacitive area.

[0090] It should be noted that in some embodiments one or more of the shielding electrodes 22, 24 may be rectangular. In other words, the shielding electrode offset distance 32 may be zero or approximately zero, so that the first longitudinal edge 28 and the second longitudinal edge 30 are aligned or approximately aligned.

[0091] The Fig. 2A and Fig.Figure 2B shows another embodiment of the first and second electrode layers 102, 104. In particular, each electrode layer 102, 104 can comprise a third electrode 106 and a second electrode 108. The first electrode 106 can have a base part 114. A pair of electrode arms 110 and at least one central part 112 can extend from the base part 114. The second electrode 108 can have a base part 114 extending along a longitudinal edge of the second electrode 108. The second electrode 108 can have a pair of electrode arms 110 extending from the base part 114. The electrode regions 12, 14, 16 can be substantially non-overlapping.

[0092] If we look at Fig. 1E, the multilayer broadband ceramic capacitor 100 can in some embodiments have a capacitor thickness 56 in the Z direction 136 between the upper surface 18 and the bottom surface 20.

[0093] The dielectric region 12 can have a thickness of 58 in the Z-direction 136. In some embodiments, the ratio of the capacitor thickness 56 to the thickness of the dielectric region 58 can be less than approximately 10.

[0094] The active electrode region 14 can have a thickness of 59 in the Z-direction 136. The active electrode region 14 can be free of shielding electrodes 22, 24 and / or can comprise only overlapping electrodes. The thickness of the active electrode region 59 can be defined between the lowest active electrode layer 19 and the highest electrode layer 65. The ratio of the capacitor thickness 56 to the thickness of the active electrode region 59 can be in a range of approximately 1.1 to approximately 20.

[0095] The shielding electrode region 16 can have a thickness of 61 in the Z-direction 136. The thickness of the shielding electrode region 61 can be defined between the bottom surface 20 of the capacitor 100 and the lowest electrode layer 19 of the plurality of active electrodes. The ratio of the capacitor thickness 56 to the thickness of the shielding electrode region 61 can be in a range of approximately 1.1 to approximately 20.

[0096] In some embodiments, the distance between the shield and the base surface 63 can be defined as the distance between the shielding electrodes 22, 24 and the base surface 20 of the capacitor 100. If multiple shielding electrode layers are present, the distance between the shield and the base surface 63 can be defined as the distance between the lowest of the shielding electrode layers and the base surface 20. The ratio of the capacitor thickness 56 to the distance between the shield and the base surface 63 can be greater than approximately 2.

[0097] In some embodiments, the shielding electrodes 22, 24 can be spaced apart from the active electrodes 106, 108 by a first shield-to-active distance 67. The ratio of the first shield-to-active distance 67 to the distance between the shield and the base surface 63 can be in a range of approximately 1 to approximately 20.

[0098] Furthermore, it shows Fig.2A Electrode arms 110, comprising a main part 128 and a step part 130. In particular, an electrode arm 110 of the first electrode 106 can comprise a first longitudinal edge 60 extending in the lateral direction 134 and defining an edge of the step part 130. A second longitudinal edge 62 can extend in the lateral direction 134 and define an edge of the main part 128 of the arm 110. The first longitudinal edge 60 can be offset in the longitudinal direction 132 by an arm offset distance 64 relative to the second longitudinal edge 62. One or both electrode arms 110 of the first electrode 106 and / or the second electrode 108 can each comprise a main part and a step part 128, 130. For example, both arms 110 of the two electrodes 106, 108 can each comprise main parts 128 and step parts 130, as is the case, for example, in Fig.Figure 2A shows that main arm gaps 240 can occur between the step sections 130 of the aligned arms 110. Step arm gaps 242 can occur between the main sections 128 of the aligned arms 110.

[0099] If we focus on the Fig. 2B, so that between the first electrode 106 and the second electrode 108 the electrode configuration of Fig. 2A Several capacitive regions are formed. For example, in some embodiments, a central capacitive region 122 can form between the central part 112 of the first electrode 106 and the base part 114 and / or the arms 110 of the second electrode 108. In some embodiments, a capacitive region of the main arm gap 125 can form within the main arm gap 240, and a capacitive region of the step gap 126 can form within the step arm gap 242.

[0100] If we look at Fig.Referring to 3A, in some embodiments the dielectric area 12 can comprise first dummy tab electrodes 52 connected to the first terminal and / or second dummy tab electrodes 54 connected to the second terminal 120. In particular, the dummy tab electrodes 52, 54 can be used to form (e.g., deposit) the terminals 118, 120, for example, using a copper refining process. The dummy tab electrodes 52, 54 can extend over less than 25% of the capacitor length 21 opposite the first end 119 or the second end 121.

[0101] The electrode configurations described here can allow a primary capacitive element between the central parts 112 of the adjacent electrode layers 102, 104 (i.e., parallel plate capacitance) as well as additional secondary capacitive elements, as shown, for example, above in relation to the Fig. 1C, Fig.1D and Fig. 2B is described. These configurations are in the Fig. 4A and Fig. 4B shown schematically.

[0102] In some embodiments, the capacitor 100 may comprise one or more floating electrodes 111. The floating electrode 111 may be located in the dielectric region 12. In other embodiments, however, the floating electrode 111 may be located in the active electrode region 14 and / or the shielding electrode region 16. Generally, such floating electrodes 111 are not directly connected to an external terminal 118, 120.

[0103] In some embodiments, however, the floating electrode can be part of a floating electrode layer containing at least one electrode electrically connected to an external terminal; such a floating electrode layer, however, contains at least one floating electrode that has no direct contact with such an electrode or external terminal.

[0104] The floating electrode can be positioned and configured according to any method known in the art. For example, the floating electrode can be provided such that it overlaps at least one part, such as a central part, of a first active electrode and / or a second active electrode of an active electrode layer. In this respect, the floating electrode layer can be layered and arranged alternately with the first electrode layers and the second internal electrode layers; in this respect, such layers can be separated from each other by the dielectric layers.

[0105] Furthermore, such floating electrodes can have any shape, as is generally known in the art. For example, in one embodiment, the floating electrode layers can comprise at least one floating electrode with a dagger-like configuration. For example, such a configuration can be similar to the configuration and shape of the first electrode as described herein. However, it should be noted that such a first electrode may or may not include an electrode arm with a stepped section.

[0106] Furthermore, in one embodiment, the floating electrode layer can contain at least one floating electrode in which the end of the floating electrode lies next to at least one outer terminal but does not touch that outer terminal. In this respect, such a gap can be referred to as a longitudinal floating electrode gap. Such a floating electrode gap can be greater than 0%, such as 3% or more, such as 5% or more, up to approximately 50% or less, such as 40% or less, such as 30% or less, such as 20% or less, such as 10% or less, of the longitudinal length of the capacitor.

[0107] Fig.Figure 3B shows another embodiment of a capacitor 160 according to aspects of the present disclosure. The capacitor 160 can comprise a plurality of electrode regions 162. The plurality of electrode regions 162 can comprise an active electrode region 14, a first shielding electrode region 164, and a second shielding electrode region 166. The active electrode region 14 can be located between the first shielding electrode region 164 and the second electrode region 166.

[0108] In some embodiments, the capacitor 160, or a part thereof, can be symmetrical about a longitudinal centerline 167 extending in the longitudinal direction. For example, the shielding electrodes 22, 24 of the lower shielding electrode region 164 can be symmetrical about the longitudinal centerline 167 with respect to the shielding electrodes 22, 24 of the upper shielding electrode region 166. In other words, the distance between the shield and the bottom surface 63 can be approximately equal to the distance from the shield to the upper surface 168, which can be defined between the shielding electrodes 22, 24 of the upper shielding electrode region 166 and the upper surface 18 of the capacitor 160.For example, in some embodiments the ratio of the distance between shielding and bottom surface 63 and the distance from shielding to upper surface 168 may be in a range of about 0.8 to about 1.2, in some embodiments from about 0.9 to about 1.1, in some embodiments from about 0.95 to about 1.05 and in some embodiments from about 0.98 to about 1.02.

[0109] The shielding electrodes 22, 24 of the upper shielding electrode area 166 can be spaced from the active electrodes 106, 108 by a second shielding-to-active distance 169. The ratio of the second shielding-to-active distance 169 to the distance from the shield to the upper surface 168 can be in a range of approximately 1 to approximately 20. Furthermore, the ratio of the first shielding-to-active distance 67 to the second shielding-to-active distance 169 can be in a range of approximately 0.8 to approximately 1.2.

[0110] The capacitor 160 can exhibit comparable insertion loss characteristics in the first orientation (as shown) up to the third orientation, in which the capacitor 160 is rotated 180 degrees about the longitudinal direction 132 (which appears essentially similar to the one shown). The second orientation of the capacitor 160 can be defined relative to the first orientation by a 90-degree rotation about the longitudinal direction 132, such that the shielding electrodes 22, 24 are perpendicular to the mounting surface 101.

[0111] In the first orientation, the capacitor 160 can exhibit a first insertion loss value at a test frequency greater than approximately 2 GHz. In the second orientation relative to the mounting surface, the capacitor 160 can exhibit a second insertion loss value at approximately the test frequency, which differs from the first insertion loss value by at least approximately 0.3 dB.

[0112] Fig.Figure 4 schematically shows three capacitive elements of the electrode configuration of Fig. 1C: a primary capacitive element 112' between adjacent electrode layers, a central capacitive element 122', and a capacitive arm gap element 124'. The capacitive elements 112', 122', and 124' correspond to the central region 112, the central capacitive region 122, and the capacitive arm gap region 124, respectively. Fig. 1C. Furthermore, external connections are in Fig. 4 shown as 118 and 128.

[0113] Fig. Figure 5 schematically shows four capacitive elements of the electrode configuration of Fig. 2B, in which the capacitive elements 112', 122' and 125' as well as 126' are assigned to the central area 112, the capacitive area 122, the capacitive area of ​​the main arm gap 125 and the capacitive area of ​​the step gap 126 respectively. Fig.2B corresponds. It should be understood that the dimensions of the various columns can be specifically designed to achieve the desired respective capacity values ​​for the [in] Fig. 4 and Fig. The capacitive elements shown in Figure 5 can be used to achieve the desired capacitance values. In particular, the capacitor configuration and various parameters, such as the number of electrode layers, the area of ​​the overlapping central parts of electrode pairs, the distance separating the electrodes, the dielectric constant of the dielectric material, etc., can be selected to achieve these values. However, the capacitor as revealed here can also include an arrangement of capacitors connected in series and parallel to provide effective broadband performance.

[0114] In an exemplary embodiment of an ultra-wideband capacitor, the primary capacitor 112' generally corresponds to a relatively large capacitance suitable for operation in a generally lower frequency range, such as on the order of between several kilohertz (kHz) and about 200 megahertz (MHz), while secondary capacitors 122', 124' and 126' generally correspond to capacitors of smaller value configured to operate in a higher frequency range, such as on the order of between about 200 megahertz (MHz) and many gigahertz (GHz).

[0115] Let's consider Fig.6. In some embodiments, a multilayer capacitor 300 may comprise a first outer terminal 118 located along a first end 119 and a second outer terminal 120 located along a second end 121, which is opposite the first end 119 in the longitudinal direction 132. The multilayer capacitor 300 may comprise a plurality of dielectric layers and a plurality of electrode layers, the electrode layers being arranged alternately in an opposite and spaced-apart relationship to a dielectric layer located between adjacent electrode layers.

[0116] Furthermore, as already mentioned, the multilayer capacitor can include a shielding electrode. For example, in Fig.As shown in Figure 6, the multilayer capacitor 300 can comprise a first shielding region 210 and a second shielding region 212, and each of the shielding regions 210, 212 can comprise one or more shielding electrode layers 214. The shielding regions 210, 212 can be separated from the active electrode region 216 by a dielectric region (for example, one that does not contain any electrode layers).

[0117] The shielding electrode layers 214 can have a first shielding electrode configuration in which each shielding electrode 220 is substantially rectangular. In other embodiments, the shielding electrode layers 214 can have a second shielding electrode configuration in which the shielding electrodes 222 comprise a step 224, as described above, for example, with respect to the electrodes of the Fig. 1D is explained.

[0118] In some embodiments, an active electrode region 218 can be located between the first and the second shielding regions 210, 212. The active electrode region 216 can comprise a plurality of alternating active electrode layers 218, as described, for example, in the Fig. 2A-2D is explained. Additionally, a pair of ceramic covers 227 may be located along the upper and / or lower surface of the capacitor 300.

[0119] Let's consider Fig.6. In some embodiments, the multilayer capacitor 300 may also comprise armature electrode regions 302, 304, 316, and / or 318. For example, the multilayer capacitor 300 may comprise a first armature electrode region 304 on the active electrode region 216. Furthermore, a shielding electrode region 210, containing a shielding electrode layer 214, may be located above, as on, the first armature electrode region 304. Additionally, a second armature electrode region 302 may be located above, as on, the top surface of the shielding electrode region 210. Similarly, the multilayer capacitor 300 may comprise a third armature electrode region 316 below, as directly beneath, the active electrode region 216. Furthermore, a shielding electrode region 210, containing a shielding electrode layer 214, may be located below, as directly beneath, the third armature electrode region 316.Additionally, a fourth armature electrode region 318 can be located below, as directly below, the shielding electrode region 210. In this respect, the active electrode region 216 can, for example, be located between the first armature electrode region 304 and the third armature electrode region 316. The active electrode region 216 can be configured as described above with respect to the... Fig. 1A to 1C, the Fig. as described in 2A to 2C, or as described in 8A to 8D below.

[0120] Let's consider the Fig.7A, the armature electrode regions 302, 304, 316 and / or 318 can comprise a plurality of armature electrode layers 310, each having a pair of armature electrodes 312. The armature electrodes 312 can comprise a pair of electrode arms 314. Each electrode arm 314 of the armature electrodes 312 can comprise a main part 328 and a step part 330, for example, in a similar manner to that described above with respect to the electrodes of the Fig. 1A and Fig. 2 is described.

[0121] Let's consider the Fig. 7B to 7D, the anchor electrodes can have 312 different configurations. Let us consider, for example, the Fig. 7B, in some embodiments the electrode arms 314 of the armature electrodes 312 do not include a step. For example, such electrodes may be in a C-shaped configuration without a step. Let us consider the Fig.7C, in some embodiments the electrode arms 314 of the armature electrodes 312 can comprise a step portion 320 which is displaced inwards relative to an outer lateral edge 322 of the armature electrode 312. Let us consider the Fig. 7D, in other embodiments the step part 320 can be displaced relative to an inner lateral edge 324 of the arms 314 of the armature electrodes 312. Further configurations are possible. For example, in some embodiments the step part 320 can be displaced relative to both the outer lateral edge 322 and the inner lateral edge 324.

[0122] Let's consider the Fig. 8A-8D, in some embodiments the active electrodes 106, 108 can have various other configurations. For example, consider the Fig.8A, in some embodiments the first electrodes 106 and the second electrodes 108 can each have a single arm 110 instead of a pair of arms 110, 202, as described above in relation to Fig. as described in 1A. In this respect, such electrodes may comprise an electrode containing a central part extending away from a base part and an electrode arm also extending away from the base part; however, the counter electrode may comprise a base part and only a single electrode arm extending away from the base part of this second electrode.

[0123] Let's consider the Fig.8B, in some embodiments the first electrodes 106 and the second electrodes 108 can each comprise central parts 112. For example, each electrode 106, 108 can, in addition to at least one electrode arm 110, 202, such as two electrode arms 110, 202 extending from the respective base part, comprise a central part 112 extending from a respective base part.

[0124] Let's consider the Fig. 8C, in some embodiments the electrode arms 110, 202 of the electrodes 106, 108 can have a step portion 130 which is displaced outwards from a lateral center line 236 of at least one of the electrodes 106, 108 of the electrode layers relative to an inner lateral edge 324 of the main part of an electrode arm. Finally, let us consider the Fig.8D, in some embodiments the electrode arms 110 of the electrodes 106, 108 may have step parts 130 which are displaced both relative to the outer lateral edge 322 and the inner lateral edge 324 of the electrode arms 110, 202. II. Insertion loss

[0125] Aspects of the present disclosure relate to a multilayer broadband capacitor exhibiting orientation-sensitive insertion loss characteristics. The multilayer broadband capacitor can exhibit an insertion loss at a test frequency in a first orientation that varies by more than approximately 0.3 dB compared to an insertion loss at the test frequency in a second orientation. In the first orientation, the longitudinal direction 132 of the multilayer ceramic capacitor 100 can run parallel to the mounting surface 101 (as is the case, for example, in Fig.(as shown in Figure 1E). In the first orientation, the electrodes (e.g., active electrodes 106, 108 and shielding electrodes 22, 24) can run essentially parallel to the mounting surface 101. Furthermore, in the first orientation, the shielding electrode area 1 (including the shielding electrodes 22, 24) can be located between the active electrode area 14 (including the plurality of active electrodes 106, 108) and the mounting surface 101, as shown, for example, in Figure 1E. Fig. 1E is shown.

[0126] If we look at Fig. 9, the multilayer ceramic capacitor 100 can be rotated by 180 degrees around the longitudinal direction 136 in the second orientation with respect to the first orientation (in Fig. (1E shown). Thus, in the second orientation, the dielectric region 16 can be located between the active electrode region 14 and the mounting surface 101 with respect to the Z-direction 136.

[0127] The capacitor can exhibit a first insertion loss value in the first orientation and a second insertion loss value in the second orientation at a test frequency greater than approximately 2 GHz. In some embodiments, the test frequency can be in a range from approximately 10 GHz to approximately 30 GHz or higher. The second insertion loss value can differ from the first insertion loss value by at least approximately 0.3 dB. III. Test procedure

[0128] An experimental setup can be used to test performance characteristics, such as insertion loss and return loss, of a capacitor according to aspects of this disclosure. For example, the capacitor can be mounted on a test plate. An input line and an output line can each be connected to the test plate. The test plate can include microstrip lines or test tracks that electrically connect the input and output lines to the respective outer terminals of the capacitor. The test tracks can be spaced approximately 0.432 mm (0.017 in) or approximately 0.610 mm (0.024 in) apart.

[0129] An input signal can be applied to the input line using a source signal generator (e.g., a Keithley 2400 Series 1806 Source Measurement Unit (SMU), such as a Keithley 2410-C SMU), and the resulting output signal of the capacitor can be measured at the output line (e.g., using the source signal generator). This test procedure can be repeated on several capacitors of the same construction and nominal dimensions. The insertion loss results can be measured in the first and second orientations. The difference between these insertion loss results can be calculated and averaged to determine the nominal insertion loss sensitivity values ​​for the group of capacitors.

[0130] This procedure can be repeated for the various capacitor configurations described here. Examples

[0131] Eight multilayer ceramic capacitors with the top for the Fig. Configurations 1A to 1E were manufactured and tested for insertion loss response characteristics in the first and second orientations. The multilayer ceramic capacitors had the following dimensions, which correspond to the annotated dimensions of the Fig. 1A to 1E correspond. dimension Reference sign length length 21 1000 µm (0.04 inch) Width - 500 µm (0.02 inch) First shielding gap distance 42 51 µm (0.002 inches) Shielding electrode offset distance 32 150 µm (0.006 inches) Capacitor thickness 56 510 µm (0.020 inches) Distance from floor to outer connection 142 381 µm (0.015 inches) Ground shield-to-ground distance 63 12.7 µm (0.0005 inches) Thickness of the dielectric region 58 71.1 µm (0.0028 inches) Thickness of the shielding electrode area 61 71.1 µm (0.0028 inches) Thickness of the active electrode area 59 367.8 µm (0.0145 inches)

[0132] Thus, the ratio of the length of the capacitor 21 to the distance from the ground to the outer terminal 142 was approximately 2.6.

[0133] The insertion loss response was measured for eight multilayer ceramic capacitors of the same construction and nominal dimensions (within manufacturing tolerances). Insertion loss values ​​were measured at 30 GHz and 40 GHz for each of the eight multilayer ceramic capacitors in both the first and second orientations. The difference between the first and second orientation insertion loss values ​​at 30 GHz and 40 GHz was calculated for each capacitor. The resulting insertion loss delta values ​​at 30 GHz and 40 GHz were averaged to determine the following mean insertion loss deltas at 30 GHz and 40 GHz between the first and second orientations: Test frequency (GHz) Average difference in insertion loss (dB) Standard deviation of insertion loss 30 0,332 0,041 40 0,324 0,051

[0134] As shown in the table above, the mean insertion loss for the fabricated multilayer ceramic capacitors is greater than 0.3 dB at both 30 GHz and 40 GHz, with standard deviations of 0.041 and 0.05 at 30 GHz and 40 GHz, respectively. The standard deviation of the mean insertion loss delta values ​​at 30 GHz and 40 GHz for the group of eight multilayer ceramic capacitors was also calculated, as shown in the table above.

[0135] Fig. Figure 10 shows an insertion loss characteristic of one of the multilayer ceramic capacitors that exhibited insertion loss values ​​very close to the mean value above. The difference between the insertion loss in the first orientation and the insertion loss in the second orientation compared to the insertion loss characteristic of Fig. 10 is as follows: Test frequency (GHz) Insertion loss (dB) 30 0,330 40 0,325

[0136] Furthermore, the capacitor can exhibit excellent insertion loss characteristics in the first orientation. If we look at Fig. Referring to 10, the insertion loss of 302 in the first orientation is greater than approximately -0.8 dB at approximately 10 GHz, approximately 20 GHz, approximately 30 GHz, approximately 40 GHz, approximately 50 GHz, and approximately 60 GHz. The insertion loss of 302 in the first orientation is greater than approximately -0.5 dB at approximately 10 GHz, approximately 20 GHz, approximately 30 GHz, and approximately 40 GHz.

[0137] These and other modifications and variations of the present invention can be made by a person skilled in the art without altering the essence and scope of the present invention. Furthermore, it should be understood that aspects of the various embodiments can be exchanged in whole or in part. The person skilled in the art will also recognize that the above description is only exemplary and is not intended to further limit the invention as described in the appended claims.

Claims

[1] Multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136) and wherein the capacitor (100) comprises a top surface (18) and a bottom surface (20) opposite the top surface (18) in the Z-direction (136), wherein the multilayer broadband ceramic capacitor (100) comprises: a monolithic body comprising a multitude of dielectric layers stacked in the Z direction (136); a multitude of active electrodes (106, 108) arranged within the monolithic body; a first outer terminal (118) located along the first end (119), wherein the first outer terminal (118) comprises a bottom part (138) extending along the bottom surface (20) of the capacitor (100); a second outer terminal (120) located along the second end (121), wherein the second outer terminal (120) comprises a bottom part (140) extending along the bottom surface (20) of the capacitor (100), wherein the bottom part (138) of the first outer terminal (118) and the bottom part (140) of the second outer terminal (120) are spaced apart longitudinally (132) by a bottom-outer terminal distance (142); a lower shielding electrode (22) which is arranged within the monolithic body between the plurality of active electrodes (106, 108) and the bottom surface (20) of the capacitor (100), wherein the lower shielding electrode (22) is spaced apart from the bottom surface (20) of the capacitor by a lower shielding-bottom distance (63); where: the lower shield-ground distance (63) is in a range of about 3 µm to about 100 µm; the lower shielding electrode (22, 24) is connected to the first outer terminal (118); the lower shielding electrode (22, 24) has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the lower shielding electrode (22, 24) has a second longitudinal edge (30) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) relative to the first longitudinal edge (28); the capacitor has a length (21) in the longitudinal direction (132) between the first end (119) and the second end (121) of the capacitor and the ratio of the capacitor length (21) to the lower outer connection distance (142) is less than approximately 4. [2] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein: the first outer terminal (118) comprises a top part (144) which extends along the upper surface (18) of the capacitor; the second outer terminal (120) comprises a top part (146) that extends along the upper surface (18) of the capacitor; and the upper part (144) of the first outer connection (118) and the upper part (146) of the second outer connection (120) are spaced apart in the longitudinal direction (132) by an upper-outer-connection distance (148) which is approximately equal to the lower-outer-connection distance (142). [3] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the monolithic body comprises a dielectric material and wherein the dielectric material is exposed between the bottom part (138) of the first outer terminal (118) and the bottom part (140) of the second outer terminal (120) along the bottom surface (20) of the capacitor. [4] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the lower shielding electrode (22, 24) is arranged between the plurality of active electrodes (106, 108) and the bottom surface (20) of the capacitor. [5] Multilayer broadband ceramic capacitor (100) according to claim 4, further comprising an upper shielding electrode (22, 24) arranged between the plurality of active electrodes (106, 108) and the upper surface (18) of the capacitor. [6] Multilayer broadband ceramic capacitor (100) according to claim 5, wherein: the upper shielding electrode (22) is spaced apart from the upper surface (18) of the capacitor by an upper-shielding-top distance (168); and the ratio of the upper shielding top distance (168) to the lower shielding bottom distance (63) is between approximately 0.8 and approximately 1.

2. [7] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the ratio of the capacitor thickness (56) to the lower shielding ground distance (63) is greater than about 2. [8] Multilayer broadband ceramic capacitor (100) according to claim 1, further comprising an additional lower shielding electrode (22, 24) which is aligned approximately with the lower shielding electrode (22, 24) in the Z direction (136), wherein the lower shielding electrode (22, 24) is connected to the first outer terminal (118) and the additional lower shielding electrode (22, 24) is connected to the second outer terminal (120). [9] Multilayer broadband ceramic capacitor (100) according to claim 1, further comprising an additional lower shielding electrode (22, 24) which is connected to the second outer terminal (120) and is aligned approximately with the lower shielding electrode (22, 24) in the Z direction (136), wherein: the additional lower shielding electrode (22, 24) has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the second outer terminal (120); the additional lower shielding electrode (22, 24) has a second longitudinal edge (30) which is oriented in the lateral direction (134) and faces away from the second outer terminal (120); and the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) relative to the first longitudinal edge (28). [10] Multilayer broadband ceramic capacitor (100) according to claim 9, wherein a first shielding gap distance (42) in the longitudinal direction (132) is formed between the first longitudinal edge (28) of the lower shielding electrode (22, 24) and the first longitudinal edge (28) of the additional lower shielding electrode (22, 24). [11] Multilayer broadband ceramic capacitor (100) according to claim 10, wherein the ratio of the capacitor length (21) to the first shield gap distance (42) is greater than about 2. [12] Multilayer broadband ceramic capacitor (100) according to claim 9, wherein a second shielding gap (44) in the longitudinal direction (132) is formed between the second longitudinal edge (30) of the lower shielding electrode (22, 24) and the second longitudinal edge (30) of the additional lower shielding electrode (22, 24). [13] Multilayer broadband ceramic capacitor (100) according to claim 12, wherein the ratio of the capacitor length (21) to the shield electrode offset distance (32) is greater than about 2. [14] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor is free of shielding electrodes (22, 24) above the plurality of active electrode layers (102, 104) in the Z direction (136). [15] Multilayer broadband ceramic capacitor (100) according to claim 1, further comprising a dielectric region (12) between the plurality of active electrodes (106, 108) and the upper surface (18) of the capacitor, wherein the dielectric region (12) is free of electrode layers. [16] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein at least one of the active electrode layers (102, 104) comprises a first electrode (106) comprising a base part (114) which is electrically connected to the first outer terminal (118), wherein a first electrode arm (110) extends from the base part (114) in the longitudinal direction (132) and a central part (112) extends from the base part (114) in the longitudinal direction (132). [17] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor has an insertion loss which is greater than about -0.4 dB at about 20 GHz. [18] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor has an insertion loss which is greater than about -0.4 dB at about 30 GHz. [19] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor has an insertion loss which is in the range of about -0.05 dB to about -0.4 dB from about 5 GHz to about 20 GHz. [20] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the multilayer broadband ceramic capacitor has an insertion loss which is in the range of about -0.05 dB to about -0.5 dB from about 20 GHz to about 40 GHz. [21] Method for forming a multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136) and the capacitor has a top surface (18) and a bottom surface (20) opposite the top surface (18) in the Z-direction (136), the method comprising: the formation of a multitude of active electrodes (106, 108) on a multitude of active electrode layers (102, 104); the stacking of the plurality of active electrode layers (102, 104), the shielding electrode layer (26) and a plurality of dielectric layers to form a monolithic body, wherein the lower shielding electrode (22, 24) is spaced from the bottom surface (20) of the capacitor by a lower shielding-bottom distance (63) which is in a range of about 3 µm to about 100 µm; the formation of a first outer terminal (118) at a first end (119) of the monolithic body, wherein the first outer terminal (118) comprises a bottom part (138) extending along the bottom surface (20) of the capacitor; the formation of a second outer terminal (120) at a second end (121) of the monolithic body, wherein the second outer terminal (120) comprises a bottom part (140) extending along the bottom surface (20) of the capacitor, wherein the bottom part (138) of the first outer terminal (118) and the bottom part (140) of the second outer terminal (120) are spaced apart longitudinally (132) by a lower-outer terminal distance (142), wherein: the lower shielding electrode (22, 24) is connected to the first outer terminal (118); the lower shielding electrode (22, 24) has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the first outer terminal; the lower shielding electrode (22, 24) has a second longitudinal edge (30) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) relative to the first longitudinal edge (28); and the capacitor has a capacitor length (21) in the longitudinal direction (132) between the first end (119) and the second end (121) of the capacitor and wherein the ratio of the capacitor length (21) to the lower outer terminal distance (142) is less than about 4. [22] Multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136) and wherein the capacitor (100) comprises a top surface (18) and a bottom surface (20) opposite the top surface (18) in the Z-direction (136), wherein the multilayer broadband ceramic capacitor (100) comprises: a monolithic body comprising a multitude of dielectric layers stacked in the Z direction (136); a multitude of active electrodes (106, 108) arranged within the monolithic body; a first outer terminal (118) located along the first end (119), wherein the first outer terminal (118) comprises a bottom part (138) extending along the bottom surface (20) of the capacitor (100); a second outer terminal (120) located along the second end (121), wherein the second outer terminal (120) comprises a bottom part (140) extending along the bottom surface (20) of the capacitor (100), wherein the bottom part (138) of the first outer terminal (118) and the bottom part (140) of the second outer terminal (120) are spaced apart longitudinally (132) by a bottom-outer terminal distance (142); a lower shielding electrode (22) which is arranged within the monolithic body between the plurality of active electrodes (106, 108) and the bottom surface (20) of the capacitor (100), where: the lower shielding electrode (22, 24) is connected to the first outer terminal (118); the lower shielding electrode (22, 24) has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the lower shielding electrode (22, 24) has a second longitudinal edge (30) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) relative to the first longitudinal edge (28).

Images