Multilayer ceramic capacitor with ultra-wideband performance and manufacturing process

Abstract

Multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136) and wherein the capacitor (100) comprises a top surface (18) and a bottom surface (20) opposite the top surface (18) in the Z-direction (136), wherein the multilayer broadband ceramic capacitor (100) comprises: a monolithic body comprising a plurality of dielectric layers (10) stacked in the Z direction (136); a first outer connection (118) that runs along the first end (119); a second outer connection (120) that runs along the second end (121); a multitude of active electrodes (106, 108) arranged within the monolithic body; an upper shielding electrode (22, 24) arranged within the monolithic body and located between the plurality of active electrodes (106, 108) and the upper surface (18) of the capacitor (100), wherein the upper shielding electrode (22, 24) is spaced apart from the upper surface (18) of the capacitor (100) by an upper-shielding-top distance; a lower shielding electrode (22, 24) arranged within the monolithic body and located between the plurality of active electrodes and the bottom surface (20) of the capacitor (100), wherein the lower shielding electrode (22, 24) is spaced apart from the bottom surface (20) of the capacitor (100) by a lower-shielding-bottom distance; where: The ratio of the upper shielding top distance to the lower shielding bottom distance is between approximately 0.8 and approximately 1.2; The distance between the lower shield and the ground is in a range of approximately 8 µm to approximately 100 µm. the lower shielding electrode (22, 24) is connected to the first outer terminal (118); the lower shielding electrode (22, 24) has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the lower shielding electrode (22, 24) has a second longitudinal edge (30) which is oriented in the lateral direction (134) and faces away from the first outer terminal (118); and the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) relative to the first longitudinal edge (28).

Description

Background of the invention

[0001] The diversity of modern technical applications creates a need for efficient electronic components and the integrated circuits in which they are used. Capacitors are a fundamental component used for filtering, coupling, bypassing, and other aspects of such modern applications, which include wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many others. A dramatic increase in the speed and packing density of integrated circuits necessitates advances in coupling capacitor technology. When high-capacitance coupling capacitors are subjected to the high clock frequencies of many current applications, performance characteristics become increasingly critical. Because capacitors are fundamental to such a wide range of applications, their precision and efficiency are essential.Many specific aspects of capacitor design are therefore the focus for improving their performance characteristics.

[0002] US 2018 / 0374646A1 discloses a multilayer ceramic coupling capacitor with low insertion loss over a broadband frequency range. This multilayer ceramic capacitor (MLCC) comprises a body with a top and bottom surface, a first and second opposite end, and an electrode and dielectric layer. The MLCC also includes a first and second terminal attached to the ends, and main block layer electrodes within the body, which are alternately configured such that a first main electrode is electrically connected to the first terminal and extends inward from one end, and a next main electrode is electrically connected to the second terminal and extends inward from an opposite end.

[0003] US 2012 / 0 297 596 A1 discloses a method for manufacturing a ceramic multilayer component in which a ceramic capacitor body is formed from electrode layers and dielectric layers. A first and a second external terminal are attached to opposite ends of the ceramic capacitor body. The ceramic capacitor body is coated to increase the breakdown voltage.

[0004] US 2010 / 0039749A1 discloses a device and a method for manufacturing one or more secondary capacitors in a monolithic body that already contains a first, larger capacitor to create ultra-wideband structures. Alternating electrode layers are provided with arm sections that enclose portions of adjacent electrode layers to generate additional coupling effects within the capacitor structure, thereby creating multiple additional equivalent capacitor structures within the device. Brief description of the invention

[0005] According to the invention, a multilayer broadband ceramic capacitor is provided, comprising a first end and a second end spaced from the first end in a longitudinal direction perpendicular to a lateral direction. The lateral direction and the longitudinal direction each extend perpendicular to a Z-direction, the capacitor comprising a top surface and a bottom surface oriented opposite the top surface in the Z-direction. According to the invention, the multilayer broadband ceramic capacitor further comprises a monolithic body containing a plurality of dielectric layers stacked in the Z-direction. The multilayer broadband ceramic capacitor further comprises a first outer terminal extending along the first end and a second outer terminal extending along the second end.The multilayer broadband ceramic capacitor further comprises a plurality of active electrodes arranged within the monolithic body. According to the invention, the multilayer broadband ceramic capacitor also comprises an upper shielding electrode arranged within the monolithic body and located between the plurality of active electrodes and the upper surface of the capacitor. The first shielding electrode is spaced a distance of [insert value here] from the upper surface of the capacitor. The multilayer broadband ceramic capacitor further comprises a lower shielding electrode arranged within the monolithic body and located between the plurality of active electrodes and the bottom surface of the capacitor. The lower shielding electrode is spaced a distance of [insert value here] from the bottom surface of the capacitor.The ratio of the upper shielding top distance to the lower shielding bottom distance is between approximately 0.8 and approximately 1.2. The lower shielding bottom distance is in the range of approximately 8 µm to approximately 100 µm.

[0006] The invention also discloses a method for forming a multilayer broadband ceramic capacitor. The multilayer broadband ceramic capacitor has a first end and a second end, the latter being spaced from the first end in a longitudinal direction perpendicular to a lateral direction. The lateral direction and the longitudinal direction each extend perpendicular to a Z-direction. The capacitor comprises a top surface and a bottom surface, the latter oriented opposite the top surface in the Z-direction.The process comprises: forming a plurality of active electrodes on a plurality of active electrode layers; forming an upper shielding electrode on an upper shielding electrode layer; forming a lower shielding electrode on a lower shielding electrode layer; and stacking the plurality of active electrode layers, the upper shielding electrode layer, and the lower shielding electrode layer with a plurality of dielectric layers to form a monolithic body; forming a first external terminal at a first end of the monolithic body; and forming a second external terminal at a second end of the monolithic body. The upper shielding electrode layer is located within the monolithic body and is situated between the plurality of active electrode layers and the upper surface of the capacitor.The upper shielding electrode is spaced from the top surface of the capacitor by a top-shield-top distance. The lower shielding electrode layer is arranged within the monolithic body and is located between the plurality of active electrodes and the bottom surface of the capacitor. The lower shielding electrode is connected to the first outer terminal and has a first longitudinal edge oriented laterally and facing away from the first outer terminal. The lower shielding electrode also has a second longitudinal edge oriented laterally and facing away from the first outer terminal, the second longitudinal edge being offset longitudinally from the first longitudinal edge by a shielding-electrode-offset distance. The lower shielding electrode layer may be spaced from the bottom surface of the capacitor by a bottom-shield-bottom distance.The ratio of the top-shield distance to the bottom-shield distance can be between approximately 0.8 and approximately 1.2. The bottom-shield distance can be in a range of approximately 8 µm to approximately 100 µm. Brief description of the drawings

[0007] A full and instructive disclosure of the present invention, including the best way to implement it for the person skilled in the art, is set out in particular in the remainder of the description; this includes a reference to the accompanying drawings, and the following applies: Fig. 1A shows a top view of an embodiment of an active electrode layer according to aspects of the present disclosure; Fig. Figure 1B shows a perspective view of alternating electrode layers, as shown in Fig. 1A is shown to be configured according to aspects of the present disclosure; Fig. 1C shows a top view of the embodiment of the active electrode layer of Fig. 1A, in which several capacitive areas are formed according to aspects of the present revelation; Fig. Figure 1D shows a top view of the embodiment of a shielding electrode layer in which several capacitive areas are formed according to aspects of the present disclosure; Fig. Figure 1E shows a side cross-sectional view of an embodiment of a capacitor comprising several regions in which active electrode layers are configured as described in the Fig. 1A to 1C is shown, and a shielding electrode layer is configured as shown in Fig. 1C is shown, according to aspects of the present revelation; Fig. Figure 2A shows a top view of another embodiment of an active electrode layer according to aspects of the present disclosure; Fig. 2B shows a top view of the embodiment of the active electrode layer of Fig. 2A, in which several capacitive areas are formed according to aspects of the present revelation; Fig. Figure 2C shows a perspective view of alternating electrode layers, as seen in Fig. 2A is shown, configured according to aspects of the present disclosure; Fig. Figure 3 shows a schematic representation of a circuit of the embodiment of a capacitor, which is located in the Fig. 1A to 1E is shown, with multiple capacitive areas; Fig. Figure 4 shows a schematic representation of a circuit of the embodiment of a capacitor, which is located in the Fig. 2A to 2C is shown, with several capacitive areas; Fig. Figure 5 shows a side cross-sectional view of an embodiment of a capacitor of the present invention; Fig. Figures 6A to 6D show top views of the armature electrodes, shielding electrodes, and active electrodes of the capacitor. Fig. 5 according to an embodiment of the present invention; The Fig. Figures 7A to 7D show top views of additional embodiments of active electrode layers according to certain embodiments of the present invention. Detailed description of preferred embodiments

[0008] The person skilled in the art should be aware that the present discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0009] In general terms, the present invention relates to a multilayer ceramic capacitor. The multilayer ceramic capacitor contains alternating dielectric layers and electrode layers within a single monolithic body. The capacitor comprises a plurality of active electrodes, an upper shielding electrode, and a lower shielding electrode, all arranged within the monolithic body. The upper shielding electrode is located between the plurality of active electrodes and an upper face of the capacitor and is spaced from the upper face of the capacitor by a distance equal to the top shielding distance. The lower shielding electrode is located between the plurality of active electrodes and a bottom face of the capacitor and is spaced from the bottom face of the capacitor by a distance equal to the bottom shielding distance.

[0010] According to the invention, the ratio of the upper shielding top distance to the lower shielding bottom distance is in a range of about 0.8 to about 1.2, can be about 0.9 to about 1.1 in some embodiments, about 0.95 to about 1.05 in some embodiments and about 0.98 to about 1.02 in some embodiments.

[0011] According to the invention, the lower shielding-ground distance is in a range of about 8 µm to about 100 µm, can in some embodiments be from about 9 µm to about 75 µm, in some embodiments from about 10 µm to about 65 µm and in some embodiments from about 11 µm to about 30 µm.

[0012] The inventors have discovered that such spacing can ensure low insertion loss for a multilayer ceramic capacitor over a wide frequency range. Insertion loss is generally the power loss through the capacitor and can be measured using any method commonly known in engineering.

[0013] For example, the insertion loss may be approximately -0.3 dB or more, such as -0.28 dB or more, such as -0.25 dB or more, such as -0.23 dB or more, when measured over a frequency range from 4 GHz to 10 GHz.

[0014] The insertion loss can be approximately -0.4 dB or more, such as -0.38 dB or more, such as -0.35 dB or more, such as -0.34 dB or more, when measured over a frequency range of 13 GHz to 20 GHz.

[0015] The insertion loss can be approximately -0.45 dB or more, such as -0.4 dB or more, such as -0.38 dB or more, such as -0.35 dB or more, such as -0.32 dB or more, when measured over a frequency range of 23 GHz to 30 GHz.

[0016] The insertion loss can be approximately -0.55 dB or more, such as -0.5 dB or more, such as -0.48 dB or more, such as -0.45 dB or more, such as -0.43 dB or more, when measured over a frequency range from 33 GHz to 40 GHz.

[0017] The bottom-shield-to-ground distance can be defined as the distance between the shielding electrodes and the bottom surface of the capacitor. If multiple shielding electrode layers are present, the bottom-shield-to-ground distance can be defined as the distance between the lowest of the shielding electrode layers and the bottom surface. The ratio of the capacitor thickness to the bottom-shield-to-ground distance can be greater than approximately 3, greater than approximately 5 in some embodiments, greater than approximately 10 in some embodiments, greater than approximately 15 in some embodiments, greater than approximately 20 in some embodiments, and greater than approximately 40 in some embodiments.The lower shielding-ground distance is in a range of about 8 µm to about 100 µm, can in some embodiments be from about 8 µm to about 75 µm, in some embodiments from about 8 µm to about 60 µm and in some embodiments from about 8 µm to about 30 µm.

[0018] The capacitor can comprise multiple electrode regions, including an active electrode region, an upper shielding electrode region, and a lower shielding electrode region. The active electrodes can be located within the shielding electrode region. The upper shielding electrode can be located within the upper shielding electrode region. The lower shielding electrode can be located within the lower shielding electrode region.

[0019] The ratio of the thickness of the area of ​​the upper shielding electrodes in the Z-direction to the thickness of the area of ​​the lower shielding electrode in the Z-direction can be in a range of about 0.8 to about 1.2, in some embodiments about 0.9 to about 1.1, in some embodiments about 0.95 to about 1.05 and in some embodiments about 0.98 to about 1.02.

[0020] The capacitor comprises a first outer terminal running along one end of the capacitor and a second outer terminal running along the other end. An additional lower shielding electrode may be approximately aligned with the first outer terminal in the Z-direction. The first outer terminal is connected to the first outer terminal, and the additional lower shielding electrode may be connected to the second outer terminal.

[0021] The lower shielding electrode has a first longitudinal edge and a second longitudinal edge, each oriented laterally and facing away from the first outer terminal. The second longitudinal edge is offset longitudinally from the first longitudinal edge by a shielding electrode offset distance. In some embodiments, however, one or more of the shielding electrodes may be rectangular without any step features. Furthermore, one or more of the upper shielding electrode(s) may be symmetrical laterally about a longitudinal center line extending in the longitudinal direction.

[0022] The additional lower shielding electrode is connected to the second outer terminal and can be approximately aligned with the lower shielding electrode in the Z-direction. The first longitudinal edge is oriented laterally and faces away from the first outer terminal, and a second longitudinal edge is oriented laterally and faces away from the second outer terminal. The second longitudinal edge is offset longitudinally from the first longitudinal edge by approximately the shielding electrode offset distance.

[0023] A first shielding gap can be formed longitudinally between the first longitudinal edge of the first shielding electrode and the first longitudinal edge of the second shielding electrode. The capacitor can have a length in the longitudinal direction between its first end and its second end. The ratio of the capacitor length to the first shielding gap can be greater than approximately 2, in some embodiments greater than approximately 3, in some embodiments greater than approximately 4, in some embodiments greater than approximately 5, in some embodiments greater than approximately 10, in some embodiments greater than approximately 15, in some embodiments greater than approximately 20, and in some embodiments greater than approximately 50.

[0024] A second shielding gap can be formed longitudinally between the second longitudinal edge of the lower shielding electrode and the second longitudinal edge of the additional lower shielding electrode. The ratio of the capacitor length to the second shielding gap can be greater than approximately 2, in some embodiments greater than approximately 3, in some embodiments greater than approximately 4, in some embodiments greater than approximately 5, in some embodiments greater than approximately 10, in some embodiments greater than approximately 15, in some embodiments greater than approximately 20, and in some embodiments greater than approximately 50.

[0025] The first shielding gap distance and / or the second shielding gap distance can be in a range of about 10 µm to about 200 µm, in some embodiments from about 20 µm to about 150 µm and in some embodiments from about 30 µm to about 80 µm.

[0026] The shielding electrode offset distance can be in a range of approximately 75 µm to approximately 300 µm, in some embodiments from approximately 100 µm to approximately 250 µm and in some embodiments from approximately 125 µm to approximately 175 µm.

[0027] The multilayer broadband ceramic capacitor can have a capacitor thickness in the Z-direction between the top and bottom surfaces. The ratio of the capacitor thickness to the thickness of the upper shielding electrode region in the Z-direction can range from approximately 2.0 to approximately 20, in some embodiments from approximately 2.2 to approximately 10, in some embodiments from approximately 2.5 to approximately 7, in some embodiments from approximately 2.7 to approximately 6, and in some embodiments from approximately 3 to approximately 5. The ratio of the capacitor thickness to the thickness of the lower shielding electrode region in the Z-direction can range from approximately 2.1 to approximately 20, in some embodiments from approximately 2.2 to approximately 10, in some embodiments from approximately 2.5 to approximately 7, in some embodiments from approximately 2.7 to approximately 6, and in some embodiments from approximately 3 to approximately 5.

[0028] The ratio of the capacitor thickness to the thickness of the area of ​​the active electrodes can be in a range of about 1.1 to about 20, in some embodiments about 1.5 to about 15, in some embodiments about 1.7 to about 12, in some embodiments about 2 to about 10 and in some embodiments about 3 to about 7.

[0029] In general, a capacitor comprises alternating dielectric layers and electrode layers that form at least part of the capacitor's monolithic body. By arranging the dielectric and electrode layers in a stacked or laminated configuration, the capacitor can be called a multilayer capacitor, and in particular a multilayer ceramic capacitor, for example, when the dielectric layers comprise a ceramic.

[0030] The shielding electrode region can have a thickness in the Z-direction. The thickness of the shielding electrode region can be defined between the base surface of the capacitor and the lowest electrode layer of the plurality of active electrodes. The ratio of the capacitor thickness to the thickness of the shielding electrode region can be in the range of approximately 1.1 to approximately 20, in some embodiments approximately 1.5 to approximately 10, and in some embodiments approximately 1.7 to approximately 5. I. Exemplary embodiments

[0031] If we look at the Fig. Turning to 1A-1E, an embodiment of a multilayer ceramic capacitor 100 is disclosed. Fig. Figure 1E is a simplified side view of the multilayer capacitor 100 mounted on a mounting surface 101, such as a printed circuit board or a substrate. The multilayer capacitor 100 comprises a plurality of electrode regions 10 stacked in the Z-direction 136. The plurality of electrode regions 10 includes an active electrode region 14, an upper shielding electrode region 12, and a lower shielding electrode region 16. The active electrode region 14 may be located between the upper shielding electrode region 12 and the second electrode region 16.

[0032] In some embodiments, the capacitor 160, or a portion thereof, can be symmetrical about a longitudinal centerline 167 extending in the longitudinal direction. For example, the shielding electrodes 22, 24 of the lower shielding electrode region 12 can be symmetrical about the longitudinal centerline 166 with respect to the shielding electrodes 22, 24 of the lower shielding electrode region 16. In other words, the distance between the shield and the bottom surface 63 can be approximately equal to the distance from the shield to the upper surface 168, which can be defined between the shielding electrodes 22, 24 of the lower shielding electrode region 16 and the upper surface 18 of the capacitor 100. The ratio of the distance between the shield and the bottom surface 63 to the distance from the shield to the upper surface 168 is in a range of about 0.8 to about 1.2.

[0033] The electrode regions 10 comprise a variety of dielectric layers. Some dielectric layers may include electrode layers formed on them. In general, the thickness of the dielectric and electrode layers is not restricted and can be any desired thickness depending on the performance characteristics of the capacitor. For example, the thickness of the electrode layers, without limitation, can be approximately 500 nm or more, such as 1 µm or more, such as 2 µm or more, such as 3 µm or more, such as 4 µm or more to approximately 10 µm or less, such as 5 µm or less, such as 4 µm or less, such as 3 µm or less, such as 2 µm or less. For example, the electrode layers can have a thickness of approximately 1 µm to approximately 2 µm. Furthermore, in one embodiment, the thickness of the dielectric layer can be defined according to the thickness of the electrode layers mentioned above.Furthermore, it should be noted that this thickness of the dielectric layers may also apply to the layers between the active electrode layers and / or the shielding electrode layers, if they are present and as defined here.

[0034] In general, the present invention provides a multilayer capacitor with an electrode having a unique configuration which offers various benefits and advantages. In this regard, it should be understood that the materials used in the construction of the capacitor are not limited and can be any materials generally used in the art, and can be formed using any method generally used in the art.

[0035] In general, the dielectric layers are typically formed from a material that has a relatively high dielectric constant (K), such as about 10 to about 40,000, in some embodiments about 50 to about 30,000 and in some embodiments about 100 to about 20,000.

[0036] In this respect, the dielectric material can be a ceramic. The ceramic can be provided in a variety of forms, such as a wafer (e.g., pre-fired), or as a dielectric material that is fired within the device itself.

[0037] Specific examples of materials with high dielectric constants include NPO (COG) (up to about 100), X7R (about 3000 to about 7000), X7S, Z5U, and / or Y5V. It should be understood that the materials mentioned above are described according to their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA), and as such, they should be recognized by those skilled in the art. For example, such a material may include a ceramic. Such materials may include a perovskite, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconatit titanate, barium strontium zirconatit titanate, barium calcium zirconatit titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconatit titanate, lead anthanasia zirconatit titanate), sodium bismuth titanate, etc.In a particular embodiment, for example, barium strontium titanate (“BSTO”) of the formula Ba. x Sr 1-x TiO3 can be used, where x = 0 to 1, in some embodiments approximately 0.15 to approximately 0.65, and in some embodiments approximately 0.25 to approximately 0.6. Other suitable perovskites include, for example, Ba x Approx 1-x TiO3, where x is approximately 0.2 to approximately 0.8 and in some embodiments approximately 0.4 to approximately 0.6, Pb x Zr 1-x TiO3 (“PZT”), where x is in the range of about 0.05 to about 0.4, lead anthanizirconium titanate (“PLZT”), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Further complex perovskites can include A[B1 1 / 3 B2 2 / 3 ]O3 materials, where A = Ba x Sr 1-x is (x can be a value from 0 to 1); B1 = Mg y Zn 1-yis (y can be a value from 0 to 1); B2 = Ta z Note 1-z is (z can be a value from 0 to 1). In a particular embodiment, the dielectric layers can comprise a titanate.

[0038] The electrode layers can be formed from a variety of materials, as is known in engineering. The electrode layers can consist of a metal, such as a conductive metal. The materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as sputtered layers of chromium, nickel, and gold, can also be suitable. The electrodes can also be formed from a low-resistance material, such as silver, copper, gold, aluminum, palladium, etc. In a particular embodiment, the electrode layers can comprise nickel or an alloy thereof.

[0039] If we turn again to Fig. Referring to 1E, the plurality of active electrode layers 102, 104 can be arranged within the active electrode region 14. Each active electrode layer 102, 104 can comprise one or more active electrodes, as shown below, for example, with regard to the Fig. 1A to 1C is described. For example, in some embodiments, each active electrode layer 102, 104 can comprise a third electrode 106 and a second electrode 108.

[0040] The lower shielding electrode area 16 can comprise one or more shielding electrodes, as shown below, for example, in relation to Fig. 1D is described. For example, the lower shielding electrode region 16 can include a first shielding electrode 22, which is arranged within a monolithic body of the capacitor 100. The first shielding electrode 22 can run parallel to the longitudinal direction 132. The first shielding electrode 22 is connected to a first outer terminal 118. The lower shielding electrode region 16 includes a second shielding electrode 24, which can be connected to the second outer terminal 120. The second shielding electrode 24 can be aligned approximately with the first shielding electrode 22 in the Z-direction 136.

[0041] The first outer terminal 118 can be connected to the first electrode 106 of a first electrode layer 102 and to a second (counter) electrode 108 of the second electrode layer 104. The second outer terminal 120 can be connected to the first electrode 106 of the second electrode layer 104 and to the second (counter) electrode 108 of the first electrode layer 102.

[0042] The dielectric material of the monolithic body of the capacitor 100 can be exposed along the base surface 20 of the capacitor 100 between the base part 138 of the first outer terminal 118 and the base part 140 of the second outer terminal 120. Likewise, the dielectric material of the monolithic body of the capacitor 100 can be exposed between the upper part 144 of the first outer terminal 118 and the upper part 146 of the second outer terminal 120.

[0043] In general, with regard to the embodiments discussed here, the external terminals can be made of a variety of different metals, as is known in the art. The external terminals can be made of a single metal, such as a conductive metal. The materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and so on, as well as various combinations thereof. In one particular embodiment, the external terminals can comprise copper or an alloy thereof.

[0044] The external connections can be formed using any method generally known in engineering. These include techniques such as sputtering, painting, printing, electroless deposition or copper refining (FCT), electroplating, plasma deposition, blowing agent spraying / airbrushing, and so on.

[0045] In one embodiment, the outer terminals can be designed to be relatively thick. For example, such terminals can be formed by depositing a thick film strip of metal onto exposed parts of electrode layers (e.g., by immersing the capacitor in a liquid outer terminal material). Such a metal can be in a glass matrix and can include silver or copper. As an example, such a strip can be printed and fired onto the capacitor. Subsequently, additional metal deposition layers (e.g., nickel, tin, solder, etc.) can be created over the terminal strip so that the capacitor can be soldered onto a substrate. Such an application of thick film strips can be achieved using any method generally known in the art (e.g.,by means of a connecting machine and a pressure wheel for transferring a metal-loaded paste over the exposed electrode layers).

[0046] The thickly deposited outer terminals can have an average thickness of approximately 150 µm or less, such as approximately 125 µm or less, such as approximately 100 µm or less, such as approximately 80 µm or less. The thickly deposited outer terminals can have an average thickness of approximately 25 µm or more, such as approximately 35 µm or more, such as approximately 50 µm or more, such as approximately 75 µm or more. For example, the thickly deposited outer terminals can have an average thickness of approximately 25 µm to approximately 150 µm, such as from approximately 35 µm to approximately 125 µm, such as from approximately 50 µm to approximately 100 µm.

[0047] In another embodiment, the outer terminals can be configured such that the outer terminal is a thin-film deposition of a metal. Such a thin-film deposition can be formed by depositing a conductive material, such as a conductive metal, onto an exposed portion of an electrode layer. For example, a leading edge of an electrode layer can be exposed to allow the formation of a coated terminal.

[0048] The thinly deposited outer connections can have an average thickness of approximately 50 µm or less, such as approximately 40 µm or less, such as approximately 30 µm or less, such as approximately 25 µm or less. The thinly deposited outer connections can have an average thickness of approximately 5 µm or more, such as approximately 10 µm or more, such as approximately 15 µm or more. For example, the outer connections can have an average thickness of approximately 5 µm to approximately 50 µm, such as from approximately 10 µm to approximately 40 µm, such as from approximately 15 µm to approximately 30 µm, such as from approximately 15 µm to approximately 25 µm.

[0049] In general, the outer terminal can include a deposited terminal. For example, the outer terminal can include an electroplated terminal, a electroless deposited terminal, or a combination thereof. For example, an electroplated terminal can be formed by electrolytic deposition. An electroless deposited terminal can be formed by electroless deposition.

[0050] If multiple layers form the outer terminal, the outer terminal can include an electroplated terminal and an electroless deposited terminal. For example, electroless deposition can be used first to deposit an initial layer of material. Then, the deposition technique can be switched to an electrochemical deposition system, which allows for faster material build-up.

[0051] When the deposited terminals are formed using one of the two deposition methods, a leading edge of the terminal tabs of the electrode layers, which protrudes from the main body of the capacitor, is exposed to a deposition solution. In one embodiment, the capacitor can be immersed in the deposition solution during this exposure.

[0052] The deposition solution contains a conductive material, such as a conductive metal, and is used to form the deposited terminal. Such a conductive material can be one of the materials mentioned previously or one commonly known in the trade. For example, the deposition solution can be a nickel sulfamate bath solution or another nickel solution, so that the deposited layer and the outer terminal comprise nickel. Alternatively, the deposition solution can also be a copper acid bath or another suitable copper solution, so that the deposited layer and the outer terminal comprise copper.

[0053] Furthermore, it should be noted that the deposition solution may also include other additives, as is generally known in the art. For example, the additives may include other organic additives and media that can support the deposition process. Additives may also be used to adjust the deposition solution to a desired pH value. In one embodiment, resistance-reducing additives may be included in the solutions to promote complete coverage of the deposit and adhesion of the deposit materials to the capacitor and the exposed leading edges of the terminal tabs.

[0054] The capacitor can be treated, submerged, or immersed in the deposition solution for a predetermined period of time. This exposure time is not necessarily limited, but it can be long enough to allow sufficient deposition material to form the coated terminal. In this respect, the time should be sufficient to allow the formation of a permanent bond between the desired exposed, adjacent leading edges of terminal tabs of a given polarity of the respective electrode layers within a set of alternating dielectric and electrode layers.

[0055] In general, the difference between electroplating and electroless plating is that electroplating uses an electrical bias voltage, as when using an external current source. The electroplated solution can typically withstand a high current density range, for example, ten to fifteen amperes per foot. 2 (rated at 9.4 volts). A connection can be formed with a negative connection to the capacitor, requiring the formation of the deposited terminals and a positive connection to a solid material (e.g., copper in copper plating solution) in the same deposition solution. That is, the capacitor is biased to a polarity opposite to that of the deposition solution. Using this method, the conductive material of the deposition solution is attracted to the metal of the exposed leading edge of the electrode layer terminals.

[0056] Several pretreatment steps can be employed before immersing or treating the capacitor in a deposition solution. Such steps can be performed for various purposes, including catalyzing, accelerating, and / or improving the adhesion of the deposition materials to the leading edges of the terminal tabs.

[0057] Furthermore, an initial cleaning step can be employed prior to deposition or any other pretreatment steps. Such a step can be used to remove any oxide adhesion that forms on the exposed terminals of the electrode layers. This cleaning step can be particularly helpful in aiding the removal of nickel oxide adhesion when the internal electrodes or other conductive elements are made of nickel. Component cleaning can be performed by full immersion in a pre-cleaning bath, such as one containing an acid cleaner. In one embodiment, the immersion can be carried out for a predetermined time, on the order of about 10 minutes. Alternatively, cleaning can be performed by chemical polishing or harperization steps.

[0058] Furthermore, a step can be performed to activate the exposed metallic leading edges of the electrode layer tabs to facilitate the deposition of the conductive materials. Activation can be achieved by immersion in palladium salts, photostructured metal-organic palladium precursors (via mask or laser), screen-printed or inkjet-deposited palladium compounds, or electrophoretic palladium deposition. It should be noted that palladium-based activation is currently disclosed only as one example of activation solutions, which often work well in conjunction with activation for exposed tab parts made of nickel or an alloy thereof. However, it should be understood that other activation solutions can also be used.

[0059] Furthermore, instead of or in addition to the activation step mentioned above, the activating dopant can be introduced into the conductive material when the capacitor's electrode layers are formed. For example, if the electrode layer comprises nickel and the activating dopant comprises palladium, the palladium dopant can be introduced into the nickel ink or composition forming the electrode layers. This can eliminate the need for the palladium activation step. It should also be noted that some of the activation methods described above, such as metal-organic precursors, are also suitable for co-deposition with glass formers for increased adhesion to the generally ceramic body of the capacitor.When activation steps are performed as described above, traces of the activator material often remain on the exposed conductive parts before and after the connection deposition.

[0060] Additionally, post-treatment steps can be employed after deposition. Such steps can be performed for a variety of purposes, including strengthening and / or improving the adhesion of the materials. For example, a heating (or tempering) step can be used after the deposition step. This heating can be carried out by burning, laser treatment, UV irradiation, microwave irradiation, arc welding, etc.

[0061] As already mentioned, the outer connection can comprise at least one deposit layer. In one embodiment, the outer connection can comprise only one deposit layer. However, it should be understood that the outer connections can comprise a plurality of deposit layers. For example, the outer connections can comprise a first deposit layer and a second deposit layer. Furthermore, the outer connections can also comprise a third deposit layer. The materials of these deposit layers can be any of those mentioned above and any materials generally known in the art.

[0062] For example, a deposit layer, such as a first deposit layer, can comprise copper or an alloy thereof. Another deposit layer, such as a second deposit layer, can comprise nickel or an alloy thereof. Another deposit layer, such as a third deposit layer, can comprise tin, lead, gold, or a combination thereof, such as an alloy. Alternatively, an initial deposit layer can comprise nickel, followed by deposit layers of tin or gold. In another embodiment, an initial deposit layer of copper can be formed, followed by a nickel layer.

[0063] In one embodiment, the initial or first deposition layer can consist of a conductive metal (e.g., copper). This area can then be covered with a second layer containing a polymeric resistive material for sealing. The area can then be polished to selectively remove the polymeric resistive material and subsequently metallized again with a third layer containing a conductive metallic material (e.g., copper).

[0064] The second layer mentioned above, located above the initial deposition layer, can correspond to a solder barrier layer, for example, a nickel solder barrier layer. In some embodiments, the aforementioned layer can be formed by electroplating an additional layer of metal (e.g., nickel) over an initial electroless deposited or electroplated layer (e.g., deposited copper). Other exemplary materials for the aforementioned solder barrier layer are nickel-phosphorus, gold, and silver. A third layer on the aforementioned solder barrier layer can, in some embodiments, correspond to a conductive layer, such as deposited Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable deposited solder metal.

[0065] Furthermore, a deposit layer can be formed, followed by an electroplating step to obtain a resistance alloy or a metal alloy with higher resistance, for example, an electroless deposited Ni-P alloy over such a deposit. However, it should be understood that it is possible to use any metal coating, as the person skilled in the art will understand from the present complete disclosure.

[0066] It should be understood that each of the above-mentioned steps can be performed as a batch process, such as drum deposition, fluidized bed deposition, and / or flow deposition finishing processes, all of which are well-known in engineering. Such batch processes allow for the simultaneous processing of multiple components, resulting in an efficient and rapid finishing process. This is a significant advantage over conventional finishing methods, such as thick-film terminal printing, which requires individual processing of each component.

[0067] As described here, the formation of the outer terminals is generally determined by the position of the exposed leading edges of the electrode layer terminal tabs. Such phenomena can be described as "self-determining" because the formation of the outer metallized terminals is determined by the configuration of the exposed conductive metal of the electrode layers at selected peripheral locations on the capacitor. In some embodiments, the capacitor may include dummy tabs to provide exposed conductive metal along portions of the monolithic body of the capacitor that do not include other electrodes (e.g., active or shielding electrodes).

[0068] It should be noted that additional techniques for forming capacitor terminals may also fall within the scope of this technology. Exemplary alternatives include, but are not limited to, the formation of terminals by deposition, magnetism, masking, electrophoresis / electrostatics, sputtering, vacuum deposition, printing, or other techniques for forming conductive thick and thin films.

[0069] Fig. Figure 1A shows a top view of an embodiment of an active electrode configuration for one or more electrodes in the active electrode region 14 according to aspects of the present disclosure. In particular, the active electrode region 14 can comprise first electrode layers 102 and second electrode layer 104 in an alternating arrangement, as is shown, for example, below with respect to Fig. 1B is described. If we look at Fig. Referring to 1A, each electrode layer 102, 104 can comprise a third electrode 106 and a second electrode 108. The first electrode 106 can have a base part 114 extending along a longitudinal edge of the first electrode 106 in the lateral direction 134. The first electrode 106 can have a pair of electrode arms 110 extending from a base part 114 in the longitudinal direction 132. The second electrode 108 can have a base part 114 extending along a longitudinal edge of the second electrode 108 in the lateral direction 134. The second electrode 108 can have a pair of electrode arms 110 extending from the base part 114 in the longitudinal direction 132.

[0070] The electrode arm or arms 110 of the first electrode 106 can be substantially longitudinally aligned with respect to the electrode arm or arms 110 of the second electrode 108. An arm gap or arm gaps 226 can be defined in the longitudinal direction 132 between the aligned electrode arms 110 of the first and the second electrode 106, 108.

[0071] A central edge gap 23a can be defined in the lateral direction 134 between the central part 112 of the first electrode and the second electrode arm 110. A central end gap 23b can be defined in the longitudinal direction 132 between the central part 112 of the first electrode 106 and the base part 114 of the second electrode 108. In some embodiments, the central edge gap 23a can be approximately equal to the central end gap 23b.

[0072] The central part 112 of the first electrode 106 can have a first width 27 at a first location and a second width 29 at a second location, which is larger than the first width 27. The first location of the first width 27 can be offset in the longitudinal direction 132 relative to the second location of the second width. Such a configuration makes it possible to establish an overlapping area between central parts 112 of adjacent electrodes in the Z-direction 136 without changing the central edge gap distance 23.

[0073] In Fig. 1B A plurality of first electrode layers 102 and a plurality of second electrode layers 104 can be present in an alternating mirrored configuration. As shown, for example, the central parts 112 of the respective electrode layers overlap at least partially. Fig. Figure 1B shows a total of four electrode layers; however, it should be noted that any number of electrode layers can be used to obtain the desired capacity for the intended application.

[0074] According to Fig. In 1C, several capacitive regions can form between the first electrode 106 and the second electrode 108. For example, in some embodiments, a central capacitive region 122 can form between the middle part 112 of the first electrode 106 and the base part 114 and / or the arms 128 of the second electrode 108. In some embodiments, a capacitive region 124 of the arm gap can form within the arm gap 226 between the electrode arms 110 of the first electrode 106 and the second electrode 108.

[0075] Fig. Figure 1D shows a shielding electrode layer 26. One or more shielding electrode layers 26 can be located within the upper shielding electrode area 12 and / or within the lower shielding electrode area 16 (in Fig. (1E shown) within the monolithic body of the capacitor 100. According to the above note, the first shielding electrode 22 can be parallel to the longitudinal direction 132 (e.g., parallel to the one shown in Fig. The first shielding electrode 22 has a first longitudinal edge 28, which is aligned in the lateral direction 134 and is separated from the first outer terminal 118 (in Fig. 1E) and is facing away from the first end 119. The first shielding electrode 22 has a second longitudinal edge 30, which is aligned in the lateral direction 134 and is separated from the first outer terminal (in Fig. (1E shown) and is facing away from the first end 119. The second longitudinal edge 30 is offset in the longitudinal direction 132 by a shielding electrode offset distance 32 relative to the first longitudinal edge 28.

[0076] The second shielding electrode 24 can be connected to the second outer terminal 120 (in Fig. 1E) and the second end 121. The second shielding electrode 24 can be connected in the Z-direction 136 (in Fig. (shown in Figure 1E) with the first shielding electrode 22 being approximately aligned. The second shielding electrode 24 can have a similar configuration to the first shielding electrode 22. For example, the second shielding electrode 24 can have a first longitudinal edge 28 that is aligned in the lateral direction 134 and is connected to the second outer terminal 120 (in Figure 1E). Fig. 1E) and is turned away from the second end 121. The second shielding electrode 24 can have a second longitudinal edge 30, which is oriented in the lateral direction 134 and is faced away from the second outer terminal 120 (in Fig. (1E shown) and the second end 121 is turned away. The second longitudinal edge 30 of the second shielding electrode 24 can be offset in the longitudinal direction 132 by the shielding electrode offset distance 32 relative to the first longitudinal edge 28 of the second shielding electrode 24.

[0077] A first capacitive shielding area 34 can be formed between the first longitudinal edges 28 of the first and second shielding electrodes 22, 24. A second capacitive shielding area 36 can be formed between the second longitudinal edges 30 of the first and second shielding electrodes 22, 24. In some embodiments, the width 38 of the first longitudinal edge 28 in the lateral direction 134 can be smaller than the width 40 of the first shielding electrode 22 in the lateral direction 134.

[0078] A first shielding gap 42 can be formed in the longitudinal direction 132 between the first longitudinal edge 28 of the first shielding electrode 22 and the first longitudinal edge 28 of the second shielding electrode 24. A second shielding gap 44 can be formed in the longitudinal direction 132 between the second lateral edge 30 of the first shielding electrode 22 and the second lateral edge 30 of the second shielding electrode 22.

[0079] In some embodiments, a third shielding gap 46 can be formed between a third longitudinal edge 48 of the first shielding electrode 22 and a third longitudinal edge 48 of the second shielding electrode 24. A third capacitive shielding area 51 can be formed between the third longitudinal edges 48 of the first and second shielding electrodes 119, 121. In some embodiments, the third shielding gap 46 can be approximately equal to the second shielding gap 44, so that the third capacitive shielding area 51 can have essentially the same size and shape as the second capacitive shielding area 36. For example, in some embodiments, the first shielding electrode 22 and / or the second shielding electrode 24 can be symmetrical about a longitudinal center line 50 extending in the longitudinal direction 132.

[0080] In other embodiments, however, the third shielding gap 46 can be larger or smaller than the second shielding gap 44, so that the third capacitive area 51 has a different size and / or shape than the second capacitive area 36 and produces a different capacitance than the second capacitive area.

[0081] It should be noted that in some embodiments one or more of the shielding electrodes 22, 24 may be rectangular. In other words, the shielding electrode offset distance 32 may be zero or approximately zero, so that the first longitudinal edge 28 and the second longitudinal edge 30 are aligned or approximately aligned.

[0082] The Fig. 2A and Fig. Figure 2B shows another embodiment of the first and second electrode layers 102, 104. In particular, each electrode layer 102, 104 can comprise a third electrode 106 and a second electrode 108. The first electrode 106 can have a base part 114. A pair of electrode arms 110 and at least one central part 112 can extend from the base part 114. The second electrode 108 can have a base part 114 extending along a longitudinal edge of the second electrode 108. The second electrode 108 can have a pair of electrode arms 110 extending from the base part 114. The electrode regions 12, 14, 16 can be substantially non-overlapping.

[0083] If we look at Fig. 1E, the multilayer broadband ceramic capacitor 100 can in some embodiments have a capacitor thickness 56 in the Z direction 136 between the upper surface 18 and the bottom surface 20.

[0084] The upper shielding electrode region 12 can have a first thickness of the shielding electrode region 58 in the Z-direction 136. In some embodiments, the ratio of the capacitor thickness 56 to the first thickness of the shielding electrode region 58 can be less than approximately 10.

[0085] The active electrode region 14 can have a thickness of 59 in the Z-direction 136. The active electrode region 14 can be free of shielding electrodes 22, 24 and / or can comprise only overlapping electrodes. The thickness of the active electrode region 59 can be defined between the lowest active electrode layer 19 and the highest electrode layer 65. The ratio of the capacitor thickness 56 to the thickness of the active electrode region 59 can be in a range of approximately 1.1 to approximately 20.

[0086] The lower shielding electrode region 16 can have a second thickness of the shielding electrode region 61 in the Z-direction 136. The thickness of the shielding electrode region 61 can be defined between the bottom surface 20 of the capacitor 100 and a lowest electrode layer 19 of the plurality of active electrodes. The ratio of the capacitor thickness 56 to the thickness of the shielding electrode region 61 can be in a range of approximately 1.1 to approximately 20.

[0087] In some embodiments, the distance between the shield and the base surface 63 can be defined as the distance between the shielding electrodes 22, 24 and the base surface 20 of the capacitor 100. If multiple shielding electrode layers are present, the distance between the shield and the base surface 63 can be defined as the distance between the lowest of the shielding electrode layers and the base surface 20. The ratio of the capacitor thickness 56 to the distance between the shield and the base surface 63 can be greater than approximately 2.

[0088] In some embodiments, the shielding electrodes 22, 24 of the upper shielding electrode region 12 can be spaced apart from the active electrodes 106, 108 by a first shield-to-active distance 67. The ratio of the first shield-to-active distance 67 to the distance between the shield and the base surface 63 can be in a range of about 1 to about 20, in some embodiments about 2 to about 10, and in some embodiments about 3 to about 5.

[0089] The shielding electrodes 22, 24 of the lower shielding electrode region 16 can be spaced from the active electrodes 106, 108 by a second shielding-to-active distance 169. The ratio of the second shielding-to-active distance 169 to the distance between the shielding and the upper surface 168 can be in a range of approximately 1 to approximately 20, in some embodiments approximately 2 to approximately 10, and in some embodiments approximately 3 to approximately 5. Furthermore, the ratio of the first shielding-to-active distance 67 to the second shielding-to-active distance 169 can be in a range of approximately 0.8 to approximately 1.2.

[0090] Furthermore, it shows Fig. 2A Electrode arms 110, comprising a main part 128 and a step part 130. In particular, an electrode arm 110 of the first electrode 106 can comprise a first longitudinal edge 60 extending in the lateral direction 134 and defining an edge of the step part 130. A second longitudinal edge 62 can extend in the lateral direction 134 and define an edge of the main part 128 of the arm 110. The first longitudinal edge 60 can be offset in the longitudinal direction 132 by an arm offset distance 64 relative to the second longitudinal edge 62. One or both electrode arms 110 of the first electrode 106 and / or the second electrode 108 can each comprise a main part and a step part 128, 130. For example, both arms 110 of the two electrodes 106, 108 can each comprise main parts 128 and step parts 130, as is the case, for example, in Fig. Figure 2A shows that main arm gaps 240 can occur between the step sections 130 of the aligned arms 110. Step arm gaps 242 can occur between the main sections 128 of the aligned arms 110.

[0091] If we focus on the Fig. 2B, so that between the first electrode 106 and the second electrode 108 the electrode configuration of Fig. 2A Several capacitive regions are formed. For example, in some embodiments, a central capacitive region 122 can form between the central part 112 of the first electrode 106 and the base part 114 and / or the arms 110 of the second electrode 108. In some embodiments, a capacitive region of the main arm gap 125 can form within the main arm gap 240, and a capacitive region of the step gap 126 can form within the step arm gap 242.

[0092] Fig. Figure 3 schematically shows three capacitive elements of the electrode configuration of Fig. 1C: a primary capacitive element 112' between adjacent electrode layers, a central capacitive element 122', and a capacitive arm gap element 124'. The capacitive elements 112', 122', and 124' correspond to the central region 112, the central capacitive region 122, and the capacitive arm gap region 124, respectively. Fig. 1C. Furthermore, external connections are in Fig. 4 shown as 118 and 128.

[0093] Fig. Figure 4 schematically shows four capacitive elements of the electrode configuration of Fig. 2B, in which the capacitive elements 112', 122' and 125' as well as 126' are assigned to the central area 112, the capacitive area 122, the capacitive area of ​​the main arm gap 125 and the capacitive area of ​​the step gap 126 respectively. Fig. 2B corresponds. It should be understood that the dimensions of the various columns can be specifically designed to achieve the desired respective capacity values ​​for the [in] Fig. 3 and Fig. The four capacitive elements shown can be used to achieve the desired capacitance values. In particular, the capacitor configuration and various parameters, such as the number of electrode layers, the area of ​​the overlapping central parts of electrode pairs, the distance separating the electrodes, the dielectric constant of the dielectric material, etc., can be selected to achieve the desired capacitance values. However, the capacitor as disclosed here can also include an arrangement of capacitors connected in series and parallel to provide effective broadband performance.

[0094] In an exemplary embodiment of an ultra-wideband capacitor, the primary capacitor 112' generally corresponds to a relatively large capacitance suitable for operation in a generally lower frequency range, such as on the order of between several kilohertz (kHz) and about 200 megahertz (MHz), while secondary capacitors 122', 124' and 126' generally correspond to capacitors of smaller value configured to operate in a higher frequency range, such as on the order of between about 200 megahertz (MHz) and many gigahertz (GHz).

[0095] Thus, the active electrodes can be configured to have a variety of capacitive elements within a single set of stacked electrodes. For example, a primary capacitive element may be effective at relatively low frequencies, while a secondary capacitive element (e.g., the central capacitive area 122 and / or the capacitive area 124 of the arm gap) may be effective at relatively moderate and / or high frequencies. For example, the primary capacitance may be between 1 and 500 nF, such as between approximately 10 and 100 nF, while the secondary capacitance may be between 1 and 500 pF, such as between 10 and 100 pF.

[0096] Let's consider Fig. 5. In some embodiments, the multilayer capacitor 300 may also comprise armature electrode regions 302, 304, 316, and / or 318. For example, the multilayer capacitor 300 may comprise a first armature electrode region 304 on the active electrode region 216. Furthermore, a shielding electrode region 210, containing a shielding electrode layer 214, may be located above, as on, the first armature electrode region 304. Additionally, a second armature electrode region 302 may be located above, as on, the top surface of the shielding electrode region 210. Similarly, the multilayer capacitor 300 may comprise a third armature electrode region 316 below, as directly beneath, the active electrode region 216. Furthermore, a shielding electrode region 210, containing a shielding electrode layer 214, may be located below, as directly beneath, the third armature electrode region 316.Additionally, a fourth armature electrode region 318 can be located below, as directly below, the shielding electrode region 210. In this respect, the active electrode region 216 can, for example, be located between the first armature electrode region 304 and the third armature electrode region 316. The active electrode region 216 can be configured as described above with respect to the... Fig. 1A to 1C, the Fig. 2A to 2C, or as described below with regard to the Fig. Sections 7A to 7D are described.

[0097] Let's consider the Fig. 6A, the armature electrode regions 302, 304, 316 and / or 318 can comprise a plurality of armature electrode layers 310, each having a pair of armature electrodes 312. The armature electrodes 312 can comprise a pair of electrode arms 314. Each electrode arm 314 of the armature electrodes 312 can comprise a main part 328 and a step part 330, for example, in a similar manner to that described above with respect to the electrodes of the Fig. 1A and Fig. 2 is described.

[0098] Let's consider the Fig. 6B to 6D, the anchor electrodes can have 312 different configurations. Let us consider, for example, the Fig. 6B, in some embodiments the electrode arms 314 of the armature electrodes 312 do not include a step. For example, such electrodes may be in a C-shaped configuration without a step. Let us consider the Fig. 6C, in some embodiments the electrode arms 314 of the armature electrodes 312 can comprise a step portion 320 which is displaced inwards relative to an outer lateral edge 322 of the armature electrode 312. Let us consider the Fig. 6D, in other embodiments the step part 320 can be displaced relative to an inner lateral edge 324 of the arms 314 of the armature electrodes 312. Further configurations are possible. For example, in some embodiments the step part 320 can be displaced relative to both the outer lateral edge 322 and the inner lateral edge 324.

[0099] Let's consider the Fig. 7A-7D, in some embodiments the active electrodes 106, 108 can have various other configurations. For example, consider the Fig. 7A, in some embodiments the first electrodes 106 and the second electrodes 108 can each have a single arm 110 instead of a pair of arms 110, 202, as described above in relation to Fig. as described in 1A. In this respect, such electrodes may comprise an electrode containing a central part extending away from a base part and an electrode arm also extending away from the base part; however, the counter electrode may comprise a base part and only a single electrode arm extending away from the base part of this second electrode.

[0100] Let's consider the Fig. 7B, in some embodiments the first electrodes 106 and the second electrodes 108 can each comprise central parts 112. For example, each electrode 106, 108 can, in addition to at least one electrode arm 110, 202, such as two electrode arms 110, 202 extending from the respective base part, comprise a central part 112 extending from a respective base part.

[0101] Let's consider the Fig. 7C, in some embodiments the electrode arms 110, 202 of the electrodes 106, 108 can have a step portion 130 which is displaced outwards from a lateral center line 236 of at least one of the electrodes 106, 108 of the electrode layers relative to an inner lateral edge 324 of the main part of an electrode arm. Finally, let us consider the Fig.7D, in some embodiments the electrode arms 110 of the electrodes 106, 108 may have step parts 130 which are displaced both relative to the outer lateral edge 322 and the inner lateral edge 324 of the electrode arms 110, 202. II. Test procedure

[0102] An experimental setup can be used to test performance characteristics, such as insertion loss and return loss, of a capacitor according to aspects of this disclosure. For example, the capacitor can be mounted on a test board. An input line and an output line can each be connected to the test board. The test board can include microstrip lines or test traces that electrically connect the input and output lines to the respective external terminals of the capacitor.

[0103] An input signal can be applied to the input line using a source signal generator (e.g., a Keithley 2400 series source measurement unit (SMU), such as a Keithley 2410-C SMU), and the resulting output signal of the capacitor can be measured at the output line (e.g., using the source signal generator). This was repeated for various capacitor configurations.

[0104] These and other modifications and variations of the present invention can be made by a person skilled in the art without altering the essence and scope of the present invention. Furthermore, it should be understood that aspects of the various embodiments can be exchanged in whole or in part. The person skilled in the art will also recognize that the above description is only exemplary and is not intended to further limit the invention as described in the appended claims.

Claims

[1] Multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136) and wherein the capacitor (100) comprises a top surface (18) and a bottom surface (20) opposite the top surface (18) in the Z-direction (136), wherein the multilayer broadband ceramic capacitor (100) comprises: a monolithic body comprising a plurality of dielectric layers (10) stacked in the Z direction (136); a first outer connection (118) that runs along the first end (119); a second outer connection (120) that runs along the second end (121); a multitude of active electrodes (106, 108) arranged within the monolithic body; an upper shielding electrode (22, 24) arranged within the monolithic body and located between the plurality of active electrodes (106, 108) and the upper surface (18) of the capacitor (100), wherein the upper shielding electrode (22, 24) is spaced apart from the upper surface (18) of the capacitor (100) by an upper-shielding-top distance; a lower shielding electrode (22, 24) arranged within the monolithic body and located between the plurality of active electrodes and the bottom surface (20) of the capacitor (100), wherein the lower shielding electrode (22, 24) is spaced apart from the bottom surface (20) of the capacitor (100) by a lower-shielding-bottom distance; where: The ratio of the upper shielding top distance to the lower shielding bottom distance is between approximately 0.8 and approximately 1.2; The distance between the lower shield and the ground is in a range of approximately 8 µm to approximately 100 µm. the lower shielding electrode (22, 24) is connected to the first outer terminal (118); the lower shielding electrode (22, 24) has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the lower shielding electrode (22, 24) has a second longitudinal edge (30) which is oriented in the lateral direction (134) and faces away from the first outer terminal (118); and the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) relative to the first longitudinal edge (28). [2] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the capacitor (100) has a capacitor thickness (56) in the Z direction (136) between a top surface (18) and a bottom surface (20) and wherein the ratio of the capacitor thickness (56) to the bottom-shield-bottom distance is greater than about 3. [3] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein: the capacitor (100) comprises a plurality of electrode regions (10), wherein the plurality of electrode regions comprises an active electrode region (14), an upper shielding electrode region (12) and a lower shielding electrode region (16); the multitude of active electrodes is located within the active electrode area (14); the upper shielding electrode (22, 24) is located within the upper shielding electrode area (12); and the lower shielding electrode (22, 24) is located within the lower shielding electrode area (16). [4] Multilayer broadband ceramic capacitor (100) according to claim 3, wherein the ratio of the thickness of the area of ​​the upper shielding electrodes (58) in the Z direction (136) to the thickness of the area of ​​the lower shielding electrodes (61) in the Z direction (136) is in a range of about 0.8 to about 1.

2. [5] Multilayer broadband ceramic capacitor (100) according to claim 1, further comprising an additional lower shielding electrode which is aligned approximately with the lower shielding electrode (22, 24) in the Z direction (136), wherein the lower shielding electrode (22, 24) is connected to the first outer terminal (118) and the additional lower shielding electrode is connected to the second outer terminal (120). [6] Multilayer broadband ceramic capacitor (100) according to claim 1, further comprising an additional lower shielding electrode connected to the second outer terminal (120) and aligned approximately with the lower shielding electrode (22, 24) in the Z direction (136), wherein: the additional lower shielding electrode has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the second outer terminal (120); the additional lower shielding electrode has a second longitudinal edge (30) which is oriented in the lateral direction (134) and faces away from the second outer terminal (120); and the second longitudinal edge (30) is offset in the longitudinal direction (132) approximately by the shielding electrode offset distance (32) relative to the first longitudinal edge (28). [7] Multilayer broadband ceramic capacitor (100) according to claim 6, wherein a first shielding gap distance (42) in the longitudinal direction (132) is formed between the first longitudinal edge (28) of the lower shielding electrode (22, 24) and the first longitudinal edge (28) of the additional lower shielding electrode. [8] Multilayer broadband ceramic capacitor (100) according to claim 7, wherein the capacitor (100) has a capacitor length in the longitudinal direction between the first end (119) and the second end (121) of the capacitor (100) and wherein the ratio of the capacitor length to the first shield gap distance (42) is greater than about 2. [9] Multilayer broadband ceramic capacitor (100) according to claim 6, wherein a second shielding gap (44) is formed in the longitudinal direction (132) between the second longitudinal edge (30) of the lower shielding electrode (22, 24) and the second longitudinal edge (30) of the additional lower shielding electrode. [10] Multilayer broadband ceramic capacitor (100) according to claim 9, wherein the capacitor (100) has a capacitor length in the longitudinal direction (132) between the first end (119) and the second end (121) of the capacitor (100) and wherein the ratio of the capacitor length to the second shield gap distance (44) is greater than about 2. [11] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein: the capacitor (100) has a capacitor thickness (56) in the Z-direction (136) between the upper surface (18) and the bottom surface (20); and the ratio of the capacitor thickness to the thickness of the area of ​​the upper shielding electrodes (58) in the Z direction (136) is in a range of about 2.1 to about 20. [12] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the ratio of the capacitor thickness to the thickness of the area of ​​the active electrodes (59) is in a range of about 1.1 to about 20. [13] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the lower shielding electrode (22, 24) is symmetrical in the lateral direction (134) around a longitudinal center line (167) extending in the longitudinal direction (132). [14] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein at least one of the active electrode layers (102, 104) comprises a first electrode (106) comprising a base part (114) which is electrically connected to the first outer terminal (118), wherein a first electrode arm (110) extends from the base part (114) in the longitudinal direction (132) and a central part (112) extends from the base part (114) in the longitudinal direction (132). [15] Multilayer broadband ceramic capacitor (100) according to claim 14, wherein the plurality of active electrode layers comprises a second electrode (108) which is aligned approximately with the first electrode (106) in the Z direction (136), wherein the second electrode (108) comprises a base part (114) which is electrically connected to the second outer terminal (120), and wherein a central end gap (24) is formed in the longitudinal direction (132) between the central part (122) of the first electrode (106) and the base part (114) of the second electrode (108). [16] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the capacitor (100) has an insertion loss of -0.25 dB to -0.55 dB when measured over a frequency range of 33 GHz to 40 GHz. [17] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the capacitor (100) has an insertion loss of -0.20 dB to -0.35 dB when measured over a frequency range of 23 GHz to 30 GHz. [18] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the capacitor (100) has an insertion loss of -0.15 dB to -0.40 dB when measured over a frequency range of 13 GHz to 20 GHz. [19] Multilayer broadband ceramic capacitor (100) according to claim 1, wherein the capacitor (100) has an insertion loss of -0.1 dB to -0.25 dB when measured over a frequency range of 4 GHz to 10 GHz. [20] Method for forming a multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136) and the capacitor (100) has a top surface (18) and a bottom surface (20) opposite the top surface (18) in the Z-direction (136), the method comprising: the formation of a multitude of active electrodes (106, 108) on a multitude of active electrode layers (102, 104); the formation of an upper shielding electrode (22, 24) on an upper shielding electrode layer; the formation of a lower shielding electrode (22, 24) on a lower shielding electrode layer; and the stacking of the plurality of active electrode layers (102, 104), the upper shielding electrode layer and the lower shielding electrode layer with a plurality of dielectric layers to form a monolithic body (100); the formation of a first outer connection (118) at a first end of the monolithic body (100); and the formation of a second outer connection (120) at a second end of the monolithic body (100); where: the upper shielding electrode layer is arranged within the monolithic body (100) and is located between the plurality of active electrode layers (102, 104) and the upper surface (18) of the capacitor (100), wherein the upper shielding electrode (22, 24) is spaced apart from the upper surface (18) of the capacitor (100) by an upper-shielding-top distance; the lower shielding electrode layer is arranged within the monolithic body (100) and is located between the plurality of active electrodes (106, 108) and the bottom surface (20) of the capacitor (100), the lower shielding electrode (22, 24) is connected to the first outer terminal (118), the lower shielding electrode (22, 24) has a first longitudinal edge (28) which is oriented in the lateral direction (134) and faces away from the first outer terminal (118), the lower shielding electrode (22, 24) has a second longitudinal edge (30) which is oriented in the lateral direction (134) and faces away from the first outer terminal (118); and the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shield electrode offset distance (32) relative to the first longitudinal edge (28), wherein the lower shield electrode (22, 24) is spaced apart from the bottom surface (20) of the capacitor (100) by a lower shield ground distance; The ratio of the upper shielding top distance to the lower shielding bottom distance is between approximately 0.8 and approximately 1.2: and The distance between the lower shield and the ground is in a range of approximately 8 µm to approximately 100 µm.

Images