COMPUTER SYSTEM AND PROCESSOR FOR HANDLING INSTRUCTIONS FOR ACCUMULATION OF REGISTER RESULTS IN A MICROPROCESSOR

Abstract

A computer system, a processor, and a method for processing information are disclosed, comprising at least one computer processor; a main register file associated with the at least one processor, the main register file having multiple entries for storing data, one or more write ports for writing data to the main register file entries, and one or more read ports for reading data from the main register file entries; one or more execution units, including a complex mathematical execution unit; and at least one accumulator register file having multiple entries for storing data. The results of the complex mathematical execution unit are written to the accumulator register file according to one aspect, preferably multiple times to the same accumulator register file entry, and the data from the accumulator register file are written to the main register file.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to data processing systems or computer systems, processors for handling instructions for accumulating register results in a microprocessor, and more particularly to accumulator register files in processors having accumulator registers associated with one or more complex math execution units, such as one or more matrix multiplier accumulator (MMA) units.

[0002] Processors currently used in data processing systems process more than one instruction at a time and often process these instructions non-sequentially. In modern computer architecture, several well-known approaches exist for designing a computer to execute more than one instruction at a time, or at least in the same time frame. For example, one design to improve throughput has multiple execution sections in a processor core for concurrently processing multiple instruction threads, where the threads share certain resources of the processor core. An execution section can refer to multiple data processing hardware units connected in series within a processor, like a pipeline or pipeline-like structure, for processing multiple instructions in a single processing cycle.Pipelining involves processing instructions in stages, so that several instructions are processed concurrently. Multiple execution stages can be used as part of simultaneous multithreading within a processor core.

[0003] The various time-interleaved stages may include an "instruction fetch stage" in which an instruction is read from memory. In a "decode stage," the instruction is decoded to various control bits that generally specify (i) a type of functional unit (e.g., an execution unit) to perform the operation specified by the instruction, (ii) source operands for the operation, and (iii) destinations for the results of the operation. In an "allocation stage," the decoded instruction is assigned to an issue queue (ISQ), where the instructions wait for data and an available execution unit. An instruction in the issue queue is typically issued to an execution unit in an "execute stage." The "execute stage" processes the operation as specified by the instruction.Executing an operation specified by an instruction typically involves receiving data, such as one or more operands, and providing one or more results. Register files are typically associated with the execution units and / or the issue queue to hold data and / or information for the execution units. Typically, information is read from and / or written to register files from entries or memory locations within the register file.

[0004] One approach to increasing computing throughput is to use specialized computation units, such as matrix multiplier-accumulator (MMA) units, to handle different data types and perform highly parallel tasks. Wide single-instruction multiple data (SIMD) data flows are one method for achieving high computing throughput.

[0005] In this context, document EP 0 876 026 A2 already exists. It describes crypto processing systems and associated methods. The crypto processing system has multiple processing resources integrated onto a single USLI chip. The processing systems are agile in terms of both keys and algorithms, enabling the simultaneous execution of multiple cryptographic programs. A crypto processor in conjunction with a channel program is helpful in this regard. Furthermore, there are two interface processors that allow complete isolation of readable text and encrypted data.

[0006] The inventive concept presented here is based on the task of providing a better integration of additional processors and processing units that support the main processor. SUMMARY

[0007] This problem is solved by the subject matter of the independent patent claims. Further embodiments arise from the respective dependent patent claims.

[0008] The summary of the disclosure is provided to aid in understanding a computer system, the architectural design of computers, a processor, register files including accumulator register files, and a method of using register files in a processor, and is not intended to limit the disclosure or the invention. This disclosure is directed to those of ordinary skill in the art. It is understood that different aspects and features of the disclosure may be advantageously used in some cases individually or in other cases in combination with other aspects and features of the disclosure. Accordingly, variations and modifications may be made to the computer system, the architectural design, the processor, the register files, and / or their method of operation to achieve different results.

[0009] A computer system for processing information is disclosed, the computer system comprising: at least one processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports for writing data to the main register file entries, and one or more read ports for reading data from the main register file entries; one or more execution units including a complex math execution unit; and at least one accumulator register file having a plurality of entries for storing data, the at least one accumulator register file associated with the complex math execution unit.In one or more embodiments, the processor is configured to process data in the complex math execution unit, writing the results of the complex math execution unit to the accumulator register file. In one aspect, the processor is configured to write results back to the same accumulator register file entry multiple times. In one embodiment, the processor is further configured to write data from the accumulator register file to the main register file. Preferably, the processor is configured to write data from the accumulator register file to multiple main register file entries in response to an instruction accessing a main register file entry associated with an accumulator register file.

[0010] The processor is configured, in one aspect, to enable the accumulator file registers to receive data, and in a preferred aspect, to enable the accumulator file register in response to an instruction to store data in the accumulator register file. In one embodiment, in response to enabling an accumulator register file entry, the processor marks the one or more main register file entries associated with the enabled accumulator register file as busy. The accumulator register file is preferably local to the complex math unit, and in one aspect, the complex math execution unit is a matrix-multiplier-accumulator unit (an MMA), and the accumulator register file is located in the MMA. Each entry in the accumulator register file, in one embodiment, is associated with multiple main register file entries.

[0011] In one embodiment, a processor for processing information is disclosed, the processor comprising: a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports for writing data to the main register file entries, and one or more read ports for reading data from the main register file entries; one or more execution units including a complex math execution unit; and at least one accumulator register file having a plurality of entries for storing data, the at least one accumulator register file associated with the complex math execution unit, and the bit field width of the accumulator register file being wider than the bit field width of the main register file.In one aspect, the processor is configured to process data in the complex math execution unit such that the results of the complex math execution unit are written multiple times to the same accumulator file register entry, and is configured to write data from the accumulator register file entry that has been written back multiple times to the main register file entries.

[0012] According to one aspect, a computer system for processing information is disclosed, the computer system comprising: at least one processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports for writing data to the main register file entries, and a plurality of read ports for reading data from the register file entries; one or more execution units including a complex math execution unit; at least one accumulator register file having a plurality of entries for storing data, the at least one accumulator register file having a plurality of entries for storing data, the at least one accumulator register file associated with the complex math execution unit; one or more computer-readable storage media;and programming instructions stored in the one or more computer-readable storage media for execution by the at least one processor. In one embodiment, the programming instructions cause the complex math unit, when executed by the processor, to write results to the same accumulator register file entry multiple times. Preferably, in response to processing of instructions of the complex math execution unit by the processor, the programming instructions cause the processor to: associate a single accumulator register file entry with multiple main register file entries; write results to the same accumulator register file entry multiple times; disable the accumulator register file entry that was written to multiple times;Writing the resulting data from the multi-write accumulator register file entry to the main register file and deallocating the disabled accumulator register file entry.;

[0013] A method for processing instructions in a processor is also disclosed. The method, in one or more embodiments, comprises providing an accumulator register file associated with a complex math execution unit; performing complex math operations with the complex math execution unit; and writing results of the complex math operations of the complex math execution unit to the accumulator register file. In one aspect, the method further comprises reading from and writing to the accumulator register file by the complex math execution unit without writing to a main file register. The accumulator register file, in one embodiment, is both a source and a destination for operations of the complex math execution unit.The method preferably comprises writing the same accumulator register file entry multiple times during operations of the complex math execution unit, and in one aspect, the method includes writing the accumulator register file data to a main register file.

[0014] The above and other objects, features and advantages of the invention will become apparent from the following more particular descriptions of exemplary embodiments of the invention illustrated in the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The various aspects, features, and embodiments of the computer system, the architectural design of computers, the processors, the register files, including the accumulator register files, and / or their operating methods will be better understood when read in conjunction with the provided figures. The embodiments in the figures are intended to illustrate aspects, features, and / or various embodiments of the computer system, the architectural design of computers, the processors, the register files, the accumulator register files, and their operating methods. Fig. 1 shows an example of a data processing system in which aspects of the present disclosure may be practiced. Fig. 2 shows a block diagram of a processor by which certain aspects of the present disclosure may be practiced. Fig. 3 shows a block diagram of a portion of a multi-slice processor according to certain aspects of the present disclosure. Fig. 4 shows a block diagram of a portion of a multi-slice processor with an accumulator register file according to an embodiment of the disclosure. Fig. 5 shows a simplified block diagram illustrating the structure of an MMA unit, an accumulator register file, and a physical VS register file according to an embodiment of the disclosure. Fig. Figure 6 shows a simplified block diagram of two super slices of a processor with MMA units and accumulator register files. Fig. 7 shows a flow diagram of a method for processing data in a processor according to one embodiment. DETAILED DESCRIPTION

[0016] In the following description, certain features described here may be used in any of the various possible combinations and implementations in combination with other described features.

[0017] Unless specifically stated otherwise herein, all terms are to be given their broadest possible interpretation, including meanings implied from the description as well as meanings understood by those skilled in the art and / or defined in dictionaries, contracts, etc. It is also to be understood that as used in the description and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless otherwise specified, and that the terms “comprising” and / or “including” indicate the presence of listed features, integer values, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more features, integer values, steps, operations, elements, components, and / or groups thereof.

[0018] In the following discussion, conventional features of information processing systems, including processors and microprocessor systems, and architecture that would be obvious to those skilled in the art are omitted or described only briefly. Those skilled in the art are assumed to be familiar with the general architecture of processors, and in particular with processors that operate by a non-sequential order execution method, including multi-slice processors, and their use of registers. It may be noted that a numbered element is numbered according to the figure in which the element is introduced, and that it is often, but not always, referred to by that number in subsequent figures.

[0019] Fig. 1 shows an example of a data processing system 100 in which aspects of the present disclosure may be practiced. The system includes a central processing unit (CPU) 110. The CPU 110 is coupled to various other components via a system bus 112. A read-only memory (a "ROM") 116 is coupled to the system bus 112 and includes a basic input / output system ("BIOS") that controls certain basic functions of the data processing system 100. A random access memory ("RAM") 114, an I / O adapter 118, and a communications adapter 134 are also coupled to the system bus 112. The I / O adapter 118 may be a small computer system interface ("SCSI") adapter that communicates with a disk storage device 120.The communications adapter 134 connects the bus 112 to an external network that enables the data processing system to communicate with other such systems. Input / output devices are also connected to the system bus 112 via a user interface adapter 122 and a display adapter 136. A keyboard 124, a trackball 132, a mouse 126, and speakers 128 are all connected to the bus 112 via the user interface adapter 122. A display screen 138 is connected to the system bus 112 via the display adapter 136. In this way, a user can provide input to the system via the keyboard 124, trackball 132, or mouse 126 and receive output from the system via the speaker 128 and display 138. In addition, an operating system such as AIX ("AIX" is a trademark of IBM Corporation) is used to coordinate the functions of the various devices implemented in . Fig. 1 shown components are used.

[0020] The CPU (or "processor") 110 includes various registers, buffers, memories, and other devices formed by integrated circuits and may employ reduced instruction set computing (RISC) techniques. The CPU 110 processes in processor cycles that, in some aspects, are synchronized with an internal clock (not shown).

[0021] Fig. Figure 2 shows a simplified block diagram of a processor 110 according to one embodiment. Processor 110 includes memory 202, instruction cache 204, instruction fetch unit 206, branch predictor 208, branch classifier 218, processing pipeline 210, and destination resource 220. Processor 110 may be integrated into a computer processor or otherwise distributed within a computer system. Instructions and data may be stored in memory 202, and instruction cache 204 may access the instructions in memory 202 and store the instructions to be fetched. Memory 202 may include any type of volatile or non-volatile memory. Memory 202 and instruction cache 204 may include multiple cache levels.

[0022] In Fig. 2 shows a simplified example of the instruction fetch unit 206 and the processing pipeline 210. In various embodiments, the processor 110 may include multiple processing pipelines 210 and instruction fetch units 206. In one embodiment, the processing pipeline 210 includes a decode unit 20, a dispatch unit 22, an execution unit 24, write-back logic 26, a logical register allocator 28, a history buffer, e.g., a save and restore buffer (SRB) 30, and a physical register file 32. The instruction fetch unit 206 and / or the branch predictor 208 may also be part of the processing pipeline 210. The processing pipeline 210 may also include other features such as error checking and recovery logic, one or more parallel paths through the processing pipeline 210, and other features now or later known in the art.Although in . Fig. While Figure 2 illustrates a forward path through processor 110, additional feedback and signal paths may be included between the elements of processor 110. Processor 110 may include additional circuits, functional units, and components.

[0023] The instruction fetch unit 206 fetches instructions from the instruction cache 204 according to an instruction address for further processing by the decode unit 20. The decode unit 20 decodes the instructions and forwards the decoded instructions, portions of instructions, or other decoded data to the issue unit 22. The decode unit 20 may also detect branch instructions not anticipated by the branch predictor 208. The issue unit 22 analyzes the instructions or other data and sends the decoded instructions, portions of instructions, or other data, according to the analysis, to one or more execution units 24 in the pipeline 210. The physical register file 32 holds the data for the execution units 24. The execution unit 24 performs and executes the operations specified by the instruction issued to the execution unit 24.Execution unit 24 may include multiple execution units, such as fixed-point execution units, floating-point execution units, load / store execution units (LSUs), vector-scalar execution units (VSUs), and / or other execution units. Logical register mapper 28 contains entries that provide a mapping of a logical register entry (LReg) to an entry in physical register file 32. When an instruction specifies reading a logical register entry (LReg), logical register mapper 28 informs issue unit 22, which informs execution unit 24 where the data may be located in physical register file 32.

[0024] When a mispredicted branch instruction or other exception is detected, the instructions and data following the mispredicted branch or exception are discarded, e.g., flushed from the various units of processor 110. A history buffer, e.g., a save & restore buffer (SRB) 30, contains both speculative and designed register states and saves the logical register file data when a new instruction is sent. In this regard, the history buffer stores information from the logical register allocator 28 when a new instruction displaces data in case the new instruction is flushed and the old data needs to be restored. The history buffer (SRB) 30 retains the stored information until the new instruction completes.The history buffer (SRB) 30 is networked with the logical register mapper 28 for restoring the contents of logical register entries from the history buffer (SRB) 30 to the logical register mapper 28, for updating the references in the logical register mapper 28, so that instructions know where to fetch the correct data; for example, returning the processor to the state it existed before the instruction to be interrupted, for example, the mispredicted jump instruction.

[0025] Write-back logic 26 writes results of executed instructions to a destination resource 220. Destination resource 220 may be any type of resource, including registers, a cache, other memory, I / O circuitry for communicating with other devices, other processing circuitry, or any other type of destination for executed instructions or data.

[0026] Instructions may be processed in the processor 110 in a sequence of logical, time-interleaved stages. However, it is understood that the functions of these stages may be combined, so this particular division of stages should not be construed as limiting unless such a limitation is clearly stated in the present claims. In fact, some of the stages in Fig. 2 is presented as a single logical unit for ease of understanding and further relevant details are set out below.

[0027] Fig. Figure 3 shows a block diagram of a portion of a processor 110, and in this example, a multi-slice processor 110, according to an embodiment of the disclosure. It may be noted that Fig. 3, for the purposes of discussion, only shows parts of the multi-slice processor 110 in a diagrammatic manner. It is understood that the multi-slice processor may have other configurations. As shown in Fig. As shown in Figure 3, the multi-slice processor includes two processing slices—slice 0 (slice S0 or 360) and slice 1 (slice S1 or 365). The processor includes an instruction fetch unit 310. Slices S0 and S1 each include an instruction dispatch unit (320a and 320b); a logical register allocator (350a and 350b); a history buffer (HB) (370a and 370b); an issue queue (ISQ) (330a and 330b); and an instruction completion table (ICT) (325a and 325b) and execution units (340a and 340b) including a load store unit (LSU) (304a and 304b), a vector scalar unit (VSU) (306a and 306b), and a register file (RF) (380a and 380b). The execution unit 340 may include one or more queues for holding instructions for execution by the execution unit 340.

[0028] It should be noted that the two slices are shown only for ease of illustration and explanation, and that the multi-slice processor 110 may include more than two processing or execution sections, each slice including all of the components discussed above in connection with each of slices S0 and S1 (slices 360 and 365). Furthermore, the processing slices may be grouped into super-slices (SS 395), each super-slice including two processing slices. For example, a multi-slice processor may include two super-slices SS0 and SS1, where SS0 includes slices S0 and S1, and SS1 (not shown) includes slices S2 and S3.

[0029] The instruction fetch unit 310 fetches instructions to be executed from the processor 110 or the processor slice. The instructions fetched by the instruction fetch unit 310 are sent to the instruction dispatch unit 320. The instruction dispatch unit 320 sends the instructions to the issue queue (ISQ) 330, typically in program order. The issue queue (ISQ) 330 issues the instructions to the execution unit 340. The ISQ 330 typically holds an instruction until data associated with the instruction is retrieved and ready for use. A physical register file 380 may be used to store data to be used in an operation specified in an instruction sent to an execution unit 340, and the result of the operation performed by the execution units 340 may be written to the specified destination register entry in the physical register file 380.

[0030] In certain aspects, the ISQ 330 holds a set of instructions, and the register file 380 stores the data for the instruction entries. A register file may be used to temporarily store data between memory and other functional (execution) units in the processor. Numerous register files and types may be provided. Once all the source data for the instruction is gathered, the data is passed to one or more execution units designated to execute the instruction. Each of the execution units, e.g., the LSUs 304 and VSUs 306, may make result data available via the write-back buses for writing to a register file (RF) entry.

[0031] If data is not ready, e.g., not in the correct data cache or register, this may result in a delay because the ISQ 330 does not issue the instruction to the execution unit 340. For this reason alone, the issue queue (ISQ) typically issues instructions out of order to the execution units 340 so that instructions where the required data is available can be executed. The dispatch unit 320, in one or more embodiments, tags each instruction sent to the issue queue 330 with an identifier, e.g., an identification tag (an iTag: identification tag), to identify the instruction. The dispatch unit 320 may tag instructions with additional information and metadata.

[0032] The instructions (iTags) are typically allocated (assigned) and tagged by the sending unit 320 on a per-thread basis in ascending order of the program.

[0033] The logical register mapper 350 contains metadata (e.g., an iTag, an RFtag, etc.) that ensures a mapping of entries in the logical register (e.g., GPR1) to entries in the physical register file 380 (e.g., a physical register array entry). The RFtag is the reference that relates a logical register entry to a physical register file entry. For example, if an instruction wants to read a logical register, e.g., GPR1, the logical register mapper 350 tells the issue queue 330, which then tells the execution unit 340 where in the physical register file 380 it can find the data, e.g., the physical register array entry. The execution unit 340 executes instructions in a non-sequential order, and when the execution unit 340 completes an instruction, the execution unit 340 sends the completed instruction, e.g., the iTag, to the ICT 325.The ICT 325 contains a queue of instructions sent by the sending unit 320 and tracks the history of the instructions as they are processed.

[0034] The history buffer (SRB) 390 contains logical register entries that are evicted from the logical register mapper 350 by newer instructions. The information stored in the history buffer (SRB) 390 may include the iTag of the instruction that evicted the logical register entry from the logical register (i.e., the evictor iTag). The history buffer (SRB) 390, in one embodiment, stores the iTag, the logical register entry number (the bit field that identifies the logical register entry (LReg)), and the register file identifier information (the RFTag). The history buffer (SRB) 390 may store and track other information. The history buffer (SRB) 390 interfaces with the logical register mapper 350 to recover the iTag and register file identifier (RFTag) (and other metadata) of each evicted logical register entry (LReg).The information is retained in the history buffer (SRB) 390 in a history buffer entry (SRB entry) until the new instruction (the evicting instruction) completes. At this point, in one embodiment, the entry is deleted from the history buffer (SRB) 390.

[0035] A CPU 110 with multiple processing slices may be capable of executing multiple instructions simultaneously, for example, executing one instruction in each processing slice simultaneously in one processing cycle. Such a CPU with multiple processing slices may be referred to as a multi-slice processor or a parallel-slice processor. Simultaneous processing in multiple execution slices can significantly increase the processing speed of the multi-slice processor. In single-thread (ST) mode, a single thread is processed, and in simultaneous multithreading (SMT) mode, two threads (SMT2) or four threads (SMT4) are processed simultaneously.

[0036] In one aspect, each execution / processing slice may have its own register file, as in Fig. 3. According to one aspect, a register file may be allocated per super-slice and shared by the processing slices of the super-slice. According to one aspect, a register file may be allocated to more than one super-slice and shared by the processing slices of the super-slices. For example, slices S0, S1, S2, and S3 may be allocated to share a register file. The register files are discussed in more detail below.

[0037] It is not uncommon for a processor to use a register to rename executing instructions in order to improve the execution of instructions out of sequential order. However, in situations where high-performance, high-throughput execution units are used, such as complex math operations, register renaming of executing instructions can result in a lot of data movement, which can be performance-intensive to accomplish and can also introduce unnecessary delay and latency due to one or more execution bubbles. In one or more embodiments, accumulator register files are used, and a process that utilizes accumulator register file renaming on complex math instructions is performed.Accumulator register files and accumulator register file renaming processes are used to minimize data movement during execution to reduce power and improve execution throughput. To enter accumulator register renaming mode, according to one aspect, the accumulator registers are enabled. After enabling the accumulator registers, the complex math execution unit, e.g., the matrix multiplier accumulator (MMA) unit and / or an inference engine, in one or more embodiments, can locally read from and write to the accumulator registers without having to write to the main register file. Preferably, the complex math execution unit accesses, reads, and / or writes the same accumulator register file entry multiple times without renaming a new accumulator register file and / or writing back to the main file registers.After completion of the complex mathematical operations and / or in response to predetermined operations and instructions, in one embodiment, the result(s) in the accumulator register file may be written to the main register file and / or main memory.

[0038] Preferably, the accumulator register(s) is (are) local to the MMA unit, and in one or more embodiments, the accumulator register(s) may be located in the MMA unit. In another embodiment, the accumulator register may have entries having a bit field width that is wider than the bit field width of the main register file entries. According to one aspect, the accumulator register files are deactivated when the operation of the complex math execution unit is complete. According to one aspect, when the operation of the complex math execution unit is complete, the results stored in the accumulator register file may be moved from the accumulator register file to the main register file to enable use of those results by subsequent instructions, e.g., subsequent non-complex math instructions.The accumulator register file entries written back to the main register file may be deallocated in one embodiment. In one or more embodiments, a process, processor architecture, and system are described that utilize one or more accumulator registers associated with, local to, and / or located within one or more complex math execution units, e.g., one or more inference engines and / or MMA units, to process complex math instructions. An inference engine, in one embodiment, may be a set of eight (8) matrix multiplier accumulator (MMA) units and thirty-two (32) 512-bit accumulator registers.

[0039] Fig. Figure 4 shows a simplified block diagram of a processing pipeline that uses an accumulator register file in conjunction with an execution unit, e.g., an inference engine / MMA unit, and a vector / scalar main register file (VS main register file) located in a vector / scalar execution unit (VS execution unit (VSU)). The processing pipeline or execution section includes a send unit 320, a logical allocator 350 with multiple entries 351(a)-351(n), an instruction completion table (ICT table; ITC: instruction complete) 325, an issue queue (ISQ) 330, a matrix multiplier accumulator (MMA) unit 460, an accumulator register file 470 with multiple entries 471(a)-471(n), and a VS execution unit (VSU) 340 with a (VS) main register file 380 with multiple entries 381(a)-381(n). Although the accumulator register file 470 in Fig. 4 as being associated with and local to the inference engine / MMA unit 460, in one or more embodiments the accumulator register file 470 may be located in the MMA unit 460. During operations of the inference engine and / or the MMA, in one or more embodiments the accumulator register file 470 is used as a source and destination (accumulator). This means that, in one aspect, the MMA, as it operates, uses operands from the accumulator register file and writes results back to the accumulator register file, and in one embodiment writes the results back to the same accumulator register file entry 471(n). In one or more embodiments, the result of the inference engine / MMA unit may be written back to the same destination accumulator register file entry 471(n) multiple times.In this way, the processor that has the VS or main register file is not subjected to renaming operations during inference engine or MMA operations.

[0040] In one or more embodiments, the bit field width of the accumulator register file 470 is wider than the bit field width of the (VS) main register file 380. In one embodiment, the accumulator register file 470 is a pool of wide bit accumulator register file entries 471(a)-471(n). For example, in one embodiment, the accumulator register file 470 is a pool of 64 physical 512-bit register entries 471, whereas the VS main register file is 128 bits wide. Each accumulator register file entry 471, in one embodiment, holds multiple main register file entries, and in one embodiment, a set holds four consecutive main VS register file entries (381(n)-381(n+3)). In a simplified block diagram according to Fig. 5, a VS or main register file 380 is shown having four entries 381(a)-381(d) mapped to a single accumulator register entry 471 in the accumulator register file 470. In one example, four consecutive 128-bit main VS register file entries 381(a)-381(d) map to a single 512-bit accumulator register file entry 471. In one or more embodiments, eight (8) logical accumulator registers (ACC0-ACC7) are provided per thread. These eight (8) logical accumulator registers map to thirty-two (32) physical registers in the accumulator array, e.g., the accumulator register file.

[0041] Instructions are used to set up and operate the complex mathematics execution unit, e.g., the inference engine and / or one or more MMA units. General matrix rank operation instructions (“ger” instructions; ger: general matrix rank operation) are an example and perform, according to one or more aspects, n 2Operations on 2n data. The inference engine / MMA unit workload typically has three parts. The accumulator register file is activated by initial data to perform its operations. Multiplication operations are performed in the MMA unit(s), and the results are accumulated in the accumulator register file. And, when, according to some aspect, the complex math execution unit is finished, and / or in response to certain instructions, the results in the accumulator register file are written back to memory, e.g., to the main register file and / or main memory. Accumulator instructions (“ger” instructions) typically have two VSR operand sources, an accumulator VSR destination, and an accumulator VSR source.

[0042] To initiate complex math operations, e.g., MMA unit operations, the processor, in one or more embodiments, decodes and / or detects a complex math instruction, e.g., an inference engine / MMA unit "ger" instruction. Each complex math instruction, in one embodiment, has an iTag and utilizes a full send lane and a full issue queue (ISQ) entry. In one aspect, the main register allocator 350 allocates four destinations (main register file entries) per complex math instruction, e.g., MMA unit instruction. The main register allocator 350, in one embodiment, also deletes allocator entries from the main register allocator 350. For an instruction that uses the same accumulator register file entry, according to Fig. 4, e.g., 471(a), the main register allocator 350 does not allocate new main register file identifier RFTags (entries), but rather, the register allocator 350 requires a new iTag for the new instruction. In one or more aspects, when a complex math instruction (an iTag) utilizing the accumulator register file 470 completes, the main register file entries (RFTags) are not deallocated if the accumulator register file 470 has not written the results to the main register file 380. The main register file entry (the RFTag) is deallocated upon a relocation of the data in the corresponding accumulator register file entry to write the data back to the main register file 380 and / or in response thereto, e.g., in response to a newer, non-complex math instruction.

[0043] In one embodiment, the main register allocator 350 marks the main register file entries associated with the accumulator register file entry. In one aspect, the main register allocator 350 writes the same accumulator register file iTag to multiple consecutive main register file entries 381, e.g., VSR(n) - VSR(n+3). This means that an iTag is assigned to a group of consecutive main register file entries, e.g., four main register file entries 381(n) - 381(n+3), in parallel. A newer, non-complex math instruction that reads or writes the main register file entries associated with the accumulator register file entries (the locked main register file entries) notifies the issue queue (ISQ) 330 to initiate the write-back process.In one or more embodiments, to read the contents of the accumulator register from the accumulator register file 470, a sequence of move-from-accumulator instructions is sent from the sending unit 320 and issued by the issuing unit 330. In one or more alternative embodiments, the write-back process includes stopping the sending unit 320 and notifying the issuing queue 330 to clear the data in the accumulator register file 470 before the issuing queue can resume issuing instructions. In one aspect, instructions that write the same group of main register file entries are marked for issue in order.

[0044] In one or more embodiments, complex math instructions that utilize accumulator register file 470 are preferably issued from issue queue 330 in order by register number and, in one aspect, by instruction type. The issue rate of a complex math instruction that utilizes the accumulator register file is, in one aspect, one instruction per cycle (except for the first instruction for issue to activate the accumulator register file, which may take more than one cycle). The instructions that utilize the accumulator register file are preferably issued in order and back-to-back.If there are older instructions that use the accumulator register file, the issue queue may issue the older instruction because the older instruction reads or writes to the main register file, but the accumulator register file only updates the accumulator register file until the data in the accumulator register file can be moved to the main register file for writing back.

[0045] The accumulator register file should be activated in one or more embodiments. In one or more embodiments, each accumulator register file is activated as required. If the accumulator register file is a data source, the accumulator register file, and in particular the accumulator register file entries that use the data, should be activated to initiate complex mathematical operations, e.g., MMA operations that use the accumulator register file. The accumulator register file is activated when written to from memory, e.g., from the main register file and / or main memory, or it is activated as a result of an activation instruction. For example, to synchronize the accumulator register file with the (VS) main register file, an instruction, e.g., xxmtacc, can move data from the (VS) main register file to the accumulator register file.In another example, an instruction such as lxacc can load and move data from main memory into the accumulator register file. In another example, the accumulator register file is activated when the data in its entry(s) is set to zero. Other instructions for activating the accumulator register file are also possible.

[0046] In one embodiment, the vector scalar execution unit (VSU) writes primary (VS) main register data and the iTag of the instruction executing the activation to the corresponding accumulator register file entry. Activating the accumulator register file also associates the accumulator register rename. Upon activation, the accumulator register target is renamed and mapped to a physical register file entry. Referring to Fig. 5, in one example, the activation is associated with the accumulator register rename, and the VS register data in entries 381(a)-381(d) is written to the associated accumulator register entry 471. In one or more embodiments, the VS execution unit writes the (VS) main register file data and the iTag of the instruction performing the activation to the associated accumulator register file. In one or more embodiments, an accumulator free list 472 maintains the associated and free accumulator identifiers. The accumulator identifiers identify the accumulator register file entries. In one aspect, an accumulator register file busy flag is used to indicate that the accumulator register file entry is currently active. If all accumulator register file entries are busy, the send is delayed in a manner similar to deferring a main register resource.

[0047] In one or more embodiments, upon the first issue of an instruction that utilizes the accumulator register file, activating the accumulator register file requires two consecutive cycles. If the accumulator busy flag is not set, in one embodiment, the issue of the instruction requires two cycles because the accumulator register file must be activated / reactivated and the main register file must read the accumulator register file as a source. Upon the second issue of an instruction that utilizes the accumulator register file, the issue preferably requires one cycle. When activating and deactivating the accumulator register, multiple, e.g., four, main register file identifiers are issued at once for each accumulator register file entry.

[0048] For complex mathematical operations, the accumulator register file is not read from and written to the (VS) main register file in each cycle. Instead, a large amount of data-comprising results remain locally in the complex mathematical engine, e.g., the MMA unit, throughout the entire use of the accumulator register file. This means that operations of the MMA unit are written back to the accumulator register file. According to one aspect, the same accumulator register file is written to multiple times, e.g., multiple times. In one embodiment, accumulator register file entries are not renamed with each instruction. The accumulator register file is used as a source and destination (accumulator) in MMA operations in one or more embodiments. The loop 475 in Fig. Figure 5 shows the operations of the MMA unit that overwrites the same destination entry 471 in the accumulator register 470.

[0049] Each MMA unit instruction writes a single accumulator register file entry and sets the state of the destination accumulator register entry to contaminated, indicating that the accumulator register file entry and the corresponding (VS) main register file entries are out of synchronization. For MMA unit instructions, such as "ger" instructions, the accumulator register file stores the result, and the (VS) main register file does not. Although the data is not written back to the main register file in the main execution unit, such as the VSU, the main execution unit updates the accumulator register file's iTag when it receives a new instruction from the issue queue. For an instruction that uses an accumulator register file entry, the iTag of the newer instruction using the accumulator register file replaces the older iTag, but the main register file identifier (the RFTag) is not changed.

[0050] The accumulator register file is disabled and its data is written back in response to a number of scenarios. In one embodiment, the accumulator register file is written back and / or disabled in response to instructions and / or access to the (VS) main register file as a source following contamination of the accumulator register. For example, in response to an instruction to move from the accumulator register to the (VS) main register file, e.g., xxmfacc, the accumulator register file is disabled and the results in the accumulator register file are moved out of the accumulator register file and written back to the (VS) main register file. In another example, in response to an instruction to move from the accumulator register file and store, e.g.,stxacc, the accumulator register file is disabled, and the results in the accumulator register file are written back to main memory. In one or more embodiments, if an accumulator register file entry is contaminated and accessed from the main (VS) register file, the hardware disables the accumulator register. In one embodiment, the hardware executes a sequence that writes all accumulator registers back to the main (VS) register file. In one aspect, each accumulator register file entry is disabled, the data in the accumulator register file is written to the main VS register file, and the accumulator register file is also deallocated from the rename pool.In one or more embodiments, even if the accumulator register has not been contaminated, the accumulator register is disabled when the accumulator register is enabled and the (VS) main register file is targeted.

[0051] In response to a recent instruction from the main execution unit, e.g., a VSU instruction, that touches a main register file associated with an active accumulator register file, the issue queue is, in one embodiment, signaled to initiate the write-back of the affected accumulator register file entry. In a preferred embodiment, this may occur through the execution of a series of internal operations included in the instruction flow. According to one aspect, the issue queue pauses the dispatch unit until the accumulator register is emptied. This means that the accumulator register file writes data back to the corresponding main register file entries. According to one aspect, writing data back to the main register file requires multiple cycles, e.g., four cycles if the accumulator register file entry is associated with four main register file entries. The main execution unit, e.g.,the VSU, completes the write-back when the last part of the accumulator register file data is written back. The "ACC Busy" flag is reset (cleared) when the write-back is complete. The complex math instruction that uses the accumulator register file is a single instruction and occupies an entry in the instruction completion table (ICT) 325. The accumulator register instruction completes when the last part of the data in the accumulator register file is written back to the main register file. The iTag of the completed instruction is used to deallocate the main register file entries (RFTags) from the (in . Fig. 4 (not shown). The processor then processes the newer, less complex math instructions, which include reading data from the main register file. Furthermore, after the accumulator register file is flushed and the ACC busy flag is cleared, the issue queue can resume issuing instructions, and the sending unit can resume sending instructions.

[0052] According to one aspect, when a complex math instruction, e.g., a "ger" instruction, uses an accumulator register file as a source that hasn't been activated since it was last deactivated (e.g., by xxmtacc or ldacc), the hardware activates that accumulator register file entry. The hardware executes a sequence that activates the accumulator register file and allocates an accumulator register file entry (renaming). The complex math instruction is then executed.

[0053] Fig. 6 shows another embodiment of a processor having one or more complex math execution units, e.g., matrix multiplier accumulator (MMA) units, in conjunction with a local accumulator register file, wherein the processor is configured so that the operations of the one or more complex math units write results back to the same accumulator register file entry multiple times. Fig. Figure 6 shows two super slices of a processor for processing data. Each super slice includes at least one MMA unit 460, two vector-scalar execution units (VS execution units) 306, and two load store units (LS units) 304. A single accumulator register file 470 is used in conjunction with the two MMA units 460. In an alternative embodiment, each execution section could include its own MMA unit with a local accumulator register file, and according to a further aspect, each MMA unit in each execution section includes the accumulator register file contained in the MMA unit. In the embodiment according to Fig. 6, the issue queue (ISQ) 1 330b in super-slice 0 and the issue queue (ISQ) 2 330c in super-slice 1 issue instructions, e.g., "ger" instructions, to the respective MMA units (460a and 460b). Alternatively, the issue queue (ISQ) 0 330a and the issue queue (ISQ) 3 330d could, as in Fig. 6 shown by dashed lines, issue instructions, e.g., “ger” instructions, to each MMA unit (460a and 460b) in the respective super slice.

[0054] Fig. 7 is an exemplary flow diagram according to an embodiment illustrating and describing a method for handling data, e.g., executing instructions, in a processor, which in one embodiment includes processing and handling complex math instructions, e.g., MMA (“ger”) instructions, in a processor according to an embodiment of the present disclosure. Although method 700 is described for convenience and not with the intent to limit the disclosure to include a sequence and / or series of steps, it is to be understood that the process need not be performed as a sequence of steps and / or the steps need not be performed in the manner described with reference to Fig. 7, but that the process may be integrated and / or one or more steps may be performed together, simultaneously, or the steps may be performed in the disclosed order or in an alternative order.

[0055] The procedure 700 according to Fig. 7 relates to the processing of data in a processor, more specifically, the handling of complex mathematical operations using a complex math execution unit, for example, an MMA execution unit. At 705, a complex math execution unit is provided. In one example, a complex math execution unit is a matrix multiplier-accumulator (MMA) unit. In one or more examples, a complex math execution unit may be multiple MMA units arranged as an inference engine. Other complex math execution units are contemplated. In one or more embodiments, an accumulator register file is provided at 710 in association with the complex math execution unit.In one embodiment, the accumulator register file is local to one or more of the complex math execution units, and in one aspect, the accumulator register file is located in an MMA unit. Preferably, the accumulator register file has a bit field width that is wider than the bit field width of the main register file in the processor. In one embodiment, the accumulator register file is 512 bits wide, whereas the main register file in the processor is 128 bits wide. In one aspect, more than one main register file entry is associated with an accumulator register file. For example, four consecutive main register files are associated with an accumulator register file.

[0056] In one or more embodiments, in response to an instruction for operations of the complex math execution unit at 715, the accumulator register is activated. For example, if the accumulator register file is a source for the operations of the complex math execution unit, the accumulator register file is activated. Activation of the accumulator register file, in one embodiment, includes synchronizing the data in the accumulator register file with data contained in the main register file, e.g., the VS register file, or data contained in main memory. Activation of the accumulator register file may also include clearing the data in the accumulator register file, e.g., resetting the data in the accumulator register file entry to zero. In one or more embodiments, a complex math instruction, e.g.,A "ger" instruction may not have any accumulator register file source data, and this complex math instruction is considered self-activating. The accumulator register file is activated when it is first written to from the main register file, from main memory, or it is activated as a result of a self-activation instruction (when the data in the accumulator register file entry is set to zero). In one or more embodiments, the accumulator register file allocates an accumulator register file rename, the accumulator file is activated, and the value of the data in the accumulator register file is set to the value in a main register file, in main memory, or to zero.

[0057] The complex math execution unit, e.g., the MMA and / or the inference engine, performs complex math operations in one or more embodiments at 720. This means that the complex math operations are performed using the one or more complex math execution units, e.g., the inference engine and / or the MMA unit(s). The results of the complex math execution unit, e.g., the results of the inference engine and / or the MMA unit(s), are written back to the accumulator register file in one embodiment at 725. This means that the accumulator register file is used as both a source and a destination in operations of the complex math execution unit. The results of the complex math execution unit are preferably written back to the same destination accumulator register file multiple times without renaming.This means that in one embodiment, a single accumulator register file target rename may be overwritten multiple times. In one or more aspects, in response to an instruction to the complex math execution unit, e.g., a "ger" instruction, no write-back to the main register file occurs, and instead, the accumulator register local to the complex math execution unit, e.g., the MMA unit, stores the result, whereas the main register file does not store the result. In this way, the complex math execution unit, e.g., the inference engine and / or the MMA unit, operates without renaming the main register file entries. In one embodiment, in response to the complex math execution unit writing the results back to the accumulator registers, the accumulator register file entry is identified or marked, e.g., marked as contaminated.

[0058] At 730, in one or more embodiments, the accumulator register file results are written back to the main register file and / or main memory. In one embodiment, when the operations of the complex math execution unit are complete, the results of the accumulator register file are written back to the main register file and / or main memory. In one embodiment, the accumulator register is disabled, the value in the accumulator register file is written to the main register file (or main memory), and the accumulator register file entry is deallocated. According to one embodiment, the main register file is written back in response to instructions, e.g., move from the accumulator register file entry to the main register file (xxmfacc) and move from the accumulator register file entry and store (stxacc) instructions.The results of the accumulator register are also written back to the main register file if the main register file entry associated with the accumulator register file entry is used as a source or destination and the accumulator register file entry is contaminated. In one aspect, a specified accumulator read instruction moves the data from the accumulator register file to the main register file. In one embodiment, after reading the accumulator, a sequence of memory operations, e.g., octo / quad word memory operations, reads the main register file and writes it to main memory.

[0059] In one embodiment, the hardware disables the accumulator register file when the accumulator register file entry is contaminated and is accessed from the main register. In one aspect, the hardware disables the accumulator register even if the accumulator register has not been contaminated when the main register file entry is used as a target when the associated accumulator register entry is activated. The hardware executes a sequence that writes all of the accumulator register file entries back to the main register file, the operation using the main register file entry as a target is performed, and the allocation of each accumulator register file entry in the rename pool is deallocated.

[0060] According to one aspect, the hardware enables the accumulator register file entry when a complex math instruction, e.g., a "ger" instruction, uses an accumulator register file as a source that has not been enabled since it was last disabled (e.g., by xxmtacc or ldacc). According to one aspect, the hardware executes a sequence that enables the accumulator register file and allocates (renaming) an accumulator register file entry. The complex math instruction is then executed.

[0061] Although the exemplary embodiments described above are preferably implemented in hardware, such as units and circuits of a processor, various aspects of the exemplary embodiments may also be implemented in software. For example, it should be understood that each block of the Fig.7 and combinations of blocks in the flowchart representation may be implemented by computer program instructions. These computer program instructions may be made accessible to a processor or other programmable data processing device to produce a machine such that the instructions, executed by the processor or other programmable data processing device, provide means for implementing the functions specified in the flowchart block(s).These computer program instructions may also be stored in a computer-readable memory or storage medium that can instruct a processor or other programmable data processing device to operate in a particular manner such that the instructions stored in the computer-readable memory or storage medium constitute a manufactured article that includes instruction means for implementing the functions specified in the flowchart block or blocks.

[0062] Accordingly, blocks of the flowchart representations support combinations of means for performing the specified functions, combinations of steps for performing the specified functions, and program instruction means for performing the specified functions. It is also understood that each block of the flowchart representation and combinations of blocks in the flowchart representations may be implemented by special-purpose hardware-based computer systems that perform the specified functions or steps, or by combinations of special-purpose hardware and computer instructions.

[0063] The present invention may be a system, a method, and / or a computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions embodied therein for causing a processor to carry out aspects of the present invention.

[0064] The computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.A non-exhaustive list of specific examples of computer-readable storage media includes the following: a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, a mechanically encoded device such as punched cards or raised structures in a groove with instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, shall not be defined as transient signals per se such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating via a waveguide or other transmission media (e.g.,light pulses passing through a fiber optic cable) or electrical signals sent over a cable.

[0065] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to respective computing / processing devices or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, network switching computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium in the respective computing / processing device.

[0066] Computer-readable program instructions for performing operations according to the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, integrated circuit configuration data, or any source code or object code written in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages ​​such as the "C" programming language or similar programming languages.The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer over any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, over the Internet using an Internet service provider).In some embodiments, electronic circuits, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute the computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuits to carry out aspects of the present invention.

[0067] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented by computer-readable program instructions.

[0068] These computer-readable program instructions may be made accessible to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, executing via the processor of the computer or other programmable data processing apparatus, provide a means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium having instructions stored therein comprises a product of manufacture that includes instructions that implement aspects of the function / operation specified in the flowchart and / or block diagram block or blocks.

[0069] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a sequence of method steps to be performed on the computer, other programmable device, or other device to produce a computer-implemented process, such that the instructions executing on the computer, other programmable device, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0070] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to different embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions listed in the blocks may appear out of the order noted in the figures. For example, depending on the functionality involved, two blocks shown as consecutive may actually execute substantially concurrently, or the blocks may occasionally execute in reverse order.It will also be appreciated that each block of the block diagram and / or flowchart illustration, and combinations of blocks of the block diagram and / or flowchart illustration, may be implemented by special purpose hardware-based systems that perform the specified functions or operations, or by combinations of special purpose hardware and computer instructions.

[0071] Furthermore, according to various embodiments, a system may comprise a processor and logic integrated into and / or executable by the processor, wherein the logic is configured to perform one or more of the process steps listed herein. Integrated means that the processor has logic embedded therein as hardware logic such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc. Processor-executable means that the logic is hardware logic; software logic such as firmware, part of an operating system, part of an application program; etc., or a combination of hardware and software logic that can be accessed by the processor and that is configured to cause the processor to perform a function when executed by the processor.Software logic may be stored in local and / or remote memory of any memory type known in the art. Any processor known in the art, such as a software processor module and / or a hardware processor such as an ASIC, an FPGA, a central processing unit (CPU), an integrated circuit (IC), a graphics processing unit (GPU), etc., may be used.

[0072] It is clear that the different features of the above systems and / or methodologies can be combined in any way, resulting in several combinations from the descriptions presented above.

[0073] It is further understood that embodiments of the present invention may be provided in the form of a service deployed on behalf of a customer to provide a service tailored to their needs.

Claims

[1] Computer system for processing information, the computer system comprising: at least one processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports for writing data to the main register file entries, and one or more read ports for reading data from the main register file entries; one or more execution units including a complex mathematics execution unit; and at least one accumulator register file having a plurality of entries for storing data, wherein the at least one accumulator register file is associated with the complex mathematics execution unit, wherein the processor is designed to process data in the complex math execution unit, wherein the results of the complex math execution unit are written to the accumulator register file, wherein the processor is configured to write data from the accumulator register file to a plurality of main register file entries in response to an instruction accessing a main register file entry associated with an accumulator register file, and where the complex mathematics execution unit is a matrix multiplier-accumulator unit or an inference engine. [2] The computer system of claim 1, wherein the processor is configured to write results back to the same accumulator register file entry multiple times. [3] The computer system of claim 1, wherein the processor is configured to write data from the accumulator register file to the main register file. [4] The computer system of claim 1, wherein the processor is configured to prepare the accumulator file register to receive data. [5] The computer system of claim 4, wherein the processor is configured to prepare the accumulator file register in response to an instruction to store data in the accumulator register file. [6] The computer system of claim 4, wherein the processor, in response to preparing an accumulator register file entry, marks the one or more main register file entries associated with the prepared accumulator register file as busy. [7] The computer system of claim 1, wherein the accumulator register file is local to the complex math unit. [8] The computer system of claim 8, wherein the accumulator register file is located in the matrix multiplier accumulator (MMA) unit. [9] The computer system of claim 1, wherein the bit field width of the accumulator register file is wider than the bit field width of the main register file. [10] The computer system of claim 9, wherein each entry in the accumulator register file is associated with a plurality of main register file entries. [11] The computer system of claim 1, wherein the processor comprises a vector scalar execution unit (VSU) and the complex math execution unit is a matrix multiplier accumulator unit (MMA) and the main register file is a VS register file located in the VSU and the accumulator register file is associated with multiple consecutive VS register file entries. [12] Processor for processing information, the processor comprising: a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports for writing data to the main register file entries, and one or more read ports for reading data from the main register file entries; one or more execution units including a complex mathematics execution unit, wherein the complex mathematics execution unit is a matrix multiplier-accumulator unit or an inference engine; and at least one accumulator register file having a plurality of entries for storing data, wherein the at least one accumulator register file is associated with the complex mathematics execution unit, and the bit field width of the accumulator register file is wider than the bit field width of the main register file, wherein the processor is designed to process data in the complex math execution unit such that the results of the complex math execution unit are written multiple times into the same accumulator file register entry, and wherein the processor is configured to, Preparing the accumulator register file, Writing results multiple times to the same accumulator register file entry, Disabling the accumulator register file entry that has been written to multiple times, Writing the resulting data from the accumulator register file entry that was written to multiple times to the main register file, and Deallocate the disabled accumulator register file entry. [13] The processor of claim 12, wherein the processor is configured to map multiple main register file entries to a single accumulator register file entry in response to processing complex math instructions. [14] The processor of claim 12, wherein the processor is configured to prepare the accumulator register file to receive data. [15] The processor of claim 12, wherein the processor is configured to mark the accumulator register file as contaminated in response to the complex math execution unit writing data to one of the plurality of accumulator register file entries. [16] The processor of claim 12, wherein the one or more execution units comprise a vector scalar unit (VSU), the complex math execution unit is a matrix multiplier accumulator (MMA) unit, and the main register file is a vector scalar (VS) register file located in the VSU; and the processor is configured to map multiple consecutive VS register file entries to a single accumulator register file entry. [17] A computer system for processing information, the computer system comprising: at least one processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports for writing data to the main register file entries, and a plurality of read ports for reading data from the register file entries; one or more execution units including a complex mathematics execution unit, wherein the complex mathematics execution unit is a matrix multiplier-accumulator unit or an inference engine; at least one accumulator register file having a plurality of entries for storing data, wherein the at least one accumulator register file is associated with the complex mathematics execution unit, one or more computer-readable storage media; and Programming instructions stored in the one or more computer-readable storage media for execution by the at least one processor, the programming instructions including: Programming instructions that the complex math unit writes results multiple times to the same accumulator register file entry, and Programming instructions that, in response to the processor processing instructions of the complex mathematics unit: maps a single accumulator register file entry to a plurality of main register data entries, writes results to the same accumulator register file entry multiple times, deactivates the accumulator register file entry that has been written to the majority of times, Writes result data from the accumulator register file entry that has been written multiple times to the main register file; and releases the accumulator register file entry that was disabled. [18] A computer system for processing information, the computer system comprising: at least one processor, a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports for writing data to the main register file entries, and one or more read ports for reading data from the main register file entries; one or more execution units including a complex mathematics execution unit, wherein the complex mathematics execution unit is a matrix multiplier-accumulator unit or an inference engine; and at least one accumulator register file having a plurality of entries for storing data, wherein the at least one accumulator register file is associated with the complex mathematics execution unit, wherein the processor is configured to - Preparing an entry in an accumulator register file to receive data, - In response to preparing an accumulator register file to receive data, mark the one or more main register file entries mapped to the prepared accumulator register file entry as occupied - Processing data in the complex math execution unit, with the results of the complex math execution unit being written to the accumulator register file. [19] The computer system of claim 18, wherein the processor is configured to store the accumulator data register in response to an instruction to store data in the accumulator register file. [20] The computer system of claim 18, wherein the processor is configured to write results back to the same accumulator register file. [21] The computer system of claim 18, wherein the processor is configured to write data from the accumulator register file to the main register file. [22] The computer system of claim 18, wherein the accumulator register file is located in the matrix multiply accumulator (MMA) unit. [23] The computer system of claim 18, wherein a bit field width of the accumulator register file is larger than the bit field width of the main register file. [24] The computer system of claim 23, wherein each entry in the accumulator register file is mapped to a plurality of main register file entries. [25] The computer system of claim 18, wherein the accumulator register file is local to the complex math execution unit, and wherein the accumulator register file is mapped to a plurality of main register file entries.

Images