Stacked FET SRAM cell with bottom pFET

Abstract

A semiconductor structure is provided comprising a bottom field-effect transistor (FET) including a plurality of bottom source / drain (S / D) epitaxial regions, an top FET including a plurality of top S / D epitaxial regions, a dielectric interconnect layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S / D epitaxial region of the plurality of bottom S / D epitaxial regions of the bottom FET through the dielectric interconnect layer and into the top FET. The bottom FET includes an inverter gate. The top FET is electrically connected to back-end-of-line (BEOL) components, and the bottom FET is electrically connected to a back-side power supply network (BSPDN).

Claims

[1] Semiconductor structure that has: a lower field effect transistor, FET, having a plurality of lower source / drain, S / D epitaxial regions; an upper FET having a plurality of upper S / D epitaxial regions; a dielectric interconnect layer disposed directly between the lower FET and the upper FET; and a node contact extending from a lower S / D epitaxial region of the plurality of lower S / D epitaxial regions of the lower FET through the dielectric interconnect layer into the upper FET. [2] The semiconductor structure of claim 1, wherein the lower FET comprises an inverter gate. [3] The semiconductor structure of claim 2, wherein a gate cap is disposed on a gate metal of a lower pFET. [4] The semiconductor structure of claim 2, wherein the inverter gate is in direct contact with a plurality of the plurality of lower S / D epitaxial regions. [5] The semiconductor structure of claim 2, wherein the node contact is vertically aligned with a portion of the inverter gate. [6] The semiconductor structure of claim 1, wherein the upper FET is electrically connected to back-end-of-line, BEOL components and wherein the lower FET is electrically connected to a back-side power supply network, BSPDN. [7] The semiconductor structure of claim 1, wherein a bit line, BL, is in direct contact with an upper S / D epitaxial region of the plurality of upper S / D epitaxial regions. [8] A semiconductor structure according to claim 7, wherein a word line, WL, is in direct contact with a metal gate arranged in the upper FET. [9] The semiconductor structure of claim 8, wherein a gate cap is in direct contact with a cross-coupling in the lower FET. [10] Semiconductor structure having: a dielectric interconnect layer disposed directly between a lower field-effect transistor, FET, and an upper FET; and a node contact extending from the lower FET through the dielectric interconnect layer and into the upper FET to provide electrical connection to an inverter gate. [11] The semiconductor structure of claim 10, wherein a gate cap is disposed on a gate metal of a lower pFET. [12] The semiconductor structure of claim 10, wherein the inverter gate is in direct contact with a plurality of lower S / D epitaxial regions of the lower FET. [13] The semiconductor structure of claim 10, wherein a gate cap is in direct contact with a cross-coupling in the lower FET. [14] The semiconductor structure of claim 10, wherein the upper FET is electrically connected to back-end-of-line, BEOL components and wherein the lower FET is electrically connected to a back-side power supply network, BSPDN. [15] The semiconductor structure of claim 10, wherein a bit line, BL, is in direct contact with an upper S / D epitaxial region of the upper FET. [16] A semiconductor structure according to claim 10, wherein a word line, WL, is in direct contact with a metal gate arranged in the upper FET. [17] Method comprising: Forming bottom nanosheet stacks between a plurality of bottom source / drain, S / D epitaxial regions over sacrificial placeholders; Making a cut in a p-type field effect transistor, pFET; Depositing a sacrificial material into the pFET trench; Forming a gate cap over the sacrificial material to form a bottom FET; Forming a dielectric interconnect layer over the lower FET; Forming upper nanosheet stacks over the dielectric interconnect layer and between a plurality of upper S / D epitaxial regions; Removing sacrificial layers from the top and bottom nanosheet stacks to define initial openings; Depositing a replacement metal gate in the first openings; Forming a gate cut and a node contact, the node contact extending from the lower FET through the dielectric interconnect layer and into the upper FET; Selectively removing the sacrificial placeholders and sacrificial material to define second openings; and Filling the second openings with a cross coupling. [18] The method of claim 17, wherein a bit line, BL, is in direct contact with an upper S / D epitaxial region of the plurality of upper S / D epitaxial regions. [19] The method of claim 18, wherein a word line, WL, is in direct contact with the replacement metal gate disposed in the upper FET. [20] The method of claim 17, wherein the upper FET is electrically connected to back-end-of-line, BEOL components and wherein the lower FET is electrically connected to a back-side power supply network, BSPDN.

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