Device for testing a plurality of integrated circuits on a semiconductor wafer

Abstract

Probe card (3002) for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), said probe card (3002) comprising: - a plurality of probes (3002a) adapted to ensure a temporary electrical connection with the connectors (2000) of a plurality of integrated circuits (1001) to be tested on a semiconductor wafer (1000); - at least one buffer circuit (4001a) arranged to share the same power supply resource (SC1) of a tester (3004) with the power supply inputs (VCC) of a group of at least four integrated circuits (1001a-d) from among the plurality of integrated circuits (1001) to be tested;- at least one group (4002) of at least four multiplexer circuits (4002a-d) arranged so that the same high-voltage resource (HVC1) of the tester (3004) is shared with a first input of each of the four multiplexer circuits (4002a-d), a different electronic data input / output resource (DC1-4) of the tester (3004) is in electrical communication with a second input of each of the four multiplexer circuits (4002a-d), and the output of each of the four multiplexer circuits (4002a-d) is in electrical communication with a test input / output (SPT) of an integrated circuit (1001a-d) of said group of at least four integrated circuits (1001a-d) from among the plurality of integrated circuits (1001) to be tested.;

Description

Title of the invention: Device for testing a plurality of integrated circuits on a semiconductor wafer Technical field

[0001] The present invention relates to a device and method for testing a plurality of integrated circuits on a semiconductor wafer. Technical background

[0002] In the microelectronics industry, integrated electronic circuits or chips, also called "chips", "integrated circuits", or "dies" in English, are generally mass-produced in large quantities on a single semiconductor wafer, particularly on a silicon wafer. Integrated circuits can include different elements such as a memory circuit, a microprocessor, a fuse circuit, communication buses, logic circuits such as flip-flops, latches or buffers, and other input / output interface circuits ("I / O circuits").

[0003] Before being cut and packaged, each integrated circuit is subjected to a performance or failure test in order to verify whether its electrical characteristics comply with the specifications for which it was designed. For example, a performance test may be conducted in which signals in the form of a data frame are sent to the input of the integrated circuit and the response signals at the output of the circuit are monitored and analyzed. When the response signals are not compliant, the integrated circuit is declared defective and discarded. A static failure test may also be conducted in which high voltages and / or currents are applied to the integrated circuits in order to eliminate those likely to be affected by early failure.

[0004] It is common practice to conduct performance and failure tests using an automatic tester ("ATE" - "Automated Test Equipment") which is in the form of a programmable electronic system whose main function is to implement a test program such as, for example, sending a set of data frames, or voltage and / or current values ​​at the input of the integrated circuits, then collecting and analyzing the response signals of said circuits. To ensure this function, the tester has inputs-outputs, called resources ("channels"), the number of which generally determines the number of integrated circuits that it is capable of testing simultaneously.

[0005] The automatic tester generally communicates with the integrated circuits under test conditions via an interface card, itself connected to a probe card. The probe card is configured to establish an electrical connection between the interface board and test connectors ("pads") specific to the integrated circuits. The interface board relays and, possibly, preprocesses the signals between the probe card and the tester. When under test conditions by the automatic tester, integrated circuits are often referred to as DUTs ("Devices Under Test"). They are generally tested in rows directly on the semiconductor wafer.

[0006] The probe card is generally in the form of an electronic card provided with a plurality of tips or pads, the number and dimensions of which correspond to the density and size of the test connectors specific to the integrated circuits, and the arrangement of which allows the redistribution of the electrical signals exchanged between the tester and the integrated circuits via the interface card. In use, the probe card generally remains fixed while the wafer containing the integrated circuits is placed under the probe card using a mobile plate ("prober") so as to establish electrical contact between the connectors of the integrated circuits of a row of electrical circuits and the tips of the probe card.

[0007] In the semiconductor industry, and more generally, in the microelectronics industry, the cost of testers and the time required to conduct integrated circuit performance testing procedures are major concerns in the face of ever-increasing and faster circuit production demands.

[0008] A general trend is to increase the number of integrated circuits tested simultaneously, especially when the test procedure cycles are particularly long. This is the case, for example, with integrated circuits comprising non-volatile memories which require, in their test procedures, numerous write and erase operations. Today, several dozen or even hundreds of integrated circuits are tested simultaneously in parallel depending on the available resources of the testers and probe cards. In addition to increasing the number of integrated circuits simultaneously, it is also common to optimize the test procedures or to modify the design of the circuits to reduce the test duration.

[0009] US 4956602 A, [AMBER ENGINEERING INC [US]], 11.09.1990 describes a semiconductor wafer whose surface comprises a plurality of integrated circuits and a plurality of multiplexers composed of multiplexing lines located in the cutting areas of the wafer. The integrated circuits are connected to a reduced number of test connectors via the multiplexers. A greater number of integrated circuits can be tested in parallel with the same number of test connectors.

[0010] US 6366112 B1 [MICRON TECHNOLOGY INC [US]] 09.10.2001 describes a probe card comprising a multiplexer circuit configured to selectively broadcast and transmit test signals from a tester to the integrated circuits of a wafer in semiconductor. The multiplexer circuit allows the tester's resources to be distributed over several integrated circuits tested in parallel. The probe card comprises a silicon-based substrate on which contactors are formed by chemical etching. The contactors are of suitable dimensions to be placed in contact with the connectors of the integrated circuits to be tested. Each multiplexer circuit is formed of a plurality of field-effect transistors allowing the contactors to be selected using control signals. Each multiplexer circuit redistributes the resources of each tester's test site to multiply the number of integrated circuits that can be originally tested by each test site.

[0011] US 6400173 B1 [HITACHI LTD [JP] 04.06.2002 discloses a system for reducing the testing time of integrated circuits on a semiconductor wafer. The system comprises a probe card provided with a plurality of tips spatially arranged so as to be connectable to the connectors of the integrated circuits. The tips are connected to a plurality of test circuits included in the probe card. The test circuits are configured to exchange electrical signals with the integrated circuits and generate test results according to a given test program.

[0012] US 2003 074611 Al [TOWER SEMICONDUCTOR LTD [US]] 17.04.2003 describes a system for increasing the number of non-volatile memory integrated circuits that can be tested simultaneously in parallel. The system comprises a tester, a probe card and an alignment plate. The probe card comprises a substrate provided with an auxiliary circuit, a first series of connectors arranged on one of its surfaces and adapted to be electrically connected to the tester, and a second series of connectors arranged on its other surface and adapted to be electrically connected to connectors arranged on the wafer comprising the integrated circuits to be tested. The two series of connectors are also connected to the auxiliary circuit via switches configured to possibly bypass it.The auxiliary circuit comprises a plurality of self-diagnostic circuits which can be respectively associated in parallel with the integrated circuits of a wafer. This configuration makes it possible to reduce the time required to carry out read or erase operations in the non-volatile memory of the integrated circuits. Self-diagnostic circuits can also be directly integrated in the cutting lines of the wafer comprising the integrated circuits to be tested. They are configured to exploit only a limited number of connectors of the integrated circuits and to share certain connectors between several circuits, thus increasing the number of circuits which can be tested in parallel.

[0013] US 6903565 B2 [INFINEON TECHNOLOGIES AG [DE]] 07.06.2005 describes a system for parallel testing of a plurality of integrated circuits on a semiconductor wafer. The system comprises a probe card provided with tips and a interface card. The system comprises an external power supply unit for providing a supply voltage to a plurality of integrated circuits. The interface card comprises a voltage regulation unit controlled by a reference voltage source, and an electrical current limiting unit for measuring the current consumed by the integrated circuits. The electrical current limiting unit is configured to operate an electrical isolation device when the current consumed exceeds a certain threshold.

[0014] WO 2006 083856 Al [FORMFACTOR INC [US]] 10.08.2006 and WO 2007 146583 A2 [FORMFACTOR INC [US]] 21.12.2007 describe a probe card comprising a circuit for sharing a power supply resource of a tester between four integrated circuits. Each integrated circuit is associated with a voltage regulation module for isolating an integrated circuit in the event of a current overload. The probe card may comprise a multiplexer circuit for redirecting the output signals of the integrated circuits to the tester.

[0015] US 8378698 B2 [SAMSUNG ELECTRONICS CO LTD [KR]] 19.02.2013 describes a probe card provided with tips adapted to be in electrical contact with the connectors of a plurality of integrated circuits on a semiconductor wafer. The probe card comprises a plurality of test circuits, each test circuit itself comprising a plurality of signal transmitters corresponding to an integrated circuit to be tested on the semiconductor wafer. Electrical voltages and control signals from a tester are relayed by the signal transmitters and sent to the integrated circuits. The signal transmitters are further configured to relay response signals from the integrated circuits to the tester.

[0016] US 2016011232 Al [INFINEON TECHNOLOGIES AG [DE]] 14.01.2016 describes a system for increasing the number of integrated circuits that can be tested simultaneously in parallel without having to increase the number of resources of the tester. The system comprises a tester, an interface card and a probe card in the form of a circuit provided with a plurality of connectors adapted to be connected to a plurality of integrated circuits. The circuit of the probe card is configured to exchange an identical instruction with all the integrated circuits to which it is connected and exchange an instruction with the tester via the interface card.

[0017] US 2022 341991 Al [WINBOND ELECTRONICS CORP [TW]] 27.10.2022 discloses a system for the number of integrated circuits that can be tested simultaneously in parallel by sharing the available resources of a tester. The system comprises a tester and a test device consisting of an interface circuit and an analysis circuit. The interface circuit is simultaneously connected to four integrated circuits to be tested on a silicon wafer and allows signals to be transmitted from the tester to the integrated circuits. The interface circuit comprises a buffer circuit coupled to the four integrated circuits to be tested and the design circuit. The buffer circuit allows the tester's power resource to be redistributed between the four circuits as well as the control and input-output signals. The analysis circuit receives and serializes the output signals from the four integrated circuits using flip-flop circuits before communicating them to the tester. Summary of the invention Technical problem

[0018] A significant trend in the microelectronics industry is the development of low-power integrated circuits in order to reduce their energy consumption. Concretely, this trend results in a reduction in the operating voltages and electrical currents of integrated circuits. For example, in the field of smart cards, the development effort is currently focused on class B and C integrated circuits within the meaning of ISO / IEC 7816-3:2006, i.e. integrated circuits with operating voltages and currents respectively lower than 3.3 V and 50 mA for class B and lower than 1.98 V and 30 mA for class C.

[0019] A direct consequence of this trend is the priority development of testers adapted to this type of integrated circuits, and, due to the high costs and technical constraints of installing such testers, their preferred deployment within semiconductor foundries, in particular within shared foundries ("open foundries"). In other words, "high power" testers of electronic circuits with high operating voltages such as, for example, class A integrated circuits in the field of smart cards, are becoming less and less available in foundries. Either they are, in current foundries, gradually replaced by "low power" testers, or, in new foundries, they are no longer deployed.

[0020] Despite the general trend towards low-power electronics, there still remains a need for manufacturing high-power integrated circuits - for example, class A integrated circuits in the field of smart cards. However, the implementation of performance and failure tests, in particular static failure tests, on this type of integrated circuit requires the use of "high-power" testers, the availability of which is now becoming increasingly rare. And, for cost reasons, it is essential to test the integrated circuits on the production site, i.e. in the foundry. There therefore appears to be a need to be able to conduct performance and failure tests on "high-power" circuits such as, in particular, class A integrated circuits in the field of smart cards, using testers which are not suitable for implementing these tests on this type of integrated circuit. Technical solution

[0021] In a first aspect of the invention, there is provided a probe card for testing a plurality of integrated circuits on a semiconductor wafer, said probe card comprising: - a plurality of tips adapted to provide a temporary electrical connection with the connectors of a plurality of integrated circuits to be tested on a semiconductor wafer; - at least one buffer circuit arranged to share a same power supply resource of a tester with the power supply inputs of a group of at least four integrated circuits among the plurality of integrated circuits to be tested; - at least one group of at least four multiplexer circuits arranged so that the same high-voltage resource of the tester is shared with a first input of each of the four multiplexer circuits, a different electronic data input / output resource of the tester is in electrical communication with a second input of each of the four multiplexer circuits, and the output of each of the four multiplexer circuits is in electrical communication with a test input / output of an integrated circuit of said group of at least four integrated circuits among the plurality of integrated circuits to be tested.

[0022] In particular embodiments, the probe card according to the invention may further comprise one or more of the following characteristics, taken individually or according to all possible technical combinations:

[0023] - each multiplexer circuit of a group of multiplexer circuits is configured to simultaneously connect the high-voltage resource of the tester with the test input / output of each integrated circuit of the group of at least four integrated circuits among the plurality of integrated circuits to be tested according to a first control signal value.

[0024] - each multiplexer circuit of a group of multiplexer circuits is configured to sequentially connect the high-voltage resource of the tester with the test input / output of each integrated circuit of the group of at least four integrated circuits among the plurality of integrated circuits to be tested according to a second control signal value.

[0025] - each multiplexer circuit of a group of multiplexer circuits is configured to simultaneously connect an electronic resource of the tester with the test input / output of each integrated circuit of the group of at least four integrated circuits among the plurality of integrated circuits to be tested according to a third control signal value.

[0026] - the first value of the control signal corresponds to a static failure test integrated circuits to be tested by applying an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

[0027] - the second value of the control signal corresponds to a measurement test of the circuits integrated to be tested with an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

[0028] - the third value of the control signal corresponds to a current measurement of the integrated circuits to be tested with an electrical voltage below a threshold value, preferably below a fixed threshold value of 4.5V.

[0029] - the buffer circuits and / or the multiplexer circuit groups are integrated in an interface card in electrical communication with said probe card.

[0030] - the probe card is further adapted to be in electrical communication with a Class B and / or C integrated circuit tester, and a plurality of Class A integrated circuits to be tested according to ISO / IEC 7816-3:2006.

[0031] - the probe card is further adapted to be in electrical communication with a tester configured to test semiconductor mass memory and / or random access memory architectures.

[0032] In a second aspect of the invention, there is provided a system comprising a tester and a probe card according to the first aspect of the invention.

[0033] In a third aspect of the invention, alternative or complementary methods are provided for testing a plurality of integrated circuits on a semiconductor wafer, including: - A method for testing a plurality of integrated circuits on a semiconductor wafer, said method comprising the following steps: - sharing a power supply resource of a tester with the power supply inputs of a group of at least four integrated circuits among the plurality of integrated circuits to be tested; - connecting in parallel the same high-voltage resource of said tester with a test input / output of each integrated circuit of a group of at least four integrated circuits among the plurality of integrated circuits to be tested; - apply an electrical voltage greater than a threshold value to the test input / output of each integrated circuit of said at least four integrated circuits; - check the operation of each of the integrated circuits by analyzing the response signals via their respective test input / output. - A method for testing a plurality of integrated circuits on a wafer in semiconductor, said method comprises the following steps: - sequentially connecting a high-voltage resource of said tester with a test input / output of each integrated circuit of a group of at least four integrated circuits among the plurality of integrated circuits to be tested; - sequentially applying an electrical voltage greater than a threshold value to the test input / output of each integrated circuit of said group of at least four integrated circuits; - sequentially measure the response of each of the integrated circuits by analyzing the response signals via their respective test input / output. - A method for testing a plurality of integrated circuits on a semiconductor wafer, said method comprising the following steps: - connecting in parallel an electronic data input / output resource of said tester with a test input / output of each integrated circuit of a group of at least four integrated circuits among the plurality of integrated circuits to be tested; - sending in parallel a data frame on the test input / output of each integrated circuit of said group of at least four integrated circuits; - receive in parallel a response data frame from each of the integrated circuits by analyzing the response signals via their respective test input / output.

[0034] In a fourth aspect of the invention, there is provided a computer program comprising instructions which, when the program is executed by a computer, cause the computer to implement one of the methods according to the third aspect of the invention using a system according to the second aspect. Brief description of the drawings

[0035] [Fig-1] a schematic representation of a semiconductor wafer on which integrated circuits are formed.

[0036] [Fig.2] a schematic representation of a group of four integrated circuits.

[0037] [Fig.3] a schematic representation of a performance testing and debugging system failure of integrated circuits on semiconductor wafers.

[0038] [Fig.4] is a structural diagram of a probe card according to the first aspect of the invention.

[0039] [Fig.5] is a functional diagram of a probe card according to a first mode of realization lization.

[0040] [Fig.6] is a functional diagram of a probe card according to a second mode of realization.

[0041] [Fig.7] is a functional diagram of a probe card according to a third mode of realization. Detailed description of the embodiments

[0042] With reference to [Fig.l], the integrated circuits 1001, also called electronic chips, are generally mass-produced in large quantities on a single semiconductor wafer 1000. Their arrangement is often according to a Hippodamian plan in which the circuits are arranged in columns 1002a-n and in rows 1003a-n so as to facilitate their identification and to allow several of them to be tested in parallel during performance and failure tests.

[0043] In the context of the present invention, the term "integrated circuit" is understood to mean an indivisible set of electrically interconnected electronic components inseparably associated on a semiconductor substrate. The integrated circuit implements, through its components, logic operations for processing electromagnetic signals, in particular electrical signals. It may be a programmable microcontroller or one or more sub-elements such as a microprocessor, a random access memory, a read-only memory, a fuse circuit breaker, communication buses, logic circuits of the flip-flop, latch or buffer type, and other input / output interface circuits ("FO circuits").

[0044] With reference to [Fig. 2], an integrated circuit 1001 comprises a number of VCC, DQ, SPT inputs-outputs. Some of these VCC, DQ inputs-outputs can be used during performance and failure testing procedures, and later during the implementation and use of the integrated circuits in electronic devices. Other SPT inputs-outputs are solely dedicated to performance and failure testing procedures. The inputs-outputs have different functions. In the example of [Fig. 2], the VCC input-output is a power supply input, the DQ input-output is a data exchange input-output during the subsequent use of the circuit in electronic devices, and the SPT input-output is an input-output exclusively dedicated to the performance and failure testing procedures of the circuit 1001.

[0045] On the wafer 1000, the inputs-outputs of the circuits are connected to connectors 2000 (“pads”) in order to allow their connection with the tips of a probe card during the performance and failure test procedures. These connectors may be solely dedicated to the test procedures and not be intended for use in the electronic device in which the circuit will be subsequently implemented. They may be arranged in the cutting areas of the wafer so that they can be eliminated during the packaging of the circuits, or simply be kept in the electronic device during packaging but remain unused.

[0046] With reference to [Fig. 3], a system 3000 for testing the performance and failure of integrated circuits 1001 on a semiconductor wafer 1000 comprises a movable support ("holder" or "prober") 3001 for the semiconductor wafer, a probe card 3002, an interface card 3003 and an automatic tester (ATE) 3004. The probe card 3002 has the form of an electronic card provided with a plurality of tips or pads 3002a. The tips 3002 are brought into contact with the test connectors (not shown) specific to the integrated circuits 1001 and allow the redistribution of the electrical signals exchanged between the tester 3004 and the integrated circuits 1001 via the interface card 3003. Their number and dimensions correspond to the density and size of the test connectors of the integrated circuits 1001.

[0047] During operation of the system, the probe card 3002 generally remains fixed while the wafer 1000 comprising the integrated circuits 1001 is placed under the probe card by the support 3001 so as to establish electrical contact between the connectors 2000 of the integrated circuits 1001 of a row of electrical circuits and the tips 3002a of the probe card 3002. Each test connector of an integrated circuit 1001 is thus placed in electrical communication with a resource 3004a of the tester 3004. For example, with reference to [Fig. 2], the VCC input-output can be placed in electrical communication with a power supply resource of the tester, and the SPT input-output can be placed in electrical communication with a high-voltage resource or an electronic resource of the tester. The number of resources of the tester generally determines the number of integrated circuits that it is capable of testing simultaneously.

[0048] In the context of the present invention, the term "resources" ("channel") of a tester is understood to mean the inputs-outputs of the tester making it possible to exchange a set of data frames with electronic circuits, and / or to apply values ​​of voltages and / or electric currents at the input of the integrated circuits.

[0049] In the context of the present invention, the term "power supply resource" of a tester is understood to mean a resource making it possible to deliver a voltage and / or an electric current sufficient to power an integrated circuit and start it. The term "electronic resource" is understood to mean a resource making it possible to exchange a data frame between said tester and a connector of an integrated circuit. The term "high-voltage resource" of a tester is understood to mean a resource making it possible to deliver a voltage higher than that of one of its electronic resources. In particular, this type of resource can deliver voltages of several tens of volts, for example. up to 30 volts.

[0050] As illustrated in [Fig.3], the probe card 3002 comprises a set of electrical circuits 3002b having the function of distributing the resources of the tester to the connectors of the integrated circuits via the interface card.

[0051] In a first aspect of the invention, with reference to [Fig.3] & 4, there is provided a probe card 3002 for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000, said probe card 3002 comprising: - a plurality of tips 3002a adapted to ensure a temporary electrical connection with the connectors 2000 of a plurality of integrated circuits 1001 to be tested on a semiconductor wafer 1000; - at least one buffer circuit 4001a arranged to share a same power supply resource SCI of a tester 3004 with the power supply inputs VCC of a group of at least four integrated circuits lOOla-d among the plurality of integrated circuits 1001 to be tested; - at least one group 4002 of at least four multiplexer circuits 4002a-d arranged so that the same high-voltage resource HVC1 of the tester 3004 is shared with a first input of each of the four multiplexer circuits 4002a-d, a different data input / output electronic resource DC1-4 of the tester 3004 is in electrical communication with a second input of each of the four multiplexer circuits 4002a-d, and the output of each of the four multiplexer circuits 4002a-d is in electrical communication with a test input / output SPT of an integrated circuit lOOla-d of said group of at least four integrated circuits lOOla-d among the plurality of integrated circuits 1001 to be tested.

[0052] For illustrative purposes, in [Fig. 4], two buffer circuits 4001a, 4001b and two groups 4002, 4003 of multiplexer circuits are shown. The number of buffer circuits and groups of multiplexer circuits is a function of the number of high-voltage resources of the tester 3004. For example, for a tester such as the Magnum V EV marketed by Teradyne Inc ®, comprising 512 electronic resources, 128 high-voltage resources and 128 power supply resources, the number of buffer circuits and groups of multiplexer circuits can reach 512. The probe card 3002 according to the first aspect of the invention can be implemented with other types of tester, in particular with testers comprising 1024 electronic resources, 256 high-voltage resources and 256 power supply resources. The number of integrated circuits that can be tested simultaneously using the probe card according to the first aspect of the invention can then reach 1024.

[0053] The number of integrated circuits per buffer circuit and per group of multiplexer circuits is at least four, with one multiplexer circuit per integrated circuit. Thus, in the configuration of the previous example, a probe card 3002 according to the first aspect of the invention can allow testing 512 integrated circuits simultaneously by sharing the power resources and high-voltage resources of the tester. The number of integrated circuits per buffer circuit and per group of multiplexer circuits can be higher. It can be equal to a power N of 2 with N greater than 2.

[0054] A remarkable advantage of a probe card according to the first aspect of the invention is the possibility of carrying out static tests on integrated circuits, in particular class A integrated circuits in the field of smart cards, using testers which are not suitable for implementing these tests on this type of integrated circuit. In the previous example, the electrical voltage delivered by the electronic resources of the Magnum V tester is suitable for class B and C integrated circuits. The probe card according to the first aspect of the invention makes it possible to use such a tester on a class A integrated circuit, in particular for a static performance or failure test on non-volatile memory type elements, for example Flash, of the integrated circuits.

[0055] The multiplexer circuits 4002a-d, 4003a-d of each group 4002, 4003 are configured to propagate one of their inputs to their output depending on the value of a control signal CS1, CS2. This operation can be executed in a different manner depending on the nature of the test implemented on the integrated circuits.

[0056] According to a first embodiment, with reference to [Fig. 5], each multiplexer circuit of a group 4002 of multiplexer circuits 4002a-d is configured to simultaneously connect the high-voltage resource HVC1 of the tester 3004 with the test input / output SPT of each integrated circuit of the group of at least four integrated circuits 1001a-d among the plurality of integrated circuits 1001 to be tested according to a first control signal value CSL. According to a first control signal value CS1, the multiplexer circuits 4002a-d of the group 4002 simultaneously, therefore in parallel, propagate the same high-voltage resource HVC1 on their output to the test input / output SPT of each integrated circuit 1001a-d.

[0057] This first embodiment is particularly suitable for implementing static failure tests on integrated circuits, in particular on the memory elements of class A integrated circuits. Thus, according to a preferred variant, the first value of the control signal CS1 corresponds to a static failure test of the integrated circuits to be tested by applying an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

[0058] According to a second embodiment, alternative or complementary to the first embodiment, with reference to [Fig.6], each multiplexer circuit of a group 4002 of multiplexer circuits 4002a-d is configured to sequentially connect the high-voltage resource HVC1 of the tester 3004 with the test input / output SPT of each integrated circuit of the group of at least four integrated circuits 1001a-d among the plurality of integrated circuits 1001 to be tested according to a second value of control signal CS1. According to a second value of the control signal CS1, the multiplexer circuits 4002a-d of the group 4002 propagates one after the other the high-voltage resource HVC1 with the test input / output SPT of the circuits of each integrated circuit lOOla-d. The integrated circuits are tested individually one after the other.

[0059] This second embodiment is particularly suitable for implementing static performance tests on integrated circuits based on the measurement and analysis of a response signal of an integrated circuit. The measurement of the response signal may in particular consist of a measurement of the voltage on the SPT test input / output of each 1001a-d integrated circuit. Thus, according to a preferred variant, in particular applicable to class A integrated circuits, the second value of the control signal (SCI) corresponds to a measurement test of the integrated circuits to be tested with an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

[0060] According to a third embodiment, alternative or complementary to the two other previous embodiments, with reference to [Fig.7], each multiplexer circuit of a group 4002 of multiplexer circuits 4002a-d is configured to simultaneously connect an electronic resource EC1-4 of the tester 3004 with the test input / output SPT of each integrated circuit of the group of at least four integrated circuits lOOla-d among the plurality of integrated circuits 1001 to be tested according to a third control signal value CSL. According to a third control signal value CS1, the multiplexer circuits 4002a-d propagate simultaneously, and therefore in parallel, an electronic data input / output resource DC1-8 of the tester 3004 to the test input / output SPT of each integrated circuit of the group of at least four integrated circuits lOOla-d. A single DC1-8 data input / output electronic resource of the 3004 tester is used for each lOOla-d integrated circuit.

[0061] This third embodiment is particularly suitable for implementing routine measurement tests on integrated circuits such as the exchange of one or more data frames between the tester and the integrated circuits. The data frame(s) may consist of a succession of voltage values ​​whose durations and values ​​correspond respectively to time constants and bit values. For example, the tester may communicate, via its electronic resources, instructions to the integrated circuits for the execution of a succession of write and read operations in their memory element. In a preferred variant, the third value of the control signal CS 1 corresponds to a current measurement of the integrated circuits to be tested with an electrical voltage lower than a threshold value, preferably lower than a fixed threshold value of 4.5V.

[0062] In all of the embodiments and their variants described above, the buffer circuits 4001a, 4001b and the groups 4002, 4003 of multiplexer circuits are part of the probe card 3002. However, in certain systems 3000 for testing integrated circuits 1001, such as that illustrated in [Fig. 3], it may be common to use an interface card 3003 between the tester and the probe card 3002. Also, in certain alternative embodiments, the buffer circuits 4001a, 4001b and / or the groups 4002, 4003 of multiplexer circuits are integrated in an interface card 3003 in electrical communication with said probe card 3002.

[0063] A probe card 3002 according to the first aspect of the invention can operate with any type of suitable tester. However, as mentioned previously, an advantage of a probe card 3002 according to the first aspect of the invention is the possibility of carrying out static tests on class A integrated circuits 1001 in the field of smart cards using testers which are not suitable for implementing these tests on this type of integrated circuit. Also, according to preferred embodiments, combinable with all the embodiments described previously, the probe card 3002 according to the first aspect of the invention is further adapted to be in electrical communication with a tester 3004 of class B and / or C integrated circuits 1001, and a plurality of class A integrated circuits to be tested according to the ISO / IEC 7816-3:2006 standard.

[0064] A probe card 3002 according to any one of the embodiments of the first aspect of the invention can be advantageously used to test any type of integrated circuit, in particular the non-volatile memory elements of the integrated circuits. According to preferred embodiments, it can further be adapted to be in electrical communication with a tester 3004 configured to test semiconductor mass memory type architectures, for example flash memories, and / or random access memory type architectures.

[0065] In a second aspect of the invention, there is provided a system 3000 for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000. The system comprises a probe card 3002 according to the first aspect of the invention and a tester 3004. The tester 3004 may be a Class A integrated circuit tester 1001 or a Class B and / or C integrated circuit tester within the meaning of ISO / IEC 7816-3:2006.

[0066] In a third aspect of the invention, several alternative or complementary methods are provided for testing a plurality of integrated circuits on a semiconductor wafer.

[0067] According to a first variant, a method is provided for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000, said method comprises the following steps: - share a 3004 tester's SCI power supply resource with the VCC power supply inputs of a group of at least four integrated circuits 1001-d among the plurality of integrated circuits 1001 to be tested; - connecting in parallel the same high-voltage resource HVC1 of said tester 3001 with a test input / output SPT of each integrated circuit of a group of at least four integrated circuits lOOla-d among the plurality of integrated circuits 1001 to be tested; - applying an electrical voltage greater than a threshold value to the test input / output SPT of each integrated circuit of said at least four integrated circuits lOOla-d; - verifying the operation of each of the integrated circuits lOOla-d by analyzing the response signals via their respective test input / output SPT.

[0068] A method according to this first variant simultaneously subjects the integrated circuits to a static failure test by imposing on them a voltage greater than a threshold value via the sharing of the same high-voltage resource of the tester. The method is particularly suitable for implementing static failure tests on the non-volatile memory elements of class A integrated circuits. The threshold value of the voltage can advantageously be set at 4.5V.

[0069] According to a second variant, a method is provided for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000, said method comprises the following steps: - sequentially connecting a high-voltage resource HVC 1 of said tester 3004 with a test input / output SPT of each integrated circuit of a group of at least four integrated circuits lOOla-d among the plurality of integrated circuits 1001 to be tested; - sequentially applying an electrical voltage greater than a threshold value to the SPT test input / output of each integrated circuit of said group of at least four integrated circuits lOOla-d; - sequentially measure the response of each of the lOOla-d integrated circuits by analyzing the response signals via their respective SPT test input / output.

[0070] A method according to this second variant successively subjects the integrated circuits to a performance test by imposing on them a voltage greater than a threshold value via the sequential sharing of the same high-voltage resource of the tester. The method is particularly suitable for implementing static failure tests on the non-volatile memory elements of class A integrated circuits. The threshold value of the voltage can advantageously be set at 4.5V.

[0071] According to a third variant, a method is provided for testing a plurality of 1001a-d integrated circuits on a 1000 semiconductor wafer, said method comprising the following steps: - connecting in parallel a data input / output electronic resource DC1-4 of said tester 3004 with a test input / output SPT of each integrated circuit of a group of at least four integrated circuits lOOla-d among the plurality of circuits integrated 1001 to test; - sending in parallel a data frame on the SPT test input / output of each integrated circuit of said group of at least four lOOla-d integrated circuits; - receive in parallel a response data frame from each of the lOOla-d integrated circuits by analyzing the response signals via their respective SPT test input / output.

[0072] A method according to this third variant simultaneously subjects the integrated circuits to a current measurement test by exchanging a data frame between the tester and the integrated circuits via the electronic resources of the tester. For example, the tester can communicate, via its electronic resources, instructions to the integrated circuits, in particular class A integrated circuits, for the execution of a succession of write and read operations in their memory element.

[0073] The methods according to the three preceding variants can be implemented alternatively or complementary by any means. Preferably, they are implemented using a system according to the second aspect of the invention. They can be implemented by the tester itself or by means of a data processing device configured to control the tester so that it executes the steps thereof.

[0074] An example of a data processing device is a device that can be instructed to automatically execute sequences of arithmetic or logical operations to perform tasks or actions. This device, also called a computer, may include one or more central processing units (CPUs) and / or one or more graphics processors (GPUs) as well as at least one control device adapted to perform these operations. It may also include other electronic components such as input / output interfaces, non-volatile or volatile storage devices, and communication buses for transferring data between internal components of the device or with external components. One of the input / output interfaces may be a user interface for human-machine interaction, for example a graphical user interface for displaying human-understandable information.For the implementation of one or more of the methods according to the third aspect of the invention, the device may comprise an input / output interface in electronic communication with a tester, and possibly a card according to the first aspect of the invention.

[0075] In a fourth aspect of the invention, there is provided a computer program comprising instructions which, when the program is executed by a computer, cause the computer, via a system according to the second aspect of the invention, to implement one or more of the methods according to the third aspect of the invention. The program may be stored in the memory of a data processing device as described above and executed by it. Alterna tively, it can be executed by the tester itself after it has been loaded into memory.

[0076] Any type of programming language, compiled or interpreted, may be used to implement the steps of the method according to the third aspect of the invention in a computer program. The computer program may be part of a software solution, i.e. a collection of executable instructions, codes, scripts or the like and / or databases.

[0077] The computer program may be stored on a recording medium readable by the computer or the tester. The recording medium preferably is non-volatile memory, for example a hard disk or a solid-state drive. It may be a removable storage medium or a non-removable storage medium forming part of the computer. It may also be volatile memory within a removable medium or form part of a computer used as a server from which executable instructions may be downloaded and, when executed by a computer, cause the computer to execute a method according to the third aspect of the invention. References Patent literature

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[0079] US 6366112 B1 [MICRON TECHNOLOGY INC [US]] 09.10.2001.

[0080] US 6400173 B1 [HITACHI LTD [JP] 04.06.2002.

[0081] US 2003 074611 Al [TOWER SEMICONDUCTOR LTD [US]] 17.04.2003.

[0082] US 6903565 B2 [INFINEON TECHNOLOGIES AG [DE]] 07.06.2005.

[0083] WO 2006 083856 Al [FORMFACTOR INC [US]] 10.08.2006.

[0084] WO 2007 146583 A2 [FORMFACTOR INC [US]] 21.12.2007.

[0085] US 8378698 B2 [SAMSUNG ELECTRONICS CO LTD [KR]] 19.02.2013.

[0086] US 2016011232 Al [INFINEON TECHNOLOGIES AG [DE]] 14.01.2016.

[0087] US 2022 341991 Al [WINBOND ELECTRONICS CORP [TW]] 27.10.2022. Littérature non-brevet

[0088] ISO / IEC 7816-3 - Identification cards — Integrated circuit cards — Part 3: Cards with contacts — Electrical interface and transmission protocols, 2006.

Claims

Claims

1. A probe card (3002) for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), said probe card (3002) comprising: - a plurality of tips (3002a) adapted to provide a temporary electrical connection with the connectors (2000) of a plurality of integrated circuits (1001) to be tested on a semiconductor wafer (1000); - at least one buffer circuit (4001a) arranged to share a same power supply resource (SCI) of a tester (3004) with the power supply inputs (VCC) of a group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits (1001) to be tested;- at least one group (4002) of at least four multiplexer circuits (4002a-d) arranged so that the same high-voltage resource (HVC1) of the tester (3004) is shared with a first input of each of the four multiplexer circuits (4002a-d), a different data input / output electronic resource (DC1-4) of the tester (3004) is in electrical communication with a second input of each of the four multiplexer circuits (4002a-d), and the output of each of the four multiplexer circuits 4002a-d is in electrical communication with a test input / output (SPT) of an integrated circuit (1001a-d) of said group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits (1001) to be tested.;

2. A probe card (3002) according to claim 1, such that each multiplexer circuit of a group (4002) of multiplexer circuits (4002a-d) is configured to simultaneously connect the high-voltage resource (HVC1) of the tester (3004) with the test input / output (SPT) of each integrated circuit of the group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits (1001) to be tested according to a first control signal value (CS1).

3. A probe card according to any one of claims 1 to 2, such that each multiplexer circuit of a group (4002) of multiplexer circuits (4002a-d) is configured to sequentially connect the high-voltage resource (HVC1) of the tester (3004) with the test input / output (SPT) of each integrated circuit of the group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits (1001) to be tested. depending on a second control signal value (CS1).

4. A probe card (3002) according to any one of claims 1 to 3, such that each multiplexer circuit of a group (4002) of multiplexer circuits (4002a-d) is configured to simultaneously connect an electronic resource (EC1-4) of the tester (3004) with the test input / output (SPT) of each integrated circuit of the group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits 1001 to be tested according to a third control signal value (CS1).

5. Probe card (3002) according to claim 2, such that the first value of the control signal (CS1) corresponds to a static failure test of the integrated circuits to be tested by applying an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

6. Probe card (3002) according to claim 3, such that the second value of the control signal (CS1) corresponds to a measurement test of the integrated circuits to be tested with an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

7. Probe card (3002) according to claim 4, such that the third value of the control signal (CS1) corresponds to a current measurement of the integrated circuits to be tested with an electrical voltage lower than a threshold value, preferably lower than a fixed threshold value at 4.5V.

8. A probe card (3002) according to any one of claims 1 to 7, such that the buffer circuits (4001a, 4001b) and / or the groups (4002, 4003) of multiplexer circuits are integrated in an interface card (3003) in electrical communication with said probe card (3002).

9. A probe card (3002) according to any one of claims 1 to 8, as further adapted to be in electrical communication with a tester (3004) of integrated circuits (1001) of class B and / or C, and a plurality of integrated circuits to be tested of class A according to ISO / IEC 7816-3:2006.

10. A probe card (3002) according to any one of claims 1 to 9, as further adapted to be in electrical communication with a tester (3004) configured to test semiconductor mass storage and / or random access memory architectures.

11. A system (3000) for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000) comprising a tester (3004) and a probe card (3002) according to any one of claims 1 to 10.

10.

12. A method for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), said method comprising the following steps: - sharing a power supply resource (SCI) of a tester (3004) with the power supply inputs (VCC) of a group of at least four integrated circuits lOOla-d among the plurality of integrated circuits (1001) to be tested; - connecting in parallel the same high-voltage resource (HVC1) of said tester (3001) with an SPT test input / output of each integrated circuit of a group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits (1001) to be tested; - apply an electrical voltage greater than a threshold value to the test input / output (SPT) of each integrated circuit of said at least four integrated circuits (lOOla-d); - check the operation of each of the integrated circuits (1001a-d) by analyzing the response signals via their respective test input / output (SPT).

13. A method for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), said method comprising the following steps: - sequentially connecting a high-voltage resource (HVC 1) of said tester (3004) with a test input / output (SPT) of each integrated circuit of a group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits (1001) to be tested; - sequentially applying an electrical voltage greater than a threshold value to the test input / output (SPT) of each integrated circuit of said group of at least four integrated circuits (lOOla-d); - sequentially measure the response of each of the integrated circuits (1001a-d) by analyzing the response signals via their respective test input / output (SPT).

14. A method for testing a plurality of integrated circuits (1001a-d) on a semiconductor wafer (1000), said method comprising the following steps: - connecting in parallel a data input / output electronic resource (DC1-4) of said tester (3004) with a test input / output (SPT) of each integrated circuit of a group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits (1001) to be tested; - sending in parallel a data frame on the test input / output (SPT) of each integrated circuit of said group of at least four integrated circuits (lOOla-d); - receive in parallel a response data frame from each of the integrated circuits (1001a-d) by analyzing the response signals via their respective test input / output (SPT).

15. A computer program comprising instructions which, when the program is executed by a computer, cause the computer to implement the method of any one of claims 12 to 14 using a system according to claim 11.

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