Method and device for error correction in resistive memories

Abstract

The invention relates to a device and method for reading a codeword from an ECC-protected resistive memory where each memory cell comprises resistive devices for storing one bit of a codeword. The method (700) allows selection (740, 750), based on the value of a syndrome, of a corrected codeword after a first decoding (720) without weak-bit inversion, or a corrected codeword after a second decoding (730) with weak-bit inversion. If the calculated syndrome determines that the first decoding indicated an uncorrectable error, or determines that the second decoding indicated neither an uncorrectable error nor an n-error (i.e., a maximum of n erroneous bits per codeword), the selected codeword is the corrected codeword with weak-bit inversion. Otherwise, the selected codeword is the corrected codeword without weak-bit inversion. Figure for the abstract: Fig. 7

Description

Title of the invention: Method and device for correcting errors in resistive memories Technical field

[0001] The invention lies in the field of resistive memories or RRAM for "Resistive Random Access Memory" according to the English terminology, and relates more particularly to a method and a device making it possible to improve the correction of errors in resistive memories, in particular memories of the 1T1R and 2T2R type. State of the art

[0002] Resistive RRAM memories are non-volatile memories with high operating speed, low electrical power consumption and long lifetime. For these reasons, resistive memories are promising candidates to replace both current RAM and non-volatile memories such as flash memories.

[0003] There are several resistive memory technologies. These include conductive bridge resistive memories, also called CB RAM (for “Conductive-Bridging Random-Access Memory” in English terminology), or oxide-based resistive memories, also called OxRAM (for “Oxide-based Random-Access Memory” in English terminology), or phase change memories, also called PCM (for “Phase Change Memory” in English terminology).

[0004] A resistive memory is composed of a multitude of resistive memory cells arranged in rows and columns so as to form a matrix. An RRAM memory cell is provided with at least one resistive element whose conductance can be modified.

[0005] Typically, an RRAM memory cell in its initial state has an insulating metal structure and is in a high resistance state (HRS). Before use, some types of resistive memory, such as OxRAM or CBRAM memories, require electrical activation. Applying an external high voltage pulse across the RRAM cell allows the formation of conductive paths in the switching layer and the RRAM cell is switched into a low resistance state (LRS). The general process of this breakdown of the insulating structure of the cell is generally called "electroforming" (or "forming" according to English terminology).

[0006] The dielectric material which is arranged between the two conductive electrodes of the cell will allow the cell to switch reversibly between two resistance states HRS and LRS, each of the states allowing a bit of information to be stored in the memory cell.

[0007] To program a memory cell, a programming voltage is applied between the electrodes of the memory cell. This may be a programming voltage in the LRS state, or a programming voltage in the HRS state. However, after a programming operation, it may happen that the memory cell does not go into the desired resistance state. For this reason, a verification operation is generally performed to ensure that the memory cell is correctly programmed by comparing its resistance value R to a predefined resistance threshold value RreF.

[0008] [Fig. 1a] illustrates in a simplified manner an elementary resistive memory cell, generally consisting of a transistor (T) and a resistive component (R) or resistor (102), where an information bit is encoded by the value of the electrical resistance of the resistor. For these elementary cells, a logic '0' can for example be encoded by programming the resistor in an LRS state, and a logic '1' can then be encoded by programming the resistor in an HRS state, and we then speak of encoding in 1T1R mode.

[0009] However, the difference between the lowest value corresponding to an HRS level and the highest value corresponding to the LRS level, also called a “memory window”, is often small. Therefore, “differential encoding” or 2T2R encoding is commonly used to code a binary value. A bit of information can then be encoded in a memory cell called 2T2R as illustrated in a simplified manner in [Fig.lb], and composed of two elementary cells 1T1R, and comprising 2 transistors (2T) or (T1, T2) and 2 resistors (2R) or (112-1, 112-2).

[0010] As each of the HRS and LRS states can be associated with a logical value, ie 1 or 0, we can consider that in a 2T2R cell one of the two resistive elements encodes the bit to be programmed in non-inverted version while the other resistive element encodes the same bit in inverted version. For example, a logic '1' is encoded by programming the resistor of the first 1T1R cell in an HRS state and the resistor of the second 1T1R cell in an LRS state, and a logic '0' is encoded by programming the resistor of the first 1T1R cell in an LRS state and the resistor of the second cell in an HRS state.

[0011] When performing a write operation in a 1T1R memory cell or a 2T2R memory cell, it must be ensured that each electrical resistance that is to be programmed to the HRS state or the LRS state is respectively either larger or smaller than a reference value Rrff. Comparing an electrical resistance with the Rref value is done by a read operation during which each programmed resistor is compared to the Rref value using a sense amplifier or SA (for "Sense Amplifier" according to English terminology) illustrated by the component 104 in [Fig.1a] and 114 in [Fig.1b]. Subsequently, this read operation with comparison to a reference value is called 1T1R mode reading or 1T1R reading.

[0012] In [Fig.1a], the sense amplifier 104 reacts to the difference of its input 'SL' (coming from the cell 1T1R) and its input 'Rref' (representative of a reference electrical resistance value RKu). to generate an output signal 'VOut' which indicates the resistive state of the memory element of the cell and provides information on the value which is stored in the cell 1T1R.

[0013] In [Fig. 1b], the sense amplifier 114 will react to a difference on its inputs, to generate an output signal 'VOut'. In this implementation, a multiplexer (113-1, 113-2) is respectively coupled to the output (SL1, SL2) of each 1T1R cell to perform a 1T1R reading by comparison with the reference value Rj^p. During a 2T2R reading, the output of each multiplexer corresponds to the value of each respective cell (SL1, SL2), and becomes an input of the sense amplifier 114. The output of the sense amplifier 114 then reacts to the difference in resistance of the two resistive elements of the 2T2R cell (112-1, 112-2) and provides information on the value that is stored in the selected 2T2R cell.

[0014] The use of a memory involves frequent transitions between an HRS state and an LRS state and vice versa, and each switching event between these resistive states can introduce damage. In addition, the values ​​of the programmed resistors can change due to relaxation phenomena, and lead to a loss of the information stored in the RRAM.

[0015] Furthermore, resistive memories also exhibit cell-to-cell non-uniformity which also degrades memory reliability. The origin of this variability is attributed to manufacturing process non-uniformities such as switching film thickness, etching damage and electrode surface roughness.

[0016] These variations coupled with relaxation phenomena cause the resistances of the resistive memories which are programmed in the LRS state to drift towards an HRS state, and the resistances which are programmed in the HRS state to drift towards an LRS state. Therefore, this slippage of the values ​​of the programmed resistances can cause errors during read operations.

[0017] To reduce the error rate of memories, a common solution is to use an error correcting code or ECC (for “Error Correcting Code” according to the English terminology) that encodes data before it is written to memory. When encoding data with an ECC code, check bits are added to the data bits, the check bits representing redundant information calculated from the data bits, which allows the detection and correction of errors affecting both the data bits and the check bits. The set of data bits and check bits forms a code word.

[0018] A particular type of error correcting code is binary and linear ECC. By "linear binary error correcting code" is meant a set of words which are generated by adding to a plurality k of data bits, a defined number r of check bits which is calculated from the plurality k of data bits. The check bits are generated from the data bits in accordance with the following equation (1): H • y = 0 (1), where v is a column vector corresponding to a code word (k data bits and r check bits), and where H corresponds to a parity matrix which includes only binary values ​​('0' or '1') and where, each column of the matrix is ​​different from the other columns, and includes at least one value different from O.

[0019] When programming data into an ECC-protected memory, each memory word v is programmed to store a code word. When reading data from the memory, each memory word v is checked by evaluating the value of the matrix product H v .

[0020] The result of this operation is a binary vector called a "syndrome". If the syndrome is a zero vector, i.e., each of these bits is equal to zero, the code word is considered correct. A non-zero syndrome indicates the presence of at least one error.

[0021] When the syndrome allows the positions of the erroneous bits to be identified, the code word can be corrected.

[0022] In the presence of a high error rate, one solution is to use increasingly powerful ECCs, i.e. making it possible to correct more and more erroneous bits in a code word. However, this results in an increasingly significant additional cost in terms of storage area for the verification bits and in terms of latency and consumption of the ECC decoder.

[0023] One approach to avoid the use of a powerful ECC is to reduce the primary error rate, i.e., the error rate at the output of the memory circuit as it would be obtained without the use of an ECC. To reduce the primary error rate, one method is to use 2T2R memories instead of 1T1R memories. However, there are situations where even with the use of a 2T2R memory the primary error rate remains high.

[0024] Also, in situations where (a) even with a 2T2R memory the primary error rate remains high, where (b) the cost of a 2T2R memory is considered too high, where (c) it is necessary to choose an ECC with a lower additional cost (and therefore a lower correction capacity), one solution is to identify bits, called weak bits or "weak-bits" according to the established Anglo-Saxon terminology, which are bits likely to be erroneous among the bits obtained during a memory read operation. This information is then used to improve error correction.

[0025] The article by V. Gherman, L. Ciampolini, S. Evain and S. Ricavy, "Error Correction Improvement based on Weak-Bit-Flipping for Resistive Memories," Microelectronics Reliability, volume 136, dated 2022 describes a method and devices for identifying weak-bits and increasing the correction capacity of an ECC by relying on the identification of weak-bits. The principle consists of launching a weak-bit identification procedure only if the ECC decoder indicates an uncorrectable error during a memory read operation. In the case of 1T1R memories, this procedure consists of comparing the resistance of each resistor in the read word, on the one hand to a slightly higher reference value, and on the other hand to another slightly lower reference value, than the reference value normally used during the read operation.In the case of 2T2R memories, this procedure consists of comparing the resistances of each pair of resistors used to encode the value of each bit read, by applying a slight resistive bias first to one of the resistors and then to the other resistor. Any bit whose value changes during these evaluations is labeled as weak and designated as a weak-bit. The ECC decoding of the original word is then redone with all the weak-bits inverted, which significantly increases the chances of correcting conventionally uncorrectable errors and, ultimately, reduces the error rate of the memory.

[0026] The expression "conventionally uncorrectable errors" is to be understood as meaning errors which are not correctable by the ECC decoder used for the read operations, i.e., used conventionally with the ECC capability.

[0027] Similarly, the expression "conventionally correctable errors" is to be interpreted as meaning errors that can be corrected by the ECC decoder according to the capability of the ECC.

[0028] The above-mentioned method proves effective for ECCs which allow (a) the correction of a maximum of n erroneous bits per code word, a maximum which is designated in the remainder of the description as “n-error” and (b) the detection of all errors which affect n+1 bits, a number which is designated in the remainder of the description as “(n+1)-error”.

[0029] However, for a given number of data bits per code word, the detection of (n+1)-errors requires ECCs that have one more verification bit (a "check-bit") per code word, compared to ECCs that only allow the correction of n-errors. Moreover, this overhead can be amplified in the case where it is necessary to have code words with a total number of bits that is a multiple of a certain constant D, for example a multiple of D=4. In this case, it is possible that adding an additional verification bit per word also implies the addition of D cells per word instead of the addition of a single cell. This then results in an overhead multiplied by D.

[0030] Also, faced with the problem of error correction in resistive memories, there is a need for a solution that overcomes the various drawbacks of known solutions.

[0031] The present invention meets this need. Summary of the invention

[0032] The subject of the invention is a solution making it possible to improve error correction in resistive memories protected by an error correcting code (ECC).

[0033] Generally speaking, the principle of the invention is based on a method which makes it possible to select, as a function of the value of a syndrome, a corrected word after a first decoding without inversion of weak-bits, or a corrected word after a second decoding with inversion of weak-bits. If the calculated syndrome determines that the first decoding indicated an uncorrectable error, or determines that the second decoding indicated neither an uncorrectable error nor an n-error (i.e. a maximum of n erroneous bits per code word), the selected word is the corrected word with inversion of the weak-bits. Otherwise, the selected word is the corrected word without inversion of the weak-bits.

[0034] Advantageously, the method makes it possible to increase the gain in error correction capacity, and / or makes it possible to eliminate the additional cost in terms of verification bits, by launching operations for identifying and using weak bits, not only following the detection of an uncorrectable error but also in the presence of certain correctable errors.

[0035] Thus, for example, the identification by an ECC decoder of an n-error where n is the maximum number of erroneous bits which can be corrected in a code word, is information used by the method of the invention to launch operations of identification and use of weak-bits, whatever the properties of the ECC.

[0036] If the ECC allows the correction of all n-errors but does not allow the detection of all (n+l)-errors (which is also expressed by the fact that the minimum Hamming distance between the code words is equal to 2n+l), then an (n+l)-error can produce a syndrome that will be identical to that generated by an n-error. Conventional decoders of such an ECC cannot correct an (n+l)-error that generates the same syndrome as an n-error. Advantageously, by applying the method of the present invention, such (n+l)-errors can be corrected even with a conventional decoder, by identifying and inverting possible weak-bits. However, the inventors have found that this approach opens a risk of compromising the correction of n-errors. Also, in order to minimize this risk, in the case of a word whose ECC decoding generates a syndrome that may correspond to an n-error, the inventors have improved the method of the invention in a variant where it is proposed to decode a memory word with and without inversion of weak-bits, then to choose the corrected word with inversion of weak-bits only if the resulting syndrome corresponds to an error that affects less than n erroneous bits.

[0037] In cases where ECC allows the correction of all n-errors and also the detection of all (n+1)-errors (which is also expressed by the fact that the minimum Hamming distance between the code words is equal to 2n+2), a conventional decoder combined with weak-bits can achieve the correction of almost all (n+1)-errors.

[0038] Advantageously, the inventors have developed an approach that allows the correction of (n+2)-errors. Faced with the problem that the syndromes of (n+2)-errors can be identical to those generated by n-errors, and that a conventional correction of (n+2)-errors is then not possible, the method of the present invention allows such an (n+2)-error to be corrected even with a conventional decoder, by identifying and then inverting any weak-bits. The risk of compromising the correction of n-errors is addressed as previously by choosing the corrected word with inversion of weak-bits only if the resulting syndrome corresponds to an error that affects fewer than n erroneous bits.

[0039] To achieve the desired goal, a device is proposed for reading a code word stored in a resistive memory where each memory cell comprises resistive devices for storing a bit of a code word. The reading device comprises: - means for measuring the resistance of each resistive device storing a bit of a code word to be read, and for identifying weak bits; - means for carrying out, with a decoder of an error-correcting code having a maximum correction capacity of n erroneous bits, a first and a second decoding of the code word, the first and second decodings being carried out respectively without and with inversion of the weak bits; - means for determining in each decoded version of the code word, error number information, as to detectable but non-detectable errors correctable according to the correction capacity of said error correcting code and as to errors correctable according to the correction capacity of said error correcting code and which affect a maximum number of erroneous bits; and - means for selecting, based on the error count information, the version of the decoded code word which contains the fewest erroneous bits.

[0040] According to alternative or combined embodiments: - the selection means make it possible to select the version of the code word decoded without inversion of low bits if the information on the number of errors for the version of the code word decoded without inversion of low bits does not provide a number of errors greater than n-1; - the selection means make it possible to select the version of the code word decoded with inversion of weak bits if the information on the number of errors for the version of the code word decoded without inversion of weak bits indicates a number of uncorrectable errors or if the information on the number of errors for the version of the code word decoded with inversion of weak bits does not provide a number of errors greater than n-1 and the information does not indicate an uncorrectable error. - the means for measuring the resistance of each resistive device comprises means for measuring the resistance of each resistive device relative to a reference resistance value. - the means for measuring the resistance of each resistive device comprises means for measuring the resistance of each resistive device relative to two resistance values. - the means for identifying weak bits comprises means for comparing the measured resistance of each resistive device to a resistance value slightly greater than the reference resistance value, and to a resistance value slightly less than the reference resistance value, and for identifying bits whose results of these resistance comparisons are not identical. - the means for performing a first and a second decoding of the code word comprise means for sequentially performing the first and second decoding. - the means for performing a first and a second decoding of the code word comprise means for simultaneously performing the first and second decoding.

[0041] In one embodiment, the error correcting code is of the SEC type (“Single Error Correction” according to the established Anglicism), or SEC-DED (“Single Error Correction-Double Error Detection” according to the established Anglicism).

[0042] In alternative embodiments, the error correcting code may be of the DEC (“Double Error Correction”), DEC-TED (“Double Error Correction-Triple Error Correction"), TEC ("Triple Error Correction"), TEC-QED ("Triple Error Correction-Quadruple Error Detection"), QEC ("Quadruple Error Correction") or QEC-QED ("Quadruple Error Correction-Quintuple Error Detection").

[0043] Another object of the invention covers any electronic system of FPGA or ASIC type comprising a device according to the invention.

[0044] The invention also covers a method for reading a code word stored in a resistive memory where each memory cell comprises resistive devices for storing a bit of a code word. The method according to the invention comprises at least steps for: - measure the resistance of each resistive device storing a bit of a code word to be read, and identify weak bits; - carrying out with a decoder of an error-correcting code having a maximum correction capacity of n erroneous bits, a first and a second decoding of the code word, the first and second decodings being carried out respectively without and with inversion of the weak bits; - determining in each version of the decoded code word, error number information, as to errors detectable but not correctable according to the correction capacity of said error correcting code and as to errors correctable according to the correction capacity of said error correcting code and which affect a maximum number of erroneous bits; and - select, based on the error count information, the decoded version of the code word that contains the fewest erroneous bits.

[0045] In an alternative embodiment, the decoding step consists of sequentially performing a first decoding without inversion of weak bits and a second decoding with inversion of weak bits.

[0046] In another embodiment, the decoding step consists of simultaneously performing a first decoding without inversion of weak bits and a second decoding with inversion of weak bits.

[0047] In one embodiment, the step of selecting a code word consists of: - selecting the version of the code word decoded without inversion of low bits if the error count information for the version of the code word decoded without inversion of low bits does not provide a number of errors greater than n-1; or - selecting the version of the code word decoded with inversion of low bits if the error count information for the version of the code word decoded with inversion of low bits does not provide a number of errors greater than n-1 while the error count information for the version of the code word decoded without inversion of low bits provides a number of errors greater than n-1, or if the error count information for the codeword version decoded without low bit inversion indicates an uncorrectable error count.

[0048] Advantageously, the method of the present invention can be implemented on conventional, simple and fast decoders, and has no impact on the write operations in the resistive memories concerned. Description of figures

[0049] [Fig. 1a] and [Fig. 1b] respectively illustrate examples of implementation of a 1T1R memory cell and a 2T2R memory cell.

[0050] Other characteristics, details and advantages of the invention will emerge on reading the description given with reference to the appended drawings given by way of example and which represent, respectively:

[0051] [Fig.2] represents an example of a system allowing operations of writing and reading data words in a resistive memory;

[0052] [Fig.3] illustrates the steps of the error correction method of the invention in one embodiment;

[0053] [Fig.4] illustrates an architecture of an ECC decoder which can be used in a memory controller for implementing the method of the invention;

[0054] [Fig.5] illustrates an architectural variant of an ECC decoder which can be used in a memory controller for implementing the method of the invention;

[0055] [Fig.6] illustrates an embodiment of a circuit for selecting a corrected word;

[0056] [Fig.7] illustrates the steps of the error correction method of the invention in another embodiment;

[0057] [Fig.8] illustrates an embodiment of a circuit for selecting a corrected word adapted to the method of [Fig.7];

[0058] [Fig.9] shows a graph comparing the error correction rates according to the prior art and the method of the present invention. Detailed description of the invention

[0059] [Fig. 2] shows schematically an example of a system allowing operations of writing and reading data words in a resistive memory. The general architecture of the system 200 integrates a host electronic system 210, a memory controller 220 and a resistive memory RRAM 230.

[0060] The host 210 may consist of one or more processor cores, a microcontroller, a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0061] The memory controller 220 controls the write and read operations in the resistive memory 230. It generally includes an error correcting code (ECC) encoder and decoder.

[0062] [Fig.2] also shows the data flow during a write operation in memory 230. Before being stored in memory 230, the bits of a data word sent by the host system 210 are used by the ECC encoder of the memory controller 220 to generate check bits, and deliver a code word comprising the data bits and the check bits. These check bits are stored at the same address in the resistive memory 230 as the data bits. They can be used by the ECC decoder of the memory controller to correct any storage errors.

[0063] [Fig. 3] illustrates the steps of the error-corrected reading method of the invention in one embodiment. The method 300 applies when reading from a memory protected by an ECC, and it makes it possible to improve error correction by operations of identifying weak-bits, possibly inverting weak-bits, and selecting a corrected code word with or without inverting weak-bits.

[0064] The reading method 300 begins with a step 310 of measuring the resistances of the resistive devices present in each memory cell of a read address. In the 1T1R memories, this measurement may consist of a comparison of the measured resistance with a reference resistance. In the 2T2R memories, this measurement may consist of a comparison between the resistances of the two resistive devices present in each memory cell.

[0065] Following this measurement, a logical value is associated with each memory cell. The resulting word is then decoded 320 according to the type of ECC that was used to encode the data before programming it at the read address.

[0066] The next step 330 consists of determining whether the decoding detects a number of erroneous bits greater than a predefined threshold or not. In one embodiment the threshold is 'n-1' bits for an ECC capable of correcting a maximum of 'n' bits.

[0067] If the number of erroneous bits does not exceed the threshold, the word obtained following the first ECC decoding is delivered in a following step 370 to be transmitted to the host 110.

[0068] If in step 330 it is determined that the number of erroneous bits is greater than the threshold, advantageously, the method of the invention uses additional information which can be obtained during the decoding step to improve the error correction capacity.

[0069] Indeed, during the ECC decoding phase, it is possible to determine the presence of detectable but conventionally uncorrectable errors. This detection amounts, for example, to identifying a subset of (n+1)-errors for an ECC with a minimum Hamming distance equal to 2n+l; or to identify all (n + l)-errors and a subset of (n+2)-errors for an ECC with a minimum Hamming distance equal to 2n+2.

[0070] Furthermore, the decoding step also makes it possible to identify the presence of conventionally correctable errors which affect a maximum number of erroneous bits. This detection amounts, for example, to identifying n-errors for an ECC having a minimum Hamming distance equal to 2n+1 or 2n+2.

[0071] Such detection can be implemented by conventional techniques. One possible implementation consists, for example, in knowing the syndromes (i.e. each vector resulting from the matrix product H • y) generated by all the n-errors, in comparing all these syndromes to the syndrome generated during the ECC decoding operation, and in identifying whether the memory word which has just been read contains a number of erroneous bits which exceeds the threshold of n-1.

[0072] An alternative embodiment consists of checking whether the memory word which has just been read generates a non-zero syndrome, then indicating the presence of erroneous bits, and which is different from all the syndromes generated by errors which affect less than n bits.

[0073] For BCH-type ECCs (Bose, Ray-Chaudhuri and Hocquenghem), an efficient detection variant consists in the evaluation of matrix determinants associated with error location polynomials (according to the theory of BCH codes), as described in the article by J. Freudenberger, M. Rajab and S. Shavgulidze, "A Low-Complexity Three-Error-Correcting BCH Decoder with Applications in Concatenated Codes," published in the conference "International ITG Conference on Systems, Communications and Coding" in 2019 with DOI: 10.30420 / 454862002.

[0074] Advantageously, the method of the invention considers the number of detectable but conventionally uncorrectable errors and / or the number of conventionally correctable errors which affect a maximum number of erroneous bits (n-error), to determine whether the threshold of the maximum number of bits correctable by the ECC is exceeded.

[0075] If this is verified, in a following step 340, the method makes it possible to carry out new resistance measurements of the resistive devices present in each memory cell at the read address, to identify weak-bits.

[0076] The general principle is that any read bit whose value changes during new evaluations is labeled as a "weak-bit".

[0077] The method continues with a step 350 consisting of inverting all the identified weak-bits, then performing a second ECC decoding of the initial word with all the weak-bits inverted.

[0078] Solutions for identifying and inverting weak-bits in 1T1R and 2T2R type memories are presented in the aforementioned paper by V. Gherman, L. Ciampolini, S. Evain and S. Ricavy, “Error Correction Improvement based on Weak-Bit-Flipping for Resistive Memories,” Microelectronics Reliability, volume 136, 2022.

[0079] As during the first decoding 320, the second decoding of step 350 makes it possible to signal the presence of an n-error and / or a detectable but uncorrectable error.

[0080] Returning to [Fig.3], the next step 360 consists of determining and selecting the version of the corrected code word which has the fewest erroneous bits, between the initial word after the first decoding (step 320) and the word with inversion of weak-bits after the second decoding (step 360).

[0081] The method allows the word decoded in the second decoding after inversion of the weak-bits in step 350 to be chosen if and only if: - the first decoding at step 320 indicated an uncorrectable error; or - the second decoding at step 350 indicated neither an n-error nor an uncorrectable error.

[0082] In cases where each of the two decodings indicates a detectable but uncorrectable error, the method makes it possible to send an alert signal at the system level.

[0083] The method ends with a step 370 consisting of delivering to the host the code word which was selected in the previous step.

[0084] Thus, by identifying conventionally correctable errors that affect a maximum number of erroneous bits (n-error) and / or identifying conventionally non-correctable detectable errors, the method of the invention makes it possible to correct more errors without increasing the number of verification bits.

[0085] [Fig.4] illustrates an architecture of an ECC decoder that can be used in a memory controller for implementing the method of the invention, for an embodiment of detecting conventionally uncorrectable errors.

[0086] During a read operation of an initial memory word, the ECC decoder 400 receives a code word potentially affected by programming, storage or reading errors. From this word, a syndrome is generated by a syndrome generator (module 410) which implements multiplication operations to produce the matrix product H • v (Equation (1)).

[0087] Depending on the syndrome obtained it is possible to determine whether any bit read is erroneous, as long as the total number of erroneous bits does not exceed a maximum number n of bits correctable by the ECC.

[0088] From the syndrome, an error vector generator (module 420) generates a check bit for each bit read. The set of check bits is called the error vector where the check bits whose value is equal to 1 indicate the positions of the erroneous bits in the read word.

[0089] Each bit read can be corrected using a two-input exclusive-or (xor) logic gate, one input for the bit to be corrected in the initially read word and another input driven by the control bit corresponding to it in the error vector. A correction module 430 contains all the xor gates.

[0090] The conventionally corrected code word is delivered by the module 430.

[0091] The vast majority of ECCs used for memory protection are in ability to provide information that is not solely related to correctable errors and allows the detection of syndromes that are not associated with conventionally correctable errors.

[0092] Advantageously, the device of the invention uses such error number information for the detection of errors which are not conventionally correctable.

[0093] This information may correspond to: - to a subset of (n+l)-errors, for an ECC with a minimum Hamming distance equal to 2n+l; - to all (n+l)-errors and possibly a subset of (n+2)-errors, for an ECC with a minimum Hamming distance equal to 2n+2.

[0094] The detection and use of this information is carried out by modifying a conventional decoder. On the example of the ECC decoder of [Fig.4], it is proposed to implement circuits comprising a logic or gate 440 (commonly called an “or” gate), a logic not-or gate 450 (commonly called an “nor” gate) and a logic and gate 460 (commonly called an “and” gate).

[0095] The gold gate 440 receives as input the syndrome bits from the syndrome generator 410.

[0096] The nor gate 450 receives as input the bits of the error vector from the error vector generator 420.

[0097] The outputs of the or gate 440 and the nor gate 450 become the inputs of the and gate 460 which delivers a signal which is representative of an uncorrectable error.

[0098] This configuration allows (1) to check by the result of the or gate if at least one syndrome bit is different from 0 (a syndrome in which all the bits are equal to 0 indicates the absence of an error), and allows (2) to check by the result of the nor gate if all the bits of the error vector are equal to 0. The combination of the outputs by the and gate provides the information on the presence or absence of an uncorrectable error.

[0099] In the case of ECCs having a minimum Hamming distance equal to 2n+2, the detection mechanism can be simplified by taking advantage of the fact that the code words are all even or odd. The person skilled in the art can derive implementation variants depending on the error correcting code used.

[0100] For BCH (Bose, Ray-Chaudhuri and Hocquenghem) type codes, other detection methods are described in the aforementioned article by J. Freudenberger, M. Rajab and S. Shavgulidze.

[0101] [Fig.5] illustrates another embodiment of the architecture of an ECC decoder which can be used in a memory controller for implementing the method of the invention.

[0102] The decoder 500 comprises circuits (510, 520, 530, 540, 550, 560) respectively functionally similar to the circuits (410, 420, 430, 440, 450, 460) of the decoder 400 of [Fig. 4], which are not described again.

[0103] In this variant embodiment, the decoder 500 further comprises a syndrome comparator circuit 570 which makes it possible to generate an 'n-error' signal indicating the presence or absence of an n-error.

[0104] Circuit 570 is configured to compare the syndrome generated during the ECC decoding operation to all syndromes that may be generated by an n-error to identify whether the memory word just read is affected by such an error. A less expensive implementation is to check whether the syndrome generated during a decoding operation is non-zero, which indicates the presence of the erroneous bits, and which is different from all syndromes generated by errors that affect fewer than n bits.

[0105] This signal can be used during the first decoding 320 and second decoding 350 steps to check whether the memory word that has just been read and decoded (without or with inversion of weak-bits) contains a number of erroneous bits that exceeds a certain threshold.

[0106] [Fig.6] illustrates an embodiment of a circuit for selecting a corrected word, according to step 360.

[0107] The selection circuit 600 is a device coupled to each bit at the output of an ECC decoder, and is configured to allow a choice to be made between a corrected bit without or with inversion of the weak-bits, i.e. according to the result of steps 320 or 350.

[0108] In operation after the first decoding step 320, each bit of a decoded word (i.e. the outdec signal J and the bit of the uncorrectable error signal decl which come out of the ECC decoder (for example that of [Fig.4]), are stored respectively in a flip-flop 610, 620.

[0109] An 'en' signal is used to synchronize the capture of the signals at the inputs of flip-flops 610 and 620, with the end of the first decoding operation of step 320.

[0110] In operation after the second decoding step 350, the n-error signal and the non-correctable error signal dec2 are combined by the same logic gate of type nor 630.

[0111] Unlike the first decoding, the non-correctable error signal dec2 delivered after the second decoding is not stored (i.e. in flip-flop 620), and the outraged signal 2 is not stored (i.e. in flip-flop 610).

[0112] The output of the nor gate 630 is combined in a logic or gate 640 with the bit of the uncorrectable error signal decl which was stored in the flip-flop 620 after the first decoding, to deliver a selection signal sel out.

[0113] The sel out selection signal drives a multiplexer 650 to deliver an output signal out corresponding to the selected bit (i.e. the bit corrected after the first decoding or after the second decoding with weak-bit inversion).

[0114] The multiplexer 650 takes as inputs the outdec 2 signal at the output of the decoder after the second decoding and the outdec 1 signal which was stored in the flip-flop 610 after the first decoding.

[0115] In operation, the output of the nor gate 630 provides a signal indicating whether the ECC decoder (which allows the correction of a maximum of n erroneous bits per code word) had to manage an error which affects a maximum of n-1 erroneous bits.

[0116] Thus, after step 350, if neither of the two input bits of the nor gate 630 is equal to 1 (the second decoding has indicated neither an n-error nor an uncorrectable error), and if there was no uncorrectable error during the first decoding step 320, the signal selout allows the multiplexer 650 to select the signal outdeC2, that is to say the word decoded during step 350, i.e. with inversion of weak-bits.

[0117] Furthermore, if the ECC decoder indicates an uncorrectable error during the first decoding step 320, the or gate 640, which takes the output of the nor gate 630 and the output of the flip-flop 620, generates a sel out signal which also allows the multiplexer 650 to select the outdec 2 signal, i.e. the word decoded during step 350, i.e. with inversion of weak-bits.

[0118] The values ​​of the bits at the output of the ECC decoder at the end of the second decoding step 350 are retained at least until the end of the corrected word selection step 360.

[0119] A flip-flop 610 and a multiplexer 650 must be provided for each corrected bit that comes out of the ECC decoder in the memory controller 120.

[0120] In the case where step 330 has indicated that the number of erroneous bits is less than the threshold (branch no), a distinction between signals of the same name but different indexes (decl, dec2) no longer makes sense. In this case, the two signals n-error dec 2 and uncorrectable error dec 2 at the input of gate 630 are at 0, and the signal sel out is at 1, then making it possible to select the corrected initial word without inversion of weak-bits, i.e. the signal outdec 2 as indicated in [Fig.6].

[0121] In the event that the ECC decoder indicates an uncorrectable error at the end of each of the two decoding steps 320 and 350, the memory controller indicates an uncorrectable error to the host that made the memory read request.

[0122] In one embodiment, flip-flops 610 and 620 are latch-type circuits.

[0123] [Fig.7] illustrates the steps of the error-correcting reading method of the invention in another embodiment. The method 700 begins with a step 710 of resistance measurements with identification of weak bits.

[0124] Step 710 corresponds to resistance measurements, on the one hand by comparison with a reference value such as the measurements described for step 310, and on the other hand by comparison with a modified reference value (i.e. slightly higher and slightly lower) such as the measurements described for step 340.

[0125] Step 710 makes it possible to identify the weak bits.

[0126] A circuit implementation of step 710 may be with three sense amplifiers (or “triple sense amplifiers”) per bit read.

[0127] Following step 710, all weak-bits of the word read at the memory address indicated by the host are identified.

[0128] The method continues with two word decoding operations, executed in parallel.

[0129] A first ECC decoding (step 720) is done without inversion of weak-bits, and a second ECC decoding (step 730) is done simultaneously with all weak-bits inverted as identified during resistance measurements with the modified reference value.

[0130] In this embodiment, the memory controller 120 contains two ECC decoders.

[0131] After the ECC decoding steps (720, 730), the method makes it possible in a following step 740 to determine and select the version of the corrected code word which has the fewest erroneous bits, between the version of the word decoded by the first decoding without inversion of the weak-bits, and the version of the word decoded by the second decoding with inversion of weak-bits.

[0132] The method ends with a step 750 consisting of delivering the corrected word which is selected.

[0133] A circuit implementation of the method 700 is illustrated in [Fig.8]. It is based on a device similar to that of [Fig.6], where the gold logic gate 840 and the multiplexer 850 are equivalent to the gold logic gate 640 and the multiplexer 650 of the implementation shown in [Fig.6].

[0134] The circuit of [Fig.8] further comprises a logic gate 820 which makes it possible to invert the input signal n-errordeci, an error information signal indicating the presence of more than n-1 errors in the decoded code word without inversion of weak-bits (step 720).

[0135] The circuit also includes a nor 830 gate equivalent in function to the nor 630 gate of [Fig.6], but having an additional input produced by the output of gate 820.

[0136] The signals making it possible to generate error information to determine the corrected word to be delivered are, on the one hand, generated by an ECC decoder performing the decoding without inversion of weak-bits (signals denoted “outdec i”, “n-erreurdeci” and “erreur non-correctigeabledeci”), and on the other hand, generated by an ECC decoder performing the decoding with inversion of weak-bits (signals denoted “outdec 2”, “n-erreurdec2” and “erreur non-correctigeabledec2”).

[0137] As indicated, the method of the invention makes it possible to increase the gain in error correction capacity by carrying out operations of identification and use of weak-bits, upon detection of an uncorrectable error but also in the presence of certain correctable errors.

[0138] [Fig.9] is a graph showing error correction rates obtained with solutions of the prior art (SOTA, DEC, TEC, QEC) and with the method of the present invention.

[0139] The ordinate of the graph points to the metric “UBER” (acronym for “Uncorrectable Bit Error Rate”) which characterizes the error rate after decoding according to different types of ECC error correcting code, applied to a resistive memory configured in 2T2R with 32 bits of data per memory word.

[0140] The number of sigmas between the mean values ​​of the distributions of the differences of the electrical resistances HRS-LRS and LRS-HRS used in 2T2R to encode the logical values ​​1 and 0 is presented on the abscissa.

[0141] The points on the graph recorded by the DEC, TEC and QEC indicators represent the error rates obtained with conventional correction codes of the DEC, TEC and QEC type respectively.

[0142] The points on the graph recorded by the “SOTA” indicator (acronym for “State-Of-The-Art”) represent the results obtained with the solution presented in the aforementioned paper by V. Gherman, L. Ciampolini, S. Evain and S. Ricavy, “Error Correction Improvement based on Weak-Bit-Flipping for Resistive Memories,” Microelectronics Reliability, volume 136, 2022.

[0143] The points on the graph recorded by the “DEC-TED + weak-bit-flipping” indicator represent the error rates obtained with the method of the invention.

[0144] It appears that the proposed solution makes it possible to reduce the error rate by more than an order of magnitude (under certain conditions).

[0145] The above-mentioned acronyms are known in the field of error correcting codes (ECC). Thus: - a DEC corresponds to a correction capacity of a maximum of two erroneous bits per code word; - a DEC-TED allows the correction of two erroneous bits and the detection of three erroneous bits per code word; - a TEC corresponds to a correction capacity of a maximum of three erroneous bits per code word; - a QEC allows the correction of up to four erroneous bits per code word.

[0146] It should be noted that a DEC code requires 12 verification bits per code word with 32 data bits, and a DEC-TED code requires 13 verification bits for the same number of data bits per code word. TEC and QEC codes require 18 and 24 verification bits per code word with 32 data bits, respectively.

[0147] The present description illustrates a preferred implementation of the invention, but which is not limiting. Examples are chosen to allow a good understanding of the principles of the invention and a concrete application, but are in no way exhaustive and must allow those skilled in the art to make modifications and implementation variants to the different circuits while retaining the same principles. In alternative embodiments, each functional module for encoding, counting, comparison and inversion can be implemented by a dedicated module such as an ASIC.

[0148] The invention can be implemented from hardware and / or software elements. It can be available as a computer program product executed by a dedicated processor or by a memory controller of a storage system, and which comprises code instructions for executing the steps of the methods in their different embodiments.

Claims

Claims

1. Device for reading a code word stored in a resistive memory where each memory cell comprises resistive devices for storing a bit of a code word, the reading device comprising: - means for measuring (310) the resistance of each resistive device storing a bit of a code word to be read, and for identifying weak bits; - means for carrying out with a decoder of an error-correcting code having a maximum correction capacity of n erroneous bits, a first (320) and a second decoding (350) of the code word, the first and second decodings being respectively carried out without and with inversion of the weak bits;- means for determining (330) in each decoded version of the code word, error number information, as to errors detectable but not correctable according to the correction capacity of said error correcting code and as to errors correctable according to the correction capacity of said error correcting code and which affect a maximum number of erroneous bits; and - means for selecting (360) as a function of the error number information, the decoded version of the code word which contains the fewest erroneous bits.;

2. The device according to claim 1 wherein the selection means makes it possible to select the version of the code word decoded without inversion of weak bits if the error number information for the version of the code word decoded without inversion of weak bits does not provide an error number greater than n-1.

3. The device according to claim 1 or 2 wherein the selection means makes it possible to select the version of the code word decoded with inversion of weak bits if the error number information for the version of the code word decoded without inversion of weak bits indicates a number of uncorrectable errors or if the error number information for the version of the code word decoded with inversion of weak bits does not provide a number of errors greater than n-1 and the information does not indicate an uncorrectable error.

4. The device according to any one of claims 1 to 3 wherein the means for measuring the resistance of each resistive device comprises means for measuring the resistance of each resistive device relative to a reference resistance value.

5. The device of any one of claims 1 to 4 wherein the means for measuring the resistance of each resistive device comprises means for measuring the resistance of each resistive device relative to two resistance values.

6. The device of any one of claims 1 to 5 wherein the means for identifying low bits comprises means for comparing the measured resistance of each resistive device to a resistance value slightly greater than the reference resistance value, and to a resistance value slightly less than the reference resistance value, and for identifying bits whose results of these resistance comparisons are not identical.

7. The device according to any one of claims 1 to 6 wherein the means for performing a first and a second decoding of the code word comprises means for sequentially performing the first and second decoding.

8. The device according to any one of claims 1 to 7 wherein the means for performing a first and a second decoding of the code word comprises means for simultaneously performing the first and second decoding.

9. The device according to claim 8 wherein the error correcting code is of type SEC, SEC-DED, DEC, DEC-TED, TEC, TEC-QED, QEC, QEC-QED.

10. An electronic system of FPGA or ASIC type comprising a device according to one of claims 1 to 9.

11. Method (300) for reading a code word stored in a resistive memory where each memory cell comprises resistive devices for storing a bit of a code word, the method comprising at least steps for: - measuring (310) the resistance of each resistive device storing a bit of a code word to be read, and identifying weak bits; - performing with a decoder of an error correcting code having a maximum correction capacity of n erroneous bits, a first (320) and a second (350) decoding of the code word, the first and second decodings being respectively carried out without and with inversion of the weak bits; - determining (330) in each decoded version of the code word, error number information, as to errors detectable but not correctable according to the correction capacity of said error correcting code and as to errors correctable according to the correction capacity of said error correcting code and which affect a maximum number of erroneous bits; and - selecting (360) according to the error number information, the decoded version of the code word which contains the fewest erroneous bits.

12. The method of claim 11 wherein the decoding step comprises sequentially performing a first decoding without inversion of low bits and a second decoding with inversion of low bits.

13. The method of claim 11 wherein the decoding step comprises simultaneously performing a first decoding without inversion of low bits and a second decoding with inversion of low bits.

14. The method according to any one of claims 11 to 13 wherein the step of selecting a code word comprises: - selecting the version of the code word decoded without inversion of low bits if the error count information for the version of the code word decoded without inversion of low bits does not provide a number of errors greater than n-1; or - selecting the version of the code word decoded with inversion of low bits if the error count information for the version of the code word decoded with inversion of low bits does not provide a number of errors greater than n-1 while the error count information for the version of the code word decoded without inversion of low bits provides a number of errors greater than n-1, or if the error count information for the version of the code word decoded without inversion of low bits indicates a number of uncorrectable errors.

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