Semiconductor device and electronic equipment

Abstract

To provide a semiconductor device that can perform product-sum operation with less power consumption.SOLUTION: In a semiconductor device, a circuit MC includes a holding node nd1, and a circuit MCr includes a holding node nd1r. The circuit MC is electrically connected to input wiring IL, and wirings OL, OLB. The circuit MCr is electrically connected to input wiring ILB and the wirings OL, OLB. The circuits MC, MCr have functions of holding first and second potentials according to first data in the holding nodes nd1, nd1r, respectively. When a potential according to second data is input to the input wirings IL, ILB, the circuit MC outputs a current to one of the wirings OL, OLB, and the circuit MCr outputs a current to the other of the wirings OL, OLB. The currents output by the circuits MC, MCr to the wiring OL or OLB are determined in accordance with the first and second potentials held in the holding nodes nd1, nd1r.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an object, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the present invention relates to a technique according to one embodiment of the present invention disclosed in the present specification. Fields of application include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, signal processing device, processor, electronic device, system, driving method thereof, and a method for inspecting the same. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is actively progressing. The brain's mechanism is incorporated as an electronic circuit, and the brain's "neurons" and "systems" are connected in a way similar to that of the human brain. Such an integrated circuit has a circuit equivalent to the neuromorph. It is also sometimes called "brain-morphic," "brain-inspired," or "brain-morphic." The integrated circuit has a non-von Neumann architecture, and power consumption decreases with increasing processing speed. Compared to the large von Neumann architecture, it can perform parallel processing with extremely low power consumption. It is expected that this will be possible.

[0004] The model of information processing that mimics a neural network with "neurons" and "synapses" is an artificial This is called an artificial neural network (ANN). For example, see Non-Patent Document 1 and Non-Patent Document 2 uses SRAM (Static Random Access Memory) The document discloses a computing device that configures an artificial neural network. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-Patent Document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In artificial neural networks, the strength of the synapse that connects two neurons is called the Multiply the weighting factor (sometimes called a weighting coefficient) by the signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, the first layer of the network is composed of multiple first The strength of each synapse between the neuron and one of the second neurons in the second layer, Each signal input from multiple first neurons in the first layer to one of the second neurons in the second layer is It is necessary to multiply and add the numbers, and depending on the scale of the artificial neural network, For example, the number of connection strengths and the number of parameters that represent the signal are determined. The more layers and neurons in a neural network, the more "neurons" and The number of circuits equivalent to each "synapse" can increase, and the amount of calculations can become enormous. .

[0007] As the number of circuits that make up a chip increases, power consumption increases, and the amount of electricity generated when the device is running also increases. The amount of heat also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements included in the chip deteriorate. Therefore, the circuits that make up the chip have circuit elements that are less susceptible to temperature effects. It is preferable that

[0008] One aspect of the present invention is a semiconductor device in which a hierarchical artificial neural network is constructed. Another object of the present invention is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a method for manufacturing a semiconductor device that is not affected by the temperature of the environment. Another object of the present invention is to provide a semiconductor device or the like that is less susceptible to cracking. An object of the present invention is to provide a new semiconductor device or the like.

[0009] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. However, this does not preclude the existence of other problems. The other problems are described below. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by reading the specification or can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above problems and other problems. There is no need to solve all of them. [Means for solving the problem]

[0010] (1) One embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, has a first holding node, the second circuit has a second holding node, and the first circuit has a first input The second circuit is electrically connected to the wiring, the second input wiring, the first wiring, and the second wiring. The first circuit is electrically connected to the first power wiring, the second input wiring, the first wiring, and the second wiring. The second circuit has a function of holding a first potential corresponding to data at a first holding node, The first circuit has a function of holding a second potential corresponding to the first input wiring at a second holding node. When a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, The function of outputting a current according to the potential to the first wiring and inputting a low-level potential to the first input wiring When a high-level potential is input to the second input wiring, a current according to the first potential is supplied to the second input wiring. The function of outputting a low-level potential to the first input wire and a low-level potential to the second input wire is also provided. When a bell potential is input, a current corresponding to the first potential is output to the first wiring and the second wiring. The second circuit has a function of not having a high level potential input to the first input wiring and a function of not having a high level potential input to the second input wiring. When a low-level potential is input to the input wiring, a current corresponding to the second potential is output to the second wiring. function, when a low-level potential is input to the first input wire and a high-level potential is input to the second input wire When a voltage is input, the device outputs a current to the first wiring according to the second potential, and also outputs a low When a high-level potential is input to the first input wiring and a low-level potential is input to the second input wiring, and a function of not outputting a current corresponding to the first wiring and the second wiring. .

[0011] (2) Alternatively, in one aspect of the present invention, in the configuration (1), the first circuit includes first to fourth transistors. the second circuit includes fifth to eighth transistors and a second capacitance element; a capacitance element, and the first holding node is connected to a first terminal of the first transistor, a first terminal of the first capacitance element; and a gate of the second transistor. The terminal is electrically connected to the second terminal of the first capacitive element, and the second terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the fourth transistor; The gate of the third transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is The second terminal of the third transistor is electrically connected to the second input wiring, and the second terminal of the third transistor is electrically connected to the first wiring. The second terminal of the fourth transistor is electrically connected to the second wiring, and the second terminal of the fourth transistor is electrically connected to the second wiring. The holding node is connected to the first terminal of the fifth transistor, the gate of the sixth transistor, and the second capacitor. the first terminal of the sixth transistor is electrically connected to the first terminal of the second capacitance element; The second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor. a gate of the seventh transistor electrically connected to the first terminal of the eighth transistor; The gate of the eighth transistor is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. The second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the second wiring. The second terminal of the transistor is a semiconductor device electrically connected to the first wiring.

[0012] (3) Alternatively, in the above-mentioned (1), the first circuit includes first to fourth transistors. the second circuit includes the fifth to eighth transistors, a first holding node connected to the first transistor, a tenth transistor, and a second capacitance element; a first terminal of the transistor, a gate of the second transistor, a gate of the ninth transistor, and The second terminal of the first capacitance element is electrically connected to the second transistor. a first terminal of the ninth transistor and a first terminal of the second transistor; The second terminal of the transistor is electrically connected to the first terminal of the third transistor, and the second terminal of the ninth transistor is electrically connected to the first terminal of the third transistor. The second terminal is electrically connected to the first terminal of the fourth transistor and to the gate of the third transistor. The gate of the fourth transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is electrically connected to the second input wiring. a second terminal of the third transistor electrically connected to the first wiring; and a fourth terminal of the fourth transistor electrically connected to the first wiring. The second terminal of the transistor is electrically connected to the second wiring, and the second holding node is connected to the fifth transistor. a first terminal of the transistor, a gate of the sixth transistor, a gate of the tenth transistor, The second terminal of the second capacitance element is electrically connected to the sixth transistor. a first terminal of the sixth transistor and a first terminal of the tenth transistor; The second terminal of the seventh transistor is electrically connected to the first terminal of the tenth transistor. The second terminal of the transistor is electrically connected to the first terminal of the eighth transistor, and the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor. The gate of the eighth transistor is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. the second terminal of the seventh transistor is electrically connected to the second wiring; The second terminal of the eighth transistor is a semiconductor device electrically connected to the first wiring.

[0013] (4) Alternatively, in one aspect of the present invention, in the configuration (1), the first circuit includes first to fourth transistors. a first logic circuit and a second logic circuit, the second circuit including fifth to eighth transistors. a third logic circuit and a fourth logic circuit, This has a function of outputting from an output terminal an inverted signal of a signal input to an input terminal, The nodes are the input terminal of the first logic circuit, the output terminal of the second logic circuit, and the first transistor. The first logic circuit has an output terminal electrically connected to the first terminal and the gate of the second transistor. , the second terminal of the second transistor is electrically connected to the input terminal of the second logic circuit, a first terminal of the third transistor electrically connected to the first terminal of the fourth transistor and the first terminal of the fourth transistor; The gate of the fourth transistor is electrically connected to the first input wiring, and the gate of the fourth transistor is The second terminal of the third transistor is electrically connected to the second input wiring, and the second terminal of the third transistor is electrically connected to the first wiring. The second terminal of the fourth transistor is electrically connected to the second wiring, and the second terminal of the fourth transistor is electrically connected to the second wiring. The input terminal of the third logic circuit, the output terminal of the fourth logic circuit, and the first terminal of the fifth transistor and the gate of the sixth transistor, and the output terminal of the third logic circuit is electrically connected to the gate of the fourth transistor. The second terminal of the sixth transistor is electrically connected to the input terminal of the logic circuit. a first terminal of the seventh transistor electrically connected to the first terminal of the eighth transistor and the first terminal of the seventh transistor; The gate of the eighth transistor is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. The second terminal of the seventh transistor is electrically connected to the input wiring, and the second terminal of the seventh transistor is electrically connected to the second wiring. The second terminal of the eighth transistor is electrically connected to the first wiring. do.

[0014] (5) Alternatively, in one aspect of the present invention, in the configuration (1), the first circuit includes first to fourth transistors. The second circuit has sixth to eighth transistors. The first logic circuit and the second logic circuit each have a transistor, and a signal input to the input terminal from the output terminal, and the first holding node is an input of the first logic circuit. a terminal, an output terminal of the second logic circuit, a first terminal of the first transistor, and a The output terminal of the first logic circuit is electrically connected to the gate of the second logic circuit. a second terminal of the second transistor is connected to a first terminal of the third transistor and a fourth terminal of the fourth transistor. the gate of the third transistor is electrically connected to the first terminal of the first input transistor; The gate of the fourth transistor is electrically connected to the second input wiring. The second terminal of the third transistor is electrically connected to the first wiring, and the third terminal of the fourth transistor is electrically connected to the first wiring. The second terminal is electrically connected to the second wiring, and the second holding node is an input terminal of the second logic circuit. the output terminal of the first logic circuit and the gate of the sixth transistor are electrically connected to the sixth transistor; The second terminal of the seventh transistor is connected to the first terminal of the eighth transistor. The gate of the seventh transistor is electrically connected to the first input wiring. The gate of the eighth transistor is electrically connected to the second input wiring, and the gate of the seventh transistor is The second terminal is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the first wiring. The semiconductor device is electrically connected.

[0015] (6) Another embodiment of the present invention is a semiconductor device including a first circuit and a second circuit, The first circuit has a first load circuit, and the second circuit has a second load circuit. and two load circuits, each of which has a first terminal and a second terminal. The load circuit and each of the load circuit and the load circuit change a resistance value between the first terminal and the second terminal in accordance with the first data. The first circuit has a function of converting a first input wiring into a second input wiring, a first wiring, and a second wiring. The second circuit is electrically connected to the first input wiring, the second input wiring, the first wiring, and the second wiring. The first circuit is electrically connected to the first input wiring, and a high-level potential is input to the first input wiring. When a low-level potential is input to the input wiring, a current according to the resistance value of the first load circuit is generated. The function of outputting to the wiring and inputting a low level potential to the first input wiring and a high level potential to the second input wiring. When a level potential is input, a current according to the resistance value of the first load circuit is output to the second wiring. The function of inputting a low-level potential to the first input wiring and a low-level potential to the second input wiring is also provided. When input is made, a current according to the resistance value of the first load circuit is output to the first wiring and the second wiring. The second circuit has a function of not inputting a high level potential to the first input wiring and a function of not inputting a high level potential to the second input wiring. When a low-level potential is input to the second input wiring, a current according to the resistance value of the second load circuit flows through the first The function of outputting to two wires and inputting a low-level potential to the first input wire and When a high-level potential is input, a current according to the resistance value of the second load circuit is output to the first wiring. A function of inputting a low-level potential to the first input wiring and a low-level potential to the second input wiring. When the input is made, a current according to the resistance value of the second load circuit is supplied to the first wiring and the second wiring. The semiconductor device has a function of not outputting.

[0016] (7) Alternatively, in one aspect of the present invention, in the configuration (6) above, the first circuit includes a third transistor and a fourth transistor, and the second circuit includes a seventh transistor and an eighth transistor. and a first terminal of the first load circuit is connected to a first terminal of the third transistor and a first terminal of the fourth transistor. The gate of the third transistor is electrically connected to the first input wiring and the The gate of the fourth transistor is electrically connected to the second input wiring, and the gate of the third transistor is electrically connected to the second input wiring. The second terminal of the transistor is electrically connected to the first wiring, and the second terminal of the fourth transistor is electrically connected to the second wiring, and the first terminal of the second load circuit is a terminal electrically connected to the first terminal of the eighth transistor; and a gate of the seventh transistor. The gate of the eighth transistor is electrically connected to the first input wiring, and the gate of the eighth transistor is electrically connected to the second input wiring. The second terminal of the seventh transistor is electrically connected to the second wiring, and the second terminal of the eighth transistor is electrically connected to the second wiring. The second terminal of the transistor is a semiconductor device electrically connected to the first wiring.

[0017] (8) Alternatively, in the configuration of (7), the first circuit includes a first transistor the second circuit includes a second transistor, and the first terminal of the first transistor is connected to a first negative terminal. the first terminal of the second transistor is electrically connected to the first terminal of the second load circuit; The semiconductor device is electrically connected to the first terminal.

[0018] (9) Alternatively, one aspect of the present invention is the first negative electrode in any one of the above configurations (6) to (8). The load circuit includes any one of a resistance change element, an MTJ element, and a phase change memory, and a second load circuit The present invention relates to a semiconductor device having any one of a resistance change element, an MTJ element, and a phase change memory.

[0019] (10) Alternatively, one aspect of the present invention is a third embodiment in any one of the above configurations (1) to (9). a third circuit and a fourth circuit, and the third circuit is connected to the first input wiring and the second input wiring, The fourth circuit has a function of inputting a potential according to the second data to the first wiring, the second wiring, The current flowing from each of the four circuits is compared, and the first data and the second data are output from the output terminal of the fourth circuit. The semiconductor device has a function of outputting a potential according to the product of the input and output data.

[0020] (11) Another embodiment of the present invention includes a semiconductor device according to any one of (1) to (10), This is an electronic device that performs neural network calculations using semiconductor devices.

[0021] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. A circuit including a semiconductor element (transistor, diode, photodiode, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in a package are called semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. It may itself be a semiconductor device or may include a semiconductor device.

[0022] In addition, in the present specification and the like, when it is described that X and Y are connected, X and When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in the present specification. In addition, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or text, and may be modified without departing from the spirit or scope of the present invention. Connections other than those shown in the figure or text are also considered to be disclosed. X and Y are Assume that the object is an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.) .

[0023] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function of being controlled to be on and off. A switch can be in a conductive state (on) or a non-conductive state (off) and can either pass current or It has a function to control whether or not water is flushed.

[0024] An example of a case where X and Y are functionally connected is the case where the functional connection between X and Y is possible. Circuits that perform the functions of the following: logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that can adjust the signal amplitude or Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There is one or more circuits between X and Y. It is possible to connect X and Y together. For example, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be so.

[0025] In addition, when it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is placed between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly (i.e. when they are connected through another circuit) , when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it should simply be "" is the same as if it were expressly stated that the

[0026] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source ( or the first terminal, etc.) is electrically connected to X, and the drain (or the second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The Y is electrically connected to the X through the drain (or second terminal, etc.) and the The source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor are The technical scope can be determined by distinguishing between the above. Note that these methods of expression are merely examples. , and are not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0027] In addition, the circuit diagram shows that independent components are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0028] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are selected based on the transistor conductivity type (n-channel type, p-channel type) and the transistor Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain can be interchanged. In addition, in this specification and the like, when describing the connection relationship of a transistor, "One of the source or drain" (or the first electrode, or the first terminal), "the source or drain The term "second electrode" or "second terminal" is used. In some cases, a back gate may be provided in addition to the three terminals described above. In this specification, either the gate or the back gate of a transistor is referred to as a first gate. The other of the gate or back gate of the transistor is sometimes called the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" are interchangeable. In addition, when a transistor has three or more gates, In this specification, each gate is referred to as a first gate, a second gate, a third gate, etc. It is sometimes referred to as:

[0029] In this specification, a node may be a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. The wiring etc. can be called a node in other words.

[0030] In addition, in this specification, the terms "voltage" and "electric potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we define "voltage" as "ground potential," then "potential" can be used instead of "ground potential." The potential does not necessarily mean 0V. Note that the potential is relative and the reference Depending on the potential, the potential applied to the wiring etc. may be changed.

[0031] "Current" refers to the phenomenon of the movement of electric charges (electrical conduction). For example, "the electric current of a positively charged The statement "electrical conduction is occurring in the opposite direction" should be interpreted as "electrical conduction is occurring in the opposite direction for negatively charged bodies." In other words, the term "current" is used in this specification and the like unless otherwise specified. In this case, the term "electrical conduction" refers to the phenomenon of charge transfer accompanying the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the carriers through which electric current flows. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a wire, etc. is the direction in which positive carriers move, and is indicated by the amount of positive current. In other words, the direction in which the negative carriers move is opposite to the direction of the current, and the negative Therefore, in this specification, the positive and negative currents (or the direction of the current) Unless otherwise specified, a statement such as "current flows from element A to element B" is equivalent to "current flows from element B to element In addition, "current flows into element A" can be expressed as "current flows into element A". Descriptions such as "current is input from element A" can be rephrased as "current is output from element A" Let us assume that.

[0032] In addition, in this specification, the ordinal numbers "first," "second," and "third" refer to components. Therefore, the number of components is not limited. In addition, the order of the components is not limited. The components referred to as "first" in the above may be included in other embodiments or in the claims. In addition, for example, the second component may be referred to as a "second" component in the present specification. A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0033] In addition, in this specification, the terms "above" and "below" that indicate an arrangement are used to refer to the relationship between components. The positional relationship may be used for convenience in explaining the drawings. The relative positions of the elements change depending on the direction in which each element is depicted. The term is not limited to the words and phrases explained in the notes, etc., and can be rephrased appropriately according to the situation. For example, For example, in the expression "insulator on top of conductor," the orientation of the drawing shown is rotated 180 degrees. By rotating it, it can be rephrased as "insulator located on the underside of a conductor."

[0034] In addition, the terms "above" and "below" refer to the positional relationship of a component directly above or below and directly adjacent to it. For example, if the expression is "electrode B on insulating layer A," It is not necessary that the electrode B is formed directly on the insulating layer A. This does not exclude the inclusion of other components in between.

[0035] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, words such as "film" and "layer" may be omitted and substituted with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." For example, the terms "insulating layer" and "insulating film" may be changed to "insulator." In some cases, it may be possible to change the term to something like this:

[0036] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not intended to be limiting. For example, an "electrode" may be used as a part of a "wire." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the wiring is formed integrally.

[0037] In addition, in this specification and the like, the terms "wiring," "signal line," "power line," etc. may be used interchangeably. Depending on the circumstances, they can be interchanged. For example, "wiring" In some cases, it may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" will be changed to the term "wiring". It may be possible to change terms such as "power line" to terms such as "signal line." In addition, the opposite is also true, and terms such as "signal line" may be used interchangeably with "power line" In addition, the term "potential" applied to the wiring may be changed to another term. In some cases or circumstances, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used to refer to "potential". It may be possible to change the term.

[0038] In this specification, impurities in a semiconductor are, for example, any impurities other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic percent is an impurity. This can result in the formation of DOS (Density of States) in semiconductors. In some cases, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, other than the main component Transition metals, particularly hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, if the semiconductor is a silicon layer, In this case, impurities that change the properties of a semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 2, Group 13, and Group 15.

[0039] In this specification, a switch refers to a device that is in a conductive state (on state) or a non-conductive state (off state). A switch is a device that has the function of controlling whether or not current flows by switching on or off. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The present invention is not limited to a specific one, and may be applied to any device capable of controlling a current.

[0040] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor can be considered to be electrically shorted. The "non-conducting state" of a transistor refers to the state in which the source and drain electrodes of the transistor are in a non-conducting state. This refers to a state in which the gate electrodes can be considered to be electrically disconnected. When the transistor is operated as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0041] An example of a mechanical switch is the MEMS (Micro-Electro-Mechanical System). There are switches that use stem technology. These switches are electrically actuated by a mechanical It has poles, and the movement of these electrodes controls whether the element is conductive or non-conductive. Effect of the Invention

[0042] According to one aspect of the present invention, a semiconductor device having a hierarchical artificial neural network is provided. According to one embodiment of the present invention, a semiconductor device having low power consumption can be provided. Alternatively, according to one aspect of the present invention, a device for detecting the influence of the temperature of the environment can be provided. According to one embodiment of the present invention, a semiconductor device or the like that is not easily affected by the above-mentioned defects can be provided. It is possible to provide a new semiconductor device.

[0043] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. However, this does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to those skilled in the art. can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, the [Brief description of the drawings]

[0044] [Figure 1] 1A and 1B are diagrams for explaining a hierarchical neural network. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration example of the semiconductor device. [Diagram 3] 3A, 3B, 3C, 3D, 3E, and 3F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 4] 4A, 4B, 4C, 4D, 4E, and 4F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Diagram 5] 5A, 5B, 5C, 5D, 5E, and 5F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] 9A, 9B, and 9C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 10] 10A and 10B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 11] 11A and 11B are circuit diagrams showing examples of the configuration of a circuit included in a semiconductor device. [Figure 12] 12A and 12B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 13] 13A, 13B, and 13C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 14] 14A, 14B, and 14C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 15] 15A, 15B, and 15C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 16] 16A and 16B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 18] 18A, 18B, 18C, and 18D are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 19] FIG. 19 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. [Figure 20] 20A and 20B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 22] 22A, 22B, and 22C are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 23] 23A, 23B, and 23C are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 24] 24A and 24B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Diagram 25] 25A and 25B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 26] 26A and 26B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 27] 27A and 27B are circuit diagrams showing configuration examples of circuits included in a semiconductor device. [Figure 28] FIG. 28 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 29] FIG. 29 is a cross-sectional view showing a configuration example of a semiconductor device. [Diagram 30] 30A, 30B, and 30C are cross-sectional views showing examples of the structure of a transistor. [Diagram 31]31A, 31B, and 31C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 32] 32A, 32B, and 32C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 33] 33A, 33B, and 33C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 34] 34A, 34B, and 34C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 35] 35A, 35B, and 35C are a top view and a cross-sectional view illustrating an example of a structure of a transistor. [Diagram 36] 36A and 36B are a top view and a perspective view illustrating an example of a structure of a transistor. [Figure 37] 37A and 37B are cross-sectional views showing examples of the structure of a transistor. [Figure 38] 38A, 38B, and 38C are a top view and a perspective view showing a structural example of a capacitive element. [Figure 39] 39A, 39B, and 39C are a top view and a perspective view showing a structural example of a capacitive element. [Diagram 40] 40A, 40B, 40C, and 40D are perspective views showing examples of a semiconductor wafer and an electronic component. [Diagram 41] FIG. 41 is a perspective view showing an example of an electronic device. [Diagram 42] FIG. 42A is a front view showing an example of an electronic device, and FIGS. 42B and 42C are perspective views showing examples of the electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] In artificial neural networks (hereafter referred to as neural networks) The strength of the synapses is calculated by feeding the neural network with existing information. In this way, we can feed the neural network with existing information and get The process of determining the combined strength is sometimes called "learning."

[0046] In addition, no changes were made to the neural network that had undergone "learning" (the connection weights were determined). By providing some information, new information can be output based on the connection strength. In this way, in a neural network, the The process of computing information and outputting new information is sometimes called "inference" or "cognition."

[0047] Neural network models include, for example, Hopfield type and hierarchical type. In particular, neural networks with multi-layered structures are called "deep neural networks." They call machine learning using deep neural networks "DNN" and call machine learning using deep neural networks " This is sometimes called “deep learning.”

[0048] In this specification, the term "metal oxide" refers to metals in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called "OS"), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have the functions of amplification, rectification, and forming a channel forming region of a transistor having at least one switching function. If possible, the metal oxide is called a metal oxide semiconductor. It can also be called OS FET or OS transistor. In the above description, the transistor may be expressed as a transistor including a metal oxide or an oxide semiconductor. It is possible.

[0049] In the present specification and the like, metal oxides having nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0050] In addition, in this specification and the like, the configurations shown in each embodiment may be the same as the configurations shown in other embodiments. The above-mentioned embodiments can be combined appropriately to form one aspect of the present invention. In the case where multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0051] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the embodiment and one or more other embodiments The content described in the article (or a part of it) is applied to, combined with, or at least one of the contents. Alternatively, a replacement or the like can be performed.

[0052] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. The content is described in the specification or using sentences in the description.

[0053] In addition, a figure (or a part of it) described in one embodiment may be replaced with another part of the figure. In the embodiment, another figure (or a part of it) and one or more other embodiments may be used. At least one of the figures (or a part of the figures) described in the embodiment is combined. By adding more, more figures can be constructed.

[0054] The embodiments described in this specification are described with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be easily understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals. The same description may be used in different drawings and repeated explanations may be omitted. In some cases, in order to make the drawings clearer, the illustration of some components may be omitted. be.

[0055] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as “_1”, “[n]”, or “[m,n]” is added to the code. In some cases, this may be stated.

[0056] Also, in the drawings of this specification, the sizes, layer thicknesses, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely illustrative examples, and are not limited to the shapes or values ​​shown in the drawings. For example, signal, voltage, or current variations due to noise, or timing errors This may include signal, voltage or current variations, and the like.

[0057] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The arithmetic circuit that performs the calculation will be described.

[0058] <Hierarchical neural network> First, we will explain about hierarchical neural networks. For example, the network may have one input layer, one or more intermediate layers (hidden layers), and one output layer. The hierarchical neural network shown in FIG. 1A has a layer and a layer, which is composed of three or more layers in total. An example of such a network is shown in FIG. 1. The neural network 100 is a The layer has R layers (where R can be an integer of 4 or more). The first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to intermediate layers. In addition, in FIG. 1A, the (k-1)th layer and the kth layer (where k is 3 or more, R-1) are shown as intermediate layers. The intermediate layers are shown in the figure, and the other intermediate layers are omitted. .

[0059] Each layer of the neural network 100 includes one or more neurons. In this case, the first layer is made up of neurons N1 (1) Neuron N p (1) (Here p is 1 or more. ), and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer equal to or greater than 1), and the kth layer has neurons N1 ( k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer is Neuron N1 (R) Neuron N q (R) (Here, q is an integer greater than or equal to 1.) has.

[0060] In addition, in Figure 1A, neuron N1 (1) , neuron Np (1) , neuron N1 ( k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , Neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j ( k) (where j is an integer between 1 and n) is also shown. The illustration of the .

[0061] Next, the transmission of signals from the neurons in the previous layer to the neurons in the next layer, and In this explanation, we will explain the signals input and output in the k-th layer of the neural network. N j (k) We are focusing on:

[0062] Figure 1B shows the kth layer of neurons N j (k) and neuron N j (k) Signal input to and neuron N j (k) 4 shows a signal output from the

[0063] Specifically, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1 ) The output signals of each (k-1) ~z m (k-1) But neuron Nj ( k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is used as the output signal (k+1) The output is directed to each neuron in a layer (not shown).

[0064] The signals input from the neurons in the previous layer to the neurons in the next layer are The strength of the synapse (hereafter referred to as the weighting factor) that connects the In the neural network 100, the output from the previous layer of neurons is The signal is multiplied by the corresponding weighting coefficient and input to the next layer of neurons. The (k-1)th layer neuron N i (k-1) and the kth layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the kth layer Yuron N j (k) The signal input to can be expressed by equation (1.1).

[0065]

number

[0066] That is, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) of From each of them, the kth layer neuron Nj (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients (w1 (k-1 ) j (k) Or even w m (k-1) j (k) ) is multiplied by the k-th layer neuron N j (k) For w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) · z m (k-1) At this time, the kth layer neuron N j (k) The signal input to The sum of the numbers j (k) becomes equation (1.2).

[0067]

number

[0068] Neuron N j (k) u j (k) Depending on j (k) Generate In. Neuron N j (k) Output signal z from j (k) is defined as follows:

[0069]

number

[0070] The function f(u j (k) ) is the activation function in a hierarchical neural network. , step functions, linear ramp functions, sigmoid functions, etc. The activation function may be the same for all neurons or may be different. Therefore, the activation functions of neurons in each layer may be the same or different.

[0071] By the way, the signals output by the neurons in each layer can be analog values ​​or digital values. The digital value may be, for example, a binary value or a ternary value. For analog values, the activation function can be, for example, a linear ramp function, a sigmoid function, etc. In the case of binary digital values, for example, the output can be set to -1 or 1, or 0 or A step function that sets the signal output by each layer of neurons to 1 or 2 can be used. may be ternary or more, in which case the activation function has three values, e.g., the outputs are -1, 0, or If we use a step function with 1, or a step function with 0, 1, or 2, good.

[0072] The neural network 100 receives an input signal in the first layer (input layer). In each layer from the first layer (input layer) to the last layer (output layer), the input from the previous layer is sequentially Based on the input signal, an output signal is generated using equations (1.1) to (1.3), and the output signal is The signal output from the last layer (output layer) is This corresponds to the result calculated by the neural network 100.

[0073] <Example of arithmetic circuit configuration> Here, in the above-mentioned neural network 100, the formula (1.2) and the formula (1 An example of an arithmetic circuit capable of performing the above arithmetic operations is described below. In this case, for example, the weight coefficients of the synapse circuits of the neural network 100 are expressed as binary (e.g., a combination of "-1" and "+1" or a combination of "0" and "+1"), or 3 The activation function of a neuron is a binary function (such as a combination of "-1", "0", and "1"). (e.g., a combination of "-1" and "+1" or a combination of "0" and "+1"), or 3 The function outputs a value (such as a combination of "-1", "0", and "1"). In the literature, the weighting coefficients and the signals input from the previous layer neurons to the next layer neurons are One of the two values ​​(sometimes called the calculated value) is called the first data. The other is referred to as second data.

[0074] The arithmetic circuit 110 shown in FIG. 2 includes, as an example, an array section ALP, a circuit ILD, and a circuit W The semiconductor device includes an LD, a circuit XLD, and a circuit AFP. Neuron N1 in layer k in Fig. 1A and Fig. 1B (k) Neuron N n (k) To Input signal z1 (k-1) ~z m (k-1) and neuron N1 (k) No To Neuron N n (k) The signal z1 output from each of (k) ~z n (k) Generate This is a circuit that:

[0075] The entire or part of the arithmetic circuit 110 may be implemented as a neural network or It may be used for purposes other than AI, such as graphics calculations or scientific calculations. In the case of performing multiply-and-accumulate processing or matrix processing in the above, the entire arithmetic circuit 110, In other words, it can be used not only for AI calculations, but also for general purposes. For such calculations, the entirety of the arithmetic circuit 110 or a portion thereof may be used.

[0076] The circuit ILD includes, for example, wirings IL[1] to IL[n] and wiring ILB[1] The circuit WLD is, for example, electrically connected to the wiring WL The circuit XLD is electrically connected to wirings S[1] to WLS[m]. The circuit AFP is electrically connected to the wirings XLS[1] to XLS[m]. The wiring OL[1] to wiring OL[n], the wiring OLB[1] to wiring OLB[n], is electrically connected to

[0077] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. In the array section ALP, the pixels are arranged in a matrix of m rows and n columns. In Figure 2, the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) The circuit MP located at i,j is written as circuit MP[i,j]. is the circuit MP[1,1], the circuit MP[m,1], the circuit MP[i,j], the circuit MP[1,n ], only the circuit MP[m,n] is shown, and the other circuits MPC are omitted. is doing.

[0078] For example, the circuit MP[i,j] includes a wiring IL[j], a wiring ILB[j], and a wiring W LS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j] are electrically connected to each other. is connected to

[0079] A circuit MP[i,j] is, for example, a network of neurons N i (k-1) and neuron N j (k ) The weighting coefficient between the first data and the second data (sometimes called either the first data or the second data) Specifically, the circuit MP[i,j] has a function of holding a first data. According to the first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j] It stores information (such as potential, resistance, and current). In addition, the circuit MP[i,j] is , neuron N i (k-1) The signal z output from i (k-1) (First data or second data The product of the first data and the second data (sometimes called the other data) As a specific example, the circuit MP[i,j] has a function of outputting the wiring XLS[i ] to the second data z i (k-1) By inputting, the product of the first data and the second data is Information corresponding to the first data and the second data (e.g., current, voltage, etc.) or information related to the product of the first data and the second data The information (e.g., current, voltage, etc.) is output to wiring OL[j] and wiring OLB[j]. Although an example in which the wiring IL[j] and the wiring ILB[j] are placed has been shown, One embodiment of the present invention is not limited to this. Only one of the wirings OL[j] and OLB[j] may be arranged. However, one embodiment of the present invention is not limited to this. ] and wiring OLB[j] alone may be provided.

[0080] <<Circuit ILD>> The circuit ILD includes, for example, wirings IL[1] to IL[n] and wiring ILB[1] through wiring ILB[n], and through the circuits MP[1,1] to MP[m,n]. For each of them, the first data w1 (k-1) 1 (k) Or even w m (k-1) n (k) The input device has a function of inputting information corresponding to the above (for example, potential, resistance value, current value, etc.). As a specific example, the circuit ILD is a first weighting coefficient for the circuit MP[i,j]. Data W i (k-1) j (k) Information corresponding to the potential, resistance, or current etc.) are supplied via wiring IL[j] and wiring ILB[j].

[0081] <<Circuit WLD>> For example, the circuit WLD receives information (e.g., The MOS transistor has a function of selecting a circuit MP to which a certain value (such as a potential, a resistance value, a current value, etc.) is to be written. For example, the circuits MP[i,1] to MP[i,n] located in the i-th row of the array unit ALP When writing information (such as a potential, a resistance value, a current value, etc.) to the For example, the write switching elements included in the circuits MP[i,1] to MP[i,n] A signal for turning on or off the child is supplied to the wiring WLS[i], and the A potential for turning off the write switching element included in the circuit MP is supplied to the wiring WLS. Although an example in which the wiring WLS[i] is arranged has been shown, One embodiment is not limited to this. For example, the wiring WLS[i] is arranged as a plurality of wirings. This is also fine.

[0082] <<Circuit XLD>> As an example, the circuit XLD is connected to the circuit M via wirings XLS[1] to XLS[m]. For each of P[1,1] to MP[m,n], neuron N1 (k-1) No To Neuron N m (k) The second data z1 corresponds to the calculated value output from (k-1) ~ z m (k-1) Specifically, the circuit XLD has a function of supplying the circuit MP[i,1 ] or circuit MP[i,n], neuron N i (k-1) The second data output from Taz i (k-1) The information corresponding to the wiring XLS[i] (e.g., potential, current value, etc.) is Although an example in which the wiring XLS[i] is arranged has been shown, One aspect of the present invention is not limited to this. For example, the wiring XLS[i] is arranged as a plurality of wirings. You may do so.

[0083] <<Circuit AFP>> As an example, the circuit AFP includes circuits ACTF[1] to ACTF[n]. The circuit ACTF[j] is, for example, a wiring OL[j] and a wiring OLB[j]. The circuit ACTF[j] is electrically connected to the wiring OL[j]. According to each piece of information (e.g., potential, current value, etc.) input from wiring OLB[j] For example, the signal input from the wiring OL[j] and the wiring OLB[j] is generated. The respective pieces of information (for example, potential or current value) are compared, and a signal corresponding to the comparison result is generated. This signal is generated by neuron N j (k) The signal z output from j (k) Equivalent to That is, the circuits ACTF[1] to ACTF[n] are, for example, It functions as a circuit that calculates the activation function of the neural network. One embodiment is not limited to this. For example, the circuits ACTF[1] to ACTF[n] are , may have a function of converting an analog signal into a digital signal. ACTF[1] to ACTF[n] have the function of amplifying and outputting analog signals, that is, The ACTF circuit may have a function of converting the output impedance. However, the present invention is not limited to this embodiment. may not be placed.

[0084] The circuits ACTF[1] to ACTF[n] have the circuit configuration shown in FIG. 3A as an example. FIG. 3A shows an example of input from wiring OL[j] and wiring OLB[j]. Depending on the current, the signal z j (k) Specifically, FIG. 3A shows a circuit that generates Output signal z represented by two values j (k) An example of an activation function calculation circuit that outputs is.

[0085] In FIG. 3A, the circuit ACTF[j] includes a resistor RE, a resistor REB, and a comparator CM P. The resistor elements RE and REB have the function of converting current into voltage. Therefore, any element or circuit that has the function of converting current into voltage is not limited to a resistive element. The wiring OL[j] is connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP. , and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the comparator CM The second terminal of the resistor element RE is electrically connected to the second input terminal of the resistor element P. The second terminal of the resistor REB is electrically connected to the wiring VAL. The second terminal of the resistor element RE and the second terminal of the resistor element REB are connected to the same wiring. Alternatively, it may be connected to another wiring having the same potential.

[0086] It is preferable that the resistance values ​​of the resistor elements RE and REB are equal to each other. For example, the difference between the resistance values ​​of the resistors RE and REB is preferably within 10%. It is preferable that the difference is within 5%. However, in one embodiment of the present invention, However, the resistance elements RE and REB may be changed depending on the circumstances. The resistance values ​​may be different from each other.

[0087] The wiring VAL functions as a wiring that applies a constant voltage, for example. For example, VDD is a high-level potential, VSS is a low-level potential, and GND is a ground potential. The constant voltage can be set appropriately according to the configuration of the circuit MP. It is preferable that a pulse signal, not a constant voltage, is supplied to the wiring VAL. It may be possible.

[0088] The voltage between the first and second terminals of the resistor element RE is the current flowing from the line OL[j]. Therefore, the resistance value of the resistor RE is input to the first input terminal of the comparator CMP. Similarly, the first and second terminals of the resistor element REB are The voltage between the comparator CM A voltage according to the resistance value of the resistor REB and the current is input to a second input terminal of P.

[0089] As an example, the comparator CMP receives a first input terminal and a second input terminal, A function that compares voltages and outputs a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP has a function of detecting a voltage at its second input terminal that is lower than the voltage at its first input terminal. When the voltage input to the comparator CMP is high, a high-level potential is output from the output terminal of the comparator CMP. When the voltage input to the first input terminal is higher than the voltage input to the second input terminal, the low level The bell potential can be output from the output terminal of the comparator CMP. The potential output from the output terminal can be either high level or low level. Output signal z output by ACTF[j] j (k) can be binary. For example, the comparison The high-level potential and the low-level potential output from the output terminal of the CMP are output signals z j (k) It can correspond to "+1" and "-1" as follows. Also, in some cases, The high level potential and the low level potential output from the output terminal of the comparator CMP are signal z j (k)may correspond to "+1" and "0".

[0090] In addition, in the circuit ACTF[j] of FIG. 3A, the resistor elements RE and REB are used. The element or circuit is not limited to a resistive element, so long as it has a function of converting a current into a voltage. Therefore, the resistor elements RE and REB of the circuit ACTF[j] in FIG. 3A are different circuit elements. For example, the circuit ACTF[j] shown in FIG. 3B can be replaced by the circuit The resistor elements RE and REB included in the circuit ACTF[j] are the capacitor elements CE and This is a circuit in which CEB has been replaced, and it operates in a manner similar to that of the circuit ACTF[j] in Figure 3A. The capacitance values ​​of the capacitance elements CE and CEB are For example, the capacitance values ​​of the capacitance elements CE and CEB are preferably equal to each other. The difference should be within 10%, and more preferably within 5%. However, one embodiment of the present invention is not limited to this. For example, a circuit for initializing the accumulated charge may be provided in parallel with the capacitance element CE. A switch may be provided. That is, the second terminal of the switch is connected to the wiring VAL. The first terminal of the switch is connected to the first terminal of the capacitance element CE, the wiring OL[j], and the comparator Alternatively, the second terminal of the switch may be connected to the first input terminal of the CMP. AL is connected to a wiring different from the first terminal of the switch, and the first terminal of the capacitance element CE is connected to the wiring OL[j] and the first input terminal of the comparator CMP. The circuit ACTF[j] shown in FIG. This is a circuit in which the resistor element REB is replaced with a diode element DE and a diode element DEB. , it can perform almost the same operation as the circuit ACTF[j] in FIG. 3A. E. The direction of the diode element DEB (the connection point between the anode and cathode) is the same as the current of the wiring VAL. It is desirable to change it appropriately depending on the magnitude of the position.

[0091] In addition, the comparator CMP included in the circuit ACTF[j] in FIG. 3A to FIG. 3C is, for example, , can be replaced by an operational amplifier OP. The circuit ACTF[j] shown in FIG. 3D can be replaced by an operational amplifier OP. The circuit diagram of A is shown in which the comparator CMP of the ACTF[j] circuit is replaced with an operational amplifier OP. do.

[0092] In addition, even if the switch S01a and the switch S01b are provided in the circuit ACTF[j] of FIG. 3B, As a result, the circuit ACTF[j] has the following capacitance elements CE and CEB: It is possible to maintain the potential according to the current input from wiring OL[j] and wiring OLB[j]. As an example of a specific circuit, as shown in FIG. 3E, A wiring OL[j] is electrically connected to the terminal of the switch S01a, and a capacitance element CE The first terminal of the switch S01b is electrically connected to the first input terminal of the comparator CMP. The wiring OLB[j] is electrically connected to the first terminal of the switch S01b, and the capacitive element It is sufficient if the first terminal of CEB is electrically connected to the second input terminal of the comparator CMP. In the circuit ACTF[j] of FIG. 3E, the first and second input terminals of the comparator CMP are When the potential of the wiring OL[j] and wiring OLB[j] is input to the switch S01a, This can be done by turning on each of the switches S01b and S01b. , the switch S01a and the switch S01b are turned off, The potentials input to the first and second input terminals of the capacitor CMP are fed to the capacitance element CE and the capacitance The capacitance element CEB can be held in the capacitance element CEB. For example, an electrical switch such as an analog switch or a transistor may be used. In addition, the switches S01a and S01b may be, for example, mechanical switches. In addition, transistors may be applied to the switches S01a and S01b. In the case of using a silicon-doped transistor as a channel forming region, the transistor is an OS transistor or The transistor may be a transistor having a gate insulating film (hereinafter referred to as a Si transistor). Alternatively, the period during which each of the switches S01a and S01b is kept in the on state is controlled. By doing so, it is possible to control the voltage values ​​of the capacitance elements CE and CEB. For example, when the current flowing through the capacitance elements CE and CEB is large, the switch S01a By shortening the period during which each of the switches S01b and S01b is in the on state, This can prevent the voltage values ​​of the capacitance element CE and the capacitance element CEB from becoming too large.

[0093] The comparator CMP included in the circuit ACTF[j] in FIG. 3A to FIG. 3C and FIG. 3E is, for example, For example, the comparator CMP shown in FIG. 3F is a chopper type comparator. The comparator CMP is a comparator of the type shown in FIG. The switch S03, the capacitance element CC, and the inverter circuit INV3. The switches S02a, S02b, and S03 are the same as the switches S01a and S02b. As with 01b, mechanical switches, OS transistors, Si transistors, and other transistors are used. It can be a gistar.

[0094] A first terminal of the switch S02a is electrically connected to the terminal VinT, and a second terminal of the switch S02b is electrically connected to the terminal VinT. A first terminal of the switch S02a is electrically connected to the terminal VrefT, and a second terminal of the switch S02a is electrically connected to the terminal VrefT. The second terminal of the switch S02b and the first terminal of the capacitive element CC are electrically connected to each other. The second terminal of the capacitance element CC is connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. The terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3. The input terminal of the switch S01 is electrically connected to the output terminal of the switch S02 and to the second terminal of the switch S03.

[0095] The terminal VinT functions as a terminal for inputting the input potential to the comparator CMP, and the terminal V refT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal Vout The terminal T functions as a terminal for outputting the output potential from the comparator CMP. nT corresponds to one of the first terminal or the second terminal of the comparator CMP in FIG. 3A to FIG. 3C and FIG. 3E. The terminal VrefT corresponds to the first or second terminal of the comparator CMP shown in FIGS. 3A to 3C and 3E. It can correspond to the other child.

[0096] The circuit ACTF[j] of FIG. 3A to FIG. 3E outputs an output signal z j (k) The activation function ACTF[j] outputs the output signal z j (k) of It may be configured to output three or more values, or as an analog value.

[0097] 4A to 4F show the currents input from the wiring OL[j] and the wiring OLB[j]. , signal z j (k)is a circuit that generates an output signal z represented by a ternary value. j (k) Leave 1 shows an example of a calculation circuit for an activation function to be input.

[0098] The circuit ACTF[j] shown in FIG. 4A includes a resistor RE, a resistor REB, a comparator CMPa , and a comparator CMPb. The wiring OL[j] is connected to a first terminal of the resistor RE and a comparator CM The wiring OLB[j] is electrically connected to the first input terminal of the resistor REB. The terminal is electrically connected to a first input terminal of the comparator CMPb. The second input terminal of the comparator Pa and the second input terminal of the comparator CMPb are electrically connected to the wiring VrefL. Furthermore, a second terminal of the resistor element RE is electrically connected to the wiring VAL. A second terminal of the resistor element REB is electrically connected to the wiring VAL.

[0099] The wire VrefL is a constant voltage V ref It acts as a wiring that provides V ref For example, It is preferable that the voltage is greater than GND and less than VDD. ref GN It may be a potential lower than D or a potential higher than VDD. ref is the comparator CMPa, It is used as a reference potential (potential for comparison) in comparator CMPb.

[0100] The voltage between the first and second terminals of the resistor element RE is the current flowing from the line OL[j]. Therefore, the first input terminal of the comparator CMPa is connected to the resistor element RE. Similarly, the first and second terminals of the resistor element REB are The voltage between is determined by the current flowing from the wiring OLB[j]. The first input terminal of the resistor CMPb receives a voltage according to the resistance value of the resistor REB and the current. will be done.

[0101] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal. Then, a signal is output from the output terminal of the comparator CMPa according to the comparison result. The comparator CMPa detects that the voltage input to the second input terminal ( V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPa, and The voltage input to the input terminal (V ref ) when the voltage input to the first input terminal is higher than , a low-level potential can be output from the output terminal of the comparator CMPa.

[0102] Similar to the comparator CMPa, the comparator CMPb has a first input terminal and a second input terminal. The voltage input to the comparator CMPb is compared with the voltage input to the For example, the comparator CMPb outputs a signal when the voltage input to the second input terminal is lower than the voltage input to the first input terminal. The voltage input to the input terminal (V ref When CMPb is high, the high-level potential is The voltage input to the second input terminal (V ref ) to the first input terminal. When the input voltage is high, a low-level potential is output from the output terminal of the comparator CMPb. can be done.

[0103] At this time, the potentials output from the output terminals of the comparators CMPa and CMPb are Depending on j (k) For example, the output of the comparator CMPa can be expressed as A high-level potential is output from the input terminal, and a low-level potential is output from the output terminal of the comparator CMPb. If the output signal z j (k) is set to "+1", and a low level is output from the output terminal of the comparator CMPa. When a high-level potential is output from the output terminal of comparator CMPb, signal z j (k) is set to "-1", and a low-level potential is output from the output terminal of the comparator CMPa. When a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) teeth It can be set to “+0”.

[0104] In addition, the circuit ACTF[j] is not limited to the circuit configuration shown in FIG. 4A. Depending on the situation, For example, in the circuit ACTF[j] of FIG. 4A, the comparator CMPa If you want to combine the two output results of the comparator CMPb into one signal, The circuit ACTF[j] in FIG. 4B is the same as the circuit in FIG. 4A. This is a configuration example in which a conversion circuit TRF is provided in ACTF[j]. Each output terminal is electrically connected to an input terminal of the conversion circuit TRF. A specific example of an RF is a digital-to-analog conversion circuit (in this case, a signal z j (k) Is A (The value is analog.)

[0105] Also, for example, in FIG. 4A, the second inputs of the comparators CMPa and CMPb are The wire VrefL electrically connected to the input terminal is The circuit ACTF[j] in FIG. 4C is the same as the circuit ACTF[j] in FIG. 4A. The second terminal of the comparator CMPa included in [j] is connected to the wiring Vref1 instead of the wiring VrefL. L, and the second terminal of the comparator CMPb is electrically connected to the line Vref instead of the line VrefL. The inputs to the wiring Vref1L and Vref2L are electrically connected to By making the potentials outputted from the comparators CMPa and CMPb different from each other, The reference potentials for the respective inputs can be set separately.

[0106] For example, as a configuration different from the circuit ACTF[j] of FIG. 4A to FIG. 4C, an amplifier circuit Alternatively, an impedance conversion circuit or the like may be used. For example, the circuit AC TF[j] can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. ACTF[j] is a resistor RE, a resistor REB, an operational amplifier OPa, and an operational amplifier OP b, which functions as an amplifier circuit.

[0107] The wiring OL[j] is connected to the first terminal of the resistor RE and the non-inverting input terminal of the operational amplifier OPa. , electrically connected, and the wiring OLB[j] is a first terminal of the resistor REB and a second terminal of the operational amplifier O It is electrically connected to the non-inverting input terminal of Pb. It is also electrically connected to the inverting input terminal of the operational amplifier OPa. The terminal is electrically connected to the output terminal of the operational amplifier OPa and the inverting input terminal of the operational amplifier OPb. The terminal is electrically connected to the output terminal of the operational amplifier OPb. The second terminal of the resistor REB is electrically connected to the wiring VAL. is electrically connected to

[0108] In other words, the operational amplifiers OPa and O Pb is connected as a voltage follower. This allows the op-amp OPa to The potential output from the output terminal is the same as the potential input to the non-inverting input terminal of the operational amplifier OPa. The voltage output from the output terminal of the operational amplifier OPb is almost equal to the voltage output from the output terminal of the operational amplifier OPb. In this case, the output signal z j (k) teeth , are output from the circuit ACTF[j] as two analog values. The output terminal of the operational amplifier OPb is connected to the input terminal of the comparator CMP. The output from the comparator CMP may then be connected to the output signal z j (k) It is also possible to use the following.

[0109] Also, for example, as a configuration different from the circuit ACTF[j] of FIG. 4A to FIG. 4D, an integrating circuit A current-voltage conversion circuit, etc. may be used. Furthermore, an integrating circuit, a current A voltage conversion circuit may be configured. For example, the circuit ACTF[j] shown in FIG. 4E may be configured as This can be applied to the circuit AFP of the arithmetic circuit 110. The circuit ACTF[j] in FIG. It has an operational amplifier OPa, an operational amplifier OPb, a load element LEa, and a load element LEb.

[0110] The wiring OL[j] is connected between the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa and the negative The first terminal of the load element LEa is electrically connected to the line OLB[j]. b and a first terminal of the load element LEb. Also, the second input terminal (for example, the non-inverting input terminal) of the operational amplifier OPa is , electrically connected to the wiring Vref1L, and the second input terminal (for example, the non- The inverting input terminal of the load element LEa is electrically connected to the wiring Vref2L. The terminal is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load element LEa is , and is electrically connected to the output terminal of the operational amplifier OPb.

[0111] In this case, the wiring Vref1L and the wiring Vref2L may be equal to each other or may be different from each other. Therefore, the wiring Vref1L and wiring Vref2 L can be combined into a single wire.

[0112] In the circuit ACTF[j] of FIG. 4E, the load elements LEa and LEb are, for example, For example, it can be a resistor element or a capacitor element. By using a capacitance element as the op-amp OPa, the load element LEa, and the op-amp OPb and the load element LEb each function as an integrator. Or, depending on the amount of current flowing through the wiring OLB[j], each capacitance element (load element LEa , LEb) is stored. In other words, charges flow from wiring OL[j] and wiring OLB[j]. The current is integrated by an integrator circuit and converted into a voltage, which is then output as a signal z j (k) year The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb are connected to each other. , and the input terminals of the comparator CMP. The output signal z j (k) The capacitive elements of the load elements LEa and LEb may be For example, a circuit for initializing the charge stored in the load element LEa ( A switch may be provided in parallel with the capacitance element. That is, the second terminal of the switch may be , the first terminal of the switch is connected to the output terminal of the operational amplifier OPa, and the second terminal of the switch is connected to the wiring OL[j], Also, it may be connected to the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa. stomach.

[0113] In addition, in the circuit ACTF[j] of FIG. 4E, from the wiring OL[j] and wiring OLB[j] When converting a flowing current into a voltage and outputting it, the load elements LEa and LEb are as follows: As an alternative to the capacitance element, a resistance element can be used.

[0114] Also, for example, as a configuration different from the circuit ACTF[j] of FIG. 4A to FIG. 4E, The circuit ACTF[j] shown can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. The circuit ACTF[j] in FIG. 4F includes a resistor RE, a resistor REB, and an analog-to-digital converter. It has a circuit ADCa and an analog-to-digital conversion circuit ADCb.

[0115] The wiring OL[j] is connected to the input terminal of the analog-to-digital conversion circuit ADCa and the resistor element RE. The first terminal is electrically connected to the wiring OLB[j], and the wiring OLB[j] is connected to the analog-to-digital conversion circuit AD The input terminal of the resistor element REB is electrically connected to the input terminal of the resistor element Cb and the first terminal of the resistor element REB. The second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring It is electrically connected to VAL.

[0116] In the circuit ACTF[j] of FIG. 4F, the current flows from the wiring OL[j] and the wiring OLB[j]. The potentials of the first terminals of the resistor elements RE and REB are determined according to the current. Then, the circuit ACTF[j] converts the analog value of the potential into an analog-to-digital conversion circuit. Depending on the ADCa and ADCb, digital signals with two values ​​or more than three values ​​(for example, 256 values) can be Then, convert the signal z j (k) It has the function of outputting as

[0117] The resistor elements RE and REB shown in FIGS. 4A to 4F are the same as those shown in FIGS. 3B and 3C. Similarly, the capacitance element CE, the capacitance element CEB, or the diode element DE, the diode element DE In particular, the resistor element RE and the resistor element B shown in FIGS. When REB is replaced with the capacitance element CE and the capacitance element CEB, the switch is turned on as in FIG. 3E. By providing switches S01a and S01b, the wiring OL[j] and wiring OLB[j] can be The input potential can be held.

[0118] In addition, the arithmetic circuit 110 in FIG. 2 performs the following operations depending on the circuit configuration of the circuit MP[i,j]: i,j] can be changed. For example, in Figure 2, In the arithmetic circuit 110, the wiring WLS[i ] can be one or more wires. For example, in the circuit MP[i,j] The electrically connected wiring XLS[i] can be one or more wirings. .

[0119] <<Circuit MP>> Next, a configuration example of the circuit MP[i,j] included in the arithmetic circuit 110 will be described.

[0120] FIG. 5A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 110. The path MP[i,j] includes, for example, a circuit MC and a circuit MCr. In the circuit MP, the weight coefficients, the input signals (calculated values) of the neurons, and the circuit MCr The circuit MC is a circuit that calculates the product of the two. The circuit MC may have the same configuration as the circuit MCr, or may have a different configuration from the circuit MCr. Therefore, the circuit MCr is designated by the symbol MCr in order to distinguish it from the circuit MC. The circuit elements included in the circuit MCr, which will be described later, are designated by the letter "r". It also has an "r" attached to it.

[0121] For example, the circuit MC has a holding portion HC, and the circuit MCr has a holding portion HCr. The holding unit HC and the holding unit HCr each store information (e.g., potential, resistance, current, etc.) ) is stored in the circuit MP[i,j]. i (k -1) j (k) The information held in the holding unit HC and the holding unit HCr (for example, Therefore, the holding part HC and the holding part HCr are determined according to the value of the holding part HC. Each of the first data w i (k-1) j (k) Each piece of information (e.g., potential, resistance) The wires IL[j] and ILB[j] are electrically connected to the wires IL[j] and ILB[j] that supply the There are.

[0122] The wiring WL[i] shown in FIG. 5A corresponds to the wiring WLS[i] in FIG. L[i] is electrically connected to each of the holding units HC and HCr. The first data w is stored in each of the holding units HC and HCr included in P[i,j]. i (k -1) j (k)When writing information according to the distribution (e.g., potential, resistance, current, etc.), By supplying a predetermined potential to the line WL[i], the wiring IL[j] and the holding unit HC are connected. The wiring ILB[j] and the holding unit HCr are brought into a conductive state. The first data w i (k-1) j (k) The potential according to By supplying the potential, the holding part HC and the holding part HCr are respectively supplied with the potential, etc. Then, a predetermined potential is applied to the wiring WL[i], and the wiring IL[j ] and the holding unit HC are brought into a non-conductive state, and the wiring ILB[j] and the holding unit HCr are brought into a non-conductive state. Then, the first data w i (k-1 ) j (k) Each potential according to the above is maintained.

[0123] For example, the first data i (k-1) j (k) can take one of the three values ​​"-1", "0" or "1". Consider the case where either of the first data w i (k-1) j (k) If is “1”, for example As a result, a high level potential is held in the holding unit HC, and a low level potential is held in the holding unit HCr. Also, the first data i (k-1) j (k) is "-1", as an example, the holding part H A low level potential is held in the storage section C, and a high level potential is held in the storage section HCr. Tw i (k-1)j (k) When is "0", for example, the holding unit HC is at a low level potential. The first data w i (k-1) j (k) is an analog value, specifically, a “negative analog value”, “0”, or Let us consider the case where the first data w i (k-1) j (k) is "positive In the case of the "analog value", for example, a high-level analog potential is held in the holding unit HC, The holding unit HCr holds a low level potential. Also, the first data w i (k-1) j (k) but" In the case of the "negative analog value", for example, a low level potential is held in the holding unit HC, and A high level analog potential is held in HCr. Then, the first data w i (k-1) j (k ) is "0", for example, a low level potential is held in the holding section HC, and the holding section HCr The analog value is a multi-bit (multiple-value) digital value. That is, as an example, the first data w i (k-1) j (k) But, "1", In the case where the numbers are "2" and "3", for example, the holding portion HC is The high level potential having the potential set by the voltage source HCr is held, and the low level potential is held in the holding section HCr. , 1st data w i (k-1) j (k)If is "-1", "-2", "-3", for example The holding section HC holds a low level potential, and the holding section HCr holds "-1" and "-2" Holds a high level of potential according to the absolute values ​​of "1", "2", and "3" And the first data w i (k-1) j (k) When is "0", as an example, the holding part A low level potential is held in HC, and a low level potential is held in the holding unit HCr.

[0124] In addition, as an example, the circuit MC stores information (e.g., potential, resistance value, etc.) stored in the storage unit HC. , current value, etc.) to either wiring OL[j] or wiring OLB[j] The circuit MCr has a function of outputting information (e.g., potential, The current, voltage, etc. according to the resistance value, current value, etc. are connected to wiring OL[j] or wiring OLB[j]. For example, when a high-level potential is held in the holding section HC, In this case, the circuit MC outputs a current having a first current value, and a low-level potential is held in the holding section HC. When the holding unit HC is in the ON state, the circuit MC outputs a current having a second current value. When r is held at a high level potential, the circuit MCr outputs a current having a first current value; When the holding portion HCr holds a low level potential, the circuit MCr flows a current having a second current value. The magnitudes of the first current value and the second current value are respectively determined by the circuit MC , the configuration of the circuit MCr, the holding unit HC, the holding unit HCr, etc., and the first data w i (k-1) j ( k) For example, when the first current value is greater than the second current value, In addition, one of the first current value and the second current value may be zero current, and In other words, the current value may be 0. Or, there may be a current having a first current value and a current having a second current value. In some cases, the direction of the current flow may be different. i (k-1) j (k) When the value of the first current or the second current is "-1", "0", or "1", It is preferable to configure the circuit MC and the circuit MCr so that one of the current values ​​is 0. , 1st data w i (k-1) j (k) is an analog value, e.g., “negative analog value”, “0 " or "positive analog value", the first current value or the second current value For example, it may take an analog value.

[0125] In this specification and the like, the information held in the holding unit HC and the holding unit HCr (for example Current, voltage, etc. according to the potential, resistance, current value, etc. are positive current, voltage, etc. It may be a positive current or voltage, or it may be a mixture of positive and negative current or voltage. That is, for example, the information held in the holding unit HC described above (for example, potential, resistance value, current value, etc.) The current, voltage, etc. according to the current, voltage, etc., is output to either wiring OL[j] or wiring OLB[j]. The circuit MCr has a function of storing information (for example, potential, resistance value, current The current, voltage, etc. according to the current value (current value, etc.) is output to the other side of wiring OL[j] or wiring OLB[j]. The description "has a function of inputting information stored in the storage unit HC (for example, potential, resistance)" is replaced with "has a function of inputting information stored in the storage unit HC (for example, potential, resistance)". The current, voltage, etc. according to the resistance, current value, etc. of the wiring OL[j] or wiring OLB[j] The circuit MCr has a function of discharging a voltage according to the potential held in the holding section HCr. The description "has the function of discharging the current from the other of the wiring OL[j] or the wiring OLB[j]" This can be rephrased as:

[0126] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 5A correspond to the wiring XLS [i]. The second data z i (k-1) teeth For example, the potentials and currents of the wirings X1L[i] and X2L[i] are Therefore, in the circuit MC and the circuit MCr, for example, the wiring X1L[ i] and the line X2L[i], i (k-1) Each potential is input according to can be.

[0127] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j]. r is electrically connected to the wiring OL[j] and the wiring OLB[j]. As an example, the circuit MCr is a According to the position, the first data w is applied to the wiring OL[j] and the wiring OLB[j]. i (k-1) j (k ) and the second data z i (k-1) It outputs the current, potential, etc. according to the product of In this case, the current output destination from the circuits MC and MCr is the wiring X1L[i] and the wiring X2L[i For example, each of the circuits MC and MCr is determined by the potential of the circuit M The current output from C flows to either wiring OL[j] or wiring OLB[j], and the circuit MCr A circuit configuration in which the current output from flows to the other of the wiring OL[j] or wiring OLB[j]. In other words, the currents output from the circuit MC and the circuit MCr are as follows: The current flows through different wirings, not through the same wiring. There are also cases where no current flows from the path MCr to either the wiring OL[j] or the wiring OLB[j]. be.

[0128] For example, the second data z i (k-1) can take one of three values: "-1", "0", or "1". For example, the second data z i (k-1) If is "1", the circuit MP The circuit MC and the wiring OL[j] are in a conductive state, and the circuit MCr and the wiring OLB[j] are in a conductive state. In addition, for example, the second data z i (k-1) If is "-1", The MP circuit brings the circuit MC and the wiring OLB[j] into a conductive state, and the circuit MCr and the wiring OL[ j] is in a conductive state. For example, the second data z i (k-1) If is "0", The currents output by the circuits MC and MCr are connected to the wiring OL[j] and wiring OLB[j]. In order to prevent the current from flowing to either of the circuits, the circuit MP is connected between the circuit MC and the wiring OL[j], And, the circuit MC and the wiring OLB[j] are put into a non-conductive state, and the circuit MCr and the wiring OL[j ] and between the circuit MCr and the wiring OLB[j] are brought into a non-conductive state.

[0129] Here is an example of the above operations. i (k-1) j (k) is "1" In this case, a current is output from the circuit MC, and the first data w i (k-1) j (k) is "-1" In this case, the circuit MCr outputs a current. i (k-1) is "1" In the case of , between the circuit MC and the wiring OL[j], and between the circuit MCr and the wiring OLB[j] The second data z i (k-1) If is "-1", then the circuit MC and Conduction occurs between the wiring OLB[j] and between the circuit MCr and the wiring OL[j]. From the above, the first data i (k-1) j (k) and the second data z i (k-1) Product of When the first data w is a positive value, a current is output to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1) If the product is negative, the current flows through wiring OLB[j]. The first data w is output. i (k-1) j (k) and the second data z i (k-1) The product of is zero When the value is , no current is output to either wire.

[0130] To take the above example as a specific example, the first data w i (k-1) j (k) is "1" And the second data z i (k-1) When the value is "1", for example, the line OL A current I1[i,j] having a first current value flows through the wiring OLB[j] from the circuit MCr. A current I2[i,j] having a second current value flows through the first transistor. At this time, the magnitude of the second current value is For example, it is zero. In other words, strictly speaking, the current from the circuit MCr to the wiring OLB[j] is It doesn't flow. First data i (k-1) j (k) is "-1", and the second data z i (k -1) When the value of the second current value is “1”, for example, a current having a second current value flows from the circuit MC to the wiring OL[j]. A current I1[i,j] flows, and a current I2 having a first current value flows from the circuit MCr to the wiring OLB[j]. [i, j] flows. At this time, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OL[j]. i (k- 1) j (k) is "0", and the second data z i (k-1) If is "1", the circuit M A current I1[i, j] having a second current value flows from C to the wiring OL[j], and a current I2[i, j] flows from the circuit MCr to the wiring OL[j]. A current I2[i, j] having a second current value flows through the line OLB[j]. At this time, the second current value For example, the magnitude of is zero. In other words, strictly speaking, the wiring OL[j ], and no current flows from circuit MCr to wiring OLB[j].

[0131] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1 )is "-1", a current I1[ i, j] flows from the circuit MCr to the wiring OL[j], and a current I2[i, j] having a second current value flows At this time, the magnitude of the second current value is, for example, zero. In the first data w, no current flows from the circuit MCr to the wiring OL[j]. i (k-1) j ( k) is "-1", and the second data z i (k-1) If is "-1", the circuit MC A current I1[i, j] having a second current value flows from the circuit MCr to the wiring OLB[j]. A current I2[i, j] having a first current value flows through OL[j]. At this time, a current I2[i, j] having a second current value flows through OL[j]. For example, the magnitude is zero. In other words, strictly speaking, the wiring OLB[j] from the circuit MC No current flows through the first data i (k-1) j (k) is "0", and the second data z i (k-1) If is "-1", a second current value is sent from the circuit MC to the wiring OLB[j]. Current I1[i, j] flows, and current I2 with a second current value flows from circuit MCr to wiring OL[j]. [i, j] flows. At this time, the magnitude of the second current value is, for example, zero. Strictly speaking, no current flows from the circuit MC to the wiring OLB[j], and no current flows from the circuit MCr to the wiring O No current flows through L[j].

[0132] In addition, the second data z i (k-1) When is "0", for example, the circuit MC and the wiring OL[j] and between the circuit MC and the wiring OLB[j]. Between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j] Therefore, the first data w i (k-1) j (k) Whatever the value of No current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j]. stomach.

[0133] Thus, as an example, the first data w i (k-1) j (k) and the second data z i (k -1) If the product of is positive, the wiring is A current flows through OL[j]. At this time, the first data w i (k-1) j (k) If is positive, In this case, a current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the value of the first data is negative, a current flows from the circuit MCr to the wiring OL[j]. w i (k-1) j (k) and the second data z i (k-1) If the product of is negative, A current flows through the wiring OLB[j] from either the circuit MC or the circuit MCr. First data w i (k-1) j (k) If is a positive value, the wiring OLB[j] from the circuit MC A current flows through the first data w i (k-1) j (k)If is negative, the circuit MCr Current flows through the wiring OLB[j]. Therefore, the multiple circuits M connected to the wiring OL[j] The sum of the currents output from C or the circuit MCr flows through the wiring OL[j]. In other words, a current that is the sum of positive values ​​flows through the wiring OL[j]. On the other hand, the current output from multiple circuits MC or circuits MCr connected to wiring OLB[j] The sum of the negative current flows to the wiring OLB[j]. As a result of the above operation, a current that is the sum of the values ​​of the wiring OL[ The total current value flowing through wiring OLB[j], that is, the sum of the positive values, and the total current value flowing through wiring OLB[j], In other words, by using the sum of negative values, it is possible to perform product-sum calculations. For example, the total current flowing through wiring OL[j] is greater than the total current flowing through wiring OLB[j]. If it is larger, it can be determined that the result of the multiplication and accumulation operation will be a positive value. If the total current value flowing through OL[j] is smaller than the total current value flowing through wiring OLB[j], In this case, it can be determined that the result of the multiplication and accumulation operation is a negative value. ] and the total current value flowing through wiring OLB[j] are approximately the same value. It can be determined that the result of the multiplication and accumulation operation is zero.

[0134] In addition, the second data z i (k-1) is one of two values: "-1", "0", or "1". For example, the binary cases of "-1" and "1" or "0" and "1" are also the same. Similarly, the first data w i (k-1) j (k) is "-1", Any two values ​​of "0" and "1", for example, "-1" and "1", Alternatively, the same operation can be achieved for the binary values ​​"0" and "1".

[0135] In addition, the first data i (k-1) j (k) is an analog value or multi-bit (multiple values) A specific example would be a negative analog value instead of "-1". value” and “positive analog value” instead of “1”. In this case, the circuit M The magnitude of the current flowing from C or the circuit MCr is, for example, the first data w i (k-1 ) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0136] Next, an example of a modification of the circuit MP[i,j] in FIG. 5A will be described. Regarding the modified example of [i,j], the difference from the circuit MP[i,j] of FIG. 5A will be mainly described. 5A. Explanation of parts common to the circuit MP[i,j] in FIG. 5A may be omitted.

[0137] The circuit MP[i,j] shown in FIG. 5B is a modified example of the circuit MP[i,j] in FIG. 5A. The circuit MP[i,j] of FIG. 5B is the same as the circuit MP[i,j] of FIG. 5A, but includes a circuit MC and a circuit However, the circuit MP[i,j] in FIG. 5B includes a holding unit HCr in the circuit MCr. 5A in that it does not include

[0138] In addition, since the circuit MCr does not have a holding unit HCr, the circuit MP[i,j] in FIG. The applied arithmetic circuit uses the wiring ILB[j] to supply the potential to be held in the holding section HCr. In addition, the circuit MCr may not be electrically connected to the wiring WL[i]. Good too.

[0139] In the circuit MP[i,j] of FIG. 5B, the holding unit HC included in the circuit MC is a circuit MCr That is, the circuit MP[i,j] in FIG. 5B is electrically connected to the circuit MCr and the circuit The holding unit HC is shared by the MC and the MC. The inverted signal of the signal held by C is supplied from the holding unit HC to the circuit MCr. This allows the circuit MC and the circuit MCr to operate differently. Alternatively, the internal circuit configurations of the circuits MC and MCr may be made different. For the same signal held in the holding unit HC, the circuit MC and the circuit MCr output It is also possible to make the magnitude of the flow different. Here, the first data w i (k-1) j (k) The potential corresponding to the second data z i (k-1) The potential is set according to By supplying the line X1L[i] and the wiring X2L[i], the circuit MP[i,j] is The first data w i (k-1) j (k) And Day 2 Taz i (k-1) It is possible to output a current according to the product of

[0140] The arithmetic circuit 110 to which the circuit MP of FIG. 5B is applied has the same circuit configuration as the arithmetic circuit 120 shown in FIG. The arithmetic circuit 120 can be changed to a wiring configuration from the arithmetic circuit 110 in FIG. This configuration excludes wiring B[1] through ILB[m].

[0141] The circuit MP[i,j] shown in FIG. 5C is a modified example of the circuit MP[i,j] in FIG. Specifically, this is a configuration example of a circuit MP[i,j] that can be applied to the arithmetic circuit 120 in FIG. The circuit MP[i,j] of C is a circuit MC and a circuit M Cr. However, the circuit MP[i,j] in FIG. 5C and the circuit MP[i,j] in FIG. 5A have , the configuration of the wiring that is electrically connected is different.

[0142] The wiring W1L[i] and the wiring W2L[i] shown in FIG. 5C correspond to the wiring WLS The wiring W1L[i] is electrically connected to the holding portion HC, and the wiring W2L[i ] is electrically connected to the holding portion HCr.

[0143] In addition, the wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr. .

[0144] In the circuit MP[i,j] of FIG. 5C, different holding units HC and HCr are When holding the potential, the holding operation of the potential to the holding part HC and the holding part HCr is not simultaneous. For example, the first data w of the circuit MP[i,j] i (k-1) j (k ) can be expressed by holding a first potential in the holding part HC and a second potential in the holding part HCr. First, a predetermined voltage is applied to each of the wiring W1L[i] and the wiring W2L[i]. A potential is applied to bring the holding unit HC and the wiring IL[j] into a conductive state, and the holding unit HCr and the wiring IL[j] are also connected to each other. Next, a first potential is supplied to the wiring IL[j] to make the wiring IL[j] non-conductive. Then, the first potential can be applied to the holding unit HC. A predetermined potential is applied to each of the lines W2L[i] to connect the holding unit HC and the wiring IL[j]. The holding unit HCr and the wiring IL[j] are brought into a non-conductive state, and a conductive state is brought between the holding unit HCr and the wiring IL[j]. By supplying the second potential to the wiring IL[j], the second potential can be applied to the holding unit HCr. As a result, the circuit MP[i,j] receives w i (k-1) j (k) of It can be set.

[0145] In addition, when the holding parts HC and HCr are held at approximately the same potential (circuit M The first data w of P[i,j] i (k-1) j (k) However, the difference between the holding part HC and the holding part HCr is When the voltage is set by holding the potentials of the holding section HC and the wiring IL [j] and the holding unit HCr and the wiring IL[j] are in a conductive state. In order to achieve this, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i]. Then, the potential is supplied to the wiring IL[j].

[0146] The circuit MP[i,j] in FIG. 5C stores the first data w i (k -1) j (k) The potential corresponding to the second data z i (k-1) Wire the potential according to X 1L[i] and wiring X2L[i], the circuit MP[i,j] in FIG. Similarly, the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0147] The circuit MP[i,j] shown in FIG. 5D is a modified example of the circuit MP[i,j] in FIG. 5A. The circuit MP[i,j] of FIG. 5D is a circuit MC and a circuit MCr, where the circuit MP[i,j] in FIG. 5D and the circuit MP[i,j] in FIG. 5A The configurations of the electrically connected wiring are different.

[0148] The wiring IOL[j] in FIG. 5D is a combination of the wiring IL[j] and the wiring OL[j] in FIG. 5A. The wire IOLB[j] in FIG. 5D functions as a bundled wire. It functions as a single wiring that combines LB[j] and wiring OLB[j]. The IOL[j] is electrically connected to the holding portion HC, the circuit MC, and the circuit MCr, and is connected to the wiring The IOLB[j] is electrically connected to the holding unit HCr, the circuit MC, and the circuit MCr. There are.

[0149] The circuit MP[i,j] in FIG. 5D is provided with the first data w i (k-1) j (k) When holding the In order to achieve this, between the circuit MC and the wiring IOL[j], and between the circuit MC and the wiring IOLB[j] becomes non-conductive, and the circuit MCr and the wiring IOL[j] and The wiring X1L[i] and the wiring X2L[ A given potential is then input to the wiring WL[i] and held. The holding unit HC and the wiring IOL[j] are electrically connected to each other, and the holding unit HCr and the wiring IOLB[j ] is connected to the wiring IOL[j] and the wiring IOLB[j]. 1 data w i (k-1) j (k) By supplying each potential according to Each potential can be input to the holding unit HCr and the holding unit HCr. The line IOL[j] is in a non-conductive state, and the holding portion HCr and the wiring IOLB[j] are in a non-conductive state. A certain potential is input to the wiring WL[i] so that the gap between the wirings is non-conductive. The first data w is stored in each of the holding portion HC and the holding portion HCr. i (k-1) j (k) Depending on each The potential can be maintained.

[0150] The first data w is stored in each of the holding unit HC and the holding unit HCr. i (k-1) j (k) Depending on After the potential is held, the second data z i (k-1) The potential according to the wiring X1L[i] and By supplying the signal to the wiring X2L[i], the wiring OL[j] and wiring OLB[j] are assigned the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0151] The arithmetic circuit 110 to which the circuit MP of FIG. 5D is applied has the same circuit configuration as the arithmetic circuit 130 shown in FIG. The arithmetic circuit 130 can be modified to the circuit configuration of the arithmetic circuit 110 in FIG. The lines IL[1] to IL[n] and the lines OL[1] to OL[n] are connected to the wiring IO L[1] to IOL[n], and wiring ILB[1] to ILB[n]. , wiring OLB[1] to wiring OLB[n], and wiring IOLB[1] to wiring IOLB[ n]. In the arithmetic circuit 130, the wiring IOL[1 ] to IOL[n], and wirings IOLB[1] to IOLB[n] are connected to the circuit ILD. In other words, the wiring IOL[j] and the wiring IOLB[j] are electrically connected to the circuit MP For [i,j], the first data w i (k-1) j (k) A signal line for transmitting the In this case, the circuit MP [i,j] is the first data w i (k-1) j (k) When transmitting, the circuit ILD transmits The state between LD and wiring IOL[j] and between circuit ILD and wiring IOLB[j] is made conductive. The circuit ACTF[j] is connected between the circuit ACTF[j] and the wiring IOL[j] and between the circuit AC It is preferable to make the connection between TF[i] and the wiring IOLB[j] non-conductive. When supplying current to the circuit ACTF[j], the circuit ILD is connected to the circuit ILD and the wiring IOL[j ] and between the circuit ILD and the wiring IOLB[j] are non-conductive, and the circuit ACTF[ j] is between the circuit ACTF[j] and the wiring IOL[j], and between the circuit ACTF[j] and the wiring I It is preferable to establish a conductive state between OLB[j] and OLB[j].

[0152] The circuit MP[i,j] shown in FIG. 5E is a modified example of the circuit MP[i,j] in FIG. Specifically, this is a configuration example of a circuit MP[i,j] that can be applied to the arithmetic circuit 110 in FIG. The circuit MP[i,j] of E is a circuit MC and a circuit M Cr. However, in the circuit MP[i,j] of FIG. 5E, the circuit MC has the wiring OLB[j] The circuit MCr is electrically connected to the wiring OL[j]. 5A and in that there is no

[0153] The wiring WL[i] shown in FIG. 5E corresponds to the wiring WLS[i] in FIG. L[i] is electrically connected to the holding unit HC and the holding unit HCr.

[0154] 2. The wiring XL[i] shown in FIG. 5E corresponds to the wiring XLS[i] in FIG. The wiring XL[i] is electrically connected to the circuit MC and the circuit MCr.

[0155] As described above, the circuit MP[i,j] in FIG. 5E is electrically connected to the wiring OLB[j]. , and the circuit MCr is not electrically connected to the wiring OL[j]. The circuit MP[i,j] in FIG. 5E is different from the circuit MP[i,j] in FIG. 5A to FIG. 5D in that The current output from the circuit MC does not flow through the wiring OLB[j], and the current output from the circuit MCr does not flow to wiring OL[j].

[0156] Therefore, the circuit MP[i,j] of FIG. 5E receives the second data z i (k-1) is "0", or For example, when the second data z i (k-1) When the value of the OL[j] is “1”, the circuit MP establishes a conductive state between the circuit MC and the wiring OL[j]. In addition, the second device is turned on to turn on the circuit MCr and the wiring OLB[j]. Data z i (k-1) When the value of In order to prevent current from flowing through either wiring OL[j] or OLB[j], the circuit MP is The circuit between MC and wiring OL[j] is made non-conductive, and the circuit between MCr and wiring OLB[j] is made non-conductive. Put into a non-conducting state.

[0157] The circuit MP[i,j] in FIG. 5E can be applied to the arithmetic circuit 110 to obtain, for example, is the first data w i (k-1) j (k) can take one of three values: "-1", "0", or "1". Take the second data z i (k-1) When the value of 0 or 1 is taken, the calculation is performed. In addition, the circuit MP[i,j] in FIG. 5E stores the first data w i (k-1) j ( k) is one of two values, "-1", "0", or "1". For example, "-1" and "1" It can also operate in binary or binary "0" and "1" cases. First data w i (k-1) j (k) is an analog value or a multi-bit (multiple-value) digital For example, instead of "-1" you can use a "negative analog value" and In addition, instead of "1" a "positive analog value" may be used. In this case, the circuit MC or The magnitude of the current flowing from the circuit MCr is, for example, the first data w i (k-1) j (k ) The result is an analog value that corresponds to the absolute value of the value.

[0158] The circuit MP[i,j] shown in FIG. 5F includes the wiring OL[j] and the wiring OLB[j] in the same manner as in FIG. 5A. [j], the first data w i (k-1) j (k) and the second data z i (k-1) Depending on the product of The circuit MP[i,j] in FIG. 5F is a circuit that can output a current. For example, it can be applied to the arithmetic circuit 110 in FIG.

[0159] The circuit MP[i,j] of FIG. 5F includes a circuit MC and a circuit MCr, as well as a transistor Has MZ.

[0160] The first terminal of the transistor MZ is connected to the first terminal of the circuit MC and to the first terminal of the circuit MCr. The second terminal of the transistor MZ is electrically connected to the wiring VL. The gate of the transistor MZ is electrically connected to the wiring XL[i].

[0161] The wiring VL functions as, for example, a wiring that applies a constant voltage. It is preferable to determine the constant voltage based on the configuration of MP[i,j] and the arithmetic circuit 110. Examples of such potentials include VDD, which is a high-level potential, VSS, which is a low-level potential, and the ground potential. This can be done.

[0162] 5F corresponds to the wiring WLS[i] in the arithmetic circuit 110 in FIG. The wiring WL[i] is electrically connected to the holding portion HC and the holding portion HCr. It is being done.

[0163] The wiring OL[j] is electrically connected to the second terminal of the circuit MC. OLB[j] is electrically connected to a second terminal of the circuit MCr.

[0164] The wiring IL[j] is electrically connected to the holding unit HC, and the wiring ILB[j] is electrically connected to the holding unit HC. It is electrically connected to the HCr part.

[0165] In the circuit MP[i,j] of FIG. 5F, the first data is stored in each of the holding unit HC and the holding unit HCr. The operation of the circuit MP[i,j] in FIG. 5A when maintaining a potential according to the data is as follows: Please refer to the description of the operation of holding the potential according to the first data.

[0166] In the circuit MP[i,j] of FIG. 5F, the circuit MC has a first terminal connected to the wiring VL. When a constant voltage is applied, a current corresponding to the potential held in the holding section HC is generated. The circuit MCr has a function of passing current between the first terminal and the second terminal of the circuit MC. When a constant voltage is applied to the first terminal of the The circuit MCr has a function of passing a current corresponding to the potential between the first terminal and the second terminal of the circuit MCr. The first data w is stored in the holding unit HC and the holding unit HCr of the circuit MP[i,j]. i (k -1) j (k) By holding the potential according to Determine the amount of current flowing between the first and second terminals of the circuit MCr. In addition, a constant voltage is applied to the first terminal of the circuit MC (circuit MCr) through the wiring VL. If not supplied, the circuit MC (circuit MCr) may, for example, It is also possible that no current flows between the first terminal and the second terminal.

[0167] For example, the first data w of "1" is stored in each of the storage units HC and HCr. i (k-1) j (k) When the potential according to is held, a constant voltage is applied to the circuit MC via the wiring VL. As a result, the circuit MC flows a predetermined current between the first terminal and the second terminal of the circuit MC. Therefore, a current flows between the circuit MC and the wiring OL. No current flows between the first and second terminals of the circuit MCr. Therefore, No current flows between MCr and the wiring OLB. The first data w of "-1" for each of r i (k-1) j (k) The potential is maintained according to When the constant voltage is applied to the circuit MC through the wiring VL, the circuit MCr A predetermined current flows between the first terminal and the second terminal of the circuit MCr. At this time, the current flows between the first terminal of the circuit MC and the third terminal of the circuit MC. No current flows between the two terminals. Therefore, no current flows between the circuit MC and the wiring OL. In addition, for example, the first data of "0" is stored in each of the holding parts HC and HCr. Tw i (k-1) j (k)When a potential according to Regardless of whether a constant voltage is applied to the line VL, the circuit MC is connected to the first terminal of the circuit MC. No current flows between the first and second terminals of the circuit MCr, and the circuit MCr is connected between the first and second terminals of the circuit MCr. In other words, no current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OL. No current flows between line OLB.

[0168] In the circuit MP[i,j] of FIG. 5F, , 1st data w i (k-1) j (k) For a specific example of the potential according to P[i,j]. Also, in the circuit MP[i,j] of FIG. 5F, the holding unit H C, the holding part HCr, like the circuit MP[i,j] in FIG. 5A, stores current and resistance values ​​instead of potentials. The circuit MC and the circuit MCr pass a current according to the information. The function may be

[0169] The wiring XL[i] shown in FIG. 5F corresponds to the wiring XLS[i] in the arithmetic circuit 110 in FIG. In addition, the second data z input to the circuit MP[i,j] corresponds to i (k-1) As an example, The potential of the wiring XL[i] is determined by the potential, current, etc. of the wiring XL[i]. The gate of MZ is connected to the second data z i (k-1) Depending on The potential is input.

[0170] For example, the second data z i (k-1) Consider the case where the value of For example, the second data zi (k-1) If XL[i] is “1”, the line XL[i] has a high level. At this time, the transistor MZ is in the on state, so The circuit MP brings the wiring VL and the first terminal of the circuit MC into a conductive state, and the wiring VL and the circuit MC r and the first terminal of the second data z i (k-1) is "1" At this time, a constant voltage is applied from the wiring VL to the circuit MC and the circuit MCr. For example, the second data z i (k-1) When is "0", the wire XL[i] has a low-level potential. In this case, the circuit MP is a non-connection between the circuit MC and the wiring OLB[j]. The second data line is turned on, and the second data line is turned off. Data z i (k-1) When is "0", the circuit MC and the circuit MCr are connected to the wiring VL. No constant voltage is given by these.

[0171] Here, for example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) When is "1", current flows between the circuit MC and the wiring OL, and the circuit MC As a result, no current flows between r and the wiring BLB. i ( k-1) j (k) is "-1", and the second data z i (k-1) If is "1", No current flows between the circuit MC and the wiring OL, and no current flows between the circuit MCr and the wiring OLB. For example, the first data w i (k-1) j (k) is "0" , the second data z i (k-1) When the value is "1", the line between the circuit MC and the wiring OL and the line between the circuit As a result, no current flows between MCr and the wiring OLB. i (k-1) If it is "0", the first data w i (k-1) j (k) "-1", "0 " or "1", the circuit MC and the wiring OL, and the circuit MCr and the wiring O As a result, no current flows between LB.

[0172] That is, the circuit MP[i,j] in FIG. 5F is, for example, As the first data w i (k-1) j (k) can take one of the three values ​​"-1", "0", or "1". Then, the second data z i (k-1) When takes two values, "0" and "1", In addition, similarly to the circuit MP[i,j] in FIG. 5E, the circuit MP[ i,j] is the first data w i (k-1) j (k) Of the three possible values, "-1", "0" and "1", Any two values, for example, "-1" and "1", or "0" and "1" In addition, the first data w i (k-1) j (k) Hey, Anna It may be a logarithmic value or a multi-bit (multi-value) digital value. Specific examples include: "Negative analog value" instead of "-1" and "Positive analog value" instead of "1" In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr is, for example, As for the first data, i (k-1) j (k) The result is an analog value that corresponds to the absolute value of the value.

[0173] <Example of operation of the calculation circuit> Next, an example of the operation of the arithmetic circuit 110 in FIG. 2 will be described. In the explanation of this example of the operation, As an example, an arithmetic circuit 110 shown in FIG. 8 is used.

[0174] The arithmetic circuit 110 in FIG. 8 is illustrated by focusing on the circuit located in the j-th column of the arithmetic circuit 110 in FIG. That is, the arithmetic circuit 110 of FIG. 8 is the neural network shown in FIG. Neuron N in Network 100 j (k) The input to neuron N1 (k-1 ) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) And weight Coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) and the sum of products of The calculation circuit 11 in FIG. 8 corresponds to the calculation of the activation function using the result of the calculation. The circuit MP included in the array unit ALP of 0 is assumed to be the circuit MP of FIG. 5A. do.

[0175] First, in the arithmetic circuit 110, the first Data w1 (k-1) j (k) Or even w m (k-1) j (k) The first data w i (k-1) j (k) The method of setting is as follows: A predetermined potential is input to the wiring WLS[m] in order to connect the circuits MP[1,j] to MP[m , j] in order, and the holding part HC of the circuit MC included in the selected circuit MP, For the holding part HCr of the circuit MCr, from the circuit ILD, the wiring IL[j], the wiring ILB [j], a potential according to the first data is supplied. After the potential is supplied, the circuit W Deselecting each of the circuits MP[1,j] to MP[m,j] by the LD By this, the circuit MC of each of the circuits MP[1,j] to MP[m,j] is held. The first data w1 is stored in the holding section HCr of the circuit MCr and the holding section HCr of the circuit MCr. (k-1) j (k) Or even w m ( k-1) j (k) As an example, the potential according to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) For each of the above, if it takes a positive value In the hold section HC, a value corresponding to the positive value is input, and in the hold section HCr, a value corresponding to zero is input. On the other hand, the first data w1 (k-1)j (k) Or even w m (k-1) j (k ) If each of the values ​​is negative, the hold part HC should be filled with a value equivalent to zero. A value corresponding to the absolute value of the negative value is input to the holding unit HCr.

[0176] Next, the wirings X1L[1] to X1L[m] and the wiring X2L[1 ] to the wiring X2L[m], (k-1) ~z m (k-1) of As a specific example, the second data is supplied to the wiring X1L[i] and the wiring X2L[i]. z1 (k-1) The wiring X1L[i] and the wiring X2L[i] are shown in FIG. This corresponds to the wiring XLS[i] of the arithmetic circuit 110.

[0177] The second data z1 input to each of the circuits MP[1,j] to MP[m,j] ( k-1) ~z m (k-1) According to the above, the circuits MP[1,j] to MP[m,j] are included in the The conduction state between the circuit MC and the circuit MCr and the wiring OL[j] and the circuit OLB[j] As a specific example, the circuit MP[i,j] is i (k-1) To In response, "the circuit MC and the wiring OL[j] are electrically connected, and the circuit MCr and the wiring OLB[j ] is connected to the circuit MC and the wiring OLB[j] is connected to the circuit MC. "Circuit MCr and wiring OL[j] are conductive" and "Circuit MC and circuit MCr are conductive." Either "it is non-conductive to wiring OL[j], OLB[j]" or "it is non-conductive to wiring OL[j], OLB[j]". As an example, the second data z1 (k-1) If the value is positive, then wire X1L In [1], the circuit MC and the wiring OL[j] are in a conductive state, and the circuit MCr and the wiring Input a value that allows the line OLB[j] to be in a conductive state. Then, input the value of the line X2L [1] In the case where the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit MCr A value that allows the second data line to be in a non-conductive state is input. Data z1 (k-1) When the value is negative, the wiring X1L[1] is connected to the circuit MC and the wiring OLB[j] are in a conductive state, and the circuit MCr and the wiring OL[j] are in a conductive state. Then, input a value that allows the circuit MC and the wiring OL[j] are in a non-conductive state, and the circuit MCr and the wiring OLB[j] are in a non-conductive state. The second data z1 is input as a value that allows the connection between the first and second data z1 to be in a non-conductive state. (k-1) To When the value of zero is taken, the wiring X1L[1] has a circuit MC and a wiring OLB[j]. and the circuit MCr and the wiring OL[j] are in a non-conductive state. Then, for the wiring X2L[1], input the value that can be used to connect the circuit MC and the wiring OL[j ] is in a non-conducting state, and the circuit MCr and the wiring OLB[j] are in a non-conducting state. Enter the value that can be.

[0178] The second data z input to the circuit MP[i,j] i (k-1) Depending on the circuit MP[i, [j], a circuit MC and a circuit MCr, wiring OL[j] and a circuit OLB[j], By determining the conductive state or non-conductive state between the circuit MC and the circuit MCr, Current is input and output between the wiring OL[j] and the wiring OLB[j]. The amount of flow is the first data w set in the circuit MP[i,j]. i (k-1) j (k) and / or is the second data z i (k-1) It depends on.

[0179] For example, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MCr. Let I[i,j] be the current flowing through the wiring OLB[j] to the circuit MC or the circuit MCr. The current flowing through the B [i,j]. Then, the current flows from the circuit ACTF[j] to the wiring OL[j]. The current flowing through the out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] I Bout [j], then I out [j] and I Bout [j] can be expressed by the following formula: This can be done.

[0180]

number

[0181] In the circuit MP[i,j], for example, the first data w i (k-1) j (k) "+ 1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1). The first data w i (k-1) j (k) When is "-1", the circuit MC is I(-1 ) and the circuit MCr outputs I(+1), and the first data w i (k-1) j (k) When is "0", the circuit MC emits I(-1) and the circuit MCr emits I(-1). shall be discharged.

[0182] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) When is “+1”, The circuit MC and wiring OL[j] are connected, and the circuit MCr and wiring OLB[j] are connected. Conduction occurs, and there is no continuity between the circuit MC and the wiring OLB[j], and there is no continuity between the circuit MCr and the wiring OL [j] is in a non-conductive state, and the second data z i (k-1) is "-1" When this happens, "there is continuity between the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j ] is conductive, and the circuit MC and the wiring OL[j] are non-conductive, and the circuit MCr and The second data z i (k-1) "0 "When "circuit MC and wiring OL[j], and circuit MC and wiring OLB[j] There is no continuity between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OL[j] and B[j] is non-conductive, and the circuit MCr and the wiring OL[j] and the circuit MC The state between r and OLB[j] is assumed to be "non-conductive."

[0183] At this time, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MC The current I[i,j] flowing through r and the current I[i,j] flowing through wiring OLB[j] to circuit MC or circuit MCr The current I B[i,j] is as shown in the table below. In some cases, I(- The circuit MP[i,j] may be configured so that the current amount of 1) is 0. i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] flows from the circuit MC or the circuit MCr to the wiring OLB[j] It may be a current.

[0184] [Table 1]

[0185] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [ j] and I Bout [j] is input to the circuit ACTF[j]. , Circuit ACTF[j] is, for example, I out [j] and I Bout [j] Comparison For example, the circuit ACTF[j] may select a neuron according to the result of the comparison. N j (k) The signal z sent to the (k+1)th layer neuron j (k) Output.

[0186] As an example, the arithmetic circuit 110 of FIG. j (k) is entered into Neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~ z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1)j (k) And, It is possible to perform a multiplication and accumulation operation and to calculate an activation function using the result of the multiplication and accumulation operation. In the array part ALP of the arithmetic circuit of FIG. 8, the circuits MP are provided in n columns, so that the arithmetic circuit of FIG. In other words, the arithmetic circuit 110 in FIG. -Lon N1 (k) Neuron N n (k) and the multiplication and accumulation in each of the The activation function can be calculated using the result of the calculation at the same time.

[0187] <<Examples of changes to circuits included in arithmetic circuits>> The array portion ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit Some or all of the transistors included in each of the MP, etc., are, for example, For example, it is desirable to have a low off-state current. For example, a transistor like this can be used to hold the charge stored in a capacitor. The transistor having the above-mentioned structure is preferably an OS transistor. When an OS transistor is used as the transistor, the OS transistor may be the transistor described in the third embodiment. However, in one embodiment of the present invention, Not limited to.

[0188] In addition, the array portion ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP The transistors included in the above are, in addition to OS transistors, for example, channel-type As a transistor containing silicon in the composition region (hereinafter referred to as a Si transistor), As the silicon, for example, single crystal silicon or hydrogenated amorphous silicon can be used. The OS transistor may be made of, for example, microcrystalline silicon or polycrystalline silicon. For example, transistors other than Si transistors include those using semiconductors such as Ge. Layered transistors, ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. Transistors with compound semiconductors as active layers, transistors with carbon nanotubes as active layers A transistor having an organic semiconductor as an active layer, or the like can be used.

[0189] Note that the metal oxide semiconductor layer of the OS transistor is preferably a metal oxide containing indium. In oxides containing zinc (e.g., In oxide), However, it is difficult to fabricate p-type semiconductors due to the mobility and reliability issues. Therefore, the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 are n circuits included in LP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit MP, etc. An OS transistor is used as a p-channel transistor. A configuration in which a Si transistor is used may be used.

[0190] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0191] (Embodiment 2) In this embodiment, a specific configuration example of the circuit MP described in the first embodiment will be described. do.

[0192] In the first embodiment, the reference numerals of the circuits MP are denoted by [1,1 ], [i,j], [m,n], etc. are added, but in this embodiment, unless otherwise specified, In the symbols of the paths MP, notations such as [1,1], [i,j], and [m,n] are omitted.

[0193] <Configuration example 1> First, an example of a circuit configuration that can be applied to the circuit MP of FIG. 5A will be described. The circuit MP is an example of the configuration of the circuit MP of FIG. 5A, and the circuit included in the circuit MP of FIG. 9A The circuit MC includes, for example, transistors M1 to M4, a capacitance element C1, For example, the holding unit HC is formed by the transistor M1 and the capacitance element C1. It is composed.

[0194] The transistors M1 to M4 shown in FIG. The transistor is an n-channel type with a multi-gate structure that has gates on the top and bottom of the panel. Each of the transistors M1 to M4 has a first gate and a second gate. However, in this specification and the like, for the sake of convenience, the first gate is referred to as a gate (front gate) as an example. The first gate is sometimes written as the first gate. The second gate is sometimes written as the back gate to distinguish it from the first gate. However, the first gate and the second gate can be interchanged. In the above, the term "gate" is replaced with the term "backgate." Similarly, the term "backgate" can be interchanged with the term "gate." As a specific example, the gate is electrically connected to the first wiring, The back gate is electrically connected to the second wiring. The gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring. can be substituted as a configuration.

[0195] In addition, the semiconductor device according to one embodiment of the present invention does not depend on the connection structure of the back gate of a transistor. In each of the transistors M1 to M4 shown in FIG. Although a back gate is illustrated, and the connection configuration of the back gate is not illustrated, The electrical connection destination of the back gate can be determined at the design stage. In a transistor having a gate, in order to increase the on-current of the transistor, The gate and the back gate may be electrically connected. In each of the transistors M1 to M4, the gate and the back gate are electrically connected to each other. For example, in a transistor having a back gate, the transistor In order to change the threshold voltage of the transistor or to reduce the off-state current of the transistor, In order to achieve this, wiring electrically connected to an external circuit or the like is provided, and the external circuit or the like is used to A potential may be applied to the back gate of the transistor. rather, it may be a transistor described elsewhere in the specification or illustrated in another drawing. The same is true for the transistors.

[0196] In addition, the semiconductor device according to one embodiment of the present invention may include a transistor structure For example, the transistors M1 to M4 shown in FIG. As shown in FIG. 9C, the transistors M1r to M4r do not have a back gate. In other words, a transistor having a single gate structure may be used. Some of the transistors have a back gate, and some of the transistors have a back gate. The circuit may be configured without a lock gate. as well as transistors described elsewhere in the specification or illustrated in other drawings. The same is true for the transistors that are connected.

[0197] In this specification and the like, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples of such transistors include transistors having single crystal silicon, or transistors having amorphous silicon or polycrystalline silicon. Amorphous silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) For example, a transistor having a non-single crystal semiconductor film, such as a single crystal semiconductor film, can be used. Alternatively, thin-film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, they are Since it can be manufactured at a very low temperature, it is possible to reduce manufacturing costs and to increase the size of manufacturing equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, the manufacturing cost can be reduced. Therefore, a substrate having low heat resistance can be used. Alternatively, a display element can be manufactured using a transistor on a light-transmitting substrate. The light transmission can be controlled. Also, the transistor is thin, so the A part of the film that forms the photodiode can transmit light. This improves the aperture ratio. It is possible.

[0198] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having a Zn-Zn-O or the like can be used. These compound semiconductors or thin-film transistors made by thinning these oxide semiconductors These can be used to lower the manufacturing temperature, for example, in a trans at room temperature. As a result, it is possible to manufacture a transistor on a substrate with low heat resistance, such as a plastic substrate. The transistors can be formed directly on the substrate or film substrate. Compound semiconductors or oxide semiconductors are not only used for the channel portion of transistors, but also for For example, these compound semiconductors or oxide semiconductors can be used for other purposes. It can be used as a wiring, a resistor element, a pixel electrode, a light-transmitting electrode, or the like. These can be deposited or formed simultaneously with the transistors, which reduces costs.

[0199] An example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, low vacuum, or can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it is possible to manufacture without using resist, which reduces material costs and the number of processes. Or, since it is possible to apply the film only to the necessary parts, after forming the film on the entire surface, This method wastes less material and is less costly than the conventional method of etching.

[0200] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. This allows transistors to be mounted on a flexible substrate. Transistors with organic semiconductors and carbon nanotubes can be formed. The device using the method can be made shock resistant.

[0201] Note that transistors having various other structures can also be used. For example, transistors include MOS transistors, junction transistors, bipolar transistors, and A MOS transistor can be used. By using this, the size of the transistor can be reduced. It is possible to mount a bipolar transistor as a transistor. This allows a large current to flow, making it possible to operate the circuit at high speed. It is also possible to combine MOS transistors and bipolar transistors on a single substrate. This can achieve low power consumption, small size, high speed operation, etc. can.

[0202] An example of a transistor is a structure in which gate electrodes are arranged above and below an active layer. The above-mentioned transistor can be applied to a structure in which gate electrodes are arranged above and below the active layer. This results in a circuit configuration in which multiple transistors are connected in parallel. Since the channel forming region is increased, the current value can be increased. A structure in which gate electrodes are arranged above and below makes it easier for a depletion layer to form. , the S value can be improved.

[0203] An example of a transistor is a structure in which a gate electrode is disposed on an active layer. A structure in which a gate electrode is placed under an active layer, a positive staggered structure, a reverse staggered structure, a channel A structure in which the region is divided into multiple regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series Alternatively, a transistor having a structure such as a pre-transistor may be used. FIN type, TRI-GATE type, top gate type, bottom gate type, double gate type (gates are placed above and below the channel), etc. A variety of configurations can be used.

[0204] An example of a transistor is a transistor having a source electrode and a drain electrode in the active layer (or a part of it). A transistor with an overlapping active layer (or By making the structure such that the source electrode and drain electrode overlap with the active layer, This can prevent the operation from becoming unstable due to accumulation of electric charges.

[0205] As an example of a transistor, a structure in which an LDD region is provided can be applied. By providing a region, the off-state current can be reduced or the withstand voltage of the transistor can be improved (improved reliability). Alternatively, by providing an LDD region, it is possible to reduce the Even if the voltage between the drain and source is changed, the drain current does not change much and the slope is A flat voltage-current characteristic can be obtained.

[0206] For example, in this specification, a transistor can be formed using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, sapphire glass substrate, metal substrate, stainless steel substrate, stainless Substrate with less steel foil, tungsten substrate, tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, base films, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Glass, soda lime glass, etc. Flexible substrates, laminated films, base film Examples of films include the following: Polyethylene naphthalate (PET), Polyethersulfone (PES) ), and polytetrafluoroethylene (PTFE). An example of the material is a synthetic resin such as acrylic. Another example is polypropylene. Examples include polyethylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and the like. In particular, transistors using semiconductor substrates, single crystal substrates, or SOI substrates are By manufacturing the stator, there is little variation in characteristics, size, or shape, and the current capacity is This allows the manufacture of transistors with high power and small size. By configuring a circuit using a capacitor, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit. Cut.

[0207] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic material such as a tungsten film and a silicon oxide film. The structure may be a laminated structure of films or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0208] That is, one substrate is used to form a transistor, and then another substrate is used to form the transistor. The transistor may be transposed and placed on another substrate. As an example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan boards, aramid film boards, polyimide film boards, stone boards, wood boards, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of transistors with low power consumption, manufacturing of devices that are not easily damaged, heat resistance It is possible to provide a thinner, lighter, or thinner device.

[0209] All circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate such as a silicon substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. This allows for cost reduction by reducing the number of components, and for the reduction in the number of connections to circuit components. This can improve reliability.

[0210] It is possible that all of the circuits required to realize a given function are not formed on the same substrate. In other words, part of the circuitry required to realize a given function can be formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a given function can be implemented using a gate. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. It is possible to form a semiconductor device on a substrate (or SOI substrate) and realize a desired function. The single crystal substrate (also called an IC chip) on which another part of the circuitry required for the (Chip On Glass) connects to the glass substrate and attaches the I Alternatively, the IC chip can be mounted on a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology, or a printed circuit board, etc. In this way, part of the circuit is formed on the same substrate as the pixel section. This reduces the number of components, resulting in cost savings, and the number of connection points with the circuit components. The number of components can be reduced to improve reliability. Also, circuits with high drive frequencies often consume a lot of power. Therefore, such a circuit is formed on a substrate (such as a single crystal substrate) separate from the pixel section, and By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0211] In the circuit MP of FIG. 9A, a first terminal of the transistor M1 is electrically connected to the line IL. The second terminal of the transistor M1 is connected to the first terminal of the capacitance element C1 and the transistor M2. The gate of the transistor M1 is electrically connected to the wiring WL. The first terminal of the transistor M2 is connected to the second terminal of the capacitance element C1 and the wiring VL The second terminal of the transistor M2 is electrically connected to the first terminal of the transistor M3. The first terminal of the transistor M3 is electrically connected to the first terminal of the transistor M4. The second terminal of the transistor M3 is electrically connected to the wiring OL. The second terminal of the transistor M4 is electrically connected to the wiring OLB. The gate of the transistor M4 is electrically connected to the wiring X2L. As shown, the second terminal of the capacitance element C1 is electrically connected to another wiring VLm, not to the wiring VL. Similarly, the second terminal of the capacitance element C1r may be connected to the line VLr. It should be noted that the wiring VLmr may be electrically connected to another wiring VLmr. In the circuit diagram of the drawing, the second terminal of the capacitance element C1 is not connected to the wiring VL but to another wiring VL m. In FIG. 9B, for example, VL and the wiring VLr are regarded as one and the same wiring, and the wiring VLm and the wiring VLmr are regarded as one and the same wiring. Alternatively, it may be a single wiring (not shown).

[0212] In addition, in the holding unit HC shown in FIG. 9A, the second terminal of the transistor M1 and the capacitance element C The electrical connection point between the first terminal of the transistor M1 and the gate of the transistor M2 is called a node nd1. do.

[0213] As described in the first embodiment, the holding unit HC holds, for example, The potential is stored in the storage unit HC included in the circuit MC of FIG. When the transistor M1 is turned on, the potential is input from the wiring IL. , by writing to the capacitive element C1 and then turning off the transistor M1. This allows the potential of the node nd1 to be held as a potential corresponding to the first data. can.

[0214] In addition, since the transistor M1 holds the potential of the node nd1 for a long time, the off-state current is small. It is preferable to use a transistor that does not have a low off-state current. For example, an OS transistor can be used. A transistor having a gate is applied, and a low level potential is applied to the back gate to obtain a threshold voltage. Alternatively, the voltage may be shifted to the positive side to reduce the off-state current.

[0215] The circuit MCr has a circuit configuration almost identical to that of the circuit MC. The circuit elements that have the same characteristics are marked with the letter "r" to distinguish them from the circuit elements that have the same characteristics as the circuit MC. is.

[0216] The circuit MCr has a different connection configuration from the circuit MC. Transistor M3 The second terminal of the transistor M4r is electrically connected to the wiring OLB instead of the wiring OL. The second terminal of the transistor M is electrically connected to the wiring OL, not to the wiring OLB. A first terminal of No. 2 is electrically connected to the wiring VLr.

[0217] In the operation example described later, in order to simply explain the current flowing in and out of the circuit MP, The two ends of the wiring OL shown in 9A are the nodes ina and outa, and the two ends of the wiring OLB are Let node inb and node outb.

[0218] The wiring VL functions as a wiring for supplying a constant voltage, for example. The transistor M2 or the transistor M2r is an n-channel transistor. In this case, for example, the low-level potential VSS, the ground potential, and other low-level potentials The wiring VLr is a wiring for supplying a constant voltage, similar to the wiring VL. The constant voltage can be VSS, which is a low-level potential, ground potential, etc. In this case, the circuits ACT of the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 can be 3A to 3E, 4A to 4D, and 4F as circuits F[1] to ACTF[n]. If applied, it is electrically connected to the circuits ACTF[1] through ACTF[n]. The constant voltage provided by the wiring VAL is a higher potential than the potential provided by the wiring VL and the wiring VLr. , for example, VDD.

[0219] In addition, the constant voltage supplied by the line VLr may be different from the constant voltage supplied by the line VL. For example, when the constant voltages applied by the wiring VL and the wiring VLr are substantially equal, As shown in the circuit MP of FIG. 10A, the wiring VLr can be the same wiring as the wiring VL. .

[0220] The configuration of the circuit MP in FIG. 9A can be changed depending on the situation. For example, As shown in FIG. 10B, the transistor M2, the transistor M2r, and the transistor M1 of the circuit MP of FIG. Transistor M3, transistor M3r, transistor M4, and transistor M4r, The transistors M2p, M2pr, and M2p are p-channel transistors. The transistors M3p, M3pr, M4p, and M4pr are In particular, the transistors M2 and M2r may be replaced with p-channel transistors. When replacing it with a resistor, the constant voltage given by the wiring VL is set to VDD, which is the high-level potential. In addition to this case, the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 are preferably 3A to 3E, 4A to 4E, and 4F. D, when FIG. 4F is applied, the circuits ACTF[1] to ACTF[n] are electrically The constant voltage provided by the connected wiring VAL is preferably the ground potential or VSS. In this way, when the potential of the wiring is changed, the direction of the current flow is also changed. do.

[0221] Similarly, the transistor M1 is replaced with a p-channel transistor. Also, in FIG. 10B, the transistor M2 and the transistor M2 r, transistor M3, transistor M3r, transistor M4, and transistor M4r The transistors M2p and M2pr are p-channel transistors, respectively. , transistor M3p, transistor M3pr, transistor M4p, transistor M4 pr, but the transistors M2, M2r, and M3 of the circuit MP in FIG. A transistor M3, a transistor M3r, a transistor M4, and a transistor M4r are selected from the group consisting of One or more of the transistors may be replaced with a p-channel transistor.

[0222] Also, for example, as shown in FIG. 11A, the transistors M3 and M3r in the circuit MP in FIG. , transistor M4, and transistor M4r are connected to analog switches A3 and A4, respectively. The switch A4 may be replaced with an analog switch A3r and an analog switch A4r. In addition, in FIG. 11A, analog switch A3, analog switch A4, analog switch Wires X1LB and X2LB are also shown to operate analog switch A3r and analog switch A4r. The wire X1LB is electrically connected to analog switch A3 and analog switch A3r. The wire X2LB is electrically connected to the analog switch A4 and the analog switch A4r. The inverted signal of the signal input to the wire X1L is input to the wire X1LB. An inverted signal of the signal input to the line X2L is input to the line X2LB. As shown in FIG. 1B, the wiring X1L and the wiring X2L are designated as wiring XL, and the wiring X1LB and the wiring X2L are designated as wiring XL. B may be combined into a wiring XLB. Analog switch A4, analog switch A3r, and analog switch A4r are n-channel Alternatively, a CMOS configuration using n-channel transistors and p-channel transistors may be used.

[0223] Also, for example, as shown in FIG. 12A, the transistor M4 of the circuit MP of FIG. The transistors M4p and M4r are p-channel transistors, respectively. In the circuit MP of FIG. 12A, the transistor M3 may be replaced by the transistor M4pr. The gate is electrically connected to the gate of the transistor M4p and the wiring XL. L corresponds to two wirings X1L and X2L in FIG. 9A combined into one. The polarities of the transistors M3 and M4p are opposite to each other. The gates of the transistors M3 and M4p are electrically connected to the wiring XL. Therefore, by applying a predetermined potential to the wiring XL, the transistors M3 and One of the transistors M4p is turned on, and the other of the transistors M3 and M4p is turned on. It can be turned off.

[0224] 12B, for example, a transistor M2m, a transistor The first transistor M2mr is added, and the first transistor M4 and the first transistor M4r are added. The electrical connection destination of the terminal may be changed. The first terminal of 2m is connected to the second terminal of the capacitance element C1, the first terminal of the transistor M2, and the wiring V L, and the second terminal of the transistor M2m is electrically connected to the first terminal of the transistor M4. In the circuit MP of FIG. 9A, the second terminal of the transistor M2 is electrically connected to the The terminal was electrically connected to the first terminal of transistor M4, but the circuit MP In the example, the second terminal of the transistor M2 is electrically connected to the first terminal of the transistor M4. In the circuit MP shown in FIG. 12B, the currents flowing through the transistors M3 and M4 are This is determined by the gate potentials of the transistors M2 and M2m. For example, the size of the transistor M2 and the transistor M2m, e.g., the channel length or It is preferable that the channel widths are equal to each other. In addition, the current flowing through transistors M3 and M4 can be reduced. It may be possible to align the currents that are sent.

[0225] <<Example of operation>> Next, an example of the operation of the circuit MP shown in FIG. 9A will be described.

[0226] 13A to 13C, 14A to 14C, and 15A to 15C show the circuit MP 1 is a timing chart showing an example of operation of the wiring IL, the wiring ILB, and the wiring WL. , the fluctuations in the potentials of the wiring X1L, the wiring X2L, the node nd1, and the node nd1r are shown. In addition, as shown in Figs. 13A to 13C, 14A to 14C, and 15A to 15C, The high indicates a high level potential, and the low indicates a low level potential. The amount of current output to node outa (or from node outa to wiring OL) is I OL Also, from wiring OLB to node outb (or from node outb to wiring The amount of current output to the OLB is I OLB As shown in Figs. 13A to 13C and 14A In the timing charts shown in FIGS. 14C to 15C, the amount of current I OL , I O LB The change in is also shown.

[0227] In this operation example, the constant voltage provided by the wiring VL and the wiring VLr is VSS (low level potential). In this case, current flows from the wiring VAL through the wiring OL to the wiring VL. Similarly, a current flows from the wiring VAL through the wiring OLB to the wiring VLr. become.

[0228] In this specification and the like, the terms "low level potential" and "high level potential" are used in particular It does not mean a fixed potential, but rather the specific potential may be different for different wirings. For example, the low level potential and the high level potential held at the node nd1 and the node nd1r are These are potentials different from the low-level potential and high-level potential applied to the wiring X1L and wiring X2L. may be also possible.

[0229] Before describing the operation example, the weighting coefficients held by the circuit MP are defined as follows. A high-level potential is held at node nd1 of C, and a low-level potential is held at node nd1r of holding unit HCr. When the weighting factor is set to +1, the MP circuit holds the weighting factor. A low level potential is stored at the node nd1 of the HC, and a high level potential is stored at the node nd1r of the storage unit HCr. When the weighting factor is held, the MP circuit is assumed to hold "-1". A low level potential is applied to the node nd1 of the holding unit HC, and a low level potential is applied to the node nd1r of the holding unit HCr. When this is held, the circuit MP is assumed to hold a weighting factor of "0." The high level potential held at the nodes nd1 and nd1r may be, for example, VDD or The potential can be set to be slightly lower than VDD, and the potentials at the nodes nd1 and nd1r can be maintained. The low-level potential to be maintained may be, for example, VSS. It is also possible to use analog values. In that case, for example, a “positive analog” value is used as the weighting coefficient. In the case of "value", a high-level analog potential is applied to the node nd1 of the holding unit HC, and A low-level potential is held at node nd1r. The weighting coefficient is set to "negative analog value". In this case, for example, the node nd1 of the holding unit HC is at a low level potential, and the node n A high-level analog potential is held in d1r. When the weighting coefficient is "0", For example, a low level potential is applied to the node nd1 of the holding unit HC, and a low level potential is applied to the node nd1r of the holding unit HCr. The level potential is maintained.

[0230] In addition, the neuron signal (calculated value) input to the circuit MP is, for example, as follows: When a high-level potential is applied to the wiring X1L and a low-level potential is applied to the wiring X2L, In the circuit MP, a neuron signal of “+1” is input. When a high-level potential is applied to the wire X2L, the circuit MP has a neuron The signal "-1" is input to the wire X1L and the wire X2L. When the Bell potential is applied, the MP circuit receives a "0" as a neuron signal. It is assumed that.

[0231] In this specification and the like, the transistor M2 and the transistor M2r are In the case where there is no transistor, the transistor will eventually operate in the saturation region when in the on state. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are , including the case where the device is appropriately biased to a voltage in the range in which it operates in the saturation region. However, one embodiment of the present invention is not limited to this. In order to achieve this, the transistors M2 and M2r may operate in the linear region. In the case of using analog values, the weighting coefficients are determined by, for example, the transistors M2 and M2 r may operate in a linear region and in a saturation region at the same time.

[0232] In this specification, the transistors M1, M3, and M 4. Transistor M1r, transistor M3r, transistor M4r, unless otherwise specified In the case where the on-state is not the case, the on-state includes the case where the device finally operates in the linear region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors are as follows: This includes the case where the device is properly biased to a voltage within the range in which it operates in its linear region.

[0233] Below, for each combination of the weight coefficients and the neuron's signals, An example of the operation of the circuit MP will now be described.

[0234] [Condition 1] First, as an example, a neuron whose weight coefficient w is "0" and is input to the circuit MP Consider the case where the signal (calculated value) of the circuit M is “+1”. 1 is a timing chart of P.

[0235] Between time T1 and time T2, the wiring IL and the wiring ILB each have a holding The potential of the node nd1 of the holding unit HCr is initialized by Initialization potential V ini In FIG. 13A, V ini is a low level potential The potential is shown as higher than the high-level potential and lower than the high-level potential, but V ini is the low level potential Alternatively, the potential may be set to be lower than the high-level potential or higher than the high-level potential. i ni may be set to the same potential as the low level potential or the high level potential. In addition, the initialization potential V ini are different from each other Note that the wirings IL and ILB may be supplied with an initialization potential V ini of In other words, there is no need to provide a period between time T1 and time T2. .

[0236] In addition, a low-level potential is input to the wiring WL between time T1 and time T2. Therefore, the transistor M1 and the transistor M1r are both in an off state. It is.

[0237] In addition, between time T1 and time T2, The potentials of the nodes nd1 and nd The potential of each of 1r is higher than the low level potential, V ini The potential is set to be lower than .

[0238] A low-level potential is input to the wiring X1L and the wiring X2L. , transistor M3, transistor M4, transistor M3r, and transistor M4r are each in the off state.

[0239] Next, between time T2 and time T3, a high-level potential is input to the wiring WL. As a result, the transistors M1 and M1r are turned on. , the line IL and the node nd1 are in a conductive state, and the line ILB and the node nd1r are in a conductive state. Therefore, the potentials of the nodes nd1 and nd1r are V ini The potentials of the nodes nd1 and nd1r are initialized to the initial potential V ini So. In other words, there is no need to provide a period from time T2 to time T3.

[0240] Between time T3 and time T4, a low level is applied to each of the wiring IL and the wiring ILB. A bell potential is applied and a weighting coefficient w is input as “0”. Since the high-level potential continues to be input and the weighting coefficient w is set to "0", Therefore, the transistors M1 and M1r are in the on state. The potentials of the node nd1 and the node nd1r are both at a low level potential.

[0241] Between time T4 and time T5, a low-level potential is input to the line WL. As a result, the transistors M1 and M1r are turned off, and the capacitance element The capacitance elements C1 and C1r of the nodes nd1 and nd1r are The respective potentials are maintained.

[0242] The weighting factor of the circuit MP is set to "0" by the operation from time T1 to time T5. can be.

[0243] By the above operations, the gates of the transistors M2 and M2r The potentials of the transistors M2 and M2r are at a low level. Since the potential of the first terminal of the transistor M1 is VSS, the potential of the transistors M2 and M2r is Each of them is in the off state.

[0244] Between time T5 and time T6, for example, the wiring IL and the wiring ILB are initialized. Potential V ini This is not a necessary operation, so wiring I L and wiring ILB are initialized to potential V ini That is, from time T5 It is not necessary to provide a period until time T6. In this case, different potentials may be input.

[0245] After time T6, the wire X is used as the input of the neuron signal “+1” to the circuit MP. A high-level potential is input to the wiring X1L, and a low-level potential is input to the wiring X2L. The transistors M3 and M3r are turned on, and the transistors M4 and The transistors M4r and M4r are turned off. Conduction is established between the wiring OL, and conduction is established between the circuit MCr and the wiring OLB.

[0246] At this time, in the circuit MC, the transistor M2 is in an off state, so that the wiring O No current flows from L to the wiring VL. In other words, the output from node outa of wiring OL The current I OL does not change before and after time T6. Similarly, in the circuit MCr, Since the transistor M2r is in the off state, a current flows from the wiring OLB to the wiring VLr. In other words, the current I output from node outb of wiring OLB OLB Also, time There is no change before and after T6.

[0247] By the way, this condition is that the weight coefficient is set to "0" and the neuron signal input to the circuit MP is Since we set the value of 1 to "+1", by using equation (1.1), the product of the weight coefficient and the neuron signal is The result of the product of the weight coefficient and the neuron signal being "0" is that the circuit MP In operation, from time T6 onwards, the current I OL and current I OLB If each of these does not change, Corresponds to the case.

[0248] Once the weighting coefficient w is input, the value is not updated and only the calculated value is changed. In this case, the weighting coefficient w does not need to be updated. Since the weight coefficient w is updated less frequently, power consumption can be reduced. In order to achieve this, it is necessary to hold the weight coefficient w for a long period of time. By using a capacitor, it is possible to maintain the weighting factor w for a long period of time by taking advantage of the low off-current. It becomes.

[0249] [Condition 2] Next, as an example, a neuron whose weight coefficient w is "+1" and is input to the circuit MP Consider the case where the signal (calculated value) of the circuit M is “+1”. 1 is a timing chart of P.

[0250] For the operation from time T1 to time T3, condition 1: from time T1 to time T3 Since the operation is the same as that during the period from time T1 to time T3 in Condition 1, refer to the explanation of the operation during the period from time T1 to time T3 in Condition 1. To pour drinks.

[0251] Between time T3 and time T4, the line IL is at a high level potential and the line ILB is at a low level potential. A bell potential is applied and a weighting coefficient w is input as “1”. Since the high-level potential continues to be input and the weighting coefficient w is set to "1", Therefore, the transistor M1 and the transistor M1r are in the on state. The potential of the node nd1 becomes a high level potential, and the potential of the node nd1r becomes a low level potential.

[0252] Between time T4 and time T5, a low-level potential is input to the line WL. As a result, the transistors M1 and M1r are turned off, The capacitance element C1 and the capacitance element C1r are connected to the nodes nd1 and nd1r, respectively. The potential of each of the electrodes r is maintained.

[0253] The weighting coefficient of the circuit MP is set to “+1” by the operation from time T1 to time T5. will be done.

[0254] By the above operations, the potential of the gate of transistor M2 is at a high level potential, The potential of the gate of the transistor M2r is at a low level potential, and the transistors M2 and The potential of the first terminal of each of the transistors M2r and M2r is VSS, so the transistor M2 is in the on state. In the on state, the transistor M2r is in the off state.

[0255] Regarding the operation from time T5 to time T6, from time T5 to time T6 under condition 1 Since the operation is the same as that during the period from time T5 to time T6 in Condition 1, please refer to the explanation of the operation during the period from time T5 to time T6 in Condition 1. To pour drinks.

[0256] After time T6, the wire X is used as the input of the neuron signal “+1” to the circuit MP. A high-level potential is input to the wiring X1L, and a low-level potential is input to the wiring X2L. The transistors M3 and M3r are turned on, and the transistors M4 and The transistors M4r and M4r are turned off. Conduction is established between the wiring OL, and conduction is established between the circuit MCr and the wiring OLB.

[0257] At this time, in the circuit MC, the transistor M2 is in an on state, so that the wiring O A current flows from L to the wiring VL. In other words, the current is output from the node outa of the wiring OL. The current I OL increases after time T6 (in FIG. 13B, the current I OL The increase in On the other hand, in the circuit MCr, the transistor M2r is in the off state. Therefore, no current flows from the wiring OLB to the wiring VLr. The current I output from node outb of LB OLB does not change before and after time T6.

[0258] By the way, this condition is that the weight coefficient w is set to "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "+1", the weighting coefficient and the new The product of the weight coefficient and the neuron signal is “+1”. As a result, in the operation of the circuit MP, the current I OL changes, and the current I OLB but This corresponds to the case where there is no change.

[0259] [Condition 3] Next, as an example, a neuron whose weight coefficient w is "-1" and is input to the circuit MP Consider the case where the signal (calculated value) of the circuit M is “+1”. 1 is a timing chart of P.

[0260] For the operation from time T1 to time T3, condition 1: from time T1 to time T3 Since the operation is the same as that during the period from time T1 to time T3 in Condition 1, refer to the explanation of the operation during the period from time T1 to time T3 in Condition 1. To pour drinks.

[0261] Between time T3 and time T4, the line IL is at a low level potential and the line ILB is at a high level potential. A bell potential is applied, and “−1” is input as the weighting coefficient w. Since a high-level potential has been input continuously since before, the transistors M1 and The register M1r is in the ON state. Therefore, "-1" is input as the weighting coefficient w. The potential of the node nd1 becomes a low level potential, and the potential of the node nd1r becomes a high level potential. do.

[0262] Between time T4 and time T5, a low-level potential is input to the line WL. As a result, the transistors M1 and M1r are turned off, The capacitance element C1 and the capacitance element C1r are connected to the nodes nd1 and nd1r, respectively. The potential of each of the electrodes r is maintained.

[0263] The weighting coefficient of the circuit MP is set to "-1" by the operation from time T1 to time T5. will be done.

[0264] By the above operations, the potential of the gate of the transistor M2 is at a low level potential, The potential of the gate of the transistor M2r becomes high level potential, and the potential of the gate of the transistor M2 and the Since the potential of the first terminal of each transistor is VSS, the transistor M2 is in the off state, and the transistor Sta M2r is turned on.

[0265] Regarding the operation from time T5 to time T6, from time T5 to time T6 under condition 1 Since the operation is the same as that during the period from time T5 to time T6 in Condition 1, please refer to the explanation of the operation during the period from time T5 to time T6 in Condition 1. To pour drinks.

[0266] After time T6, the wire X is used as the input of the neuron signal “+1” to the circuit MP. A high-level potential is input to the wiring X1L, and a low-level potential is input to the wiring X2L. The transistors M3 and M3r are turned on, and the transistors M4 and The transistors M4r and M4r are turned off. Conduction is established between the wiring OL, and conduction is established between the circuit MCr and the wiring OLB.

[0267] At this time, in the circuit MC, the transistor M2 is in an off state, so that the wiring O No current flows from L to the wiring VL. In other words, the output from node outa of wiring OL The current I OL does not change before and after time T6. Since the resistor M2r is in the ON state, a current flows from the wiring OLB to the wiring VLr. In other words, the current I output from node outb of wiring OLB OLB At time T6 (In FIG. 13C, the current I OLB The increase in is listed as ΔI.

[0268] By the way, this condition is that the weight coefficient w is set to "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "+1", the weighting coefficient and the new The product of the weight coefficient and the neuron signal is "-1". The result is that in the operation of the circuit MP, the current I OL does not change, and the current I OL B This corresponds to the case where changes.

[0269] [Condition 4] In this condition, for example, the weight coefficient w is set to "0", and the neuron input to the circuit MP Consider the operation of the circuit MP when the signal (operation value) is set to "-1". 13 is a timing chart of the circuit MP in this case.

[0270] Regarding the operation from time T1 to time T6, from time T1 to time T6 under condition 1 Since the operation is the same as that during the period from time T1 to time T6 in Condition 1, please refer to the explanation of the operation during the period from time T1 to time T6 in Condition 1. To pour drinks.

[0271] After time T6, the neuron signal (operation value) “-1” is input to the circuit MP. As a result, a low level potential is input to the wiring X1L and a high level potential is input to the wiring X2L. , transistor M3, and transistor M3r are each turned off, and transistor M4 and the transistor M4r are both turned on. There is a conductive state between the circuit MC and the wiring OLB, and there is a conductive state between the circuit MCr and the wiring OL. become.

[0272] At this time, in the circuit MC, the transistor M2 is in an off state, so that the wiring O No current flows from LB to the wiring VL. In other words, from node outb of wiring OLB Output current I OLB does not change before and after time T6. Similarly, in the circuit MCr Since the transistor M2r is in the off state, No current flows. In other words, the current I OL Also, time There is no change before and after T6.

[0273] By the way, this condition is that the weight coefficient w is set to "0" and the signal of the neuron input to the circuit MP is Since the calculation value is set to "-1", the weighting coefficient and the neuron The product of the weight coefficient and the neuron signal is "0". In the operation of the circuit MP, after time T6, the current I OL and current I OLB Each of This corresponds to the case where there is no change, which coincides with the result of the circuit operation under condition 1.

[0274] [Condition 5] In this condition, for example, the weight coefficient w is set to "+1", and the neuron input to the circuit MP is Consider the operation of the circuit MP when the signal (operation value) of the input is set to "-1". 11 is a timing chart of the circuit MP in the case where

[0275] For the operation from time T1 to time T6, condition 2, from time T1 to time T6 Since the operation is the same as that during the period from time T1 to time T6 in Condition 2, please refer to the explanation of the operation during the period from time T1 to time T6 in Condition 2. To pour drinks.

[0276] After time T6, the neuron signal (operation value) “-1” is input to the circuit MP. As a result, a low level potential is input to the wiring X1L and a high level potential is input to the wiring X2L. , transistor M3, and transistor M3r are each turned off, and transistor M4 and the transistor M4r are both turned on. The circuit MC and wiring OLB are in a conductive state, and the circuit MCr and wiring OL are in a conductive state. become.

[0277] At this time, in the circuit MC, the transistor M2 is in an on state, so that the wiring O Current flows from LB to the wiring VL. In other words, the current flows from the node outb of the wiring OLB. The input current I OLB increases after time T6 (in FIG. 14B, the current IOLB of The amount of increase is indicated as ΔI. On the other hand, in the circuit MCr, the transistor M2r is turned on. Since the line is in the off state, no current flows from the line OL to the line VLr. The current I output from node outa of wiring OL OL does not change before and after time T6.

[0278] By the way, this condition is that the weight coefficient w is set to "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "-1", when using formula (1.1), the weighting coefficient and the new The product of the weight coefficient and the neuron signal is "-1". The result is that in the operation of the circuit MP, the current I OL does not change, and the current I OL B This corresponds to the case where changes, which is consistent with the result of the circuit operation in condition 3.

[0279] [Condition 6] In this condition, for example, the weight coefficient w is set to "-1", and the neuron input to the circuit MP is Consider the operation of the circuit MP when the signal (operation value) of the input is set to "-1". 11 is a timing chart of the circuit MP in the case where

[0280] For the operation from time T1 to time T6, condition 3, from time T1 to time T6 Since the operation is the same as that during the period from time T1 to time T6 in Condition 3, please refer to the explanation of the operation during the period from time T1 to time T6 in Condition 3. To pour drinks.

[0281] After time T6, the neuron signal (operation value) “-1” is input to the circuit MP. As a result, a low level potential is input to the wiring X1L and a high level potential is input to the wiring X2L. , transistor M3, and transistor M3r are each turned off, and transistor M4 and the transistor M4r are both turned on. There is a conductive state between the circuit MC and the wiring OLB, and there is a conductive state between the circuit MCr and the wiring OL. become.

[0282] At this time, in the circuit MC, the transistor M2 is in an off state, so that the wiring O No current flows from LB to the wiring VL. In other words, from node outb of wiring OLB Output current I OLB does not change before and after time T6. On the other hand, in the circuit MCr, Since the transistor M2r is in the on state, a current flows between the wiring OL and the wiring VLr. In other words, the current I output from node outa of wiring OL OL At time T6 (In FIG. 14C, the current I OL The increase in is listed as ΔI.

[0283] By the way, this condition is that the weight coefficient w is set to "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "-1", when using formula (1.1), the weighting coefficient and the new The product of the weight coefficient and the neuron signal is “+1”. The result is that in the operation of the circuit MP, the current I OL changes, and the current I OLB does not change, which is consistent with the result of the circuit operation under condition 2.

[0284] [Condition 7] In this condition, for example, the weighting coefficient w is "0" and the new Consider the operation of the circuit MP under condition 7, where the signal (calculated value) of the RON is “0.” 15A is a timing chart of the circuit MP in this case.

[0285] Regarding the operation from time T1 to time T6, from time T1 to time T6 under condition 1 Since the operation is the same as that during the period from time T1 to time T6 in Condition 1, please refer to the explanation of the operation during the period from time T1 to time T6 in Condition 1. To pour drinks.

[0286] After time T6, the neuron signal (operation value) “0” is input to the circuit MP. A low level potential is input to the wiring X1L, and a low level potential is input to the wiring X2L. The transistors M3, M3r, M4, and M4r are In other words, this operation causes the circuits MC and MCr to In either case, the connection between the wiring OL and the wiring OLB is non-conductive.

[0287] Therefore, in the circuit MC, between the wiring OL and either the wiring VL or the wiring VLr, No current flows. In other words, the current I output from node outb of wiring OLB OLB teeth, There is no change before and after time T6. Similarly, in the circuit MCr, In other words, no current flows from node outa of wiring OL to the other end of wiring VLr. The current I OL Also, there is no change before and after time T6.

[0288] By the way, this condition is that the weight coefficient w is "0" and the signal of the neuron input to the circuit MP is Since the signal (calculated value) is set to "0", when using formula (1.1), the weight coefficient and the neuron The product of the signal is "0". The result of the product of the weight coefficient and the neuron signal being "0" is In the operation of the MP circuit, the current I OL and current IOLB Each of the changes This corresponds to the case where no such condition is set, and coincides with the results of the circuit operation under conditions 1 and 4.

[0289] [Condition 8] In this condition, for example, the weighting coefficient w is "+1" and the nucleus input to the circuit MP is Consider the operation of the circuit MP under condition 8, that is, when the signal (calculated value) of the input terminal is “0”. FIG. 15B is a timing chart of the circuit MP in this case.

[0290] For the operation from time T1 to time T6, condition 2, from time T1 to time T6 Since the operation is the same as that during the period from time T1 to time T6 in Condition 2, please refer to the explanation of the operation during the period from time T1 to time T6 in Condition 2. To pour drinks.

[0291] After time T6, the neuron signal (operation value) “0” is input to the circuit MP. In other words, a low-level potential is input to the wiring X1L, and a low-level potential is input to the wiring X2L. Since the operation after time T6 is the same as that of the circuit MC, the wiring OL, O LB, the circuit MCr is in a non-conducting state. Therefore, from the wiring OL or the wiring OLB, Since no current flows between the wiring VL or VLr, the node of the wiring OL The current I output from the output OL , and the signal output from node outb of the wiring OLB current I OLB do not change before and after time T6.

[0292] By the way, this condition is that the weight coefficient w is set to "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "0", the weighting coefficient and the neuron The product of the weight coefficient and the neuron signal is "0". In the operation of the circuit MP, after time T6, the current I OL and current I OLB Each of This corresponds to the case where there is no change, which is consistent with the results of the circuit operation under conditions 1, 4, and 7. do.

[0293] [Condition 9] In this condition, for example, the weighting coefficient w is "-1" and the nucleus input to the circuit MP is Consider the operation of the circuit MP under condition 9, that is, when the signal (calculated value) of the input terminal is “0”. FIG. 15C is a timing chart of the circuit MP in this case.

[0294] For the operation from time T1 to time T6, condition 3, from time T1 to time T6 Since the operation is the same as that during the period from time T1 to time T6 in Condition 3, please refer to the explanation of the operation during the period from time T1 to time T6 in Condition 3. To pour drinks.

[0295] After time T6, the neuron signal (operation value) “0” is input to the circuit MP. In other words, a low-level potential is input to the wiring X1L, and a low-level potential is input to the wiring X2L. Since this operation is the same as the operation after time T6 in the previous example, the circuit MC is The circuit MCr is in a non-conductive state between the wiring OL and the wiring OLB. Therefore, the line OL or the line OLB is in a non-conductive state. Therefore, no current flows between the wiring VL and the wiring VLr, so the wiring OL Current I output from node outa OL , and the output from node outb of wiring OLB The current I OLB do not change before and after time T6.

[0296] By the way, this condition is that the weight coefficient w is set to "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "0", the weighting coefficient and the neuron The product of the weight coefficient and the neuron signal is "0". In the operation of the circuit MP, after time T6, the current I OL and current I OLB Each of This corresponds to the case where there is no change, which is the result of the circuit operation under conditions 1, 4, 7, and 8. Matches.

[0297] The results of the operation examples under conditions 1 to 9 above are summarized in the table below. The high level potential is described as high, and the low level potential is described as low.

[0298] [Table 2]

[0299] Here, one circuit MC and one circuit MCr are connected to the wiring OL and the wiring OLB. As shown in Figs. 2, 6, 7, and 8, A plurality of circuits MC and a plurality of circuits MCr are connected to the wiring OL and the wiring OLB. In this case, the current output from each circuit MC and circuit MCr is calculated based on Kirchhoff's current law. As a result, the sum is calculated. In the circuits MC and MCr, a multiplication operation is performed, and the multiple circuits MC and MCr are The sum is calculated by adding up the currents. As a result, the multiply-and-accumulate process is performed. This will be the case.

[0300] By the way, in the operation of the circuit MP, the weighting coefficients are limited to two values, "+1" and "-1", By performing calculations with only two neuron signals, "+1" and "-1", the circuit MP It can perform the same operation as an exclusive OR negation circuit (match circuit).

[0301] In addition, in the operation of the circuit MP, the weighting coefficient is limited to only two values, "+1" and "0", and the new By performing calculations with only two values ​​for the signal of the RON, "+1" and "0", the circuit MP is It can perform the same operation as the circuit.

[0302] In this operation example, the circuit MC of the circuit MP, the holding unit HC of the circuit MCr, and the holding unit The potential held in the holding section HCr was set to a high level potential or a low level potential. The holding unit HCr may hold a potential indicating an analog value. For example, In the case of a "positive analog value", a high-level analog potential is applied to the node nd1 of the holding unit HC. A low level potential is held at the node nd1r of the holding unit HCr. In the case of "analog value of" for example, a low level potential is applied to the node nd1 of the holding unit HC, A high-level analog potential is held at the node nd1r of HCr. And the current I O L and current I OLB The magnitude of the current depends on the analog potential. Regarding the holding of potentials indicating analog values ​​in the HC and HCr sections, the circuit MP The present invention is not limited to the above operation example, and may be applied to other circuits MP shown in this specification.

[0303] <Configuration example 2> Next, an example of a circuit configuration that can be applied to the circuit MP shown in FIG. 5C and FIG. 5D will be described. do.

[0304] The circuit MP shown in FIG. 16A is a configuration example of the circuit MP in FIG. 5C, and is the same as the circuit MP in FIG. 9A. The difference from P is that the wiring IL and wiring ILB are combined into one, and the wiring WL in Figure 9A is The point is that it has wiring W1L and wiring W2L.

[0305] In the circuit MP of FIG. 16A, the first terminal of the transistor M1 and the The first terminal is electrically connected to the wiring IL. In addition, the gate of the transistor M1 is The gate of the transistor M1r is electrically connected to the wiring W2L. The circuit MP in FIG. 16A has the same connection configuration as the circuit MP in FIG. 9A. The explanation of the above points will be omitted.

[0306] When setting weighting coefficients in the circuit MP of FIG. 16A, first, By changing the potential supplied to the transistor M1, the transistor M1r is turned on and the transistor M1r is turned off. Then, a potential for holding is supplied from the wiring IL to the holding section HC, and the transistor Then, the potentials supplied to the wirings W1L and W2L are changed. Then, the transistor M1 is turned off and the transistor M1r is turned on. A potential for holding is supplied from the line IL to the holding unit HCr, and the transistor M1r is turned off. In this way, in the case of the circuit MP of FIG. 16A, the wiring IL is connected to the holding unit HC, By sequentially supplying potentials to the holding units HC and HCr, the weighting coefficients corresponding to the weighting coefficients are applied to the holding units HC and HCr. The potential can be maintained.

[0307] The circuit MP shown in FIG. 16B is a configuration example of the circuit MP of FIG. 5D, and is different from the circuit MP of FIG. 9A. The difference with P is that the wiring IL and wiring OL are combined into wiring IOL, and the wiring ILB and wiring OLB are combined into wiring IOL. The point is that these are all consolidated into a wiring IOLB.

[0308] In the circuit MP of FIG. 16B, the first terminal of the transistor M1 is electrically connected to the line IOL. A first terminal of the transistor M1r is electrically connected to the wiring IOLB. In addition, the second terminal of the transistor M3 is electrically connected to the line IOL. The second terminal of M4 is electrically connected to the wiring IOLB, and the second terminal of the transistor M3r is The second terminal of the transistor M4r is electrically connected to the wiring IOL. Note that the circuit MP in FIG. 16B has a similar connection structure to the circuit MP in FIG. 9A. The explanation of the parts that are composed of the above will be omitted.

[0309] In the circuit MP of FIG. 16B, the wiring IOL is electrically connected to the holding part HC, and the holding part HCr is The wiring IOLB is electrically connected to the wiring WL. Since the gates of the two transistors are electrically connected, the holding unit H C, a potential corresponding to the weighting coefficient can be simultaneously written to the holding unit HCr.

[0310] <Configuration example 3> The circuit MP shown in FIG. 17 differs from the circuit MP shown in FIG. 9A in that only the holding portion HC and the holding portion HCr HCs and HCsr.

[0311] The circuit MC included in the circuit MP of FIG. 17 is added to the circuit elements included in the circuit MP of FIG. 9A. Eh, transistor M1s, transistor M2s, transistor M5, transistor M5s , and a capacitance element C1s. The circuit MCr included in the circuit MP of FIG. Since the circuit has the same circuit elements as MC, the transistors M1s and M2 s, transistor M5, transistor M5s, and capacitance element C1s, Transistor M1sr, Transistor M2sr, Transistor M5r, Transistor M5s r, and a capacitive element C1sr.

[0312] In this specification, the transistor M5, the transistor M5s, the transistor Unless otherwise specified, transistors M5r and M5sr are ultimately connected to the line when they are on. This includes the case where the transistors operate in the MOSFET region. The gate voltage, source voltage, and drain voltage are appropriate for the voltage range in which the device operates in the linear region. This includes cases where the information is biased towards

[0313] Next, the configuration of the circuit MP in Fig. 17 will be described. In the circuit MP in Fig. 17, Portions having the same configuration as the circuit MP in FIG. 9A are omitted.

[0314] The gate of the transistor M1 is electrically connected to the wiring W1L. A first terminal of transistor M5 is electrically connected to a second terminal of transistor M2, and a The second terminal is electrically connected to the first terminal of the transistor M3 and the first terminal of the transistor M4. , and the gate of the transistor M5 is electrically connected to the wiring S1L.

[0315] A first terminal of the transistor M1s is electrically connected to the wiring IL. The second terminal of the capacitance element C1s is electrically connected to the first terminal of the capacitance element C1s and the gate of the transistor M2s. The gate of the transistor M1s is electrically connected to the wiring W2L. The first terminal of the transistor M2s is electrically connected to the second terminal of the capacitance element C1s and the wiring VLs. and the second terminal of the transistor M2s is electrically connected to the first terminal of the transistor M5s. The second terminal of the transistor M5s is connected to the first terminal of the transistor M3. The first terminal of the transistor M4 is electrically connected to the gate of the transistor M5s. Electrically connected to S2L.

[0316] In the circuit MP of FIG. 17, the circuit MCr has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is followed by "r."

[0317] The wiring VLs functions as a wiring for supplying a constant voltage, and the constant voltage is a low-level voltage. The potential may be VSS, which is a high potential, a low level potential other than VSS, or a ground potential. The constant voltage may be a high-level potential VDD. The constant voltage supplied by the line VL may be different from or may be the same as the constant voltage supplied by the line VL. When the constant voltages given by VL and the wiring VLs are almost equal, the wiring VLs is the same wiring as the wiring VL. It can be a line.

[0318] The line VLsr functions as a line that supplies a constant voltage, and the constant voltage is a low level The potential may be VSS, a low-level potential other than VSS, or a ground potential. The constant voltage may be a high-level potential VDD. The constant voltage supplied may be different from the constant voltage supplied by the line VLr, or may be the same. If the constant voltages applied by the wiring VLr and the wiring VLsr are almost equal, the wiring VLsr is It can be wired the same as Lr.

[0319] In addition, the constant voltages given by the wiring VL, wiring VLs, wiring VLr, and wiring VLsr are The voltages may be different from each other or may be the same. The constant voltages applied by two or three wires selected from the line VLr and the wiring VLsr are equal to each other. It's okay.

[0320] The wiring S1L turns the transistor M5 and the transistor M5r on or off. The wiring S2L functions as a wiring for supplying a potential to the transistors M5s and This functions as a wiring that supplies a potential to turn on or off the transistor M5sr. It works.

[0321] The circuit MP shown in FIG. 5C and FIG. 5D can be realized by applying the configuration shown in the circuit MP of FIG. Specifically, the circuit MP in FIG. A potential corresponding to the weighting coefficient of the 1st is stored in the holding section HC of the circuit MC and in the holding section HCr of the circuit MCr. , and a potential according to the second weighting coefficient is stored in the holding unit HCs of the circuit MC and the The circuit MP in FIG. The weighting coefficients used in the calculation can be switched by the potential applied from the wiring S2L. For example, the circuits MP[1,j] to MP[m,j] included in the arithmetic circuit 110 The weighting coefficient w1 is assigned to each of the holding parts HC and HCr. (k-1) j (k) Or even w m (k-1 ) j (k) The circuits MP[1,j] to MP Each holding part HCs, HCsr included in [m,j] is weighted by w1 (k-1) h ( k) Or even w m (k-1) h (k) (Here, h is an integer greater than or equal to 1 and not equal to j.) 17. The wirings XLS[1] to XLS[m] (in the circuit MP in FIG. 17) are held at a potential corresponding to the Signal z1 is connected to the wires X1L and X2L. (k-1) ~z m (k-1) Input the electric potential according to At this time, a high-level potential is applied to the wiring S1L to turn on the transistors M5 and The transistor M5r is turned on, and a low-level potential is applied to the wiring S2L, By turning off the transistor M5sr, the circuit MP[1,j] of the arithmetic circuit 110 To circuit MP[m,j], weight coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) and signal z1 (k-1) ~z m (k-1) It is possible to calculate the sum of products and activation functions with In addition, a low-level potential is applied to the wiring S1L to turn on the transistors M5 and M5 r is turned off, and a high-level potential is applied to the wiring S2L, turning on the transistors M5s and By turning on the register M5sr, the circuits MP[1,j] to MP[1,j] of the arithmetic circuit 110 are MP[m,j] is the weighting coefficient w1 (k-1) h (k) Or even wm (k-1) h (k) and signal z1 (k-1) ~z m (k-1) It is possible to perform product-sum and activation function calculations with

[0322] As described above, by applying the circuit MP of FIG. 17 to the arithmetic circuit 110, the weight coefficients are It is possible to hold two weight coefficients, and to switch between them to perform product sum and activation function calculations. The arithmetic circuit 110 constituting the circuit MP in FIG. 17 can be used to, for example, When the number of eigenvalues ​​is greater than n, when performing calculations in a hidden layer other than the kth layer, etc. In the circuit MP of FIG. 17, the holding unit of the circuit MC and the circuit MCr However, depending on the situation, the circuit MC and the circuit MCr may each have three. The above holding portions may be provided.

[0323] <Configuration Example 4> The circuit MP shown in FIG. 18A is a circuit that can be applied to the circuit MP in FIG. 5A, and includes a holding unit HC, and the holding unit HCr are respectively connected to the load circuit LC 9A in that it includes a load circuit LCr.

[0324] In the circuit MC of the circuit MP of FIG. 18A, the first terminal of the load circuit LC is connected to a transistor M A power supply is connected to a second terminal of transistor M1, a first terminal of transistor M3, and a first terminal of transistor M4. A second terminal of the load circuit LC is pneumatically connected to the wiring VL.

[0325] The circuit MCr of the circuit MP in FIG. 18A has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is followed by "r."

[0326] The wiring VL and the wiring VLr function as wirings for supplying a constant voltage VCNS. CNS can be, for example, the ground potential (GND), or the load circuit LC and the load circuit LCr. It can be set to a low potential within the range in which it is always operated.

[0327] The load circuit LC and the load circuit LCr are, for example, the resistance between the first terminal and the second terminal The first and second terminals of the load circuit LC and the load circuit LCr can be changed. By changing the resistance between the first and second terminals of the load circuit LC and the load circuit LCr, The amount of current flowing between the two terminals can be changed.

[0328] In the circuit MP of FIG. 18A, the first terminal and the second terminal of the load circuit LC and the load circuit LCr are A method for changing the resistance between the two terminals will be described. First, the wiring X1L and the wiring X2 A low-level potential is input to each of transistors M3, M3r, and L. Next, a high-level potential is applied to the wiring WL. This input turns on the transistors M1 and M1r, changing the potential of the wiring IL (wiring ILB). By doing so, the resistance value between the first and second terminals of the load circuit LC (load circuit LCr) is For example, the first load circuit LC (load circuit LCr) is set to the wiring IL (wiring ILB). Input a voltage to reset the resistance between the terminal and the second terminal, and then connect the wiring IL (Wire ILB) is the resistor between the first and second terminals of the load circuit LC (load circuit LCr). There are two ways to input a voltage that will make the load circuit LC have the desired value. After setting the resistance between the first and second terminals of the The bell potential is input to turn off the transistors M1 and M1r.

[0329] The load circuits LC and LCr are, for example, resistor transformers as shown in FIG. The load circuit LC and the load circuit LCr can be, for example, For example, as shown in FIG. 18C, a circuit VC including an MTJ element MR can be used. In addition, the load circuit LC and the load circuit LCr may be, for example, a phase change A resistive element containing a phase change material (referred to as a phase change material in this specification) is used in a phase-change memory (PCM) or the like. For convenience, a phase change memory (PCM) can be used.

[0330] In addition, the circuit MP using the load circuit LC and the load circuit LCr is not limited to the configuration shown in FIG. The configuration of the circuit MP in FIG. 18A can be changed depending on the situation. As an example of a modification of the circuit MP, the circuit MP of FIG. 18A is modified by adding wiring IL, wiring ILB, and a transistor The circuit configuration may be such that the transistor M1 and the transistor M1r are not provided. 5D. This is a circuit diagram showing the circuit configuration, which is one of the configuration examples of the circuit MP in FIG. 5D.

[0331] In the circuit MP of Figure 19, setting the resistance value between the first and second terminals of the load circuit LC A high-level potential is input to the wiring X1L and a low-level potential is input to the wiring X2L, and the transistor M 3 is turned on, transistor M4 is turned off, and the line IOL is connected via transistor M3. This can be done by applying a potential to the first terminal of the load circuit LC. A potential is applied from the wiring IOLB to the first terminal of the load circuit LCr through the transistor M3r. Therefore, the first and second terminals of the load circuit LCr can be connected simultaneously to the load circuit LC. The resistance value between the resistor R and the resistor B can also be set.

[0332] In addition, the resistance between the first and second terminals of the load circuit LC is set by connecting a low level A high-level potential is input to the wiring X2L to turn off the transistor M3. The load circuit LC This can also be achieved by applying a potential to the first terminal of the wiring IOL. , a potential can be applied to the first terminal of the load circuit LCr via the transistor M4r. Therefore, the resistance between the first and second terminals of the load circuit LCr must be set at the same time as the load circuit LC. It is also possible to set

[0333] The first terminals of the load circuits LC and LCr shown in FIG. 18A and FIG. The resistance between the terminal and the second terminal may be two values, three values ​​or more, and may further be an analog value. You may do so.

[0334] <Configuration Example 5> The circuit MP shown in FIG. 20A is applicable to the circuit MP in FIG. 5A. Each of the holding units HCr is an inverter loop instead of the capacitance element C1 and the capacitance element C1r. 9A in that it has a circuit configuration as shown in FIG.

[0335] In the circuit MC of the circuit MP of FIG. 20A, the holding unit HC includes an inverter circuit INV1 and The input terminal of the inverter circuit INV1 is connected to an inverter circuit INV2. the output terminal of the inverter circuit INV2, the second terminal of the transistor M1, and the gate of the transistor M2 As in the description of FIG. 9A, the first 2 terminal, the gate of the transistor M2, the input terminal of the inverter circuit INV1, The electrical connection point between the output terminal of the data circuit INV2 and the node nd1 is called the node nd2. The terminal nd1 is not the input terminal of the inverter circuit INV1, but the output terminal of the inverter circuit INV1. It may be connected to a power terminal.

[0336] The circuit MCr of the circuit MP in FIG. 20A has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is followed by "r."

[0337] The holding unit HC included in the circuit MC is an inverter circuit INV1 and an inverter circuit I NV2 and the inverter loop are formed, and the holding unit H Cr is an inverter circuit INV1r and an inverter circuit INV2r. That is, the circuit MP in FIG. 20A includes a holding section HC and a holding section H Each inverter loop of Cr can hold a potential corresponding to a weighting coefficient. can.

[0338] In the circuit MP of FIG. 20A, the inverter circuit INV1 and the inverter circuit INV1r , inverter circuit INV2, inverter circuit INV2r are shown, circuit INV1, inverter circuit INV1r, inverter circuit INV2, inverter circuit IN At least one of V2r is a logic circuit that receives an input signal and outputs an inverted signal of the input signal. The logic circuit may be replaced with a circuit. For example, a NAND circuit, a NOR circuit, XOR circuits, and combinations of these circuits. When replacing the circuit with a NAND circuit, set one of the two input terminals of the NAND circuit to a fixed potential. By inputting a high-level potential, the NAND circuit can function as an inverter circuit. Also, when replacing the inverter circuit with a NOR circuit, the two input terminals of the NOR circuit By inputting a low-level potential as a fixed potential to one of the terminals, the NOR circuit becomes an inverter circuit. Also, if the inverter circuit is replaced with an XOR circuit, By inputting a high-level potential as a fixed potential to one of the two input terminals of the R circuit, an XOR circuit can function as an inverter circuit.

[0339] As described above, the inverter circuit described in this specification and the like is a NAND circuit, a NOR circuit, The logic circuits can be replaced with a logic circuit such as an OR circuit, an XOR circuit, or a combination of these. Therefore, in this specification and the like, the term "inverter circuit" is used interchangeably with "logic circuit." It can be called as follows.

[0340] Also, the circuit MP of FIG. 20A can change its configuration depending on the situation. A modified example of the circuit MP of FIG. 20B is shown in FIG. 20B. The circuit MP of FIG. 20A is The MP circuit MCr is configured by removing the holding unit HCr, and the holding unit HC of the circuit MC is configured by removing the holding unit HCr from the circuit It is electrically connected to the gate of the transistor M2r of MCr.

[0341] In FIG. 20B, the output terminal of the inverter circuit INV1 and the input terminal of the inverter circuit INV2 The electrical connection point between the terminal and is the node nd2. The potential of the node nd2 is input to the output.

[0342] In the circuit MP shown in FIG. 20B, the circuit MCr does not include the holding unit HCr, and the transistor The potential applied to the gate of M2r is held by the holding section HC of the circuit MC. The section HC is an inverter loop consisting of an inverter circuit INV1 and an inverter circuit INV2. Since the node nd1 has a flip-flop configuration, either a high level potential or a low level potential is held at the node nd1. The node nd2 is held at the other of the high level potential or the low level potential.

[0343] In addition, due to the configuration of the inverter loop, the holding unit HC holds the node nd1 and the node nd2. It is not possible to hold the same potential on each of them. Therefore, in the circuit MP of FIG. , nd1, and nd2 are held at the same potential. Specifically, in the above example of operation, the transistor M 2. Since the gates of the transistors M2r cannot be held at a low level, The weighting factor "0" cannot be set for B's circuit MP.

[0344] <Configuration Example 6> The circuit MP shown in FIG. 21A is applicable to the circuit MP in FIG. 5A. Each of the holding units HCr has two transistors and two capacitance elements. 9A.

[0345] In the circuit MC of the circuit MP shown in FIG. 21A, the holding unit HC includes a transistor M1, The first transistor M1 has a first capacitance element M1s, a second capacitance element C2, and a third capacitance element C2s. The first terminal of the transistor M1 is electrically connected to the wiring IL, and the second terminal of the transistor M1 is connected to the capacitance element C2. and a gate of the transistor M6. The gate of the transistor M1s is electrically connected to the wiring WL. IL, and the second terminal of the transistor M1s is electrically connected to the first terminal of the capacitive element C2s. The gate of the transistor M1s is electrically connected to the gate of the transistor M7. , and is electrically connected to the wiring WL. As in the description of FIG. 9A, the transistor M1 an electrical connection between the second terminal of the transistor M6 and the first terminal of the capacitive element C2; The point is called nd1, the second terminal of the transistor M1s, the gate of the transistor M7, The electrical connection point with the first terminal of the capacitance element C2s is referred to as nd1s.

[0346] The second terminal of the capacitance element C2 is electrically connected to the wiring X1L, and the second terminal of the capacitance element C2s is The terminal is electrically connected to the wiring X2L.

[0347] The first terminal of the transistor M6 is electrically connected to the first terminal of the transistor M7 and the wiring VL. The second terminal of the transistor M6 is electrically connected to the wiring OL. A second terminal of the resistor M7 is electrically connected to the wiring OLB.

[0348] The circuit MCr of the circuit MP in FIG. 21A has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is followed by "r."

[0349] The holding unit HC included in the circuit MC holds a potential Specifically, a high-level potential is input to the wiring WL, and the transistor After turning on the transistor M1 and the transistor M1s, a predetermined potential is input to the wiring IL. As a result, the potential is written to the first terminals of the capacitance elements C2 and C2s. After that, a low-level potential is input to the wiring WL, and the transistors M1 and By turning off M1s, the nodes nd1 and nd1s of the holding unit HC are The potential can be written to the holding section HC and held therein. In this case, the potentials of the wirings X1L and X2L are set to, for example, constant potentials. It is preferable, and particularly preferable that the potential is higher than the low-level potential and lower than the high-level potential. For convenience, the constant potential is called the reference potential.

[0350] In the circuit MP of FIG. 21A, the wiring WL is connected to the holding portion HC and the holding portion HCr. Since the holding part HC and the holding part HCr are electrically connected to each other, When writing and holding a potential corresponding to the write coefficient, when the potential of the wiring WL is a high level potential, At the same time, a predetermined potential is written to the holding portion HC and the holding portion HCr, and then the wiring WL The potential is set to a low level, and the transistors M1, M1s, and M1r , and the transistor M1sr may be turned off simultaneously.

[0351] Here, the neuron signals input to the circuit MP are defined as follows: A voltage higher than the reference potential (hereafter referred to as high-level potential) is applied to wire 1L, and the reference potential is applied to wire X2L. When a voltage lower than the low level (hereinafter referred to as the low level potential) is applied to the circuit MP, When a neuron receives a signal of “+1”, the wire X1L is at a low level potential, and the wire X2 When a high-level potential is applied to L, the circuit MP receives a neuron signal of "-1 When " is input and a low-level potential is applied to each of the wiring X1L and the wiring X2L, ,It is assumed that a neuron signal of "0" is input to the circuit MP.

[0352] For example, after the potentials corresponding to the weighting coefficients are held in the holding units HC and HCr, the circuit When inputting a neuron signal of “+1” to MP, a high-level potential is input to the wire X1L. Therefore, the potentials of the nodes nd1 and nd1r are the same as those of the capacitance element C2 and the capacitance element C2. This is due to the capacitive coupling caused by r. This causes the transistor M6 Since the potential of the gates of transistors M6 and M6r becomes high, In addition, a low-level potential is input to the wiring X2L, so that the nodes nd1s, The potentials of the nodes nd1sr and nd2sr are capacitively coupled by the capacitive elements C2s and C2sr. This causes the gates of the transistors M7 and M7r to Since the potential of the port becomes low, the transistor M7 and the transistor M7r are turned off. In other words, when a neuron inputs a signal of “+1” to the circuit MP, the circuit M There is a conductive state between C and wiring OL, and there is a conductive state between circuit MCr and wiring OLB. .

[0353] In addition, for example, after the potentials corresponding to the weighting coefficients are held in the holding units HC and HCr, When inputting “-1” as a neuron signal to the circuit MP, a low-level current is applied to the wire X1L. Since the potential of the node nd1 and the node nd1r is input, the potentials of the capacitive elements C2 and This is lowered by the capacitive coupling of the capacitive element C2r. The potential of the gates of the transistors M6 and M6r becomes low, so that the The node M6r is turned off. Also, a high-level potential is input to the wire X2L, so the node The potentials of the nodes nd1s and nd1sr are connected to the capacitance elements C2s and C2sr, respectively. This increases the capacitance of the transistors M7 and M7r. Since the potential of each gate becomes high, transistor M7 and transistor M7r are turned on. In other words, when "-1" is input as a neuron signal to the circuit MP, As a result, the circuit MC and the wiring OLB are in a conductive state, and the circuit MCr and the wiring OL are in a conductive state. It will be in normal state.

[0354] In addition, for example, after the potentials corresponding to the weighting coefficients are held in the holding units HC and HCr, When inputting “0” as a neuron signal to the circuit MP, a low-level potential is applied to the wire X1L. Since the potentials of the nodes nd1 and nd1r are input, the potentials of the capacitance elements C2 and This is due to the capacitive coupling of the capacitance element C2r. The potential of the gate of each of the transistors M6 and M6r becomes low. The transistor M6r is turned off. Also, a low-level potential is input to the wiring X2L. The potentials of the nodes nd1s and nd1sr are the capacitance elements C2s and C2 This is due to the capacitive coupling caused by sr. The potential of the gates of the transistors M7 and M7r becomes low, so that the transistors M7 and The M7r is in the off state. In other words, a "0" is input to the circuit MP as a neuron signal. As a result, the distance between the circuit MC and the wiring OL and the wiring OLB is , it becomes non-conductive.

[0355] In addition, the transistor M6, the transistor M6r, the transistor M7, and the transistor As an example, it is preferable that the on-state of M7r operates in the saturation region. The transistors M6, M6r, M7, and M7r The gate, source, and drain of each transistor are appropriately designed to operate in the saturation region when on. It is preferable that the transistor M6, the transistor M6r, and the transistor By operating the on-states of the transistors M7 and M7r in the saturation region, When the gate-source potential becomes high, the current that flows between the source and drain of the transistor In other words, when the wiring X1L (wiring X2L) is at a high level potential, the transistor The source-drain of transistor M6 and transistor M6r (transistor M7 and transistor M7r) The current flowing between the drains is 1sr) is determined by the magnitude of the potential. However, one embodiment of the present invention is not limited thereto. stomach.

[0356] Also, the circuit MP in FIG. 21A can change its configuration depending on the situation. A modified example of the circuit MP is shown in FIG. 21B. The circuit MP of FIG. 21B is a modified version of the circuit of FIG. A bias voltage is generated from the transistors M6, M6r, M7, and M7r. Therefore, the transistors included in the circuit MP M6, transistor M6r, transistor M7, and transistor M7r are transistors. This can be determined at the design stage and is independent of the structure of the converter.

[0357] For example, transistor M6, transistor M6r, transistor M7, and The transistor M7r includes single crystal silicon or non-single crystal silicon in the active layer. The transistor M6 in FIG. The transistor M6r, the transistor M7, and the transistor M7r include an oxide semiconductor in the active layer. The transistor M6 and the transistor M6r, transistor M7, and transistor M7r may be organic semiconductors, compound semiconductors, or the like. The transistor may have a body.

[0358] As described above, by applying the circuit MP of FIG. 21A and FIG. 21B to the arithmetic circuit 110, ,Like the circuit MP of FIG. 9A, it is possible to perform product-sum and activation function calculations.

[0359] <Configuration Example 7> In the configuration examples 1 to 6, the weighting coefficients held by the circuit MP are “+1”, “−1”, “0 " and the neuron signal according to the potential input from wires X1L and X2L is " This section describes the MP circuit, which can calculate the product of the three values ​​"+1", "-1", and "0" and As explained above, in this configuration example, the weighting coefficients are assumed to have three values, "+1", "-1" and "0". The signal (calculated value) of the neuron can be multiplied with the two values ​​"+1" and "0". Next, we will explain the circuit MP.

[0360] The circuit MP shown in FIG. 22A is the circuit MP shown in FIG. 9A except that the transistors M4 and M4r are removed. In addition, since the transistors M4 and M4r are removed, in FIG. , transistor M4, and transistor M4r. The wire X2L is also excluded. Also, the wire equivalent to the wire X1L is marked as wire XL in FIG. 22A. It is listed.

[0361] The weighting coefficient set in the circuit MP in FIG. 22A is a weighting coefficient set in the circuit MP in FIG. In this case, when a low-level potential is held at the node nd1r of the holding unit HCr, the potential is set to “+1”. , a low level potential is applied to the node nd1 of the holding unit HC, and a high level potential is applied to the node nd1r of the holding unit HCr. When the potential is held, it is set to "-1" and a low level potential is applied to the node nd1 of the holding unit HC. When a low level potential is held at the node nd1r of the holding unit HCr, it is set to "0".

[0362] In addition, the neuron signal input to the circuit MP in FIG. 22A is a high-level potential on the wire XL. When a low-level potential is applied to the XL line, the signal is set to "+1". Let it be “0”.

[0363] For the operation of the circuit MP in FIG. 22A, the explanation of the operation example of the configuration example 1 should be referred to.

[0364] In the circuit MP of FIG. 22A, as described above, the weight coefficients and the input neuron signals When we define the weight coefficients, the signal of the neuron is input to the circuit MP. As a result, the current I OL Changes in Current I output from node outb of wiring OLB OLB The presence or absence of change is as follows: In the table below, high level potential is indicated as "high" and low level potential is indicated as "low". is described as low.

[0365] [Table 3]

[0366] As shown in the table above, the circuit MP in FIG. 22A has three weighting coefficients: “+1”, “-1”, and “0”. The product of this and the two values ​​of the neuron's signal, "+1" and "0", can be calculated. The weighting coefficient may be two values ​​or more than three values ​​instead of three values. For example, It may be two values, 1 and 0, or two values, +1 and -1. Or, a weighting coefficient may be an analog value or a multi-bit (multiple-valued) digital value.

[0367] In this operation example, the holding units HC The potential held in the holding unit HCr is set to a high level potential or a low level potential. The weighting coefficient HC and the holding coefficient HCr may hold a potential indicating an analog value. In the case of a “positive analog value” as a number, a high-level analog A low level potential is held at the node nd1r of the holding unit HCr. In the case of a "negative analog value", for example, a low level potential is applied to the node nd1 of the holding unit HC, A high-level analog potential is held at the node nd1r of the holding unit HCr. Flow I OL and current I OLB The magnitude of the current corresponds to the analog potential.

[0368] The circuit MP of FIG. 22A is similar to the circuit MP of FIG. 16A in that the wiring IL and the wiring ILB are connected in a single line. Alternatively, the wiring WL may be divided into wirings W1L and W2L. The configuration is shown in FIG. 22B. The circuit MP in FIG. 22B is applied to the arithmetic circuit 120 in FIG. The operation method of the circuit MP in FIG. 22B can be described in the same manner as that of the circuit MP in FIG. Please refer to the description of how P works.

[0369] In addition, the circuit MP in FIG. 22A is configured by dividing the wiring XL into wiring X1L and wiring X2L. Such a circuit configuration is shown in FIG. 22C. When a high-level potential or a low-level potential is applied, the The combination of the on and off states of the holding parts HC and HC is four. The nodes nd1 and nd1r of HCr are connected to a high level potential or a low level potential. If the potentials held at the nodes nd1 and nd1r are There are four ways to do this.

[0370] Specifically, a high-level potential is held at the node nd1, and a high-level potential is applied to the wiring X1L. When the line OL is turned on, the line OL and the line VL are electrically connected, so that the current The amount of current I OL Also, a high level potential is held at the node nd1r, and the line X2 When a high-level potential is applied to L, the wiring OLB and the wiring VLr are electrically connected. Therefore, the current flowing through the wiring OLB is I OLB In the circuit MP of FIG. The combination of the potentials held at the nodes nd1 and nd1r and the wiring X1L and X2L are given. The potentials of the output terminals of the wiring OL are determined by the combination of the potentials of the output terminals of the wiring OL and the potentials of the output terminals of the wiring OL. current I OLand the current I output from node outb of wiring OLB OLB The presence or absence of change is as shown in the table below. In the table below, high level potential is called "high". and a low level potential is described as low.

[0371] [Table 4]

[0372] Next, a circuit having a different configuration from the circuit MP of FIGS. 22A to 22C will be described.

[0373] The circuit MP shown in FIG. 23A has weighting coefficients of “+1” and “−1” in the same manner as the circuit MP shown in FIG. 22A. Calculate the product of the ternary values ​​"1" and "0" and the binary values ​​"+1" and "0" of the neuron signal The circuit MP of FIG. 21A includes a transistor M1s, a transistor M1sr, and a transistor M1sr. A circuit in which the transistor M7, the transistor M7r, the capacitance element C2s, and the capacitance element C2sr are not provided In addition, since the capacitance elements C2s and C2sr are omitted, Then, for inputting a potential to the second terminal of each of the capacitance elements C2s and C2sr, Wiring X2L is also excluded. Also, the wiring equivalent to wiring X1L is wiring XL in Figure 23A. It is stated.

[0374] For the operation of FIG. 23A, refer to the description of configuration example 6.

[0375] As in the circuit MP of FIG. 22A, the weight coefficients and the neurons By defining the signal and , the weighting coefficients are “+1”, “-1”, “ The product of the ternary value of “0” and the binary value of the neuron signal, “+1” and “0”, can be calculated. The weighting coefficient may be two values ​​or more than three values ​​instead of three values. For example, it may be two values, "+1" and "0", or two values, "+1" and "-1". The weighting coefficients may be analog values ​​or multi-bit (multi-value) digital values. For example, , the circuit MC of the circuit MP, the circuit MCr has a holding unit HC, the circuit MCr has a holding unit HCr The potential was set to a high level potential or a low level potential, but the holding part HC and the holding part HCr were analog. For example, in the case of a "positive analog value" as the weighting coefficient, A high-level analog potential is applied to the node nd1 of the holding unit HC, and a high-level analog potential is applied to the node nd1 of the holding unit HCr. r holds a low level potential. In the case of a "negative analog value" as the weighting coefficient, e.g. For example, a low level potential is applied to the node nd1 of the holding unit HC, and a high level potential is applied to the node nd1r of the holding unit HCr. The analog potential of the bell is held. And the current I OL and current I OLB Large current The magnitude corresponds to the analog potential.

[0376] The circuit MP in FIG. 23A is similar to the circuit MP in FIG. 16A in that the wiring IL and the wiring ILB are connected in a single line. Alternatively, the wiring WL may be divided into wiring W1L and wiring W2L. The circuit configuration is shown in FIG. 23B. The circuit MP in FIG. 23B corresponds to the arithmetic circuit 120 in FIG. It should be noted that the operation method of the circuit MP in FIG. 23B can be applied to the circuit in FIG. Please refer to the description of the operation method of the MP.

[0377] 22C, the circuit MP of FIG. 23A is similar to the circuit MP of FIG. 22C in that the wiring XL is connected to the wiring X1L, Such a circuit configuration may be divided into wiring X1 and wiring X2L. If a high level potential or a low level potential is applied to each of the wirings X1L and X2L, Combinations of the on and off states of the transistors M6 and M6r There are four ways. In addition, the nodes nd1 and n If a high level potential or a low level potential is held at node nd1, There are four combinations of potentials held at the node nd1r. For example, in the circuit MP The potentials held in the holding units HC and HCr of the circuits MC and MCr are Although it is set to a level potential or a low level potential, the holding part HC and the holding part HCr show analog values. For example, in the case of a "positive analog value" as the weighting coefficient, the holding unit A high-level analog potential is applied to the node nd1 of the HC, and a low-level analog potential is applied to the node nd1r of the holding unit HCr. In the case of a "negative analog value" as the weighting coefficient, for example, A low-level potential is applied to the node nd1 of the HC section, and a high-level potential is applied to the node nd1r of the HCr section. A log potential is maintained. And the current I OL and current I OLB The magnitude of the current is The magnitude depends on the analog potential.

[0378] In the circuit MP of FIG. 23C, the change in the current flowing through the wiring OL and wiring OLB is Therefore, in the circuit MP of FIG. The combination of the potentials held at the nodes nd1 and nd1r and the wiring X1L and X2L is given. The potentials of the output terminals of the wiring OL are determined by the combination of the potentials of the output terminals of the wiring OL and the potentials of the output terminals of the wiring OL. current I OL and the current I output from node outb of wiring OLB OLB The presence or absence of change is as shown in the above table explained for the circuit MP in FIG. 22C.

[0379] <Configuration Example 8> The circuit MP shown in FIG. 24A is an example of a circuit that can be applied to the circuit MP of FIG. 5F.

[0380] The circuit MP in FIG. 24A includes a circuit MC, a circuit MCr, and a transistor MZ.

[0381] The circuit MCr of the circuit MP in FIG. 24A has a circuit configuration similar to that of the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is followed by "r."

[0382] The circuit MC also includes a holding unit HC and a transistor M8. The circuit has a portion HCr and a transistor M8r.

[0383] The holding unit HC included in the circuit MC of the circuit MP of FIG. 24A is, for example, Circuit MP of FIG. 9C, FIG. 10A, FIG. 10B, FIG. 11A, FIG. 11B, FIG. 12A, FIG. 12B, etc. The holding unit HC included in the circuit MC can have a similar configuration.

[0384] The first terminal of the transistor M8 is electrically connected to the first terminal of the transistor MZ. The gate of the transistor M8 is connected to the second terminal of the transistor M1 and the first terminal of the capacitance element C1. , and the second terminal of the transistor M8 is electrically connected to the wiring OL. A second terminal of the capacitance element C1 is electrically connected to the wiring CVL. A first terminal of M1 is electrically connected to the wiring IL.

[0385] In addition, the first terminal of the transistor M8r is electrically connected to the first terminal of the transistor MZ. The gate of the transistor M8r is connected to the second terminal of the transistor M1r and the capacitance element C1 The first terminal of the transistor M8r is electrically connected to the wiring OLB. The second terminal of the capacitance element C1r is electrically connected to the wiring CVL. A first terminal of the transistor M1 is electrically connected to a wiring ILB.

[0386] The line CVL functions as a line that applies a constant voltage, for example. , for example, a high-level potential, a low-level potential, a ground potential, etc.

[0387] The holding unit HC and the holding unit HCr included in the circuit MP of FIG. 24A are the same as those shown in FIG. 9A etc. Similarly to the holding units HC and HCr included in the circuit MP, the potential according to the weighting coefficient Specifically, for example, a predetermined potential is applied to the wiring WL to hold the transistor. The first transistor M1 and the second transistor M1r are turned on, and the first terminal of the capacitance element C1 is connected to the wiring IL. A potential is supplied to the first terminal of the capacitor C1r from the wiring ILB. After that, a predetermined potential is applied to the wiring WL to turn on the transistor M1 and the transistor M1 Just turn r off.

[0388] Here, for example, the weighting coefficient set in the circuit MP of FIG. 24A is When a high level potential is held at d1 and a low level potential is held at node nd1r of the holding unit HCr, When the node nd1 of the holding unit HC is set to a low level potential, the node n When a high level potential is held at node nd1r, the node nd2 of the holding unit HC is set to "-1". When a low level potential is held at node nd1r of the holding unit HCr, and a low level potential is held at node nd2r of the holding unit HCr, Let it be “0”.

[0389] The potentials corresponding to the weighting coefficients are held in the holding section HC and the holding section HCr. Therefore, the potentials of the gates of the transistors M8 and M8r are determined. Here, by applying a potential to the wire XL according to the value of the neuron's signal, , the current flowing from the circuit MP to the wiring IL and / or the wiring ILB is determined. For example, When a high-level potential is applied to L as the second data of “1”, the constant voltage applied by the line VL is applied to a first terminal of a transistor M8 and a first terminal of a transistor M8r. When the potential of the gate of the transistor M8 is at a high level potential, the transistor M8 A current flows between the first and second terminals of the transistor M1 and the potential of the gate of the transistor M8 becomes low. When the potential is at V 1 , no current flows between the first and second terminals of transistor M8. When the potential of the gate of the transistor M8r is at a high level potential, A current flows between the first and second terminals of the transistor M8r, and the potential of the gate of the transistor M8r becomes low. When the transistor M8r is at the buffer potential, no current flows between the first and second terminals of the transistor M8r. Also, for example, when a low level potential is applied to the line XL as the second data of "0", A wiring VL is provided between a first terminal of the transistor M8 and a first terminal of the transistor M8r. Since no constant voltage is applied, the current between the first and second terminals of each transistor is It doesn't flow.

[0390] In other words, to summarize the above, the product of the weight coefficient and the neuron's signal value is "+1". When the MC is turned on, a certain current flows from the circuit MC to the wiring OL, and a certain current flows from the circuit MCr to the wiring OLB. When the product of the weight coefficient and the neuron signal value is "-1", the A specified current flows from circuit MCr to wiring OLB, and a specified current flows from circuit MC to wiring OL. Also, when the product of the weight coefficient and the value of the neuron's signal is "0", No current flows through the wiring OL, and no predetermined current flows from the circuit MCr to the wiring OLB.

[0391] As described above, the circuit MP of FIG. 24A has the weighting coefficients The three values ​​are "+1", "-1", and "0", and the neuron signal (calculated value) is "+1" and "0". The circuit MP of FIG. 24A can calculate the product of the two values ​​of and . As with the MP circuit, the weighting coefficients can be analog values ​​or multi-bit (multiple-valued) digital values. This is also fine.

[0392] In addition, the circuit MP may be changed appropriately depending on the situation.

[0393] For example, when the circuit MP of FIG. 24A is applied to the arithmetic circuit 130 of FIG. The MP circuit can be changed to the circuit MP shown in FIG. In the circuit MP of A, the wiring OL and the wiring IL are combined into a single wiring IOL. In addition, the wiring OLB and the wiring ILB are combined into a single wiring called the wiring IOLB. The wiring XL shown in FIG. 24B corresponds to the wiring XLS[1] to the wiring XLS[m], and the wiring WL shown in FIG. 24B corresponds to the wiring WLS shown in FIG. It corresponds to any one of wirings [1] to WLS[m].

[0394] Moreover, the circuit that can be applied to the circuit MP of FIG. 5A is not limited to the circuit MP of FIG. 24A.

[0395] For example, the circuit MP of FIG. 18A described in the configuration example 4 can be applied to the circuit MP of FIG. The circuit MP shown in FIG. 25A can be applied to the circuit MP of FIG. A circuit including a load circuit LC similar to that shown in FIG. 18A and a load circuit LCr. The operation of FIG. 25A is the same as that of the circuit MP in FIG. 24A. Please refer to the explanation of the operation example of the circuit MP etc. in FIG. 18A.

[0396] For example, when the circuit MP of FIG. 25A is applied to the arithmetic circuit 130 of FIG. The circuit MP may be changed to the circuit MP shown in FIG. 25B. In the circuit MP of FIG. 25A, the wiring OL and the wiring IL are integrated into a single wiring IOL. Then, the wiring OLB and the wiring ILB are combined into a single wiring called wiring IOLB. Furthermore, the transistor M1 and the transistor M1r are not provided. The wiring XL shown in FIG. 25B is any one of the wirings XLS[1] to XLS[m] shown in FIG. 25B corresponds to the wiring WLS[1] to the wiring WL shown in FIG. It corresponds to one of S[m].

[0397] Also, for example, the circuit MP of FIG. 20A described in the configuration example 5 can be applied to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 26A can be modified to the circuit MP of FIG. 20A, the inverter circuit INV1 and the inverter circuit IN A holding unit HC including V2, and an inverter circuit INV1r and an inverter circuit INV2r The circuit MP in FIG. 26A includes a transistor M3, a transistor The transistor M3r, the transistor M4, and the transistor M4r are not provided. For the operation of the circuit MP, please refer to the explanation of the operation examples of the circuit MP in FIG. 24A and the circuit MP in FIG. 20A. do.

[0398] Also, for example, the circuit MP of FIG. 20B described in the configuration example 5 can be applied to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 26B can be modified to a circuit that can be applied to the circuit MP of FIG. 20B, the inverter circuit INV1 and the inverter circuit IN The circuit MP in FIG. 26B includes a transistor M3, a transistor The transistors M3r, M4, and M4r are not provided. For the operation of B, please refer to the explanation of the operation examples of the circuit MP of FIG. 24A and the circuit MP of FIG. 20B. To pour drinks.

[0399] Also, for example, the circuit MP of FIG. 22A described in the configuration example 7 can be applied to the circuit MP of FIG. 5A. The circuit MP shown in FIG. 27A can be modified to the circuit MP shown in FIG. 5A. This circuit is a modification of the circuit MP of FIG. 22A. The second terminal of the capacitance element C1 is electrically connected to the wiring VL, and the third terminal of the capacitance element C1r is electrically connected to the wiring VL. The first terminal of the transistor M1 and the second terminal of the transistor M2 are electrically connected to the wiring VL. The first terminal of the transistor M2 is electrically connected to the first terminal of the transistor MZ. This circuit differs from the circuit MP of FIG. 22A in that it does not include transistors M3 and M3r. The operation of FIG. 27A is the same as that of the circuit MP of FIG. 24A, the circuit MP of FIG. 22A, etc. Please refer to the explanation of the operation example.

[0400] For example, when the circuit MP of FIG. 27A is applied to the arithmetic circuit 120 of FIG. The circuit MP may be changed to the circuit MP shown in FIG. 27B. In the circuit MP of FIG. 27A, the wiring IL and the wiring ILB are connected as a single wiring IL. The wiring XL shown in FIG. 27B is the wiring XLS shown in FIG. The wiring WL shown in FIG. 27B corresponds to any one of the wirings XLS[1] to XLS[m]. 1 corresponds to any one of the wirings WLS[1] to WLS[m] shown in FIG.

[0401] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0402] (Embodiment 3) In this embodiment mode, an OS transistor applicable to the semiconductor device described in the above embodiment mode will be described. A configuration example of the data recorder will be described below.

[0403] <Example of semiconductor device configuration> The semiconductor device shown in FIG. 28 includes a transistor 300, a transistor 500, and a capacitance element 30A is a cross-sectional view of the transistor 500 in the channel length direction. 30B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 1 is a cross-sectional view of a transistor 300 in the channel width direction.

[0404] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). Since the off-state current of the transistor 500 is small, In particular, the transistors M1 and M3 of the circuit MP included in the arithmetic circuit 110, By using it for transistor M4, etc., it is possible to retain written data for a long period of time. In other words, it is possible to perform the refresh operation less frequently or Since no operation is required, the power consumption of the semiconductor device can be reduced.

[0405] The transistor 500 is provided above the transistor 300, and the capacitance element 600 is The capacitor 600 is disposed above the transistor 300 and the transistor 500. can be the capacitive element C1, the capacitive element C1r, etc. in the circuit MP.

[0406] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate 316. A semiconductor region 313 formed of a part of 311, a low-temperature region functioning as a source region or a drain region The transistor 300 has a resistive region 314a and a low resistive region 314b. For example, the present invention can be applied to the transistors in the above embodiments.

[0407] The transistor 300 is formed by forming a top surface of the semiconductor region 313 and a channel region 314 as shown in FIG. The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 300 a fin type, the effective channel width is increased, The on-characteristics of the transistor 300 can be improved. Since the temperature can be increased, the off-state characteristics of the transistor 300 can be improved. .

[0408] The transistor 300 may be either a p-channel type or an n-channel type. .

[0409] The region in which the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b which become the drain region, silicon It is preferable that the semiconductor material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the semiconductor material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Alternatively, the insulating layer 12 may be formed of a material having a conductivity of 0.1 to 1.0 m / s, such as gallium aluminum arsenide (GaAlAs) or gallium aluminum arsenide (GaAlAs). The effective mass of silicon is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 30 may be made of GaAs and GaAlAs. 0 stands for High Electron Mobility Transistor (HEMT) ) can also be used.

[0410] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that impart n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. Contains an element that imparts electrical conductivity.

[0411] The conductor 316 that functions as the gate electrode is made of arsenic, phosphorus, or the like that imparts n-type conductivity. An element, or a semiconductor material such as silicon that contains an element that gives it p-type conductivity, such as boron For example, a conductive material such as a graphite material, a metal material, an alloy material, or a metal oxide material can be used.

[0412] In addition, since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. In this way, the threshold voltage of the transistor can be adjusted. It is preferable to use a material such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as laminations for the conductor. It is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0413] Note that the transistor 300 shown in FIG. 28 is just an example, and the present invention is not limited to this structure. For example, a semiconductor device may be an OS transistor. In the case of a unipolar circuit consisting of transistors only, the structure of transistor 300 is as shown in FIG. The structure of the transistor 500 including an oxide semiconductor may be similar to that of the transistor 500 including an oxide semiconductor. The transistor 500 will be described in detail below.

[0414] Covering the transistor 300 are an insulator 320, an insulator 322, an insulator 324, and an insulator 326. The bodies 326 are stacked in order.

[0415] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum oxynitride, aluminum nitride, or the like may be used.

[0416] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen. Silicon oxide nitride refers to a material that contains more nitrogen than oxygen in its composition. In this specification, aluminum oxynitride refers to a material with a high content. Aluminium oxide nitride refers to a material that contains more oxygen than nitrogen as a composition. This refers to a material that has a higher nitrogen content than oxygen content as a composition.

[0417] The insulator 322 serves to eliminate a step caused by the transistor 300 and the like provided below. For example, the upper surface of the insulator 322 may have a function as a planarizing film. In order to improve flatness, the surface is flattened by a planarization process using a chemical mechanical polishing (CMP) method or the like. It may be possible.

[0418] The insulator 324 is provided with a transistor-insulating layer 324. The transistor-insulating layer ... A film having a barrier property to prevent diffusion of hydrogen and impurities is used in the area where the capacitor 500 is provided. It is preferable that

[0419] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. When hydrogen diffuses into a semiconductor element, the characteristics of the semiconductor element may deteriorate. Therefore, a film for suppressing hydrogen diffusion is provided between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is one that reduces the amount of hydrogen desorption. The membrane is thin.

[0420] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be calculated by TDS analysis. In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5×10 15 a toms / cm 2 The following is acceptable.

[0421] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. It is more preferable to use a material with a low dielectric constant as the interlayer film to reduce the parasitic capacitance between wirings. It can be reduced.

[0422] In addition, the insulators 320, 322, 324, and 326 are provided with a capacitance element 6. 00, or a conductor 328 and a conductor 330 connected to the transistor 500 are embedded. The conductor 328 and the conductor 330 function as plugs or wiring. In addition, the conductor having the function of a plug or wiring is a single structure that is integrated with multiple structures. In addition, in this specification, wiring and a plug connected to the wiring may be In other words, a part of the conductor functions as a wiring, and In some cases, a portion of the conductor serves as the plug.

[0423] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or in a laminated form. High melting point materials such as tungsten and molybdenum that are both heat resistant and conductive can be used. It is preferable to use a ferroelectric material, and it is preferable to use tungsten. Alternatively, it is preferable to use aluminum. It is preferable to form the conductive layer from a low-resistance conductive material such as copper. This allows the wiring resistance to be reduced.

[0424] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is provided using the same material as the conductors 328 and 330. It is possible.

[0425] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen as the conductor 356. In particular, the insulator 350 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0426] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0427] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using similar materials.

[0428] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen as the conductor 366. In particular, the insulator 360 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0429] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using similar materials.

[0430] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen as the conductor 376. In particular, the insulator 370 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0431] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using similar materials.

[0432] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, the insulator 380 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0433] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the conductor 376 The wiring layer including the conductor 386 and the wiring layer including the conductor 387 have been described above. However, the semiconductor device to be used is not limited to this. Alternatively, the number of wiring layers may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more. Good too.

[0434] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , are stacked in this order. It is preferable that any of the bodies 516 is made of a material that has a barrier property against oxygen and hydrogen. .

[0435] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. Hydrogen and impurities diffuse from the region where the transistor 300 is provided to the region where the transistor 500 is provided. It is preferable to use a film having a barrier property that prevents the insulator 324 from scattering. The same materials as those mentioned above can be used.

[0436] As an example of a film that has a barrier property against hydrogen, silicon nitride formed by CVD method is used. Here, a semiconductor element having an oxide semiconductor, such as a transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that reduces the amount of hydrogen desorption. do.

[0437] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0438] In particular, aluminum oxide is highly resistant to oxygen and hydrogen, which are factors that affect the electrical characteristics of transistors. The membrane has a high blocking effect, preventing both impurities such as oxygen and water from penetrating the membrane. Aluminum oxide is highly resistant to insufficient hydrogen, moisture, and other impurities during and after the transistor manufacturing process. It is possible to prevent the inclusion of impurities in the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. It is suitable for use as a protective film against 00.

[0439] For example, the insulator 512 and the insulator 516 are made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. For example, the insulator 512 and the insulator A silicon oxide film, a silicon oxynitride film, or the like can be used as 516 .

[0440] In addition, the insulators 510, 512, 514, and 516 are each provided with a conductor 5 18, and conductors (e.g., conductor 503) constituting the transistor 500 are embedded. Note that the conductor 518 is connected to the capacitor 600 or the transistor 300. The conductor 518 functions as a plug or a wiring. It can be provided using the same material as 30.

[0441] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are oxidized to oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 500 have a barrier property against oxygen, hydrogen, and water. The layers can be separated, and hydrogen diffusion from transistor 300 to transistor 500 can be prevented. can be suppressed.

[0442] Above the insulator 516 is a transistor 500 .

[0443] As shown in FIGS. 30A and 30B, the transistor 500 includes an insulator 514 and an insulator 516. A conductor 503 disposed so as to be embedded in an insulator 516, and an insulator 516 and a conductor 50 3, an insulator 520 disposed on the insulator 520, and an insulator 522 disposed on the insulator 520. An insulator 524 is disposed on the edge 522, and an oxide 53 is disposed on the insulator 524. 0a, oxide 530b disposed on oxide 530a, and oxide 530b disposed on oxide 530b. Conductor 542a and conductor 542b are arranged apart from each other, and conductor 542a and conductor 54 2b, and an opening is formed between the conductor 542a and the conductor 542b. The edge 580, the oxide 530c disposed on the bottom and side surfaces of the opening, and the shape of the oxide 530c An insulator 550 disposed on the forming surface, and a conductor 560 disposed on the forming surface of the insulator 550; has.

[0444] As shown in FIG. 30A and FIG. 30B, the oxide 530a, the oxide 530b, and the conductive The insulator 544 is disposed between the conductor 542a and the insulator 580. As shown in FIG. 30A and FIG. 30B, the conductor 560 is preferably made of an insulator 5 50, and a conductor 560a provided inside the conductor 560a so as to be embedded inside the conductor 560a. It is preferable that the conductor 560b is provided. As shown, an insulator 574 is disposed over an insulator 580, a conductor 560, and an insulator 550. It is preferable that the

[0445] In the following, the oxide 530a, the oxide 530b, and the oxide 530c are collectively referred to as oxides 530a, 530b, and 530c. This is sometimes called oxide 530.

[0446] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which three layers of oxide 530a, oxide 530b, and oxide 530c are laminated. However, the present invention is not limited thereto. For example, a single layer of oxide 530b, A two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, Alternatively, a stacked structure of four or more layers may be provided. Although the conductor 560 is shown as having a two-layer laminate structure, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a laminated structure of three or more layers. In addition, the transistor 500 shown in FIG. 28 and FIG. 30A is only an example, and the structure is not limited to this example. It is only necessary to use an appropriate transistor depending on the circuit configuration and driving method.

[0447] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. The conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region. The location of 42b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is self-aligned between the source electrode and the drain electrode. Therefore, the conductor 560 can be arranged with a margin for alignment. Since the transistor 500 can be formed without any need for a gate, the area occupied by the transistor 500 can be reduced. This allows miniaturization and high integration of semiconductor devices.

[0448] Furthermore, a conductor 560 is formed in a self-aligned manner in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the conductor 560 has an overlapping region with the conductor 542a or the conductor 542b. As a result, the conductor 560 is not formed between the conductor 542a and the conductor 542b. Therefore, the switching speed of the transistor 500 can be improved. It is possible to improve the transmission efficiency and provide high frequency characteristics.

[0449] The conductor 560 may function as a first gate (also called a top gate) electrode. The conductor 503 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 may be different from the potential applied to the conductor 560. By changing the threshold voltage of the transistor 500 independently, the threshold voltage of the transistor 500 can be controlled. In particular, applying a negative potential to the conductor 503 can turn on the transistor 5 It is possible to increase the threshold voltage of 00 to be higher than 0V and reduce the off-current. Therefore, applying a negative potential to the conductor 503 increases the current flow rate of the conductor 560 compared to when no negative potential is applied. This can reduce the drain current when the potential applied to is 0V.

[0450] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field and the electric field generated by the conductor 503 are connected, forming a channel in the oxide 530. In the present specification and the like, the first gate electrode and the second gate electrode can cover the region where the first gate electrode and the second gate electrode are formed. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called This is called a surrounded channel (S-channel) structure.

[0451] The conductor 503 has the same configuration as the conductor 518, and the insulators 514 and 5 A conductor 503a is formed in contact with the inner wall of the opening 16, and a conductor 503b is formed further inside. In the transistor 500, a conductor 503a and a conductor 503b are stacked. However, the present invention is not limited to this. The body 503 may be configured as a single layer or a laminated structure of three or more layers.

[0452] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has a function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material having the above-mentioned function (i.e., being difficult for oxygen to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or the above The function is to suppress the diffusion of any one or all of the oxygen.

[0453] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 It is possible to suppress the oxidation of b and the decrease in electrical conductivity.

[0454] In addition, when the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, etc. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based material. Although the conductor 503b is illustrated as a single layer, it may have a multilayer structure. It may also be a laminate of titanium dioxide and the above-mentioned conductive material.

[0455] Insulator 520, insulator 522, insulator 524, and insulator 550 form a second gate insulator. It functions as a membrane.

[0456] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. That is, the insulator 524 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed in the oxide 530. By providing the oxide 530 in contact with the oxide 530, oxygen vacancies in the oxide 530 are reduced, and the signal quality of the transistor 500 is improved. The reliability can be improved.

[0457] As an insulator having an excess oxygen region, specifically, an oxide insulator in which a part of oxygen is released by heating is used. It is preferable to use oxide materials that release oxygen when heated. Thermal Desorption Spectroscopy (DSA) analysis revealed that oxygen atoms The converted amount of oxygen released is 1.0 x 10 18 atoms / cm 3 More than or equal to 1.0, preferably ×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / c m 3 or more than 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower, or The temperature range is preferably from 0° C. to 400° C.

[0458] In addition, the insulator having the excess oxygen region is brought into contact with the oxide 530 and then heat-treated. Alternatively, one or more of microwave processing, RF processing, or the like may be performed. By performing the above process, water or hydrogen in the oxide 530 can be removed. For example, At 530, a reaction occurs in which the VoH bond is broken, in other words, "V O H→V O + This causes the reaction "H" to occur, resulting in dehydrogenation. Some of the hydrogen produced at this time is It combines with oxygen to become H2O and is removed from the oxide 530 or the insulators adjacent to the oxide 530. In addition, some of the hydrogen may flow through the conductor 542 (the conductor 542a and the conductor 542b) may diffuse or be captured (also called gettered).

[0459] The microwave treatment may be carried out using, for example, an apparatus having a power source for generating high-density plasma. Alternatively, it is preferable to use an apparatus having a power source for applying RF to the substrate side. By using a gas containing oxygen and high-density plasma, high-density oxygen radicals are generated. By applying RF to the substrate side, the high-density plasma is generated. Efficiently introduce oxygen radicals into the oxide 530 or into the insulator near the oxide 530 The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 The pressure may be 400 Pa or more, and more preferably 400 Pa or more. The gas introduced into the device is, for example, oxygen and argon, with the oxygen flow ratio (O / (O2+Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0460] In addition, during the manufacturing process of the transistor 500, the surface of the oxide 530 is exposed. The heat treatment is preferably performed at a temperature of, for example, 100° C. or higher and 450° C. or lower. More preferably, the heat treatment is performed at a temperature of 350° C. or higher and 400° C. or lower. Or in an inert gas atmosphere, or oxidizing gas is 10 ppm or more, 1% or more, or For example, the heat treatment is preferably carried out in an oxygen atmosphere. This supplies oxygen to the oxide 530 to eliminate oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or nitrogen gas. After heat treatment in an active gas atmosphere, oxidizing gas was added at 10p to replace the oxygen that was removed. pm or more, 1% or more, or 10% or more. Alternatively, After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0461] In addition, by performing an oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 are filled with oxygen. In other words, the oxygen that is released into the tissue repairs the damaged tissue. O +O→null” reaction. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530. This allows the hydrogen to be removed as H2O (dehydration). Hydrogen remaining in sample 530 recombines with the oxygen vacancies to form V O Inhibits the formation of H It is possible.

[0462] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-absorbed (e.g., It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (the oxygen is less likely to permeate). is preferred.

[0463] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 530 The oxygen contained in the conductor 503 is preferably not diffused to the insulator 520 side. In this way, reaction with the oxygen contained in the insulator 524 and the oxide 530 can be suppressed.

[0464] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide. Hafnium-containing oxides (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba Insulators including so-called high-k materials such as ,Sr)TiO3(BST) are used as single layers or stacked layers. As transistors become smaller and more highly integrated, the gate insulating layer Thinning the film can cause problems such as leakage current. Functions as a gate insulating film. By using a high-k material as the insulator, the transistor operation can be improved while maintaining the physical thickness. This makes it possible to reduce the gate potential during operation.

[0465] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to penetrate ) Uses an insulator containing oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an oxide of aluminum, hafnium, or both as an insulator. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use such a material for the insulator 522. When formed, the insulator 522 prevents oxygen from being released from the oxide 530 and prevents the transistor 500 from being damaged. It functions as a layer that suppresses the intrusion of impurities such as hydrogen from the surrounding area into the oxide 530.

[0466] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, etc. may be added to these insulators. Aluminum, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the edge.

[0467] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are preferred because they are thermally stable. By combining an insulator with silicon oxide or silicon oxynitride, it is possible to obtain a thermally stable Moreover, it is possible to obtain the laminated insulator 520 having a high relative dielectric constant.

[0468] In the transistor 500 in FIG. 30A and FIG. 30B, the first layer is a three-layer laminate structure. As the second gate insulating film, an insulator 520, an insulator 522, and an insulator 524 are illustrated. However, the second gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In this case, the laminated structure is not limited to the same material, but may be made of different materials. Good too.

[0469] In the transistor 500, an oxide semiconductor is added to an oxide 530 including a channel formation region. It is preferable to use a metal oxide that functions as the oxide 530. For example, In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, Sodium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lambda Tungsten, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium In particular, the oxide 53 The In-M-Zn oxide that can be used as the In-Zn oxide is CAAC-OS, The oxide 530 is preferably an In-Ga oxide, an I n-Zn oxide may also be used.

[0470] In addition, it is preferable to use a metal oxide having a low carrier concentration for the transistor 500. When the carrier concentration of the metal oxide is reduced, the impurity concentration in the metal oxide is reduced. In the present specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, etc. Examples include silicon and silica.

[0471] In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. In addition, oxygen vacancies in the oxide 530 may form oxygen vacancies in the metal oxide. When an oxygen atom is introduced, the oxygen vacancy and hydrogen bond to form V O May form H. V O H is for Donna In some cases, hydrogen atoms function as carriers, producing electrons. It may combine with oxygen to produce electrons, which are carriers. Transistors using metal oxides that contain a lot of silicon tend to be normally-on. In addition, hydrogen in metal oxides is easily moved by stress such as heat and electric field. If the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the invention, V in oxide 530 O Reduce H as much as possible and use high purity intrinsic or It is preferable that V be substantially intrinsic with high purity. O Metal with sufficiently reduced H To obtain the oxide, it is necessary to remove impurities such as water and hydrogen from the metal oxide (dehydration, This is sometimes called oxidation treatment.) and supplying oxygen to the metal oxide to compensate for the oxygen deficiency. It is important to do this (sometimes referred to as oxygen addition treatment). O Impurities such as H are not enough By using a metal oxide with reduced conductivity in the channel formation region of a transistor, stable current can be obtained. It can give the item a special quality.

[0472] The defect where hydrogen has entered the oxygen vacancy can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, the term "metal" is used to refer to the carrier concentration rather than the metal concentration. As a parameter of the oxide, instead of the donor concentration, we use the capacitance assuming a state in which no electric field is applied. In other words, the "carrier concentration" described in this specification is the "dop This can sometimes be rephrased as "ner concentration."

[0473] Therefore, when a metal oxide is used for the oxide 530, the hydrogen in the metal oxide should be as low as possible. Specifically, in the case of metal oxides, secondary ion mass spectrometry is preferably used. (SIMS: Secondary Ion Mass Spectrometry) The hydrogen concentration obtained is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than 100%. Impurities such as hydrogen are sufficiently reduced. By using this metal oxide in the channel formation region of a transistor, stable electrical characteristics can be achieved. can be granted.

[0474] In addition, when a metal oxide is used for the oxide 530, the capacitance of the metal oxide in the channel formation region is increased. The rear concentration is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 Not yet More preferably, it is 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 Less than It is more preferable that the lower limit of the carrier concentration of the metal oxide in the channel formation region is There is no particular limitation on the -9 cm -3 It can be said that:

[0475] In addition, when a metal oxide is used for the oxide 530, the conductor 542 (the conductor 542a, When the oxide 530 comes into contact with the conductor 542b, the oxygen in the oxide 530 is transferred to the conductor 542. The conductor 542 may be oxidized by the oxidation of the conductor 542. It is highly likely that the conductivity of the conductor 542 will decrease. The diffusion of the conductor 542 into the oxide 530 can be expressed as the absorption of oxygen from the oxide 530 by the conductor 542. This can be done.

[0476] In addition, oxygen in the oxide 530 is converted into conductors 542 (conductors 542a and 542b ) at and near the interface between the conductor 542a and the oxide 530b, and In addition, the interface between the conductor 542b and the oxide 530b and the region having insulating properties near the interface Since the region contains more oxygen than the conductor 542, the region The region is estimated to have a higher electrical resistance than the conductor 542a and the conductor 542b. The three-layer structure of the conductor 542, the region, and the oxide 530b is a metal-insulator-semiconductor. It can be considered as a three-layer structure consisting of MIS (Metal-Insulator-Se A diode junction structure called a MIS structure or a MIS structure. It is sometimes called.

[0477] The insulating region is formed between the conductor 542 and the oxide 530b. For example, the insulating region may be a conductor 542 and an oxide 530c. conductor 542 and oxide 530b, and between conductor 542 and oxide 530c. It may be formed between the oxide 530c.

[0478] In addition, the metal oxide that functions as a channel formation region in the oxide 530 is a band gap metal oxide. It is preferable to use a gap of 2 eV or more, preferably 2.5 eV or more. By using metal oxides with a wide band gap, the off-state current of transistors can be reduced. It can be reduced.

[0479] The oxide 530 has an oxide 530a under the oxide 530b. The diffusion of impurities from the structure formed below the oxide 530b can be suppressed. In addition, by having the oxide 530c on the oxide 530b, the oxide 530c can be formed. Therefore, the diffusion of impurities from the structure formed above into the oxide 530b can be suppressed. do.

[0480] The oxide 530 has a layered structure made of oxides with different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the constituent elements The atomic ratio of element M in the oxide 530b is the atomic ratio of element M in the metal oxide in the constituent elements. It is preferable that the atomic ratio of the metal oxide 530a is larger than that of the element M. In the metal oxide used for the oxide 530b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element In. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In is larger than that of the element M in the metal oxide. The oxide 530c is a metal oxide that can be used for the oxide 530a or the oxide 530b. can be used.

[0481] In addition, the energy of the conduction band minimum of the oxide 530a and the oxide 530c is It is preferable that the energy of the oxide is higher than the conduction band minimum energy of the oxide. The electron affinity of oxide 530a and oxide 530c is smaller than the electron affinity of oxide 530b. is preferred.

[0482] Here, at the junctions of the oxide 530a, the oxide 530b, and the oxide 530c, The energy level of the lower band edge changes gradually. The energy levels of the conduction band minimum at the junction of 530b and oxide 530c are continuous. In order to achieve this, the oxide 530 a and the interface between oxide 530b and oxide 530c. It is preferable to reduce the defect level density of the resulting mixed layer.

[0483] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c are By having a common element other than oxygen (as the main component), a mixed layer with a low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used.

[0484] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530c as described above, the interface between the oxide 530a and the oxide 530b and the oxide The defect state density at the interface between the substrate 530b and the oxide 530c can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 has a high On-current can be obtained.

[0485] On the oxide 530b, a conductor 542a serving as a source electrode and a drain electrode is formed. The conductor 542a and the conductor 542b are provided. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, ungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, iridium, strontium, and lanthanum The metal elements mentioned above, or alloys containing the abo...

Claims

1. A semiconductor device having a first circuit and a second circuit, the first circuit includes first to fourth transistors and a first capacitor; the second circuit includes fifth to eighth transistors and a second capacitor; one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the first transistor is electrically connected to a first electrode of the first capacitance element; one of a source and a drain of the second transistor is electrically connected to a second electrode of the first capacitor element; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to a first wiring; a gate of the third transistor is electrically connected to a first input wiring; the other of the source and the drain of the fourth transistor is electrically connected to a second wiring; a gate of the third transistor is electrically connected to the first input wiring; one of a source and a drain of the fifth transistor is electrically connected to a gate of the sixth transistor; one of a source and a drain of the fifth transistor is electrically connected to a first electrode of the second capacitor element; one of a source and a drain of the sixth transistor is electrically connected to a second electrode of the second capacitor element; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the seventh transistor; the other of the source and the drain of the sixth transistor is electrically connected to one of the source and the drain of the eighth transistor; the other of the source and the drain of the seventh transistor is electrically connected to the second wiring; a gate of the seventh transistor is electrically connected to the first input wiring; the other of the source and the drain of the eighth transistor is electrically connected to the first wiring; a gate of the seventh transistor is electrically connected to the first input wiring; Semiconductor device.

2. A semiconductor device according to claim 1, The semiconductor device performs a neural network operation. electronic equipment.

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