Transceiver device

Abstract

To provide a system and a method for boosting a signal level to increase a signal-to-noise ratio of an electric subsystem using a piezoelectric transducer and transistor electronics.SOLUTION: A transceiver device is used to maximize voltage. A piezoelectric multilayer body 100 includes a substrate 109 having a first surface and a second surface facing each other, a first layer 105 of one or more piezoelectric transducers that is attached to the first surface of the substrate, a buffer layer 104 attached to the first layer, and a second layer 103 of one or more piezoelectric transducers that is attached to the buffer layer. The first layer and the second layer are connected in cascade through vias 110 and 111.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 62 / 854,933, filed May 30, 2019. No. 6,399,433, which is incorporated herein by reference in its entirety.

[0002] government fund This invention was made in accordance with Award No. 1746 awarded by the National Science Foundation (NSF). This invention was made with government support under US Provisional Patent Application No. 710 / 023,510. The United States Government has certain rights in this invention.

[0003] The present invention relates generally to a piezoelectric transceiver device, a voltage maximization method, and applications thereof, and more particularly to a CMOS circuit integrated with a transducer for increasing the received voltage. [Background technology]

[0004] In electrical engineering, a non-active amplifier of voltage is called a passive transformer. An example of a passive transformer is a magnetic transformer, which has fewer turns in the input coil than in the output coil, resulting in a voltage gain proportional to the ratio of the turns.

[0005] A related field to magnetic transformers is the ultrasonic piezoelectric transformer. In these ultrasonic piezoelectric transformers, segments of piezoelectric devices are driven with small dimensions and low voltages. A resonator drives the motion across the structure so that the second part of the resonator constitutes an electrode with a larger distance between the electrodes. The electric field integrated over a longer length results in a higher voltage, so voltage amplification is achieved at the cost of a lower output capacity. In some of these transformers, the energy injected into a set of electrodes is concentrated in the central electrode area to magnify the ultrasonic energy, i.e. the ultrasonic distortion is converted back into voltage.

[0006] Others include resonant transformers driven by a set of electrodes that drive themselves with a low input impedance, and the output is taken off at a higher impedance. In many of the transformers, the main drawback is the need for mechanical boundaries that increase the quality factor of the resonator to drive it to a high voltage. The higher the quality factor, the more ultrasonic amplitude is generated to boost the voltage at the output port. However, transformers are only useful with one additional load powered by the transformer-modified voltage source. Any load consumes energy, lowering the quality factor and reducing the voltage boost of the transformer. To maintain a high Q with the load, the mechanical energy stored in the resonator must be increased by increasing the volume of the transformer. Furthermore, the requirement to form boundary conditions typically requires etching and freeing of the resonant system. This processing is costly to manufacture and also reduces the yield of the devices produced due to effects such as internal thermal and interfacial thin film stress variations across the device, and wide variations in resonant frequency from device to device across the wafer. Therefore, a voltage transformer rigidly mounted on the substrate is desired to reduce the need for any additional processing. One example of such a voltage transformer has two thin film piezoelectric transducers placed on opposite sides of the substrate. The input transducer creates a stationary wave within the volume of the substrate. If the phasing of the ultrasonic field is correct, a voltage is generated at the output transducer. This structure separates the input and output ports and forms a transformer. A load at the output port can affect the acoustic impedance at the input port and can also change the frequency at which the received voltage is greatest.

[0007] Recent research (U.S. Patent No. 10,217,045 B2 and U.S. Patent No. 9,761, In the paper published in IEEE 802.11b (issue 324 B2) an approach is described to transmit ultrasonic pulses at carrier frequencies in the gigahertz range. RF pulses carrying tens of RF carrier frequencies are generated using thin piezoelectric membranes and moved through the bulk structure. Transducers are provided on both sides of the substrate so that one side can transmit the pulse and the other side can receive the pulse. The receiving side also receives the pulse reflected from the other side of the pulse. In these applications it is important to detect the pulse with as high a signal-to-noise ratio as possible, with as low a power as possible, and to generate as little heat as possible, to enable battery-powered applications. Summary of the Invention [Problem to be solved by the invention]

[0008] Therefore, what is needed is a system and method that uses piezoelectric transducers and transistor electronics to boost signal levels to increase the signal-to-noise ratio of electrical subsystems. [Means for solving the problem]

[0009] In the invention described herein, a voltage booster or transformer is implemented using a piezoelectric thin film in a substrate, preferably a CMOS substrate where active processing of RF signals can result in highly integrated and inexpensive ICs. Voltage gain is achieved by cascading multiple transducers formed on the same piezoelectric thin film, or membranes cascaded in series on top of each other. The array of transducers is connected in parallel or in series and connected to input or output port electrodes. The second approach described is to place the receiving transformer at a position where the diffracted field from the transmitting transducer is incident on the receiving transducer and generates a higher ultrasonic field at the receiving transducer. The third approach is to increase the voltage, connecting an array of transducers formed on the same layer, or piezoelectric layers of different layers in parallel, in the drive mode when the pulse is transmitted. The transducers are then dynamically configured to connect in series to obtain a higher voltage when the ultrasonic pulse is received back at the transducer after reflecting off the back side of the substrate. A higher transducer impedance results from a series of piezoelectric transducers arranged in series such that the overall reactive impedance is higher due to the lower capacitance.

[0010] An embodiment of the present invention is directed to a transceiver device for maximizing voltage. According to one aspect, the transceiver includes a substrate having a first surface and an opposing second surface. The transceiver also includes a CMOS device having one or more CMOS circuits attached to the first surface of the substrate and one or more piezoelectric transducers attached to an outer surface of the CMOS device. Each of the one or more piezoelectric transducers is configured to emit an ultrasonic wave toward the second surface of the substrate.

[0011] According to another aspect, the ultrasound is phased to generate high amplitude ultrasound by focusing.

[0012] According to another aspect, the substrate is constructed from a flexible, stretchable material.

[0013] According to another aspect, the substrate is comprised of at least one of a silicon wafer, a SiC wafer, and a silica wafer.

[0014] According to another aspect, the one or more piezoelectric transducers are made of piezoelectric material AlN or Al x Sc y It is composed of N.

[0015] According to another aspect, at least one of the one or more piezoelectric transducers is configured to emit stationary ultrasonic waves toward a second surface of the substrate.

[0016] According to another aspect, a transceiver includes a substrate having a first surface and an opposing second surface. The transceiver also includes a first layer of one or more piezoelectric transducers attached to the first surface of the substrate, a buffer layer attached to the first layer of one or more piezoelectric transducers, and a second layer of one or more piezoelectric transducers attached to the buffer layer. The buffer layer is between the first and second layers of one or more piezoelectric transducers. The first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers are connected in a cascade configuration via an electrical connector.

[0017] According to an additional aspect, the transceiver also includes a top insulating layer attached to an outer surface of a second of the one or more piezoelectric layers.

[0018] According to a further aspect, the transceiver also includes a CMOS device including one or more CMOS circuits, The CMOS device is coupled between the first layer of the one or more piezoelectric transducers and the substrate.

[0019] According to a further aspect, the CMOS device includes a BEOL layer and a FEOL layer, where the BEOL layer is a metallization layer and the FEOL layer is a transistor layer connected between the BEOL layer and a substrate.

[0020] According to an additional aspect, the transceiver also includes an insulating layer coupled between the first layer of the one or more piezoelectric transducers and the CMOS device.

[0021] According to a further aspect, the transceiver also includes metal vias connecting the electrical connector to the CMOS device.

[0022] According to an additional aspect, the transceiver also includes electrical pads connected to the electrical connector and extending to at least an outer surface of the first or second layer of the one or more piezoelectric transducers.

[0023] According to an additional aspect, the substrate has a backside having a pattern.

[0024] According to an additional aspect, the second layer of the one or more piezoelectric transducers comprises at least one space between two of the one or more piezoelectric transducers.

[0025] According to an additional aspect, at least one of the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers is a large transducer.

[0026] According to an additional aspect, in at least one of the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers, the piezoelectric transducers are connected in series.

[0027] According to an additional aspect, in at least one of the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers, the piezoelectric transducers are connected in parallel.

[0028] According to an additional aspect, at least one of the one or more piezoelectric transducers of the first layer or the second layer emits ultrasonic waves toward the substrate, and at least one of the one or more piezoelectric transducers is positioned based on a wave focus determined by wave focusing due to ultrasonic anisotropic wave propagation in the anisotropic substrate.

[0029] According to yet another aspect, a transceiver includes a substrate having a first surface and an opposing second surface. The transceiver also includes a first layer of one or more piezoelectric transducers attached to the first surface of the substrate, a buffer layer attached to the first layer of one or more piezoelectric transducers, and a second layer of one or more piezoelectric transducers attached to the buffer layer. The buffer layer is between the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers. The first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers are connected in a circuit with one or more transistor switches. The transistor switches can be turned on or off to achieve reconfigurability between a first configuration and a second configuration.

[0030] According to another aspect, in a first configuration, one or more piezoelectric transducers of at least one of the first and second layers transmit in parallel, and in a second configuration, one or more piezoelectric transducers of at least one of the first and second layers transmit in series.

[0031] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0032] The present invention will be more fully understood and appreciated by reading the following detailed description in conjunction with the accompanying drawings, in which: The accompanying drawings illustrate only exemplary embodiments of the disclosed subject matter, and therefore should not be considered as limiting its scope, since the disclosed subject matter may admit of other equally effective embodiments. Reference will now be made briefly to the accompanying drawings, in which: [Brief description of the drawings]

[0033] [Figure 1A] 1 is a schematic cross-sectional view of a piezoelectric transducer mounted on a solid, according to one embodiment. [Figure 1B] 1 is a graph of a typical pulse amplitude curve received on a transducer after emitting a short pulse. [Figure 2A] 1 is a schematic cross-sectional view of a piezoelectric stack, according to one embodiment. [Figure 2B] 13 is a schematic cross-sectional view of a piezoelectric stack according to an alternative embodiment. [Figure 2C] 13 is a schematic cross-sectional view of a piezoelectric stack according to another alternative embodiment. FIG. [Figure 2D] 13 is a cross-sectional schematic diagram of a piezoelectric stack according to yet another embodiment. [Figure 3A]

[0100] FIG. 1 is a graphical illustration of ultrasonic focusing patterns along crystal planes in oriented crystalline silicon. [Figure 3B] Figure 3A is a graphical representation of the receiving transformer array transducer on the anisotropic focusing pattern. [Figure 3C] 1A-1C are graphical and schematic diagrams of volume transverse waves generated and received using interdigitated transducers; [Figure 3D] 1 is a schematic cross-sectional side view of an electric field between fingers generating stress in a piezoelectric film; [Figure 4] FIG. 2 is a schematic diagram of a transducer having an HBAR resonator formed in its center, according to one embodiment. [Diagram 5] FIG. 13 is a schematic diagram of a transducer having a centrally formed HBAR resonator according to an alternative embodiment. [Figure 6] FIG. 1 is a schematic diagram of transducers in a transmitter transducer array, all connected in parallel and in series. [Figure 7A] FIG. 7 is a schematic diagram of the circuitry of the transmit transducer array of FIG. [Figure 7B] FIG. 2 is a schematic diagram of transducers and transistor switches in a parallel transmit transducer array. [Figure 7C] FIG. 2 is a schematic diagram of transducers and transistor switches in a serial transmit transducer array. [Figure 8A] FIG. 1 is a schematic diagram of a receive transducer transformer array with each transducer connected in series and connected to a transistor load. [Figure 8B] FIG. 8B is a schematic diagram of a capacitive voltage divider having capacitance of the receive transducer array of FIG. 8A. [Figure 8C] This is the formula for determining the received voltage on the amplifier input. [Figure 9A] FIG. 1 is a schematic diagram of an acoustic transformer receiving transducer connected in series with a diode rectifier load. [Figure 9B] FIG. 1 is a schematic diagram of an acoustic transformer receiving transducer connected by increasing the received voltage from a diode rectifier. [Figure 9C] FIG. 1 is a schematic diagram of a multi-stage rectifier circuit formed from integrated circuit capacitors and diodes. [Figure 10] FIG. 2 is a schematic diagram of a drive transducer. [Figure 11] 1 is a typical current versus voltage curve for a rectifier diode showing leakage and current; [Figure 12] 1 is a schematic diagram of a stacked transducer used in the transformer model. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Aspects of the present invention, as well as certain features, advantages, and details thereof, are described more fully below with reference to non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known structures are omitted so as not to obscure the invention in unnecessary detail. It should be understood, however, that the detailed description of the invention and the specific non-limiting examples thereof, while illustrating aspects of the present invention, are given by way of illustration only and not by way of limitation. Various substitutions, modifications, additions, and / or arrangements within the spirit and / or scope of the underlying inventive concept will be apparent to those skilled in the art from this disclosure.

[0035] The apparatus and method described herein details a method for increasing the voltage level of an ultrasonic signal received at a piezoelectric transducer. The method described involves the integration of the transducer with transistors in a CMOS integrated circuit to process the signal and energy contained in the ultrasonic pulse. The objective of the invention is to convert an input voltage to a higher voltage. In most applications, an increase in voltage is desired, but in some applications a decrease in voltage is desired, which can be achieved with the described device by reversing the transmit and receive ports. One example of such an application is the voltage conversion from 120 VAC at the wall AC voltage to 5 volts DC.

[0036] Referring now to FIG. 1A, a cross-sectional schematic diagram of a piezoelectric transducer 1 mounted on a solid body is shown, according to one embodiment. In FIG. 1A, the piezoelectric transducer 1 is mounted on a substrate 2. The substrate 2 shown is a CMOS substrate (CMOS layer 2A), but may also be a non-CMOS substrate. For example, the substrate 2 may be a silicon wafer, a SiC wafer, or a fused silica wafer. According to one embodiment, the thickness of the substrate 2 is in the range of 100 μm to 750 μm, which allows pulses to be transmitted and received at different times by the transducer 1 disposed on the top surface of the substrate 2. The transducer 1 may be disposed on the top and / or bottom of the substrate 2. In the embodiment shown in FIG. 1A, the piezoelectric transducer 1 is disposed on the top of the substrate 2.

[0037] When driven with a pulse of voltage, the piezoelectric transducer 1 emits an ultrasonic pulse 3. The pulse 4 can travel to the bottom of the substrate 2 and be reflected. The signal is received by the top transducer 1 for conversion back to an electromagnetic signal. Pulse 5 represents a pulse on its way back to the normal. Pulse 6 travels at an angle to the normal, which can be arranged by firing the array of transducers 1 at different phases and time delays s, as is done in RADAR and SONAR systems. Pulse 7 is reflected at an angle. FIG. 1A also shows a stationary wave 8 in the bulk substrate 2 when the drive signal is applied continuously or for a long time compared to the transit time of pulse 3. According to one embodiment, at a frequency of 1-GHz, the ultrasound has a wavelength of ∼9 microns, generating a 1-GHz wave train of 10-20 cycles, occupying a space of 90 μm to 180 μm deep.

[0038] FIG. 1B shows a typical pulse amplitude curve received on the transducer 1 after launching a short pulse 10. The pulse 10 is the received signal due to RF coupling from the driving transducer to the receiving transducer (note, the transducer 1 is shown generally in FIG. 1A). FIG. 1B also shows the received first reflected signal 9. The time difference corresponds to C / 2L, where C is the speed of sound and L is the thickness of the substrate 2. As depicted in FIG. 1B, the amplitude of the received first reflection and the resulting reflections can be small, in the range of tens of millivolts. In order to process this signal for signal amplitude extraction or demodulation using a mixer, it is desirable to amplify this signal to as high a voltage as possible. This requires a high gain amplifier that consumes power and reduces the SNR. Therefore, a passive approach to increase the amplitude is desired.

[0039] Referring now to FIG. 2A, a cross-sectional schematic diagram of a piezoelectric stack 100 is shown, according to one embodiment. The piezoelectric stack 100 can have a transducer that sends energy towards the bottom of the transducer where it can be reflected by being affected by the reflection coefficient of the interface between the substrate and the bottom body. To maximize the reflected energy, the interface can be made of a material with a very different acoustic impedance than the substrate. The material can be a soft material such as a polymer with a much lower impedance than the silicon substrate. Examples of polymers include silicon, PDMS, SU8, epoxy, glue. Another material is a soft polymer with metal nanoparticles that have a higher ultrasonic impedance to absorb the ultrasonic energy reducing the reflection of the ultrasonic waves. The material can also be an air gap by supporting the chip to a packaging layer at the end. The air gap gives a very high reflection coefficient. The backside can be patterned with different boundary conditions of absorption and reflection to control the ultrasonic distribution within the substrate. With the returning pulse, the energy is received by many smaller transducers in series.

[0040] The piezoelectric stack 100 includes a top insulating layer 101 that can be used to tailor the acoustic response of the piezoelectric stack 100 through its thickness and acoustic impedance. The piezoelectric stack 100 also includes electrodes 102 extending across the piezoelectric layers PI 103 and P2 105 for exciting and sensing charge due to mechanical waves excited in the substrate 109. The thickness and material of the electrodes 102 (i.e., electrode layers) can affect the acoustic impedance and therefore can be optimized to achieve optimal transmit-receive characteristics. The piezoelectric layers 103, 105 are made of AlN (aluminum nitride) or AlScN (or Al x Sc y N) and other thin files such as ZnO The two piezoelectric layers 103, 105 can be insulated (i.e., separated) by an ultrasonic buffer layer 104 (i.e., an insulating dielectric layer) having a thickness and ultrasonic impedance to maximize the coupling of the transmitter and receiver energy into the resonator.

[0041] 2A, the PI layer 103 is shown to be one large transducer with the top and bottom electrodes 102 connected together. The P2 layer 105 is split into smaller transducers, but connected in series. Thus, the P1 layer 103 is one large transducer and the P2 layer 105 is multiple transducers cascaded in series. The transducer is a 100-mV dielectric. The outgoing wave packet is sent through the silicon substrate 109 and received by multiple transducers in series (in the P2 layer 105), while a resonant mode can be set up within the thickness of the silicon crystal substrate 109. The thickness of the isolating SiO2 layer 104 can be optimized to maximize the signal on the receiving transducer by spacing them at half-wavelength intervals. Instead of just one layer, other insulating layers, or combinations of insulating layers, can be used. The buffer layer 104 itself is an electrical insulator, which can be made of sublayers to achieve optimal coupling.

[0042] In another embodiment, an additional insulator layer (not shown) is used on top of the piezoelectric layers 103, 105 to act as a passivation layer and to acoustically load the top and bottom piezoelectric transducer stacks to control the frequency response of the first and second piezoelectric layers 103, 105. Depending on the material selection for the metal electrode 102 and the piezoelectric layers 103, 105, a seed layer may be required under the bottom electrode 102 on the substrate 109 to orient the crystallinity of the piezoelectric material. Typical choices of materials are Molybdenum for the electrode layer 102, AlN or Al for the piezoelectric layers 103, 105. x Sc y The layers would consist of a GaN seed layer, SiO 2 for the insulator layer 104 and an AlN seed layer for the top passivation layer, and an AlN seed layer for the bottom electrode 102.

[0043] In FIG. 2A, the transducer is shown to be fabricated on a CMOS substrate 107, 108, where FEOL refers to the transistor front-end-of-line CMOS layers 108 and BEOL refers to the back-end-of-line CMOS metallization layers 107. An insulator layer (such as silicon dioxide) 106 is required to insulate the bottom electrode 102 from the CMOS top metal 107. The insulator layer 106 is required for the CMOS (e.g., CMOS BEOL) to be fabricated on a CMOS substrate 107. The CMOS FEOL layer 108 has metal vias 111 that connect the top connections in the FEOL layer 107 to the transducer through more layers of vias 110. These vias 111 electrically connect the various metal layers so that the receiving transducer electrodes 102 can be cascaded in series. The vias 111 are also used to connect the transducer electrodes 102 to the CMOS metallization 107, 108 for connection to the CMOS circuitry. The CMOS transistor layer 108 (CMOS FEOL layer 108) senses and drives the piezoelectric transducers on the device. The circuit can be connected to one of the piezoelectric transducers and used to drive ultrasonic waves and pulses within the volume of silicon 109. The receiving transducer can be connected to a transistor for energy processing.

[0044] Referring now to Figure 2B, there is shown a cross-sectional schematic diagram of a piezoelectric stack 100 according to another embodiment. This stack 100 is similar to the stack 100 shown in Figure 2A, but omits the top buffer layer 101. Additionally, the P2 piezoelectric layer 103 of the stack 100 of Figure 2B is etched away to better isolate the different transducers from air.

[0045] Referring to Figure 2C, a cross-sectional schematic diagram of a piezoelectric stack 100 is shown according to another alternative embodiment. The stack 100 in Figure 2B is similar to that shown in Figure 2A, with the continuous transducer layer P1 105 and the split transducer layer P2 103 switched. This configuration may result in better electrical performance by connecting a different number of vias 110 to the transmitter than to the receiver, since each via adds parasitic capacitance to the transducer.

[0046] Referring to Figure 2D, a schematic cross-sectional view of a piezoelectric stack 100 according to yet another embodiment is shown. The stack 100 in Figure 2D is similar to that in Figure 2A, except that now there are no CMOS substrates 107, 108 and no active electronics. Here, the transducers are connected to exposed connecting electrical pads 112 on the top. Such a transformer The transducer can be connected to the CMOS of off-the-shelf electronics via commonly used methods such as wire bonding, ball grid array, and flip chip bonding. Substrate 109 can be any substrate made of silicon, germanium, fused silica, or other materials.

[0047] The structure described in Figure 2 is for one transformer unit. The units themselves can be arranged in series and parallel to achieve the desired input and output impedance while providing voltage transformation.

[0048] In a configuration of multiple transducers in the same plane, each of the transducers receives or is exposed to approximately the same ultrasonic velocity and strain field, and each generates a voltage across it. The uniformity of the strain will be a function of how well the acoustic field reflections are designed so that the strain fields at the transducers are in phase. Due to the ultrasonic strain in the transducers, each of the pulse transducers generates a charge proportional to its area, and the voltages of each transducer are added in series to achieve a higher voltage due to the piezoelectric effect. When this voltage is applied to the input node of a transistor gate that is part of an amplifier, it conducts a current through the transistor in a typical common source or common drain amplifier configuration. The transistor current can generate an output voltage through a load impedance. Typically, an amplifier requires a DC bias current to function the transistor in an amplifying state. In general, an amplifier can consist of several stages of biased transistors. By allowing a higher input voltage to the amplifier, a lower gain can be required from the electronic amplifier without consuming power using a transformer structure. This lowers the bias current of the amplifier subcomponents, reducing power consumption of the amplifier and the entire sensor and imager device.

[0049] Since the noise voltage of a transistor amplifier is typically proportional to the power and size of the transistor, a larger voltage signal provides a higher signal and therefore a higher signal-to-noise ratio (SNR). By reducing the required electronic gain, the input signal can be made larger than the equivalent electrical noise of the transistor circuit, and therefore a higher SNR can be obtained. In some applications, such as energy harvesting, energy coming from an RF signal is converted to a DC voltage and stored for use in powering a circuit. If the higher voltage signal generated by the series connection is placed in a diode rectifier circuit as an energy detector or energy recovery element to rectify the input signal, the effectiveness of the energy transfer is higher for higher input voltages. Diodes require a voltage above a certain turn-on voltage to be able to drive current into a load, and the current is a function of the voltage above the threshold voltage. The higher the voltage, the more current can flow through the rectifier, reducing the effective resistance of the diode, thereby reducing the power consumed in transferring power across the diode.

[0050] Figure 11 shows the current vs. voltage curves for the diodes used to convert the oscillating voltage to a DC voltage stored on a capacitor. As shown, the current increases exponentially with the effective resistance of each diode as the input voltage decreases. Additionally, leakage currents are shown that limit the maximum voltage that can be reached by the amplifier.

[0051] A detailed analysis of a voltage amplifier or transformer utilizing two transducer layers separated by a buffer, described below, is explained using the following equations:

[0052]

number

[0053]

number

[0054] These equations are generally called constitutive equations that connect the electrical and mechanical variables associated with the piezoelectric layers. Four layers can be assumed for this one-dimensional model of the laminate transducer. Figure 12 shows a schematic diagram of the laminate transducer used in the model above. The first layer is the top piezoelectric layer used as a transmitter from x=0 to x=x1. This transducer can be the driving transducer or the input transducer that drives the entire laminate. The next layer can be a SiO2 layer from x=x1 to x=x2. The third layer is a receiving layer from x=x2 to x=x3. The fourth layer can be bulk silicon x=x3 to x=x4, where x i The values ​​of the variables are chosen to correspond to the thickness of the AlN and buffer layer, and the thickness of the silicon wafer. Equations 1 and 2 are used to integrate over the piezoelectric layer.

number

[0055] The electric field equation is the definition of the electric field as a function of the electric potential φ(x). The above integral for the receiving transducer goes from x=x2 to x=x3, and if V is defined to be positive at x=x2 and ground at x=x3, then we get V as the answer to the integral.

number

[0056] where u[x] is the ultrasonic displacement in the lamination in the receiving transducer. If the receiving transducer is resolved into N transducers, each transducer will generate 1 / N of the current.

number

[0057] The receiving transducer has a load impedance Z LAssume that the transducer is connected to a load impedance of 100 kV. The load impedance can be the amplifier input impedance or the load of a rectifier for RF energy harvesting. The current from this transducer drives the load to generate a voltage.

number

[0058] If the current I is defined as the current going into the transducer, then I has a negative sign because the current goes into the transducer. With this assumption, I can be written as can be done.

number

[0059] Here, V out =N*V is the voltage each of the transducers produces, V. Therefore,

number

[0060] All of this is N and 1 / jωC ox Multiplying by .

number

[0061] This voltage V is the voltage at the output of each of the segmented transducers. The distortion of the receive transducer is due to the drive / transmit transducer. The distortion of the receive S(x) is due to the voltage V in The distortion of the driver transducer driven by

number

[0062] Now, let us assume that the transmitter sets up a resonant system with a quality factor Q, e / y V in / t aln is the effective d related to the commonly used piezoelectric constitutive equation 33 Given E distortion, the factor d(x) is a factor that depends on how well the distortion is distributed across the receiving transducer and receiver.

number

[0063] The integral is the integral over x, and therefore the factor Γ×t ain can be written as:

number

[0064] This is simplified as follows:

number

[0065] Here, K 2 =e 2 / εY' is often called the electromechanical coupling constant. The voltage V is the voltage of one transducer, so the voltage across the transducers in series is:

number

[0066] This formula means that if N increases, the voltage increases, but if N 2 The factor Z indicates the voltage decrease. L As increases, the voltage increases and C AlNAs the quality factor increases, the voltage also increases. If the quality factor increases, the result of more ultrasonic amplitude building up in the resonator results in an increase in the output voltage. Now referring to FIG. 9A, an application is shown in which a series connection of acoustic transformer receiving transducers is connected in series with a diode rectifier load, for example an RFID transponder. The series connection of the transducers results in a higher input voltage being supplied to the diode rectifier (as described above). This higher input voltage allows the diode rectifier to operate in a higher efficiency regime, resulting in a higher conversion efficiency for the input RF power.

[0067] It can be incorporated into any of the other methods described herein. Another approach to amplifying the voltage uses the natural ability of crystalline anisotropic materials to focus the ultrasonic waves and corresponding mechanical energy to a specific location where the receiving transducer is specifically positioned to extract the energy. Anisotropic crystals have the ability to redirect the energy flow toward the focal point due to group velocity differences along different crystal axes. Under certain circumstances, the waves bend toward a central location determined by the transducer geometry and the reflecting boundary conditions of the substrate 109 (Figures 2A-2D). The transmitting and receiving electrodes 102 (Figures 2A-2D) are positioned such that the generated acoustic waves are focused due to the anisotropy of the crystal.

[0068] When the transformer transducer array is fabricated on an anisotropic substrate such as silicon, the transducer array can be placed in specific locations to achieve maximum signal. It is known that in anisotropic substrates, focusing effects can be observed for ultrasound waves when the ultrasound propagates more preferentially on certain crystal planes. The focusing pattern of ultrasound along crystal planes in 0100 oriented crystalline silicon, represented by the dark areas in FIG. 3A, is where the ultrasound waves are focused. In FIG. 3A, ST and FT refer to slow and fast shear waves, respectively. Therefore, to achieve maximum received signal, the receiving transformer transducer array 200 should be placed in those regions, as shown in FIG. 3B. Thus, FIG. 3B shows the optimal placement of the transducers to maximize the received signal by placing the transducers in areas where energy is concentrated due to focusing due to anisotropic wave propagation.

[0069] Each rectangle in the figure represents a transducer 200 consisting of one transducer unit or a combination of transducer units cascaded in series or parallel. These transducers 200 are then connected in series to increase the transducer output voltage. Different ways of connecting these unit transducers 200 in series are shown in FIG. 3B. For example, these receiving transducers 200 can be placed on the same side of the substrate as the transmitting part of the transformer, or on the opposite side of the substrate. Also, in the embodiment of FIG. 3B, the transducers 200 are transverse mode BAW transducers in receiving mode. Volume transverse waves can be generated and received using interdigitated transducers, as shown in FIG. 3C. In FIG. 3D, the electric field between the fingers generates stress in the piezoelectric film. By placing a set of electrodes on the transmitting side that are all connected together in transmitting mode, but then segmenting the electrodes so that the electrodes with the highest intensity are electrically isolated from the non-focused regions, the receiving waves will generate a higher voltage due to their higher intensity.

[0070] In Figures 4 and 5, an alternative method of increasing the voltage level received on the receiving ultrasonic transducers is shown. The transducer comprises a transmitter 300 with an outer transducer 301, and a receiving transducer 302 at the center of a circle (generated by the shape of the outer transducer 301). The inner, receiving transducers 302 are connected in series. The transmitted pulse from the outer transducer 301 undergoes diffraction and a significant fraction of the energy is received by the inner, receiver transducer 302. The outer diffracted waves can be lost or a secondary transducer can be used to pick up the diffracted energy. The inner, receiving transducers 302, where most of the energy is collected, can be connected in series to increase the voltage higher than if that area was occupied only by one large transducer.

[0071] In figures 4 and 5, energy is focused through diffraction and HBAR action. Figure 4 shows an HBAR resonator formed in the center. The diffracted wave is received at the receiving electrodes 301, 302. The quality factor boosts the voltage and the series connection also increases the voltage. In figure 5, an HBAR resonator is also formed in the center. The diffracted wave is received at the receiving electrodes 301, 302 and the quality factor of the resonator and the series connection of the receiving transducer serve to boost the received voltage.

[0072] In another approach to increasing the voltage generated from the piezoelectric transducers shown in FIG. 6 to continue amplifying the signal, the transducers T1, T2, T3 in the transmit transducer array 400 are all connected in parallel in a transmit mode generating an ultrasonic uniform pulse packet or continuous wave signal into the substrate. However, during the pulse transit time, some time after driving, when the energy in the substrate is accumulated by the continuous wave operation, or when the pulse returns, the transducers T1, T2, T3 are connected in series such that the voltages are placed in series. This approach requires a set of transistor switches 401, such as realized by CMOS transistors, to toggle between two different types of connections (parallel and series). If the transistors are closely integrated in close proximity to the transducers T1, T2, T3, the parasitic capacitance of the wiring can be reduced. Figs. 7A-7C show the circuits when the transducers T1, T2, T3 are in parallel and when the transducers T1, T2, T3 are in series.

[0073] Referring now to FIG. 8A, a receiver transformer transducer array is shown, with each transducer connected in series as in FIGS. 6-7C and connected to a transistor load representing the input stage of a transistor amplifier circuit. This transistor load has a load capacitance C elec This transistor load can be modeled as: This transistor load forms a capacitive voltage divider with the capacitance of the receiving transducer array, which, when driven in parallel, reduces the total capacitance of the transducer to C O Then, C O / n 2 Thus, the received voltage on the amplifier input is C, where the effect of radiation resistance is neglected in favor of the clamped capacitance which dominates the impedance of the transducer.

[0074] Typical gate capacitance values ​​for CMOS transistors can range from a single femtofarad to tens of femtofarads in commonly available technologies such as 65 nm, 130 nm, or 180 nm gate length technologies. The following example shows that the voltage present at the amplifier gate input is greater with the use of a series-connected acoustic transformer array as opposed to a single transducer of the same area.

[0075] The capacitance of a 200 mm x 200 mm square transducer AlN film with a thickness of 2 mm is about 1.6 pF. For an acoustic transformer, if this larger transducer were divided into an array of seven transducers, the combined series capacitance would be about 0.0325 pF. Assuming a total gate, source-drain, and junction capacitance of 10 fF, the voltage at the transistor gate would be about 5.39 times higher using the series connected transducer array transformer than using a single transducer. This simple analysis is meant to illustrate the functionality of the devices described herein. There may be additional variables such as the series resistance of the switching transistor that would limit the current output of the transducer and cause a higher parasitic capacitance to be present in parallel with the transistor. The transmission gate configuration of the switch in CMOS has an effective on-state resistance that is inversely proportional to the transistor size W / L, where W is the width of the transistor and L is the length of the transistor. Therefore, an optimized device will trade off the size of the switch transistor to reduce the on-state resistance and parasitic capacitance.

[0076] Another method of connecting an acoustic transformer transducer array to increase the received voltage from a diode rectifier is shown in Figure 9B. The transducers are connected in series as in 9A, but in a cascaded configuration (with cascaded diodes). In Figure 9B, the positive terminal of each transducer is also connected to a diode rectifier. This concept is similar to the use of integrated circuit capacitors and diodes to form a multi-stage rectifier circuit shown in Figure 9C, but with the RF input coupling capacitors replaced by series-connected transducers.

[0077] Referring now to FIG. 10, the driven transducer is shown with an equivalent capacitance C0 and a resonator R rad We have shown a larger transducer with an equivalent radiation resistance of . When driven off resonance, two additional components, an equivalent mechanical inductance and a capacitance, are in series with the radiation resistance. The larger transducer generates a mechanical pulse wave train that travels through the silicon volume and returns to the receiving transducer. When the pulses return to the series receiving transducer, they would ideally be distributed equally across the n smaller transducers. However, due to diffraction and material losses, they will receive less energy than ideally. In the ideal case, the equivalent capacitance C O / n and exercise resistance nR rad Each transducer has a C O / n indicates n small capacitances. In the case of series, the effective capacitance is C O / n 2 The input impedance of a typical transistor amplifier consists of the gate capacitance and the source-drain parasitic capacitance, which can range from one to several tens of femtofarads.

[0078] Although embodiments of the present invention have been particularly shown and described with reference to certain exemplary embodiments, those skilled in the art will understand that various changes in detail can be made without departing from the spirit and scope of the invention as defined by the claims which may be supported by the written description and drawings. Moreover, when an exemplary embodiment is described with reference to a certain number of elements, it will be understood that the exemplary embodiment may be implemented utilizing either fewer or more than the certain number of elements.

Claims

1. a substrate having a first surface and an opposing second surface; a first layer of one or more piezoelectric transducers attached to the first surface of the substrate; a buffer layer attached to the first layer of the one or more piezoelectric transducers; a second layer of one or more piezoelectric transducers attached to the buffer layer such that the buffer layer is between the first layer and the second layer of the one or more piezoelectric transducers; 1. A transceiver apparatus for maximizing voltage, comprising: the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers are connected in a cascade configuration via an electrical connector. Transceiver device.

2. 10. The transceiver apparatus of claim 1, further comprising: a top insulating layer attached to an outer surface of a second one of the one or more piezoelectric layers.

3. a CMOS device including one or more CMOS circuits; the CMOS device is connected between a first layer of the one or more piezoelectric transducers and the substrate; 2. The transceiver device according to claim 1.

4. the CMOS device includes a BEOL layer and a FEOL layer; the BEOL layer is a metallization layer and the FEOL layer is a transistor layer connected between the BEOL layer and the substrate; 4. The transceiver device according to claim 3.

5. 4. The transceiver apparatus of claim 3, further comprising: an insulating layer connected between the first layer of the one or more piezoelectric transducers and the CMOS device.

6. 4. The transceiver apparatus of claim 3, further comprising: a metal via connecting said electrical connector and said CMOS device.

7. 10. The transceiver apparatus of claim 1, further comprising: an electrical pad connected to the electrical connector and extending to at least an outer surface of the first layer of the one or more piezoelectric transducers or the second layer of the one or more piezoelectric transducers.

8. The transceiver device of claim 1 , wherein the substrate has a backside having a pattern thereon.

9. 10. The transceiver apparatus of claim 1, wherein the second layer of the one or more piezoelectric transducers comprises at least one space between two of the one or more piezoelectric transducers.

10. 2. The transceiver apparatus of claim 1, wherein at least one of the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers is a large transducer.

11. 2. The transceiver apparatus of claim 1, wherein in at least one of the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers, the piezoelectric transducers are connected in series.

12. 2. The transceiver apparatus of claim 1, wherein in at least one of the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers, the piezoelectric transducers are connected in parallel.

13. At least one of the first layer of the one or more piezoelectric transducers or the second layer of the one or more piezoelectric transducers emits ultrasonic waves toward the substrate; At least one of the one or more piezoelectric transducers is positioned based on a wave focus determined by anisotropic wave focusing.

2. The transceiver device according to claim 1.

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