Device and method for internal horizontal sync signal generation

Abstract

To prevent a malfunction of a display device which is generated by a timing failure caused by unintended noise induction to an internal Hsync signal and / or an internal Vsync signal.SOLUTION: A display driver includes a timing controller and a drive circuit. The timing controller receives an external horizontal sync signal and generates an internal horizontal sync signal based on the external horizontal sync signal. The drive circuit drives a display panel in synchronization with the internal horizontal sync signal. Generating the internal horizontal sync signal includes: generating a first pulse of the internal horizontal sync signal in response to detection of a first pulse of the external horizontal sync signal after a masking period has expired, wherein the masking period starts when a first previous pulse is detected in the external horizontal sync signal; and generating a second pulse of the internal horizontal sync signal in response to detection of a second pulse of the external horizontal sync signal in a non-masking period, wherein the non-masking period starts when a second previous pulse is detected in the external horizontal sync signal.SELECTED DRAWING: Figure 7A

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates generally to display devices, and more particularly to generation of an internal horizontal synchronization signal in a display device. [Background technology]

[0002] A display driver configured to drive a display panel (e.g., a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, a micro light emitting diode (μLED) display panel, etc.) may be configured to externally receive horizontal and vertical synchronization signals from an external controller and operate in synchronization with the horizontal and vertical synchronization signals. The horizontal synchronization signal may define the start and end of each horizontal synchronization period (or line period), and the vertical synchronization signal may define the start and end of each vertical synchronization period (or frame period). The externally received horizontal synchronization signal may be hereinafter referred to as an external horizontal synchronization signal, and the externally received vertical synchronization signal may be hereinafter referred to as an external vertical synchronization signal.

[0003] The display driver may generate internal horizontal and vertical synchronizing signals from the external horizontal and vertical synchronizing signals, respectively, for internal use. More specifically, the display driver may generate an internal horizontal synchronizing signal pulse in response to detecting a pulse of the external horizontal synchronizing signal, and may generate an internal vertical synchronizing signal pulse in response to detecting a pulse of the external vertical synchronizing signal. The internal horizontal and vertical synchronizing signals thus generated may be used for timing control of the display driver. Summary of the Invention

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below. It is not intended to necessarily identify key features or essential features of the present disclosure. The present disclosure may include various aspects and embodiments described below.

[0005] In an exemplary embodiment, the present disclosure provides a display driver. The display driver includes a timing controller and a driving circuit. The timing controller is configured to receive an external horizontal synchronizing signal and generate an internal horizontal synchronizing signal based on the external horizontal synchronizing signal. The driving circuit is configured to drive a display panel in synchronization with the internal horizontal synchronizing signal. The generating the internal horizontal synchronizing signal includes generating a first pulse of the internal horizontal synchronizing signal in response to detecting a first pulse of the external horizontal synchronizing signal after a masking period ends. The masking period begins when the timing controller detects a first leading pulse of the external horizontal synchronizing signal prior to detecting the first pulse of the external horizontal synchronizing signal. The generating the internal horizontal synchronizing signal further includes generating a second pulse of the internal horizontal synchronizing signal in response to detecting a second pulse of the external horizontal synchronizing signal during a non-masking period. The non-masking period begins when the timing controller detects a second leading pulse of the external horizontal synchronizing signal prior to detecting the second pulse of the external horizontal synchronizing signal.

[0006] In another exemplary embodiment, the present disclosure provides a system. The system includes an external source and a display driver. The external source is configured to provide an external horizontal synchronization signal. The display driver is configured to generate an internal horizontal synchronization signal based on the external horizontal synchronization signal and drive a display panel in synchronization with the internal horizontal synchronization signal. Generating the internal horizontal synchronization signal includes generating a first pulse of the internal horizontal synchronization signal in response to detecting a first pulse of the external horizontal synchronization signal after a masking period ends. The masking period begins when the timing controller detects a first leading pulse of the external horizontal value synchronization signal prior to detecting the first pulse of the external horizontal synchronization signal. Generating the internal horizontal synchronization signal further includes generating a second pulse of the internal horizontal synchronization signal in response to detecting a second pulse of the external horizontal synchronization signal during a non-masking period. The non-masking period begins when the timing controller detects a second leading pulse of the external horizontal value synchronization signal prior to detecting the second pulse of the external horizontal synchronization signal.

[0007] In yet another exemplary embodiment, the present disclosure provides a method. The method includes receiving an external horizontal synchronization signal. The method further includes generating a first pulse of an internal horizontal synchronization signal in response to detecting a first pulse of the external horizontal synchronization signal after a masking period ends. The masking period begins when a first leading pulse of the external horizontal value synchronization signal is detected before the detection of the first pulse of the external horizontal synchronization signal. The method further includes generating a second pulse of the internal horizontal synchronization signal in response to detecting a second pulse of the external horizontal synchronization signal during a non-masking period. The non-masking period begins when a timing controller detects a second leading pulse of the external horizontal synchronization signal before the detection of the second pulse of the external horizontal synchronization signal. The method further includes driving a display panel in synchronization with the internal horizontal synchronization signal.

[0008] Further features and aspects are described in more detail below with reference to the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating an example configuration of a display device according to one or more examples of the present disclosure.

[0010] [Diagram 2] FIG. 2 illustrates an example technique for generating an internal horizontal synchronization signal and an internal vertical synchronization signal in accordance with one or more examples of this disclosure.

[0011] [Figure 3A] FIG. 3A illustrates an example signal masking performed on an external horizontal sync signal in accordance with one or more examples of the present disclosure. [Figure 3B] FIG. 3B illustrates an example signal masking performed on an external horizontal sync signal in accordance with one or more examples of the present disclosure.

[0012] [Figure 4]FIG. 4 illustrates example waveforms of the internal horizontal and vertical synchronization signals generated using the signal masking illustrated in FIGS. 3A and 3B, in accordance with one or more examples of the present disclosure.

[0013] [Diagram 5] FIG. 5 illustrates an example operation of a timing controller according to one or more examples of the present disclosure.

[0014] [Figure 6] FIG. 6 illustrates an example operation of a timing controller corresponding to modified signal masking, in accordance with one or more examples of the present disclosure.

[0015] [Figure 7A] FIG. 7A illustrates an example operation of a timing controller during vertical synchronization periods, each of which includes duration-adjusted horizontal synchronization periods, in accordance with one or more examples of this disclosure.

[0016] [Figure 7B] FIG. 7B illustrates another example operation of a timing controller during vertical synchronization periods, each of which includes duration-adjusted horizontal synchronization periods, in accordance with one or more examples of this disclosure.

[0017] [Figure 8] FIG. 8 is a flowchart of an exemplary process for driving a display panel in accordance with one or more examples of this disclosure.

[0018] For ease of understanding, the same reference numbers are used, where possible, to designate identical elements common to the figures. It is anticipated that elements disclosed in one embodiment may be beneficially used in other embodiments without specific mention. Reference numbers may be subscripted to distinguish identical elements from one another. The drawings referred to herein should not be understood to be drawn to scale unless specifically noted. Also, for clarity of presentation and explanation, the drawings are often simplified and details or components are omitted. The drawings and discussion serve to explain the principles discussed below. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The following detailed description is merely exemplary in nature and is not intended to be limiting of the disclosed technology or the application and uses of the disclosed technology, nor is there any intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.

[0020] In the following detailed description of the embodiments, many specific details are presented to provide a deeper understanding of the disclosed technology. However, it will be apparent to those skilled in the art that the disclosed technology can be implemented without using these specific details. In other instances, well-known configurations are not described in detail to avoid unnecessarily complicating the description.

[0021] The term "coupled" as used herein means directly connected or connected via one or more intervening components or circuits. Additionally, ordinal numbers (e.g., first, second, third, etc.) may be used throughout the application as adjectives of elements (i.e., any nouns in the application). The use of ordinal numbers is not intended to imply or create a particular ordering of any elements, nor is it intended to limit any element to only a single element, unless expressly disclosed, for example, by the use of "before," "after," "single," and other similar terms. Rather, the use of ordinal numbers is intended to distinguish elements. For example, a first element is distinct from a second element, and a first element may include more than one element and may follow (or precede) a second element in the ordering of elements.

[0022] A display driver configured to drive a display panel (e.g., an LCD panel, an OLED display panel, and a μLED display panel) may be configured to receive an external horizontal synchronization (Hsync) signal and an external vertical synchronization (Vsync) signal from an external controller and operate in synchronization with the external Hsync signal and the external Vsync signal. The external Hsync signal may define the start and end of each horizontal synchronization period (or line period), and the external Vsync signal may define the start and end of each vertical synchronization period (or frame period). A horizontal synchronization period may be defined as the period between the times when two adjacent pulses appear in the external Hsync signal, and a vertical synchronization period may be defined as the period between the times when two adjacent pulses appear in the external Vsync signal.

[0023] The display driver may generate an internal Hsync signal and an internal Vsync signal from an external Hsync signal and an external Vsync signal, respectively, for internal use. More specifically, the display driver may be configured to generate a pulse of the internal Hsync signal in response to detecting a pulse in the external Hsync signal, and to generate a pulse of the internal Vsync signal in response to detecting a pulse in the external Vsync signal. The internal Hsync signal and the internal Vsync signal thus generated may be distributed to various circuits (e.g., image processing circuits, panel interface circuits, and source driving circuits) within the display driver to achieve timing control.

[0024] In a real operating environment, noise such as electrostatic discharge (ESD) noise may affect the external Hsync signal and / or the external Vsync signal. The external Hsync signal and / or the external Vsync signal may include noise-induced pulses, which may cause unintended pulses to be generated in the internal Hsync signal and / or the internal Vsync signal. The unintended pulses may cause timing disturbances during operation, resulting in malfunction of the display device (e.g., image corruption).

[0025] One way to mitigate the effects of noise may be to perform signal masking on the external Hsync and / or Vsync signals. In one implementation, signal masking may be achieved by not allowing the display device to detect and / or process pulses in the external Hsync and / or Vsync signals during a masking period. For example, during signal masking, the display device may discard or filter out noise-induced pulses when it detects pulses in the external Hsync and / or Vsync signals, thereby allowing pulses in the internal Hsync and / or Vsync signals to be generated at the correct times.

[0026] In some implementations, synchronization between the external Hsync signal and the external Hsync signal may be achieved by adjusting the duration of a particular horizontal synchronization period among the horizontal synchronization periods of each vertical synchronization period. The particular horizontal synchronization period among the horizontal synchronization periods may be referred to as a duration-adjusted horizontal synchronization period hereinafter. In an ideal operation, it is desired that the external Hsync signal and the external Vsync signal are generated such that the period of the external Vsync signal is exactly an integer multiple of the period of the external Hsync signal (e.g., the frequency of the external Hsync signal is exactly an integer multiple of the frequency of the external Vsync signal). However, in practical implementations, the external Hsync signal and the external Vsync signal may be generated by different oscillators that do not have sufficient timing accuracy for pulse generation. In such implementations, the period of the external Vsync signal may differ significantly from an integer multiple of the period of the external Hsync signal. To synchronize the external Hsync signal with the external Vsync signal, the duration of the duration-adjusted horizontal synchronization period among each vertical synchronization period may be adjusted so that the end of the last horizontal synchronization period of each vertical synchronization period coincides with the start of the next vertical synchronization period. The duration of a duration-adjusted horizontal sync period may differ from the duration of other horizontal sync periods.

[0027] This disclosure recognizes that the use of duration-adjusted horizontal sync periods may not be consistent with signal masking applied to the external Hsync signal because the signal masking may undesirably discard pulses that define the duration-adjusted horizontal sync period. This disclosure provides various techniques that may be used to properly generate an internal Hsync signal in a display device that is configured to provide signal masking to the external Hsync and / or Vsync signals.

[0028] 1 is a block diagram illustrating an example configuration of a display device 1000 according to one or more examples of the present disclosure. In the illustrated embodiment, the display device 1000 includes a display driver 100 and a display panel 200. Examples of the display panel 200 include, but are not limited to, an LCD panel, an OLED display panel, a μLED display panel, and other display panels of suitable display technologies.

[0029] The display driver 100 is configured to receive image data from an image source 300 and drive or update the display panel 200 based on the image data. In the illustrated embodiment, the display driver 100 includes an interface (I / F) 110, an image buffer 120, an image processing circuit 130, and a driving circuit 140. The interface 110 is configured to receive image data from the image source 300 and transfer the received image data to the image buffer 120. The image buffer 120 is configured to temporarily store the image data. The image processing circuit 130 is configured to receive image data from the image buffer 120 and process the received image data to generate processed image data. The image processing circuit 130 is further configured to provide the processed image data to the driving circuit 140. The driving circuit 140 is configured to drive or update the display panel 200 based on the processed image data. In one implementation, the driving circuit 140 is configured as a source driver that generates data voltages based on the processed image data and drives or updates pixels of the display panel 200 with the generated data voltages.

[0030] The display driver 100 is further configured to receive an external vertical synchronization (Hsync) signal and an external vertical synchronization (Vsync) signal from an external source 400 and operate in synchronization with the external Hsync signal and the external Vsync signal. The external Hsync signal may define the start and end of each horizontal synchronization period (or line period), and the external Vsync signal may define the start and end of each vertical synchronization period (or frame period). In some implementations, the external source 400 may be a bridge integrated circuit (IC) or other type of IC configured to interface with the display driver 100. In other implementations, the external source 400 may be a master display driver configured to provide the external Hsync signal and the external Vsync signal to the display driver 100. In such implementations, the display driver 100 may operate as a slave display driver and cooperate with the master display driver to update the display panel 200. Although FIG. 1 illustrates the external source 400 as a separate device from the image source 300, the image source 300 and the external source 400 may be formed as a single device.

[0031] In the illustrated embodiment, the display driver 100 further includes an interface 150 and a timing controller 160. The interface 150 is configured to receive an external Hsync signal and an external Vsync signal from an external source 400 and transfer the external Hsync signal and the external Vsync signal to the timing controller 160. The timing controller 160 is configured to generate an internal Hsync signal and an internal Vsync signal from the external Hsync signal and the external Vsync signal, respectively. The internal Hsync signal and the internal Vsync signal are used for timing control in the display driver 100. More specifically, the timing controller 160 is further configured to supply the internal Hsync signal and the internal Vsync signal to the drive circuit 140, thereby controlling the operation timing of the drive circuit 140. The drive circuit 140 is configured to drive the display panel 200 in synchronization with the internal Hsync signal and the internal Vsync signal. The timing controller 160 may further be configured to provide the internal Hsync signal and / or the internal Vsync signal to other circuits of the display driver 100, which may include the image processing circuit 130. The image processing circuit 130 may be configured to process image data using the internal Hsync signal and / or the internal Vsync signal.

[0032] In the illustrated embodiment, the timing controller 160 includes a register 165. In some implementations, the register 165 may be configured to store information used to control the generation of the internal Hsync and Vsync signals.

[0033] 2 illustrates an example approach for generating an internal Hsync signal and an internal Vsync signal according to one or more examples of the present disclosure. Illustrated in FIG. 2 is an example operation of the timing controller 160 for generating an internal Hsync signal and an internal Vsync signal during vertical synchronization periods 500 and 502. Each of the vertical synchronization periods 500 and 502 includes a blanking period 410 (also referred to as a back porch period), a display update period 420, and a blanking period 430 (also referred to as a front porch period). The blanking period may also be referred to as a non-display update period.

[0034] The timing controller 160 is configured to detect a pulse of the external Hsync signal and generate a pulse of the internal Hsync signal in response to detecting the pulse of the external Hsync signal. In some implementations, the timing controller 160 may be configured to detect a pulse of the external Hsync signal and generate a pulse of the internal Hsync signal after a predetermined delay from detecting the pulse of the external Hsync signal. In other implementations, the timing controller 160 may be configured to generate a different number of pulses of the internal Hsync signal than the number of pulses of the external Hsync signal. For example, the timing controller 160 may be configured to generate three pulses of the internal Hsync signal for two pulses of the external Hsync signal.

[0035] The timing controller 160 is further configured to detect a pulse in the external Vsync signal and generate a pulse in the internal Vsync signal in response to detecting the pulse in the external Vsync signal. In one implementation, the timing controller 160 may be configured to generate a pulse in the internal Vsync signal after a predetermined delay from detecting the pulse in the external Vsync signal upon detecting the pulse in the external Vsync signal.

[0036] In one or more embodiments, the timing controller 160 is configured to perform signal masking on the external Hsync signal and / or the internal Vsync signal to mitigate the effects of noise, such as electrostatic discharge (ESD) noise, applied to the external Hsync signal and / or the internal Vsync signal. The noise may generate unintended pulses in the external Hsync signal and / or the external Vsync signal, which may cause unintended pulses in the internal Hsync signal and / or the internal Vsync signal. The generation of unintended pulses may cause the display driver 100 to malfunction. The signal masking performed on the external Hsync signal and / or the internal Vsync signal may effectively prevent unintended pulses in the internal Hsync signal from being generated by the noise.

[0037] FIG. 3A illustrates an exemplary signal masking performed on the external Hsync signal, according to one or more examples of the present disclosure. As previously described, the signal masking of the external Hsync signal is performed by prohibiting the timing controller 160 from detecting any pulses in the external Hsync signal during a masking period, where a masking period begins each time the timing controller 160 detects a pulse in the external Hsync signal. Illustrated in FIG. 3A are masking periods 620, 622, and 624 that begin when the timing controller 160 detects pulses 610, 612, and 614, respectively, in the external Hsync signal. The duration of the masking period is set such that no pulses are expected to appear in the external Hsync signal during the masking period. In some implementations, the duration of the masking period (e.g., masking periods 620, 622, and 624) may be set to be slightly shorter than the period of the external Hsync signal.

[0038] The timing controller 160 discards or rejects any pulses that appear in the external Hsync signal during the masking periods 620, 622, and 624. For example, as shown in FIG 3B, when a noise-induced pulse 630 appears in the external Hsync signal during the masking period 620, the timing controller 160 discards the noise-induced pulse 630 and does not generate a corresponding pulse in the internal Hsync signal.

[0039] After the masking period 620 is finished, the timing controller 160 is allowed to detect a pulse of the external Hsync signal. In the example illustrated in FIG. 3A and FIG. 3B, after the masking period 620 is finished, the timing controller 160 detects a pulse 612 and generates a pulse of the internal Hsync signal. Meanwhile, the next masking period 622 starts in response to the detection of the pulse 612. After the masking period 622 is finished, the timing controller 160 is allowed to detect a pulse of the external Hsync signal. After the masking period 622 is finished, the timing controller 160 detects a pulse 614 and the next masking period 624 starts in response to the detection of the pulse 614. A similar process is performed every time a pulse of the external Hsync signal is detected.

[0040] The timing controller 160 may also be configured to perform signal masking on the external Vsync signal to avoid unintended pulses in the internal Vsync signal due to noise applied to the external Vsync signal. In one implementation, the timing controller 160 may be configured to discard all pulses in the external Vsync signal during a masking period that begins when a leading pulse is detected in the external Vsync signal. The masking period for the external Vsync signal may continue after the detection of the leading pulse until the number of pulses in the external Hsync signal reaches a predetermined number. Alternatively, similar to the external Hsync signal, the masking period for the external Vsync signal may be set to be slightly shorter than the period of the external Vsync period.

[0041] 4 illustrates example waveforms of the internal Hsync signal and the internal Vsync signal generated using the signal masking illustrated in FIG. 3A and FIG. 3B during the vertical synchronization period 510 and 512, according to one or more examples of the present disclosure. Although noise is applied to the external Hsync signal during the vertical synchronization period 510, the timing controller 160 discards the noise-induced pulse 632, thereby preventing an unintended pulse from being generated in the internal Hsync signal. This may effectively suppress malfunction of the display driver 100.

[0042] In some implementations, as described above, the external source 400 may be configured to adjust the duration of the duration-adjusted horizontal synchronization period of each vertical synchronization period to achieve synchronization of the external Hsync signal with the external Vsync signal. Adjusting the duration of the duration-adjusted horizontal synchronization period may be achieved by adjusting the timing of generation of a pulse that defines the end of the duration-adjusted horizontal synchronization period. The duration of the duration-adjusted horizontal synchronization period may differ from the duration of the other horizontal synchronization periods. The duration of the duration-adjusted horizontal synchronization period of each vertical synchronization period may be adjusted so that the end of the last horizontal synchronization period of each vertical synchronization period coincides with the start of the next vertical synchronization period.

[0043] 5 illustrates an exemplary operation of the timing controller 160 during vertical synchronization periods 520 and 522, each of which includes a duration-adjusted horizontal synchronization period 412, in accordance with one or more examples of the present disclosure. In the illustrated implementation, the duration-adjusted horizontal synchronization period 412 is provided in the blanking period 410 of each of the vertical synchronization periods 520 and 522 because changes in the duration of the horizontal synchronization period during the display update period 420 may cause artifacts in the image displayed on the display panel 200. In the illustrated embodiment, the duration-adjusted horizontal synchronization period 412 is provided at the end of the blanking period 410 of each of the vertical synchronization periods 520 and 522. In other implementations, the duration-adjusted horizontal synchronization period 412 may be provided at any temporal location of the blanking period 410 or 430 other than at the end of the blanking period 410. In one implementation, the external source 400 may be configured to count pulses of the external Hsync signal during each vertical synchronization period and start a duration adjusted horizontal synchronization period 412 when the number of pulses in the external Hsync signal after the start of the current vertical synchronization period reaches a predetermined value.

[0044] This disclosure recognizes that the signal masking described in connection with Figures 3A, 3B, and 4 may not be consistent with the use of duration-adjusted horizontal synchronization periods. As illustrated in Figure 5, in some cases, the duration-adjusted horizontal synchronization period 412 may have a short duration (indicated by "short 1H") such that a pulse 642 of the external Hsync signal that defines the end of the duration-adjusted horizontal synchronization period 412 falls into a masking period that begins when a leading pulse 640 is detected. Note that the leading pulses 640 respectively define the beginning of the duration-adjusted horizontal synchronization period 412. In such cases, the timing controller 160 may not detect the pulse 642 and thus fail to generate a corresponding pulse of the internal Hsync signal. The absence of a corresponding pulse in the internal Hsync signal is indicated by a "missing" in Figure 5. The absence of a pulse of the internal Hsync signal that corresponds to the pulse 642 of the external Hsync signal may cause image artifacts due to a failure of timing control. For example, the driver circuit 140 configured to operate synchronously with the internal Hsync signal may not update the horizontal lines of the display panel 200 with the correct timing. Furthermore, in an embodiment in which the masking period for the external Vsync signal is defined based on the number of pulses of the external Hsync signal during each vertical synchronization period, it may happen that the timing controller 160 does not detect a pulse 650 in the external Vsync signal and a corresponding pulse of the internal Vsync signal is not generated, as indicated by "missing" in Figure 5. The lack of a corresponding pulse of the internal Vsync signal may cause serious image corruption.

[0045] In one or more embodiments, to avoid missing detection of a pulse that defines the end of a duration-adjusted horizontal synchronization period, the timing controller 160 is configured to perform modified signal masking on the external Hsync signal. The modified signal masking defines unmasked periods during which the timing controller 160 is allowed to detect a pulse in the external Hsync signal. During the unmasked periods, the timing controller 160 does not discard any pulses in the external Hsync signal. In some embodiments, each unmasked period begins when the timing controller 160 detects a pulse in the external Hsync signal that defines the start of a duration-adjusted horizontal synchronization period.

[0046] FIG. 6 illustrates an exemplary operation of the timing controller 160 in response to modified signal masking, according to one or more examples of the present disclosure. In the example illustrated in FIG. 6, a masking period 720 begins when the timing controller 160 detects a pulse 710 in the external Hsync signal. Once the masking period 720 ends, the timing controller 160 detects a pulse 712 in the external Hsync signal. The timing controller 160 identifies the pulse 712 as a pulse that defines the start of a duration-adjusted horizontal synchronization period 722, which is a non-masking period. In one implementation, the timing controller 160 may make this identification based on the number of pulses in the external Hsync signal after the start of the current vertical synchronization period. In the illustrated embodiment, the entire duration-adjusted horizontal synchronization period 722 is defined as a non-masking period during which the timing controller 160 is permitted to detect a pulse of the external Hsync signal. Thus, the timing controller 160 successfully detects the pulse 714 in the external Hsync signal that defines the end of the duration adjusted horizontal synchronization period 722, and generates a corresponding pulse in the internal Hsync signal in response to detecting the pulse 714. The detection of the pulse 714 also initiates a masking period 724, and the timing controller 160 detects a pulse 716 in the external Hsync signal after the masking period 724 ends. A similar process is then performed each time a pulse is detected in the external Hsync signal.

[0047] 7A illustrates an example operation of the timing controller 160 during vertical synchronization periods 530 and 532, each of which includes a duration-adjusted horizontal synchronization period 414, in accordance with one or more examples of the present disclosure. In one embodiment, the duration-adjusted horizontal synchronization period 414 is provided at the end of the blanking period 410 of each vertical synchronization period. The duration-adjusted horizontal synchronization period 414 may be provided at any temporal location in the blanking period 410 or 430 other than at the end of the blanking period 410.

[0048] In the illustrated embodiment, the timing controller 160 detects a pulse 730 in the external Hsync signal during the vertical synchronization period 530 and generates a pulse 740 in the internal Hsync signal in response to detecting the pulse 730 in the external Hsync signal. The timing controller 160 further identifies the pulse 730 as a pulse that defines the start of the duration-adjusted horizontal synchronization period 414 based on the number of pulses in the external Hsync signal during the vertical synchronization period 530. Because the duration-adjusted horizontal synchronization period 414 is defined as a non-masking period, the timing controller 160 is still permitted to detect a pulse in the external Hsync signal during the duration-adjusted horizontal synchronization period 414. The timing controller 160 successfully detects a pulse 732 in the external Hsync signal that defines the end of the duration-adjusted horizontal synchronization period 414 and generates a corresponding pulse 742 in the internal Hsync signal in response to detecting the pulse 732 in the external Hsync signal. Furthermore, since the timing controller 160 correctly counts the pulses of the external Hsync signal, the timing controller 160 successfully detects a pulse 750 in the external Vsync signal after the end of the masking period for the external Vsync signal based on the number of pulses of the external Hsync signal during the vertical synchronization period 530. The timing controller 160 generates a pulse of the internal Vsync signal in response to detecting the pulse 750 in the external Vsync signal. Similar operations are performed during the vertical synchronization period 532. The operation of the timing controller 160 illustrated in FIG. 7A effectively avoids the occurrence of image artifacts that may be caused by failure to detect a pulse that defines the end of a duration-adjusted horizontal synchronization period.

[0049] 7B illustrates another exemplary operation of the timing controller 160 during vertical synchronization periods 540 and 542, each of which includes a duration-adjusted horizontal synchronization period 414, according to one or more examples of the present disclosure. The operation illustrated in FIG. 7B is similar to the operation illustrated in FIG. 7A, except for the timing of the generation of a pulse 760 of the internal Hsync signal in response to detection of a pulse 732 of the external Hsync signal that defines the end of the duration-adjusted horizontal synchronization period 414. In the embodiment illustrated in FIG. 7B, the timing controller 160 is configured to measure the time interval between two adjacent pulses of the external Hsync signal other than the pulses that define the beginning and end of the duration-adjusted horizontal synchronization period 414. The timing controller 160 further determines the designated time interval P between two adjacent pulses of the internal Hsync signal based on the measured time interval between two adjacent pulses of the external Hsync signal. HI Determine this specified time interval P HI In some implementations, the designated time interval P HI may be equal to the measured time interval between two adjacent pulses of the external Hsync signal. In an embodiment in which the number of pulses of the internal Hsync signal is different from the number of pulses of the external Hsync signal, the specified time interval P HI may differ from the measured time interval between two adjacent pulses of the external Hsync signal. The timing controller 160 further determines whether the specified time interval P HI It should be noted that the pulse 730 of the external Hsync signal defines the start of the duration adjusted horizontal synchronization period 414. HI may be advantageously used in embodiments where the number of pulses in the external Hsync signal is different from the number of pulses in the internal Hsync signal.

[0050] 8 is a flowchart of an exemplary process for driving a display panel, according to one or more examples of the present disclosure. Process 800 may be performed by the display device 1000 illustrated in FIG 1. However, it will be appreciated that a display device having additional and / or fewer components than those illustrated in FIG 1 may be used to perform process 800, any of the steps described below may be performed in any suitable order, and process 800 may be performed in any suitable environment.

[0051] The process 800 includes receiving an external horizontal sync signal in step 802 .

[0052] Process 800 further includes, at step 804, generating a first pulse of an internal horizontal synchronization signal (e.g., pulse 740 shown in FIGS. 7A, 7B) in response to detecting a first pulse of an external horizontal synchronization signal (pulses 712, 716 shown in FIG. 6 and pulse 730 shown in FIG. 7A) after a masking period (e.g., masking periods 720, 724 shown in FIG. 6) has ended. The masking period begins when a first leading pulse of the external horizontal synchronization signal (e.g., pulses 710, 714 shown in FIG. 6) is detected prior to the detection of the first pulse of the external horizontal synchronization signal.

[0053] Process 800 further includes, at step 806, generating a second pulse of the internal horizontal synchronization signal (e.g., pulse 742 shown in FIG. 7A and pulse 760 shown in FIG. 7B) in response to detecting a second pulse of the external horizontal synchronization signal (e.g., pulse 714 shown in FIG. 6 and pulse 732 shown in FIG. 7A and 7B) in the unmasking period (e.g., duration adjusted horizontal synchronization period 722 shown in FIG. 6). The unmasking period begins when a second leading pulse of the external horizontal synchronization signal (e.g., pulse 712 shown in FIG. 6 and pulse 730 shown in FIG. 7A and 7B) is detected prior to the detection of the second pulse of the external horizontal synchronization signal.

[0054] The process 800 further includes, at step 808, driving a display panel (eg, the display panel 200 shown in FIG. 1) in synchronization with the internal horizontal synchronization signal.

[0055] The use of "a", "an", "the", "at least one" and similar reference words in the context of describing the present invention (particularly in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of a list of one or more items (e.g., "at least one of A and B") following the term "at least one" should be construed to mean one item selected from the listed items (A or B) or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. The terms "comprise", "have", "include" and "include" are to be construed as open-ended terms (i.e., meaning "including, but not limited to"), unless otherwise indicated. The recitation of ranges of values ​​herein is intended merely to serve as a shorthand method for individually referring to each individual value falling within the range, and each individual value is incorporated herein as if set forth individually herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. Any examples provided herein, or the use of exemplary language (e.g., "such as"), are intended merely to better illustrate the invention and do not limit the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.

[0056] Exemplary embodiments are described herein. Variations of those exemplary embodiments will become apparent to those skilled in the art upon reading the foregoing description. The inventors expect that those skilled in the art will adopt such variations as appropriate, and the inventors do not intend to practice the invention otherwise than as specifically described herein. Accordingly, this invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the invention unless otherwise indicated herein or otherwise clearly contradicted by context.

Claims

1. a timing controller configured to receive an external horizontal synchronizing signal and generate an internal horizontal synchronizing signal based on the external horizontal synchronizing signal; a drive circuit configured to drive a display panel in synchronization with the internal horizontal synchronization signal; Equipped with generating the internal horizontal synchronization signal, generating a first pulse of the internal horizontal synchronizing signal in response to detection of a first pulse of the external horizontal synchronizing signal after a masking period has ended, the masking period beginning when the timing controller detects a first leading pulse of the external horizontal synchronizing signal prior to detection of the first pulse of the external horizontal synchronizing signal; generating a second pulse of the internal horizontal synchronizing signal in response to detecting a second pulse of the external horizontal synchronizing signal during a non-masking period; Including, The unmasking period begins when the timing controller detects a second leading pulse of the external horizontal synchronizing signal prior to detection of the second pulse of the external horizontal synchronizing signal. Display driver.

2. The timing controller is further configured to discard one or more pulses appearing in the external horizontal synchronization signal during the masking period.

2. A display driver as claimed in claim 1.

3. The timing controller is further configured not to discard pulses appearing in the external horizontal synchronization signal during the unmasking period.

2. A display driver as claimed in claim 1.

4. the unmasking period corresponds to a duration adjusted horizontal synchronization period; The duration-adjusted horizontal synchronization period has a duration adjusted such that an end of a last horizontal synchronization period of a first vertical synchronization period that includes the duration-adjusted horizontal synchronization period coincides with a start of a second vertical synchronization period that follows the first vertical synchronization period.

2. A display driver as claimed in claim 1.

5. The duration of the duration-adjusted horizontal synchronization period is different from the duration of another horizontal synchronization period of the first vertical synchronization period.

5. A display driver according to claim 4.

6. The duration-adjusted horizontal synchronization period is provided in a blanking period of the first vertical synchronization period.

5. A display driver according to claim 4.

7. the timing controller is further configured to determine a time interval between adjacent pulses of the internal horizontal synchronization signal based on the external horizontal synchronization signal; Generating the second pulse of the internal horizontal synchronizing signal includes generating the second pulse after the timing controller detects the second preceding pulse and after a period of time having the same duration as the determined time interval.

5. A display driver according to claim 4.

8. The unmasking period begins in response to the number of pulses of the external horizontal synchronization signal reaching a predetermined number.

2. A display driver as claimed in claim 1.

9. an external source configured to provide an external horizontal synchronization signal; a display driver configured to generate an internal horizontal synchronizing signal based on the external horizontal synchronizing signal and drive a display panel in synchronization with the internal horizontal synchronizing signal; Equipped with generating the internal horizontal synchronization signal, generating a first pulse of the internal horizontal synchronizing signal in response to detecting a first pulse of the external horizontal synchronizing signal after a masking period has ended, the masking period beginning when the display driver detects a first leading pulse of the external horizontal synchronizing signal prior to detecting the first pulse of the external horizontal synchronizing signal; generating a second pulse of the internal horizontal synchronizing signal in response to detecting a second pulse of the external horizontal synchronizing signal during a non-masking period; Including, The unmasking period begins when the display driver detects a second leading pulse of the external horizontal synchronizing signal prior to detection of the second pulse of the external horizontal synchronizing signal. system.

10. The display driver is further configured to discard one or more pulses appearing in the external horizontal synchronization signal during the masking period. The system of claim 9.

11. The display driver is further configured not to discard pulses appearing in the external horizontal synchronization signal during the unmasking period. The system of claim 9.

12. the unmasking period is a duration adjusted horizontal synchronization period; The external source is further configured to adjust the duration of the duration-adjusted horizontal synchronization period such that an end of a last horizontal synchronization period of a first vertical synchronization period that includes the duration-adjusted horizontal synchronization period coincides with a start of a second vertical synchronization period that follows the first vertical synchronization period. The system of claim 9.

13. The duration of the duration-adjusted horizontal synchronization period is different from the duration of another horizontal synchronization period of the first vertical synchronization period. The system of claim 12.

14. The duration-adjusted horizontal synchronization period is provided in a blanking period of the first vertical synchronization period. The system of claim 12.

15. the display driver is further configured to determine a time interval between adjacent pulses of the internal horizontal synchronization signal based on the external horizontal synchronization signal; Generating the second pulse of the internal horizontal synchronization signal includes generating the second pulse after the display driver detects the second preceding pulse and after a period of time having the same duration as the determined time interval. The system of claim 12.

16. The unmasking period begins in response to the number of pulses of the external horizontal synchronization signal reaching a predetermined number. The system of claim 9.

17. receiving an external horizontal sync signal; generating a first pulse of an internal horizontal synchronizing signal in response to detecting a first pulse of the external horizontal synchronizing signal after a masking period has ended, the masking period beginning when a first leading pulse of the external horizontal synchronizing signal is detected prior to detecting the first pulse of the external horizontal synchronizing signal; generating a second pulse of the internal horizontal synchronizing signal in response to detecting a second pulse of the external horizontal synchronizing signal during a non-masking period; driving a display panel in synchronization with the internal horizontal synchronizing signal; Including, The unmasking period begins when a second leading pulse of the external horizontal synchronizing signal is detected prior to detection of the second pulse of the external horizontal synchronizing signal. method.

18. and discarding one or more pulses appearing in the external horizontal sync signal during the masking period.

20. The method of claim 17.

19. the unmasking period is a duration adjusted horizontal synchronization period; The method further includes adjusting a duration of the duration-adjusted horizontal synchronization period such that an end of a last horizontal synchronization period of a first vertical synchronization period that includes the duration-adjusted horizontal synchronization period coincides with a start of a second vertical synchronization period that follows the first vertical synchronization period.

20. The method of claim 17.

20. The duration-adjusted horizontal synchronization period is provided in a blanking period of the first vertical synchronization period.

20. The method of claim 19.

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