Arithmetic unit and method

Abstract

To provide arithmetic unit and method capable of performing a multiplication operation on input data with different data types.SOLUTION: An arithmetic unit in an embodiment can include a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal expressing the first data type, a second signal expressing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and an arithmetic circuit that generates output data by performing a multiplication operation on the first input data and the second input data on the basis of the first signal, the second signal, and the clock signal.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The disclosed subject matter relates to computing devices and methods. [Background technology]

[0002] Deep learning, a field of artificial intelligence, enables sophisticated predictions by recognizing complex data patterns. In general, deep learning consists of a training step in which a neural network model is trained using learning data, and an inference step in which new data is input to the trained neural network model to obtain an output. This type of deep learning can improve performance by making more sophisticated predictions possible as the neural network becomes deeper, but this has the problem of requiring more power and slowing down the speed due to the enormous amount of calculations.

[0003] On the other hand, neural networks can contain many layers for sophisticated predictions, which can increase the computational complexity. Therefore, to reduce the computational complexity, algorithm lightweighting techniques such as mapping floating-point data to integers are used. Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment seeks to provide an arithmetic apparatus and method capable of performing multiplication and accumulation operations on input data having different data types.

[0005] One embodiment seeks to provide an arithmetic apparatus and method capable of performing multiplication and accumulation operations on input data having different precisions. [Means for solving the problem]

[0006] An arithmetic device according to one embodiment may include a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal indicating the first data type, a second signal indicating the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and an arithmetic circuit that performs a multiplication operation on the first input data and the second input data based on the first signal, the second signal, and the clock signal to generate output data.

[0007] An arithmetic device according to one embodiment is an arithmetic device that performs a multiplication operation on first data having a first number of bits and second data having a second number of bits different from the first number of bits, and may include a first multiplexer including a selection node that receives an output signal of a counter that counts the number of cycles of a clock signal based on the first number of bits and a plurality of input nodes that receive each bit value of the first data, a second multiplexer including a selection node that receives output data of the first multiplexer, a first input node that receives a first value, and a second input node that receives the second data or data obtained by shifting the second data by one bit at a time, and a first adder that performs an addition operation on the output data of the second multiplexer based on the clock signal.

[0008] According to an embodiment, a neural processing system includes a memory for storing data, and a neural processing unit for receiving an input matrix and a weight matrix corresponding to input data from the memory, performing a matrix dot product operation on the input matrix and the weight matrix, and outputting a result of the matrix dot product operation as an output matrix, wherein the input matrix includes elements of a first data type, and the weight matrix includes elements of a second data type different from the first data type, and the neural processing unit may include an arithmetic device for outputting exponent data of elements of the input matrix or exponent data of elements of the weight matrix as exponent data of elements of the output matrix based on the first data type and the second data type. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating a neural processing system according to one embodiment. [Diagram 2] FIG. 2 is a diagram for explaining a neural network operation according to an embodiment. [Diagram 3] FIG. 3 is a diagram for explaining the input data format. [Figure 4] FIG. 4 is a diagram showing an arithmetic circuit according to a comparative example. [Diagram 5] FIG. 5 is a flow chart illustrating a method of operation of a neural processing unit according to an embodiment. [Figure 6] FIG. 6 is a schematic block diagram of a computing device according to an embodiment. [Figure 7] FIG. 7 is a schematic block diagram of an arithmetic circuit according to an embodiment. [Figure 8] FIG. 8 is a diagram illustrating an exponent calculation unit according to an embodiment. [Figure 9] FIG. 9 is a diagram illustrating a mantissa calculation unit according to an embodiment. [Figure 10] FIG. 10 is a diagram for explaining a calculation method of the mantissa calculation unit shown in FIG. [Figure 11] FIG. 11 shows a timing diagram of the operations performed in the mantissa operation unit according to one embodiment. [Figure 12] FIG. 12 shows a timing diagram of the calculation performed in the mantissa calculation unit according to another embodiment. [Figure 13] FIG. 13 is an exemplary diagram for explaining multi-head attention according to an embodiment. [Figure 14] FIG. 14 is an exemplary diagram for explaining the scaled dot-product attention of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings, in which: FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention;

[0011] In the drawings, parts that are not relevant to the description are omitted in order to clearly explain the present invention, and similar parts are designated by similar reference numerals throughout the specification. In the flowcharts described with reference to the drawings, the order of operations may be changed, various operations may be combined, certain operations may be divided, and certain operations may not be performed.

[0012] Furthermore, expressions described in the singular can be interpreted as singular or plural unless an explicit expression such as "one" or "single" is used. Terms including ordinal numbers such as "first", "second", etc. can be used to describe various components, but the components are not limited by such terms. These terms can be used to distinguish one component from another component.

[0013] FIG. 1 is a block diagram showing a neural processing system according to an embodiment. The neural processing system 100 can infer information included in input data by training (or learning) a neural network or analyzing input data using a neural network. The neural processing system 100 can judge a situation based on the inferred information or control the configuration of an electronic device in which the neural processing system 100 is installed. For example, the neural processing system 100 can be applied to a smartphone, tablet device, smart TV, AR (Augmented Reality) device, IoT (Internet of Things) device, autonomous vehicle, robotics, medical device, drone, Advanced Driver Assistance System (ADAS), image display device, measuring device, etc., which perform voice recognition, image recognition, image classification, etc. using a neural network, and the neural processing system 100 can be installed in one of various types of electronic devices.

[0014] Referring to FIG. 1, a neural processing system 100 may include a central processing unit 110 (CENTRAL PROCESSING UNIT), a neural processing unit 120 (NEURAL PROCESSING UNIT), a volatile memory device 130 (VOLATILE MEMORY DEVICE), a non-volatile memory device 140 (NONVOLATILE MEMORY DEVICE), and a user interface 150 (USER INTERFACE). In one embodiment, some or all of the components of the neural processing system 100 (e.g., the central processing unit 110, the neural processing unit 120, the volatile memory device 130, and the non-volatile memory device 140) may be formed on a single semiconductor chip. For example, the neural processing system 100 may be embodied as a system-on-chip (SoC). The central processing unit 110, the neural processing unit 120, the volatile memory device 130, the non-volatile memory device 140, and the user interface 150 may be connected to each other via a bus.

[0015] The central processing unit 110 can control various operations of the neural processing system 100. The central processing unit 110 may include one processor core (Single Core) or multiple processor cores (Multi-Core). The central processing unit 110 can process or execute programs and / or data stored in storage areas such as the volatile memory device 130 and the non-volatile memory device 140.

[0016] The central processing unit 110 executes an application program and controls the neural processing unit 120 to perform neural network-based tasks required by the execution of the application program. The neural network may include at least one of various types of neural network models such as a Convolution Neural Network (CNN), a Region with Convolution Neural Network (R-CNN), a Region Proposal Network (RPN), a Recurrent Neural Network (RNN), a Stacking-based deep Neural Network (S-DNN), a State-Space Dynamic Neural Network (S-SDNN), a Deconvolution Network, a Deep Belief Network (DBN), a Restricted Boltzman Machine (RBM), a Fully Convolutional Network, a Long Short-Term Memory (LSTM) Network, a Classification Network, and a Transformer.

[0017] The neural network model may include a plurality of layers. Each of the plurality of layers may be embodied to receive input data of the layer and generate output data of the layer. In this case, the generated output data of the layer may be used as input data of another layer. Each of the plurality of layers may transform input data into output data through a neural network operation. For example, each of the plurality of layers may perform an inner product of an input matrix corresponding to the input data of the layer and a weight matrix to generate an output matrix corresponding to the output data of the layer. However, the scope of the present disclosure is not limited thereto, and each of the plurality of layers may generate output data by transforming an input matrix corresponding to the input data of the layer in any manner. For example, each of the plurality of layers may be embodied to generate output data of the layer by sequentially multiplying an input matrix corresponding to the input data of the layer by a plurality of weight matrices, or to generate output data of the layer by transforming an input matrix based on a transformation parameter. A more detailed description of the neural network and layers will be described with reference to FIG. 2.

[0018] The neural processing unit 120 can access the volatile memory device 130 to perform neural network operations. For example, the neural processing unit 120 can read parameters stored in the volatile memory device 130 to perform operations on layer input data, and can temporarily store intermediate data generated during the operations in the volatile memory device 130.

[0019] To perform neural network operations, the neural processing unit 120 can access the non-volatile memory device 140. For example, the neural processing unit 120 can read operation parameters (e.g., weight values, bias values, etc.) for the neural network stored in the non-volatile memory device 140, input data (e.g., input feature maps), etc., to perform neural network operations.

[0020] In one embodiment, the neural processing unit 120 may include a computing device 121 (COMPUTING DEVICE) for performing neural network operations. For example, the computing device 121 may perform an inner product operation on the input matrix and weight matrix of each layer. The computing device 121 may include a multiplication and accumulation (MAC) calculator for performing an inner product operation on the input matrix and weight matrix of each layer. The computing device 121 may perform a multiplication and accumulation operation on input data.

[0021] Meanwhile, a neural network may be implemented with a complex architecture, and the arithmetic device 121 of the neural processing unit 120 that performs neural network operations performs many operations, from hundreds of millions to tens of billions. Therefore, a weighting technique such as mapping floating point data to integer data is used to weight the neural network algorithm. In one embodiment, the arithmetic device 121 may receive a plurality of data having different data types as input data. For example, the arithmetic device 121 may receive floating point data and integer data as input data, but is not limited thereto.

[0022] In one embodiment, the arithmetic unit 121 can receive a plurality of pieces of data having different precisions, i.e., different bits, as input data. For example, the arithmetic unit 121 can receive input data having any bits within a predetermined number of bits that the arithmetic unit 121 can operate on.

[0023] In one embodiment, the volatile memory device 130 can be used as a buffer memory, working memory, or cache memory for the central processing unit 110. Volatile memory includes Dynamic RAM (DRAM), Static RAM (SRAM), Synchronous DRAM (SDRAM), Phase-change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), Ferroelectric RAM (FeRAM), etc. However, the scope of the present disclosure is not limited thereto.

[0024] The non-volatile memory device 140 can store data for the operation of the neural processing system 100. For example, the non-volatile memory device 140 can store an operating system (OS) of the neural processing system 100, operation parameters (e.g., weight values, bias values, etc.) for the neural network, parameters for quantization of the neural network (e.g., scale factors, bias values, etc.), input data (e.g., input feature maps), and output data (e.g., output feature maps). The operation parameters, quantization parameters, input data, and output data may be floating-point data or integer data. The non-volatile memory device 140 includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. However, the scope of the present disclosure is not limited thereto.

[0025] The central processing unit 110 can communicate with a user through a user interface 150. The central processing unit 110 can provide input data provided by a user through the user interface 150 to the volatile memory device 130 or the neural processing unit 120. The central processing unit 110 can return output data generated by the artificial intelligence model based on the input data to the user through the user interface 150.

[0026] FIG. 2 is a diagram for explaining a neural network operation according to an embodiment.

[0027] Referring to FIG. 2, the neural network 200 may include multiple layers. For example, the neural network 200 may include an input layer 210, one or more hidden layers 220, and an output layer 230. The input layer 210 may correspond to a vector and / or matrix representing input data 201 of the neural network 200. For example, the vector representing the input data may have elements corresponding to the number of nodes included in the input layer 210. For example, the elements included in the matrix representing the input data may correspond to each of the nodes included in the input layer 210. A signal generated at each of the nodes in the input layer 210 generated by the input data 201 may be transmitted from the input layer 210 to the hidden layer 220. The output layer 230 may generate output data 203 of the neural network 200 based on one or more signals received from the hidden layer 220. For example, the output data 203 may correspond to a vector and / or matrix having elements corresponding to the number of nodes included in the output layer 230.

[0028] Data generated in each layer may be the output of a layer and at the same time an input parameter of a node included in the next layer. Meanwhile, each node in a layer may determine output data based on data and weights received from nodes included in the previous layer. The weights are parameters used to calculate output data at each node, and may be values ​​assigned to connections between nodes. The output data generated from a node included in a layer may be data generated by calculating an inner product of the data input to the node and the weights.

[0029] As described in FIG 1, data input to each layer may be of multiple data types. The arithmetic unit 121 according to an embodiment may receive multiple pieces of data having different data types as input data and perform an inner product operation on the input data. For example, the arithmetic unit 121 according to an embodiment may perform an inner product operation on an input matrix of floating point data and a weight matrix converted to an integer for weight reduction.

[0030] As described in FIG 1, data input to each layer may be different bits. The arithmetic unit 121 according to one embodiment can receive a plurality of data of different bits as input data and perform an inner product operation on the input data. For example, the arithmetic unit 121 can perform an inner product operation on 3-bit data and 2-bit data.

[0031] The arithmetic unit 121 according to an embodiment can generate a clock signal based on bits of input data and perform an inner product operation based on the clock signal. For example, the arithmetic unit 121 can derive a multiplication result for the input data by shifting and adding data based on the clock signal.

[0032] The arithmetic device 121 according to an embodiment can improve the performance of the arithmetic device and reduce the weight of the neural network model algorithm based on a reduction in input data while maintaining the accuracy of the data.

[0033] Fig. 3 is a diagram for explaining an input data format, specifically, Fig. 3(a) is a diagram for explaining a floating point data format processed by a calculation device, and Fig. 3(b) is a diagram for explaining integer data.

[0034] Referring to Figure 3(a), floating point data can take various forms depending on the precision, but the most commonly used is the IEEE 754 standard. The IEEE 754 standard represents real numbers by dividing them into a sign, an exponent, and a mantissa. For example, a floating point number is represented as in equation (1).

number

[0035] For example, -314.625 can be represented in IEEE 754 floating point notation as follows:

[0036] First, since the sign is a negative number, s becomes 1.

[0037] In terms of the mantissa, the absolute value of the number 314.625 can be expressed in binary as 100111010.101. (2) In this case, if the decimal point is moved to the left so that only 1 remains to the left of the decimal point, it can be expressed as follows, which is called the normalized representation method.

[0038] 100111010.101 (2) =1.00111010101 (2) ×2 8 Here, the mantissa is the part to the right of the decimal point, i.e., 00111010101.

[0039] Regarding the exponent, the normalized representation of -314.625 has an exponent of 8, and adding a bias value of 127 to the exponent 8 gives us 135. In this case, converting 135 to binary gives us 10000111. (2) This value becomes the exponent.

[0040] Here, single precision is taken as an example, but in half precision or double precision, the exponent and mantissa bits and bias values ​​may be different.

[0041] Meanwhile, referring to FIG. 3(b), integer data can be represented in various types depending on the presence or absence of a sign and the data size (number of bits). As an example, an integer generally used in computing operations can be represented as 8-bit data (2's complement) including a sign as shown in FIG. 3(b), where the most significant bit indicates the sign, and the following 7 bits indicate the integer part, whose size is:

number

number

[0042] 4 is a diagram showing an arithmetic circuit according to a comparative example. Specifically, an arithmetic circuit 400 according to the comparative example can perform multiplication and accumulation operations on floating-point data.

[0043] 4, the arithmetic circuit 400 according to the comparative example can receive first input data (IN1[31:0]) and second input data (IN2[31:0]) and perform multiplication and accumulation operations on the input data. In one example, when the first input data (IN1[31:0]) and the second input data (IN2[31:0]) are 32-bit floating-point data, each of the first input data (IN1[31:0]) and the second input data (IN2[31:0]) can be composed of 1-bit sign data (S_IN1

[31] , S_IN2

[31] ), 8-bit exponent data (E_IN1[30:23], E_IN2[30:23]), and 23-bit mantissa data (M_IN1[22:0], M_IN2[22:0]).

[0044] The arithmetic circuit 400 according to the comparative example may include a multiplication unit 401 and an accumulation unit 402. The multiplication unit 401 may include a sign calculation unit 410, an exponent calculation unit 420, and a mantissa calculation unit 430, and the accumulation unit 402 may include an adder (ADDER) 450 and an accumulator (ACCUMULATOR) 460.

[0045] In the multiplication unit 401, the sign calculation unit 410 may include an exclusive OR (hereinafter, referred to as XOR) gate. The sign calculation unit 410 may receive the first code data (S_IN1

[31] ) of the first input data (IN1) and the second code data (S_IN2

[31] ) of the second input data (IN2). When the first code data (S_IN1

[31] ) and the second code data (S_IN2

[31] ) both have a value of "0" indicating a positive number or a value of "1" indicating a negative number, the XOR gate of the sign calculation unit 410 may output "0" indicating a positive number. On the other hand, when one of the first code data (S_IN1

[31] ) and the second code data (S_IN2

[31] ) has a value of "0" indicating a positive number and the other has a value of "1" indicating a negative number, the XOR gate of the sign calculation unit 410 may output "1" indicating a negative number. The sign calculation unit 410 can output the data generated as a result of the XOR calculation as 1-bit sign data (OUT

[31] ) of the output data (OUT).

[0046] The exponent calculation unit 420 may include a first exponent adder 421 and a second exponent adder 423. The first exponent adder 421 may receive the first exponent data (E_IN1[30:23]) of the first input data (IN1) and the second exponent data (E_IN2[30:23]) of the second input data (IN2). The first exponent adder 421 may perform a first addition operation on the first exponent data (E_IN1[30:23]) and the second exponent data (E_IN2[30:23]). The first exponent adder 421 may output first addition result data generated as a result of the first addition operation. The first exponent data (E_IN1[30:23]) and the second exponent data (E_IN2[30:23]) are in a state in which an exponent bias value, for example, “127”, has been added to each of them. Since the exponent bias value is doubled by the first addition operation in the first exponent adder 421, it is necessary to subtract the exponent bias value from the first addition result data. Therefore, the second exponent adder 423 receives the first addition result data output from the first exponent adder 421 and can perform a second addition operation to subtract the exponent bias value (Bias), for example, "127", from the first addition result data. The second exponent adder 423 can output data generated as a result of the second addition operation as 8-bit exponent data (E_OUT[7:0]).

[0047] The mantissa calculation unit 430 may include a multiplier 431. The multiplier 431 may receive first mantissa data (M_IN1[22:0]) of the first input data (IN1) and second mantissa data (M_IN2[22:0]) of the second input data (IN2). The multiplier 431 may perform a multiplication operation on the first mantissa data (M_IN1[22:0]) and the second mantissa data (M_IN2[22:0]). The multiplier 431 may output data generated as a result of the multiplication operation as 48-bit mantissa data (M_OUT[47:0]).

[0048] The normalizer (NORMALIZER) 440 can normalize the exponent data (E_OUT[7:0]) output from the exponent calculation unit 420 and the mantissa data (M_OUT[47:0]) output from the mantissa calculation unit 430. Normalization refers to shifting the calculated data so that the most significant bit becomes 1. The normalized data (OUT[30:0]) can be output to the accumulation unit 402 as the multiplier result value (OUT) together with the code data (OUT

[31] ) output from the code processing circuit 410.

[0049] In the accumulation unit 402 , the adder 450 performs an accumulation operation by adding the data received from the multiplication unit 401 and the data received from the accumulator 460 .

[0050] As described above, the arithmetic circuit 400 according to the comparative example can perform an inner product operation on a matrix by performing multiplication and accumulation operations on input data in the form of a matrix, but can only receive floating-point data as input data.

[0051] Meanwhile, when the multiplier 400 receives floating-point data as input data, the floating-point data is configured with a predetermined precision, and if the size of the mantissa data of the floating-point data, i.e., the number of bits, is smaller than the size of the predetermined mantissa, the remaining bits are filled with "0." This causes a problem in that the performance of the multiplier, i.e., the arithmetic device, is not improved because the multiplier performs calculations on all values ​​of the mantissa even though the size of the input data is reduced.

[0052] 5 is a flow chart illustrating a method of operation of a neural processing unit according to one embodiment, which may be performed in the neural processing unit (120 in FIG. 1) for neural network operations.

[0053] 5, the controller in the neural processing unit 120 may receive input data from the memory device 140 (S510). The input data may include input feature values, weight values, function coefficients, etc. required for neural network operation. In addition, when the neural network device 120 processes a quantized neural network, the input data may include quantization parameters. For example, the quantization parameters may include a scale value (or an inverse scale value), a bias value, etc.

[0054] In one embodiment, the controller in the neural processing unit 120 may output data type information indicating a data type of the input data (S520). In one embodiment, the input data may be the same or different data types. For example, the input data may be floating point data. The input data may be integer data. The input data may be, but is not limited to, floating point data and integer data. The data type information will be described with reference to Figures 6 to 8.

[0055] In one embodiment, the controller in the neural network device 120 may output a clock signal based on the number of bits of the input data (S530). In one embodiment, the neural network device 120 may receive input data and count the bits of the input data. In one embodiment, the controller in the neural network device 120 may output a clock signal only for the bits of the input data. In one embodiment, the controller in the neural network device 120 may output a clock signal only for one bit of the input data. In one embodiment, the neural network device 120 may not receive new input data until the clock cycle output based on the bit information of the input data has elapsed.

[0056] In one embodiment, the neural network device 120 may perform multiplication and accumulation operations on the input data (S540). The neural network device 120 may include an adder and a shifter to perform the multiplication operations. The neural network device 120 may perform exponent operations based on the data type information. The neural network device 120 may perform mantissa operations based on a clock signal.

[0057] In one embodiment, the neural network device 120 may store the final data generated in step S540 in the memory 140 (S550).

[0058] Fig. 6 is a schematic block diagram of a computing device according to an embodiment. The computing device 600 in Fig. 6 can perform an inner product operation on input data. The computing device 600 in Fig. 6 may be a MAC computing unit for performing multiplication and accumulation operations on input data.

[0059] In one embodiment, the computing device 600 may include a CONTROLLER 610 and a COMPUTING CIRCUIT 620 .

[0060] In one embodiment, the arithmetic unit 600 may receive input data (IN1, IN2) of the same or different types. The controller 610 may output data type signals (DS1, DS2) indicating the data type of the input data (IN1, IN2). For example, if the first input data (IN1) is integer data, the first data type signal (DS1) may output a "low" signal, and if the second input data (IN2) is floating point data, the second data type signal (DS2) may output a "high" signal, but is not limited thereto. In one embodiment, the arithmetic circuit 620 may perform an exponent operation based on the data type signals (DS1, DS2) of the input data (IN1, IN2). The exponent operation of the arithmetic circuit 620 will be described below with reference to FIG. 8.

[0061] In one embodiment, the controller 610 may output a clock signal (CLK) based on data bit number information of the input data (IN, IN2). For example, if the first input data (IN1) is integer data and includes a sign bit, bits other than the most significant bit may be obtained as bit number information of the first input data (IN1). If the second input data (IN2) is floating point data, the number of bits of the mantissa may be obtained as bit number information of the second input data (IN2).

[0062] In one embodiment, the controller 610 may output a clock signal (CLK) based on the number of data bits of the input data (IN, IN2). The controller 610 may output a clock signal whose cycle is repeated by the number of bits of the input data (IN1, IN2). In one embodiment, the controller 610 may output a clock signal based on the number of bits of any data among the plurality of input data (IN1, IN2). In one embodiment, the controller 610 may compare the number of bits of the plurality of input data (IN1, IN2) and output a clock signal based on the number of bits of the input data having a smaller number of bits. In one embodiment, the arithmetic circuit 620 may perform a mantissa operation based on a clock signal based on the number of data bits of the input data (IN1, IN2). The mantissa operation of the arithmetic circuit 620 will be described later with reference to FIG. 9.

[0063] In one embodiment, the controller 610 may not accept new input data until any clock signals (CLK) are available to be output.

[0064] FIG. 7 is a schematic block diagram of an arithmetic circuit according to an embodiment.

[0065] 7, the arithmetic circuit 700 may include a multiplier 701 and an accumulator 702. In one embodiment, the multiplier 701 may include a sign calculator 710, an exponent calculator 720, and a mantissa calculator 730.

[0066] In one embodiment, the sign calculation unit 710 may receive the first code data (S_IN1[A]) of the first input data (IN1) and the second code data (S_IN2[B]) of the second input data (IN2). When the first code data (S_IN1[A]) and the second code data (S_IN2[B]) both have a value of "0" indicating a positive number or a value of "1" indicating a negative number, the XOR gate of the sign calculation unit 710 may output "0" indicating a positive number. On the other hand, when one of the first code data (S_IN1[A]) and the second code data (S_IN2[B]) has a value of "0" indicating a positive number and the other has a value of "1" indicating a negative number, the XOR gate of the sign calculation unit 710 may output "1" indicating a negative number. The sign calculation unit 710 may output data generated as a result of the XOR calculation as 1-bit code data (S_OUT).

[0067] The exponent processing circuit 720 may receive the first exponent data (E_IN1[A-1:a+1]) of the first input data (IN1) and the second exponent data (E_IN2[B-1:b+1]) of the second input data (IN2). In one embodiment, the first input data (IN1) and the second input data (IN2) may both be floating point data or both be integer data, or one of the first input data (IN1) and the second input data (IN2) may be integer data and the other may be floating point data. On the other hand, if both input data are integer data, there is no exponent data for the corresponding input data. The exponent processing circuit 720 may further receive data type signals (DS1, DS2) from the controller (610 in FIG. 6). The components of the exponent processing circuit 720 and a specific operation method thereof will be described with reference to FIG. 8.

[0068] FIG. 8 is a diagram illustrating an exponent calculation unit according to an embodiment.

[0069] The exponent calculation unit 800 according to an embodiment may further include an exponent processing circuit 840 including a first exponent adder 841 and a second exponent adder 843, and multiplexers MUX_E1, MUX_E2, and MUX_E3 connected to input nodes of each adder.

[0070] In one embodiment, the first multiplexer (MUX_E1) 810 may include a first input node that receives the first exponent data (E_IN1[A-1:a+1]) of the first input data (IN1) and a second input node that receives "0". The first multiplexer (MUX_E1) 810 may receive the first data type signal (DS1) as a selection signal. The first multiplexer (MUX_E1) 810 may include a selection node that receives the first data type signal (DS1). For example, if the first input data (IN1) is integer data, the first exponent data is not present. Thus, the first multiplexer 810 may output "0" based on the first data type signal (DS1).

[0071] In one embodiment, the second multiplexer (MUX_E2) 820 may include a first input node that receives the second exponent data (E_IN2[B-1:b+1]) of the second input data (IN2) and a second input node that receives "0". The second multiplexer (MUX_E2) 820 may receive the second data type signal (DS2) as a selection signal. The second multiplexer (MUX_E2) 820 may include a selection node that receives the second data type signal (DS2). For example, if the second input data (IN2) is floating point data, the second multiplexer 820 may output the second exponent data (E_IN2[B-1:b+1]) based on the second data type signal (DS2).

[0072] According to an embodiment, the first input data (IN1) and the second input data (IN2) may be floating point data. If the first input data (IN1) and the second input data (IN2) are floating point data, the first multiplexer 810 may output the first exponent data (E_IN1[A-1:a+1]) based on the first data type signal (DS1), and the second multiplexer 820 may output the second exponent data (E_IN2[B-1:b+1]) based on the second data type signal (DS2). The first exponent adder 841 may receive the first exponent data (E_IN1[A-1:a+1]) and the second exponent data (E_IN2[B-1:b+1]) and perform a first addition operation. The first exponent data (E_IN1[A-1:a+1]) and the second exponent data (E_IN2[B-1:b+1]) are in a state where an exponent bias value, for example, “127”, has been added to each of them. Since the exponent bias value is doubled by the first addition operation of the first exponent adder 841, it is necessary to subtract the exponent bias value from the first addition result data.

[0073] Meanwhile, the third multiplexer (MUX_E3) 830 may include a first input node for receiving a negative exponent bias value (-Bias) and a second input node for receiving "0". The third multiplexer 830 may receive a signal generated by ANDing the first data type signal (DS1) and the second data type signal (DS2) from the AND operator 831 as a selection signal (SEL). The third multiplexer 830 may include a selection node for receiving a signal generated by ANDing the first data type signal (DS1) and the second data type signal (DS2) from the AND operator 831. For example, the third multiplexer 830 may output a negative exponent bias value when both the first input data and the second input data are floating point data, that is, when the selection signal (SEL) is "1". The third multiplexer 830 may output "0" when one of the first input data and the second input data is integer data, that is, when the selection signal (SEL) is "0". In one example, since the first input data (IN1) and the second input data (IN2) are both floating point data, the third multiplexer 830 can output a negative exponent bias value, for example, "-127", based on the selection signal (SEL). To this end, the second exponent adder 843 can receive the first addition result data output from the first exponent adder 841 and perform a second addition operation of subtracting an exponent bias value (Bias), for example, "127", from the first addition result data. The second exponent adder 843 can output data generated as a result of the second addition operation as exponent data (E_OUT) of the multiplication data (OUT).

[0074] According to another embodiment, the first input data (IN1) may be floating point data and the second input data (IN2) may be integer data. When the first input data (IN1) is floating point data and the second input data (IN2) is integer data, the first multiplexer 810 of the exponent calculation unit 800 may output the first exponent data (E_IN1[A-1:a+1]) based on the first data type signal (DS1), and the second multiplexer 820 may output "0" based on the second data type signal (DS2). The first exponent adder 841 may receive the first exponent data (E_IN1[A-1:a+1]) and "0" to perform a first addition calculation. The first exponent data (E_IN1[A-1:a+1]) is in a state where an exponent bias value, for example, "127", has been added, and it is not necessary to subtract the exponent bias value from the first addition result data. Therefore, the third multiplexer 830 can output "0" based on the selection signal (SEL). To this end, the second exponent adder 843 can receive the first addition result data output from the first exponent adder 841 and perform a second addition operation of subtracting "0" from the first addition result data. The second exponent adder 843 can output data generated as a result of the second addition operation as exponent data (E_OUT) of the multiplication data (OUT).

[0075] According to another embodiment, the first input data (IN1) and the second input data (IN2) may be integer data. If the first input data (IN1) and the second input data (IN2) are integer data, the first multiplexer 810 of the exponent calculation unit 800 may output "0" based on the first data type signal (DS1), and the second multiplexer 820 may output "0" based on the second data type signal (DS2). The first exponent adder 841 may receive the output data of the first multiplexer 810 and the output data of the second multiplexer 820 and perform a first addition operation. The third multiplexer 830 may output "0" based on the selection signal (SEL). To this end, the second exponent adder 843 may receive the first addition result data output from the first exponent adder 841 and perform a second addition operation of subtracting "0" from the first addition result data. The second exponent adder 843 can output the data generated as a result of the second addition operation, that is, "0", as the exponent data (E_OUT) of the multiplied data (OUT).

[0076] Referring again to FIG. 7, the mantissa calculation unit 730 may receive first mantissa data (M_IN1[a:0]) of the first input data (IN1) and second mantissa data (M_IN2[b:0]) of the second input data (IN2). If the input data is floating point data, the mantissa data may refer to a mantissa part, and if the input data is integer data, the mantissa data may correspond to an integer part. The mantissa calculation unit 730 may further receive a clock signal (CLK) from the controller (610 in FIG. 6). The components and a specific operation method of the mantissa calculation unit 730 will be described with reference to FIG. 9.

[0077] 9 is a diagram illustrating a mantissa calculation unit according to an embodiment. For convenience of explanation, it is referred to as a mantissa calculation unit, and when input data is integer data, the data input to the mantissa calculation unit may be an integer part.

[0078] The mantissa calculation unit 900 according to an embodiment may include a first multiplexer 910, a second multiplexer 920, a counter (COUNTER) 911, a shifter (SHIFTER) 921, an adder 930, and an accumulator (ACC) 940. The mantissa calculation unit 900 according to an embodiment may perform a multiplication operation on input data. The mantissa calculation unit 900 according to an embodiment may use the shifter 921 and the adder 930 to perform the multiplication operation.

[0079] The multiplication operation of the mantissa calculator 900 according to an embodiment may be performed through addition and shift operations. A method of operation of the mantissa calculator 900 will be described with reference to FIG.

[0080] FIG. 10 is a diagram for explaining a calculation method of the mantissa calculation unit shown in FIG.

[0081] Referring to FIG. 10, 0011011 (2) ×110011 (2) In multiplication, 0011011 (2) is the multiplicand, 110011 (2) can be called a multiplier. First, when the least significant bit value of the multiplier is "1" (1001), the multiplicand is the multiplicand value (0011011 (2) ) (1005) is output as is, and the multiplicand can be shifted one bit to the left (00110110 (2) )(1013).

[0082] Next, since the next bit value of the multiplier is "1" (1011), the multiplicand is output as is (00110110 (2) )(1015), previous output value (0011011 (2) ) and add the result: 01010001 (2) (1017) is output, and the multiplicand can be shifted one bit to the left (001101100 (2) )(1023).

[0083] Next, because the next bit value of the multiplier is "0" (1021), the output value becomes "0" (1025), and the previous output value (01010001 (2) )(1017) can be added. The result is 001010001 (2) (1027) is output and the multiplicand can be shifted one bit to the left.

[0084] When the calculation is performed using the method described above, the final output value is 0010101100001 (2) (1037), which is multiplied by 0011011 (2) ×110011 (2) In other words, binary multiplication can be performed using a shifter and an adder.

[0085] Referring again to Fig. 9, the operation of the mantissa calculator 900 according to an embodiment may be performed according to the method of Fig. 10. In one embodiment, the first mantissa data (M_IN1[a:0]) of the first input data (IN1) may be a multiplier, and the second mantissa data (M_IN2[b:0]) of the second input data (IN2) may be a multiplicand.

[0086] In one embodiment, the first multiplexer 910 may include a plurality of input nodes that receive the first mantissa data (M_IN1[a:0]) as input data. The first multiplexer 910 may receive each bit value (M_IN1[a], ..., M_IN1[1], M_IN1[0]) of the first mantissa data (M_IN1[a:0]) as input data. The first multiplexer 910 may receive an output signal of the counter 911 as a selection signal (SEL) 1. The first multiplexer 910 may include a selection node that receives the output signal of the counter 911. The counter 911 may count the number of times that the clock signal (CLK) output from the controller 610 is activated. That is, the counter 911 may count cycles of the clock signal (CLK). The first multiplexer 910 may sequentially output the input data (M_IN1[a], ..., M_IN1[1], M_IN1[0]) one bit at a time starting from the least significant bit based on the selection signal (SEL1) output from the counter 911. The number of cycles of the clock signal (CLK) may be the same as the number of bits of the first mantissa data (M_IN1[a:0]). The value output from the first multiplexer 910 may be input as a selection signal (SEL2) of the second multiplexer 920.

[0087] In one embodiment, the second multiplexer 920 may include a first input node receiving the second mantissa data (M_IN2[b:0]) and a second input node receiving "0." The second multiplexer 920 may receive the output value of the first multiplexer 910, i.e., each bit value (M_IN1[a], ..., M_IN1[1], M_IN1[0]) of the first mantissa data (M_IN1[a:0]), as a selection signal (SEL2). The second multiplexer 920 may include a selection node receiving the output value of the first multiplexer 910, i.e., each bit value (M_IN1[a], ..., M_IN1[1], M_IN1[0]) of the first mantissa data (M_IN1[a:0]). In one embodiment, when the selection signal (SEL2) is “0”, the second multiplexer 920 may output “0” from among the input data of the second multiplexer 920. In one embodiment, when the selection signal (SEL2) is “1”, the second multiplexer 920 may output second mantissa data (M_IN2[b:0]) of the second input data (IN2) from among the input data of the second multiplexer 920.

[0088] In one embodiment, the adder 930 may add the output data of the second multiplexer 920 and the output data from the accumulator 940 and transmit the added data to the accumulator 940 .

[0089] In one embodiment, the shifter 921 may shift the second mantissa data (M_IN2[b:0]) one bit to the left. In one embodiment, the shifter 921 may transmit the shifted data as a second input node of the second multiplexer 920.

[0090] In one embodiment, the number of cycles of the clock signal (CLK) is the same as the number of bits of the first mantissa data (M_IN1[a:0]), so that the above-mentioned operation can be repeated as many times as the number of bits of the first mantissa data (M_IN1[a:0]).

[0091] The mantissa calculation unit 900 according to an embodiment does not include a multiplier and can perform shift and add operations on input data to output a multiplied value of the input data. The mantissa calculation unit 900 according to an embodiment can receive data having different numbers of bits as input data and perform shift and add operations on the input data. The mantissa calculation unit 900 according to an embodiment has no limit on the number of bits of input data and performs shift and add operations by the number of bits of input data, so that the performance of the calculation device can be improved as the number of bits decreases.

[0092] 7, in one embodiment, when at least one of the first input data (IN1) or the second input data (IN2) is floating point data, the normalizer (NORMALIZER) 740 may normalize the exponent data (E_OUT) output from the exponent calculation unit 720 and the mantissa data (M_OUT) output from the mantissa calculation unit 730. The output data (OUT) output from the normalizer may be output to the accumulator 702 together with the sign data (S_OUT) output from the sign calculation unit 710. In another embodiment, when the first input data (IN1) and the second input data (IN2) are integer data, that is, when the exponent data (E_OUT) output from the exponent calculation unit 720 is "0", the normalizer 740 may output the mantissa data (M_OUT) output from the mantissa calculation unit 730 as the output data (OUT). The output data (OUT) output from the normalizer 740 can be output to the accumulation unit 702 together with the code data (S_OUT) output from the code calculation unit 710 .

[0093] In the accumulation unit 702 of FIG. 7, an adder (ADDER) 750 can perform an accumulation operation by adding data received from a multiplication unit 701 and data received from an accumulator (ACCUMULATOR) 760 .

[0094] FIG. 11 shows a timing diagram of the operations performed in the mantissa operation unit according to one embodiment.

[0095] Referring to FIG. 11, the first mantissa data (M_IN1[5:0]) is 6 bits, and is represented as 101101 (2) The second mantissa data (M_IN2) is 4 bits, and is 1101 (2) The first mantissa data (M_IN1) is a multiplier, the second mantissa data (M_IN2) is a multiplicand, and the clock signal (CLK) is output for 6 cycles (6CYCLE), which is the same as the number of bits of the first mantissa data (M_IN1) of the multiplier. The timing diagram of FIG. 11 will be described with reference to FIG. 9.

[0096] In the first cycle (1CYCLE), the counter 911 increments the first counter value (001 (2) ), and the first multiplexer 910 outputs the first mantissa data of the multiplier (101101 (2) The second multiplexer 920 can output the least significant bit "1" of the multiplicand. (2) The output data ("1") of the first multiplexer 910 is input as a selection signal (SEL2) of the second multiplexer 920, and the second multiplexer 920 receives the second mantissa data (1101 (2) In the first cycle, the accumulator 940 does not output any value, so the adder (ADDER) outputs the output data (1101) of the second multiplexer 920. (2) ) can be output as is and transmitted to the accumulator (ACC).

[0097] In the second cycle (2CYCLE), the counter 911 increments the second counter value (010) based on the clock signal (CLK). (2) ), and the first multiplexer 910 outputs the first mantissa data (101101 (2) The second multiplexer 920 can output the second bit “0” of the second mantissa data (1101 (2)) shifted one bit to the left, 11010 (2) The output data ("0") of the first multiplexer 910 is input as a selection signal (SEL2) of the second multiplexer 920, and the second multiplexer 920 can output "0" based on the selection signal (SEL2). In the second cycle, the accumulator 940 receives the output data (1101) of the adder 930 in the first cycle. (2) ), so the adder 930 combines the output data of the second multiplexer 920 ("0") and the output data of the accumulator 940 (1101 (2) ) added to the data (1101 (2) ) can be communicated to accumulator 940.

[0098] In the third cycle (3CYCLE), the counter 911 increments the third counter value (011 (2) ), and the first multiplexer 910 outputs the first mantissa data (101101 (2) The second multiplexer 920 can output the third bit of the second mantissa data (1101) as input data. (2) ) shifted 2 bits to the left, resulting in 110100 (2) The output data ("1") of the first multiplexer 910 is input as a selection signal (SEL2) of the second multiplexer 920, and the second multiplexer 920 receives the input data (110100) based on the selection signal (SEL2). (2) In the second cycle, the accumulator 940 can output the output data (1101 (2) ), so the adder 930 outputs the output data of the second multiplexer 920 (110100 (2) ) and the output data of the accumulator 940 (1101 (2) ) added to the data (1000001 (2) ) can be communicated to accumulator 940.

[0099] In the manner described above, after six cycles, the accumulator 940 receives as output data 1001001001 from the adder. (2) can be output to the normalizer (740 in FIG. 7).

[0100] FIG. 12 shows a timing diagram of the calculation performed in the mantissa calculation unit according to another embodiment.

[0101] In one embodiment, the controller 610 in the arithmetic device 600 may output a clock signal (CLK) based on information on the number of data bits of the input data (IN, IN2). In this case, the number of data bits of the input data (IN1, IN2) may be different. Therefore, the number of bits of the multiple input data (IN1, IN2) may be compared, and a clock signal based on the number of bits of the input data having a smaller number of bits may be output. The controller 610 may determine, among the multiple input data (IN1, IN2), the data having a smaller number of bits as a multiplier and the data having a larger number of bits as a multiplicand.

[0102] FIG. 12 shows an embodiment in which the multiplier and multiplicand are changed from those in FIG. 11. Specifically, the multiplier in FIG. 11 is 101101. (2) In FIG. 12, the second mantissa data (M_IN2) is the multiplicand, and in FIG. 11, the multiplicand 1101 is (2) In FIG. 12, this is the first mantissa data (M_IN1) of the multiplier. The clock signal (CLK) is (2) 12. In conjunction with the timing diagram of FIG. 12, reference is now made to FIG. 9.

[0103] In the first cycle (1CYCLE), the counter 911 increments the first counter value (01 (2) ), and the first multiplexer 910 outputs the first mantissa data (1101 (2) The second multiplexer 920 receives input data of "0" and the second mantissa data of the multiplicand (101101(2) The output data ("1") of the first multiplexer 910 is input as a selection signal (SEL2) of the second multiplexer 920, and the second multiplexer 920 receives the second mantissa data (101101) based on the selection signal (SEL2). (2) In the first cycle, the accumulator 940 does not output any value, so the adder 930 outputs the output data of the second multiplexer 920 (101101 (2) ) can be output as is and transmitted to the accumulator 940.

[0104] In the second cycle (2CYCLE), the counter 911 increments the second counter value (10 (2) ), and the first multiplexer 910 outputs the first mantissa data (1101 (2) The second multiplexer 920 receives the input data "0" and the second mantissa data (101101 (2) ) shifted one bit to the left (1011010 (2) ). The output data ("0") of the first multiplexer 910 is input as a selection signal (SEL2) of the second multiplexer 920, and the second multiplexer 920 can output "0" based on the selection signal (SEL2). In the second cycle, the accumulator 940 receives the output data (101101) of the adder 930 in the first cycle. (2) ), so the adder 930 combines the output data of the second multiplexer 920 ("0") and the output data of the accumulator 940 (101101 (2) ) added together (101101 (2) ) can be communicated to accumulator 940.

[0105] In the above-described manner, after four cycles, the accumulator 940 receives as output data 1001001001 from the adder. (2) can be output to the normalizer (740 in FIG. 7).

[0106] In this way, when the number of bits of the mantissa data input to the mantissa calculation unit is different, the data with the fewer bits among the input data can be determined as the multiplier, i.e., the input data of the first multiplexer 910. This has the advantage that the number of cycles of the clock signal (CLK) is reduced and the number of repetitions of the calculation performed by the mantissa calculation unit is reduced, thereby reducing the latency of the calculation on the input data.

[0107] FIG. 13 is an exemplary diagram for explaining multi-head attention according to an embodiment.

[0108] The multi-head attention 1300 is a mechanism used in a Transformer model, an Automatic Speech Recognition (ASR) model, and the like among neural network models, and has a form in which a scaled dot-product attention 1320 structure is superimposed. In one embodiment, the multi-head attention 1300 may perform self-attention regarding embedding of input data. Embedding refers to the result of converting natural language used by humans into a vector form that can be understood by machines, or a series of processes thereof.

[0109] When processing sequence data such as natural language, long-term dependency can be a problem. Self-attention is used to resolve such long-term dependency, and can be used to measure the relationship between words in a sentence. Specifically, a relationship value between each word and other words can be calculated, and this value is called an attention score. The attention score between words with a high degree of relationship can be high. Attention scores organized into a table are called an attention map. Multihead Attention 1300 can create multiple attention maps to check attention for various feature values.

[0110] In the multi-head attention 1300, the input of the scaled inner product attention layer 1320 includes a query (Q), a key (K), and a value (V). For example, when searching for the meaning of a particular word through an English dictionary, the particular word corresponds to the query, the word registered in the dictionary corresponds to the key, and the meaning of the key corresponds to the value.

[0111] The multi-head attention 1300 can reduce the dimensionality of the values ​​V, keys K, and queries Q through a first linear operation layer 1310, perform self-attention through h scaled dot-product attention layers 1320, and perform linear operations through concatenation 1330 and a second linear operation layer 1340 on the attention results.

[0112] In one embodiment, the linear operations performed by the first linear operation layer 1310 and the second linear operation layer 1340 may be referred to as matrix dot product operations. For example, the first linear operation 1310 may perform a dot product operation with a specific weight on the embedding vector of the input data in order to reduce the dimensions of the value V, key K, and query Q derived from the embedding information of the input data, and the second linear operation block 1340 may perform a dot product operation with a specific weight on the concatenated output matrix.

[0113] The first linear arithmetic layer 1310 and the second linear arithmetic layer 1340 may use an arithmetic device according to an embodiment. For example, the first linear arithmetic layer 1310 and the second linear arithmetic layer 1340 may receive an input matrix and a weight matrix as input data. In an embodiment, the elements of the input matrix and the weight matrix may be real numbers, for example, floating point data represented by a floating point, or integer data. In an embodiment, the elements of the input matrix and the weight matrix may have different precisions, i.e., bits. The arithmetic device (121 in FIG. 1) according to an embodiment may perform an inner product operation on the input matrix and the weight matrix.

[0114] FIG. 14 is an exemplary diagram for explaining the scaled dot-product attention of FIG.

[0115] The matrix multiplication layer 1311 of the scaled dot product attention 1320 may perform a dot product operation between the key K and the query Q and output an attention score indicating similarity. The scaling layer 1313 may perform scaling to adjust the magnitude of the attention score output from the first matrix multiplication layer 1311. The mask layer 1315 may prevent attention of erroneous connections through masking. The softmax calculation layer 1315 may calculate weights based on the attention scores, and the second matrix multiplication layer 1317 may perform a dot product operation between the weights output from the softmax calculation layer 1325 and the value V.

[0116] The first matrix multiplication layer 1311 and the second matrix multiplication layer 1327 may use a calculation device according to an embodiment. For example, the first matrix multiplication layer 1311 may receive a key K vector and a query Q vector as input data, and the second matrix multiplication layer 1327 may receive a value V vector and a weight matrix as input data. In an embodiment, the elements of the input data vectors of the first matrix multiplication layer 1311 and the second matrix multiplication layer 1327 may be real numbers, for example, floating point data represented by floating point numbers, or integer data. In an embodiment, the elements of the input data vectors of the first matrix multiplication layer 1311 and the second matrix multiplication layer 1327 may have different precisions, i.e., bits. The calculation device (121 in FIG. 1) according to an embodiment may perform an inner product operation on the input vector and the weight matrix.

[0117] Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims also belong to the scope of the present invention. [Explanation of symbols]

[0118] 100 Neural Processing System 110 Central Processing Unit 120 Neural Processing Unit 121 Arithmetic equipment 130 Volatile memory device 140 Non-volatile memory device 150 User Interface 600 Computing equipment 610 Controller 620, 700 arithmetic circuit 710 Sign operation section 720 Exponential calculation section 730, 900 Mantissa Calculation Section 740 Normalizer 750 Adder 760 Accumulator 810, 820, 830 Multiplexer 841, 843 Adder 911 Counter 910, 920 Multiplexer 921 Shifter 930 Adder 940 Accumulator

Claims

1. a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal indicating the first data type, a second signal indicating the second data type, and a clock signal based on the number of bits of the first input data and the second input data; an arithmetic circuit that performs a multiplication operation on the first input data and the second input data based on the first signal, the second signal, and the clock signal to generate output data; 13. A computing device comprising:

2. the first input data includes code data and integer data; The arithmetic unit of claim 1 , wherein the second input data includes sign data, exponent data, and mantissa data.

3. The arithmetic circuit includes: a first circuit for outputting code data of the output data; a second circuit for outputting exponent data of the output data based on the first signal and the second signal; 3. The arithmetic device according to claim 2, further comprising: a third circuit that outputs mantissa data of the output data based on the clock signal.

4. 4. The arithmetic device according to claim 3, wherein the first circuit includes an exclusive OR (XOR) gate that receives the code data of the first input data and the code data of the second input data and outputs the code data of the output data.

5. The second circuit is The arithmetic unit according to claim 3 , further comprising: an input section for outputting exponent data of the second input data.

6. The third circuit is 4. The arithmetic device according to claim 3, further comprising: a first input data unit that receives first data corresponding to integer data of the first input data; and a second input data unit that receives second data corresponding to mantissa data of the second input data; and a multiplication operation is performed on the first data and the second data.

7. 1. An arithmetic device for performing a multiplication operation on first data having a first number of bits and second data having a second number of bits different from the first number of bits, a first multiplexer including a selection node for receiving an output signal of a counter for counting the number of cycles of a clock signal based on the first number of bits, and a plurality of input nodes for receiving respective bit values ​​of the first data; a second multiplexer including a selection node for receiving output data of the first multiplexer, a first input node for receiving a first value, and a second input node for receiving the second data or data obtained by shifting the second data by one bit from a shifter; a first adder that performs an addition operation on the output data of the second multiplexer based on the clock signal; 13. A computing device comprising:

8. the first multiplexer sequentially outputs one bit at a time from a least significant bit value of the first data based on an output signal of the counter; 8. The arithmetic device according to claim 7, wherein the second multiplexer outputs the first value when the output data of the first multiplexer is "0", and outputs the second data or the output data of the shifter when the output data of the first multiplexer is "1".

9. The arithmetic unit according to claim 7 , wherein the first number of bits is less than the second number of bits.

10. A memory for storing data; a neural processing unit that receives an input matrix and a weight matrix corresponding to input data from the memory, performs a matrix inner product operation on the input matrix and the weight matrix, and outputs a result of the matrix inner product operation as an output matrix; A neural processing system comprising: the input matrix includes elements of a first data type and the weight matrix includes elements of a second data type different from the first data type; the neural processing unit includes a calculation device that outputs exponent data of elements of the input matrix or exponent data of elements of the weight matrix as exponent data of elements of the output matrix based on the first data type and the second data type; Neural processing system.

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