Display device

Abstract

To provide a display device capable of improving yield.SOLUTION: A display device in an embodiment includes a substrate including a display region to display images and a peripheral region around the display region, an organic insulating layer disposed over the substrate, a rib layer covering the organic insulating layer and having a plurality of pixel openings in the display region, and a plurality of display elements overlapping with the respective pixel openings. The substrate includes a first side. The organic insulating layer includes a second side existing between the first side and the display region in a plan view, and a convex part projecting from the second side toward the first side in the plan view, and provided at a position apart from an end part of the second side. The second side further includes a first linear part parallel to the first side, and a concave part existing between the first linear part and the convex part and depressed in a direction away from the first side.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present embodiment relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology that enables improvement of yields in this type of display device is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of improving the yield. [Means for solving the problem]

[0005] A display device according to one embodiment includes a substrate having a display region for displaying an image and a peripheral region around the display region, an organic insulating layer formed of an organic insulating material and disposed above the substrate, a rib layer formed of an inorganic insulating material, covering the organic insulating layer and having a plurality of pixel openings in the display region, and a plurality of display elements overlapping the plurality of pixel openings. The substrate has a first side. The organic insulating layer has a second side located between the first side and the display region in a plan view, and a convex portion protruding from the second side toward the first side in a plan view and provided at a position away from an end of the second side. Furthermore, the second side has a first straight portion parallel to the first side, and a concave portion located between the first straight portion and the convex portion and recessed in a direction away from the first side. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of a display device according to an embodiment. [Diagram 5] FIG. 5 is a schematic enlarged plan view of the vicinity of the convex portion of the organic insulating layer shown in FIG. [Figure 6] FIG. 6 is a schematic plan view of the substrate, the organic insulating layer, and the slits in the vicinity of the convex portion. [Figure 7] FIG. 7 is a schematic cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a schematic enlarged plan view of region VIII in FIG. [Figure 9] FIG. 9 is a schematic plan view of a mother substrate according to an embodiment. [Figure 10A]FIG. 10A is a schematic cross-sectional view showing a step of forming a panel portion on a mother substrate. [Figure 10B] FIG. 10B is a schematic cross-sectional view showing a step subsequent to FIG. 10A. [Figure 10C] FIG. 10C is a schematic cross-sectional view showing a step subsequent to FIG. 10B. [Figure 10D] FIG. 10D is a schematic cross-sectional view showing a step subsequent to FIG. 10C. [Figure 10E] FIG. 10E is a schematic cross-sectional view showing a step subsequent to FIG. 10D. [Figure 10F] FIG. 10F is a schematic cross-sectional view showing a step subsequent to FIG. 10E. [Figure 10G] FIG. 10G is a schematic cross-sectional view showing a step subsequent to FIG. 10F. [Figure 11] FIG. 11 is a schematic plan view of a panel portion cut out from a mother board. [Figure 12] FIG. 12 is a schematic enlarged plan view of the vicinity of the protruding portion in the panel portion. [Figure 13] FIG. 13 is a schematic plan view of the substrate, the slits and the organic insulating layer in the panel portion. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a part of a panel section on which a laminated film is formed by vapor deposition. [Figure 15] FIG. 15 is a diagram showing a comparative example to the embodiment. [Figure 16] FIG. 16 is a diagram showing a modification of the embodiment. [Figure 17] FIG. 17 is a diagram showing another modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0008] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of a plane that includes the X-direction and the Y-direction. Moreover, viewing various elements parallel to the Z-direction is called planar view.

[0009] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0010] 1 is a diagram showing an example of the configuration of a display device DSP according to an embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0011] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0012] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0013] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0014] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example of Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0016] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0018] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and a column in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG.

[0019] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio.

[0020] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.

[0021] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0022] A conductive partition wall 6A (first partition wall) is disposed above the rib layer 5. The partition wall 6A entirely overlaps the rib layer 5 and has the same planar shape as the rib layer 5. That is, the partition wall 6A has openings in each of the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition wall 6A are lattice-shaped in a planar view and surround each of the display elements DE1, DE2, and DE3. The partition wall 6A serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0023] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes unevenness caused by the circuit layer 11.

[0024] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0025] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6A is called an overhanging shape.

[0026] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0027] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6A.

[0028] The display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. The display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. The display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0029] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0030] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located around the partition wall 6A (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located around the partition wall 6A (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located around the partition wall 6A (a part that constitutes the display element DE3).

[0031] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6A around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6A around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6A around the subpixel SP3.

[0032] 3, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6A. Also, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6A.

[0033] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least throughout the entire display area DA, and a part of them extends into the peripheral area SA.

[0034] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0035] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0036] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0037] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0038] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of light-emitting layers.

[0039] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0040] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0041] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. The metal material forming the lower layer may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the upper layer may be, for example, ITO or IZO. The upper portion 62 may have a single layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0042] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0043] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.

[0044] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0045] 4 is a schematic plan view of the display device DSP. The dotted portion in the figure indicates the area where the organic insulating layer 12 is disposed. That is, the organic insulating layer 12 is disposed not only in the display area DA but also in the peripheral area SA.

[0046] The organic insulating layer 12 has an outer shape that is slightly smaller than the substrate 10. As a result, a blank area BA that does not overlap with the organic insulating layer 12 is formed on the edge of the substrate 10.

[0047] The substrate 10 has a first side S1 (the bottom side in the drawing) extending in the X direction. The organic insulating layer 12 has a second side S2 located between the first side S1 and the display area DA. The second side S2 is, for example, parallel to the first side S1.

[0048] The organic insulating layer 12 has a pair of protrusions PT1, PT2 protruding from the second side S2 toward the first side S1. The protrusion PT1 is located near the end E1 (the end on the left side in the figure) of the second side S2. The protrusion PT2 is located near the end E2 (the end on the right side in the figure) of the second side S2. In this embodiment, the protrusion PT1 is provided at a position away from the end E1. Also, the protrusion PT2 is provided at a position away from the end E2.

[0049] The rib layer 5 shown in Figures 2 and 3 is disposed not only in the display area DA but also in the peripheral area SA. For example, the outer shape of the rib layer 5 matches the outer shape of the substrate 10. The rib layer 5 has a slit 51 (first slit). The slit 51 entirely overlaps with the organic insulating layer 12. The slit 51 is formed continuously along the outer shape of the organic insulating layer 12, and surrounds the display area DA except for the second side S2 side. One end of the slit 51 overlaps with the protrusion PT1. The other end of the slit 51 overlaps with the protrusion PT2.

[0050] In the example of Fig. 4, four terminal parts T1 and four terminal parts T2 are arranged in the peripheral area SA. These terminal parts T1 and T2 are both located between the display area DA and the second side S2. Each terminal part T2 is located between the terminal part T1 and the display area DA.

[0051] A flexible circuit board for supplying a voltage or a signal to the display device DSP is mounted on each terminal T1. An IC chip (driver) for controlling image display is mounted on each terminal T2. The flexible circuit board and the IC chip are examples of electronic components.

[0052] A plurality of wirings W are further arranged in the peripheral area SA. In the example of Fig. 4, four wirings W extend in the Y direction from each terminal portion T1. One end of each wiring W is connected to the terminal portion T1, and the other end is located on the first side S1. Each wiring W intersects with the second side S2 between the protrusions PT1 and PT2. As will be described in detail later, in the manufacturing process of the display device DSP, a test pad is connected to each wiring W.

[0053] The positions and the number of the terminals T1, T2, and the wirings W are not limited to the example shown in Fig. 4. The display device DSP does not need to include the terminals T2. In this case, the IC chip described above may be mounted on another location such as a flexible circuit board.

[0054] 5 is a schematic enlarged plan view of the vicinity of the protrusion PT1. As described above, the protrusion PT1 is spaced apart from the end E1 of the second side S2. The distance Dx in the X direction between the end E1 and the protrusion PT1 is, for example, 2 mm or more.

[0055] The rib layer 5 further has lattice-shaped slits 52 (second slits) in the peripheral region SA. Furthermore, a large number of partition walls 6B (second partition walls) are arranged around the slits 52. The slits 52 are located between each side of the organic insulating layer 12, including the second side S2, and the display region DA.

[0056] The multiple partition walls 6B are arranged at intervals along the outline of the substrate 10, the outline of the organic insulating layer 12, and the slits 51. For example, the multiple partition walls 6B are located in the region between the first side S1 and the second side S2, the region between the second side S2 and the slit 51, and the region between the slit 51 and the slit 52. In the example of Fig. 5, parts of the multiple partition walls 6B overlap the protrusion PT1.

[0057] A pair of L-shaped alignment marks M1 and a cross-shaped alignment mark M2 are disposed near the protrusion PT1. The alignment marks M1 and M2 can be formed of, for example, a metal layer included in the circuit layer 11 described above.

[0058] The pair of alignment marks M1 are located between the protrusion PT1 and the end E1 in the X direction, and overlap with the blank area BA and the second side S2. The slit 51 has a bent portion 51a that is bent along the alignment marks M1. As a result, the slit 51 does not overlap with the alignment marks M1.

[0059] The alignment mark M2 is located in an area in which the slits 52 are arranged. In the example of Fig. 5, the lattice of the slits 52 opens in a rectangular shape around the alignment mark M2. As a result, the slits 52 do not overlap with the alignment mark M2.

[0060] The second side S2 has a straight line portion L1 (first straight line portion) parallel to the first side S1, and a recessed portion V located between the straight line portion L1 and the protruding portion PT1 in the X direction. The recessed portion V is recessed in a direction away from the first side S1 (upward in the figure). The slit 51 further has a bent portion 51b bent along the recessed portion V.

[0061] The blank area BA surrounded by the first side S1, the second side S2, and the protruding portion PT1 has a first area A1 located between the first side S1 and the straight portion L1 in the Y direction, and a second area A2 located between the first side S1 and the recessed portion V in the Y direction. In the example of Fig. 5, the width of the first area A1 in the X direction is larger than the width of the second area A2 in the X direction. This example is not limited to this, and the width of the second area A2 in the X direction may be equal to or larger than the width of the first area A1 in the X direction.

[0062] 5, the second side S2 also has a recess V on the right side of the protrusion PT1. That is, the protrusion PT1 is located between a pair of second regions A2.

[0063] 6 is a schematic plan view of the substrate 10, the organic insulating layer 12, and the slits 51 in the vicinity of the protrusion PT1. In this figure, the partition walls 6B and the alignment marks M1 are omitted.

[0064] In the example of FIG. 6, the protrusion PT1 has a straight line portion L2 (second straight line portion) that is perpendicular to the first side S1. The straight line portion L2 corresponds to the side of the protrusion PT1 that faces the second region A2. The recess V of the second side S2 has straight line portions L3a, L3b, and L3c (third straight line portions). The straight line portions L3a and L3c are inclined with respect to, for example, the X direction and the Y direction. The straight line portion L3b is parallel to, for example, the X direction.

[0065] The straight portions L1 and L3a form an angle θ1, the straight portions L3a and L3b form an angle θ2, the straight portions L3b and L3c form an angle θ3, and the straight portions L3c and L2 form an angle θ4. The angles θ1, θ2, θ3, and θ4 all correspond to the interior angles of the margin area BA. In the example of FIG. 6, the angles θ1, θ2, θ3, and θ4 are all obtuse angles (90° < θ1, θ2, θ3, θ4). However, any one of the angles θ1, θ2, θ3, and θ4 may form a right angle or an acute angle.

[0066] In the example of FIG. 6, the straight portions L1 and L3a are connected by the curved portion C1, the straight portions L3a and L3b are connected by the curved portion C2, the straight portions L3b and L3c are connected by the curved portion C3, and the straight portions L3c and L2 are connected by the curved portion C4. These curved portions C1, C2, C3, and C4 are all arc-shaped.

[0067] The width Wy1 of the first region A1 in the Y direction is smaller than the width Wy2 of the second region A2 in the Y direction (Wy1 < Wy2). The width Wy1 corresponds to the distance between the first side S1 and the straight portion L1. The width Wy2 corresponds to the distance between the first side S1 and the straight portion L3b.

[0068] The width Wy1 is, for example, 0.2 mm or less. The width Wy2 is, for example, 0.5 mm or more larger than the width Wy1. The width Wp of the convex portion PT1 in the X direction is, for example, smaller than the width Wy2 (Wp < Wy2).

[0069] Near the convex portion PT2, the same configuration as that near the convex portion PT1 shown in FIGS. 5 and 6 can be applied. For example, the distance in the X direction between the convex portions PT1 and PT2 is larger than the distance Dx.

[0070] FIG. 7 is a schematic cross-sectional view of the display device DSP along the line VII-VII in FIG. 5. In this figure, the illustration of a part of the substrate 10 and the circuit layer 11 is omitted.

[0071] 7, an organic insulating layer 13 is disposed below the organic insulating layer 12. Furthermore, an inorganic insulating layer 14 is disposed below the organic insulating layer 13. The organic insulating layer 13 and the inorganic insulating layer 14 are, for example, a part of the circuit layer 11.

[0072] The organic insulating layer 13 is made of an organic insulating material such as polyimide, etc. The inorganic insulating layer 14 is made of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride, etc.

[0073] 7, the width of organic insulating layer 13 is greater than the width of organic insulating layer 12. Both ends of organic insulating layer 13 protrude beyond both ends of organic insulating layer 12. The organic insulating layers 12 and 13 shown in FIG. 7 form a protrusion PT1. Similarly, protrusion PT2 can be formed by organic insulating layers 12 and 13.

[0074] The rib layer 5 covers the organic insulating layers 12 and 13 and the inorganic insulating layer 14. In the cross section of Fig. 7, a pair of partition walls 6B are disposed above the protrusion PT1, and a slit 51 is provided between these partition walls 6B.

[0075] The partition wall 6B is formed by the same process as the partition wall 6A shown in Fig. 3 and has the same structure as the partition wall 6A. That is, the partition wall 6B has a lower part 61 and an upper part 62. Furthermore, the lower part 61 of the partition wall 6B has a bottom layer 63 and a shaft layer 64.

[0076] The upper surface of the organic insulating layer 12 is exposed from the rib layer 5 through the slits 51. In the example of Fig. 7, the upper surface of the organic insulating layer 12 has a groove 120 that overlaps with the slits 51. A part of the groove 120 extends below the rib layer 5. As a result, the edge of the rib layer 5 along the slits 51 protrudes above the groove 120. In other words, an overhang structure is formed by the edge and the groove 120.

[0077] 4 to 6, the organic insulating layer 13 is also disposed substantially entirely below the organic insulating layer 12. Therefore, the slits 51 and 52 overlap the organic insulating layers 12 and 13 in plan view. Moreover, the groove 120 is formed so as to entirely overlap the slit 51, not just at the position shown in the cross section of FIG.

[0078] Fig. 8 is a schematic enlarged plan view of region VIII in Fig. 5. In the peripheral region SA, a plurality of partitions 6C (third partitions) are arranged in a region surrounded by slits 52.

[0079] For example, the partition wall 6C is formed in the same process as the partition walls 6A and 6B, and has a similar structure to the partition walls 6A and 6B. That is, the partition wall 6C has a lower portion 61 and an upper portion 62. Furthermore, the lower portion 61 of the partition wall 6C has a bottom layer 63 and an axis layer 64.

[0080] In the example of Fig. 8, the partition 6C has three openings APa, APb, and APc. These openings APa, APb, and APc have the same shape as the openings of the partition 6A surrounding the subpixels SP1, SP2, and SP3 shown in Fig. 2. That is, the openings APb and APc are aligned with the opening APa in the X direction, and the openings APb and APc are aligned with the opening APc in the Y direction. Furthermore, the opening APa is larger than the opening APb, and the opening APb is larger than the opening APc.

[0081] The partition 6C may have openings of different shapes from the openings APa, APb, and APc. The number of openings that the partition 6C has is not limited to three, and may be two or less, or four or more.

[0082] The cross-sectional structure near slit 52 is similar to the cross-sectional structure near slit 51 shown in Fig. 7. That is, a groove 120 exists below slit 52, and an overhang structure is formed by the edge of slit 52 and groove 120.

[0083] Next, an example of a method for manufacturing the display device DSP will be described. When manufacturing the display device DSP, a mother substrate on which a plurality of regions (panel portions) each corresponding to the display device DSP is formed is prepared.

[0084] 9 is a schematic plan view of the mother substrate MB according to this embodiment. The mother substrate MB has a rectangular shape as shown in the figure, but is not limited to this example.

[0085] The mother substrate MB has a large substrate 10a. The substrate 10a is made of the same material as the above-mentioned substrate 10. The substrate 10a has a plurality of panel portions PP formed thereon and arranged in a matrix.

[0086] Each panel unit PP includes various elements, such as a display area DA, that are included in the display device DSP described with reference to Figures 1 to 8. In the example of Figure 9, the mother board MB has eight panel units PP, but is not limited to this example.

[0087] The outer shape of each panel portion PP corresponds to a cut line CL1 along which each panel portion PP is cut from the mother substrate MB. Each panel portion PP also has a cut line CL2. The cut line CL2 corresponds to the first side S1 of the substrate 10 described above.

[0088] 10A to 10G are schematic cross-sectional views showing the process of forming a panel portion PP on a mother substrate MB. In Fig. 10A to 10G, elements below an organic insulating layer 12 are omitted.

[0089] In forming the panel portion PP, first, a substrate 10a shown in Fig. 9 is prepared, and a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10a. Next, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 as shown in Fig. 10A.

[0090] 10B, the rib layer 5 and the partition wall 6A are formed. The pixel openings AP1, AP2, AP3 of the rib layer 5 may be provided after the partition wall 6A is formed or before the partition wall 6A is formed. For example, the above-mentioned slits 51 and 52 are formed at the same time as the pixel openings AP1, AP2, AP3 are formed. Furthermore, the above-mentioned partition walls 6B and 6C are formed at the same time as the partition wall 6A is formed.

[0091] After the rib layer 5 and the partition walls 6A, 6B, and 6C are formed, a process for forming the display elements DE1, DE2, and DE3 is carried out. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0092] In forming the display element DE1, first, as shown in Fig. 10C, a laminated film FL1 and a sealing layer SE11 are formed. As shown in Fig. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1.

[0093] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by deposition, and the sealing layer SE11 is formed by CVD (Chemical Vapor Deposition).

[0094] The laminated film FL1 and the sealing layer SE11 are formed over the entire substrate 10a, including not only the display area DA of each panel portion PP, but also the peripheral area SA and the area between adjacent panel portions PP. The laminated film FL1 is divided into a plurality of portions by overhanging partition walls 6A, 6B, and 6C. The sealing layer SE11 continuously covers each divided portion of the laminated film FL1 and the partition walls 6A, 6B, and 6C.

[0095] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R is disposed on the sealing layer SE11 as shown in Fig. 10D. The resist R covers the subpixel SP1 and a part of the partition wall 6A around it.

[0096] Thereafter, by etching using the resist R as a mask, the laminated film FL1 and the sealing layer SE11 are removed in portions exposed from the resist R, as shown in FIG. 10E. In other words, the laminated film FL1 and the sealing layer SE11 are left in portions overlapping with the lower electrode LE1, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. For example, the etching includes wet etching and dry etching that are performed in sequence on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R is removed.

[0097] The display element DE2 is formed in the same manner as the display element DE1. That is, in forming the display element DE2, a laminated film FL2 and a sealing layer SE12 are formed on the entire substrate 10a. As shown in FIG. 3, the laminated film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0098] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by vapor deposition. The sealing layer SE12 is formed by CVD. The laminated film FL2 is divided into a plurality of parts by overhanging partition walls 6A, 6B, and 6C. The sealing layer SE12 continuously covers each divided part of the laminated film FL2 and the partition walls 6A, 6B, and 6C. By patterning such laminated film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2 as shown in FIG. 10F.

[0099] The display element DE3 is formed in the same manner as the display elements DE1 and DE2. That is, when the display element DE3 is formed, a laminated film FL3 and a sealing layer SE13 are formed on the entire substrate 10a. As shown in FIG. 3, the laminated film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0100] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by vapor deposition. The sealing layer SE13 is formed by CVD. The laminated film FL3 is divided into a plurality of parts by overhanging partition walls 6A, 6B, and 6C. The sealing layer SE13 continuously covers each divided part of the laminated film FL3 and the partition walls 6A, 6B, and 6C. By patterning such laminated film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3 as shown in FIG. 10G.

[0101] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are formed in this order as shown in Fig. 3. Furthermore, each panel portion PP is cut out from the mother substrate MB along the cut line CL1.

[0102] 11 is a schematic plan view of the panel portion PP cut out from the mother substrate MB. The panel portion PP includes a substrate 10b that is a part of the substrate 10a. The substrate 10b includes a main body portion 101 and a pad portion 102 that are separated by a cut line CL2.

[0103] The main body 101 includes the display area DA, the peripheral area SA, the terminal portion T1, and the terminal portion T2 shown in Fig. 4. The pad portion 102 includes a plurality of test pads PD. Each test pad PD is connected to the terminal portion T1 by a wire W. Each wire W crosses the cut line CL2.

[0104] The organic insulating layer 12 has a first portion 121 formed on the main body portion 101 and a second portion 122 formed on the pad portion 102. The first portion 121 and the second portion 122 are separated by a gap along the cut line CL2 and are connected by protrusions PT1 and PT2.

[0105] The first portion 121 and the second portion 122 have outer shapes that are slightly smaller than the main body portion 101 and the pad portion 102. As a result, a blank area BA that does not overlap with the organic insulating layer 12 is formed on the edge of the substrate 10b.

[0106] The above-mentioned rib layer 5 is formed, for example, on the entire main body portion 101 and the pad portion 102. The slits 51 of the rib layer 5 are formed not only in the main body portion 101 but also in the pad portion 102.

[0107] 11, the slit 51 is formed along the outline of the first portion 121 and the second portion 122 of the organic insulating layer 12, and overlaps with the protrusions PT1 and PT2. That is, the organic insulating layer 12 is provided entirely below the slit 51. For example, the above-mentioned organic insulating layer 13 is provided entirely below the organic insulating layer 12. The slit 51 surrounds the display area DA, the terminal portion T1, the terminal portion T2, the wiring W, and the test pad PD.

[0108] The test pads PD are used in an image display test process, in which, for example, a test probe is brought into contact with the test pads PD, and a voltage is applied to each of the display elements DE1, DE2, and DE3 in the display area DA via the wiring W and the terminal portion T1.

[0109] After the inspection process, the panel part PP is cut along the cut line CL2. When cutting, a scribe line is first formed along the cut line CL2 by a scribing tool (e.g., a scribing wheel). Then, the panel part PP is fractured along the scribe line. The main body part 101 from which the pad part 102 is cut corresponds to the display device DSP described with reference to FIGS. 1 to 8.

[0110] 12 is a schematic enlarged plan view of the vicinity of the protrusion PT1 in the panel portion PP. After the panel portion PP is cut, the above-mentioned first side S1 is formed along the cut line CL2.

[0111] The configuration of the main body 101 in the vicinity of the cut line CL2 is similar to the configuration of the display device DSP in the vicinity of the first side S1 shown in Fig. 5. The configuration of the pad section 102 in the vicinity of the cut line CL2 is similar to the configuration of the main body 101 in the vicinity of the cut line CL2. That is, the pad section 102 has a plurality of partition walls 6B, a pair of alignment marks M1, and slits 51 and 52, just like the main body 101. Although not shown in Fig. 12, the partition wall 6C shown in Fig. 8 is arranged in the area of ​​the pad section 102 surrounded by the slit 52.

[0112] 12, in the vicinity of the cut line CL2, the main body portion 101 and the pad portion 102 have a configuration that is line-symmetrical with respect to the cut line CL2. The cut line CL2 passes between a pair of alignment marks M1 of the main body portion 101 and a pair of alignment marks M1 of the pad portion 102. From the viewpoint of forming a good scribe line, it is preferable that the partition wall 6B is not disposed in a position that overlaps with the cut line CL2.

[0113] 13 is a schematic plan view of the substrate 10b, the slit 51, and the first and second portions 121 and 122 of the organic insulating layer 12 in the vicinity of the protrusion PT1. In this figure, the partition wall 6B and the alignment mark M1 are omitted.

[0114] Scribing is performed in the scribing direction CD in the drawing. That is, the scribing tool first contacts the starting point ST of the substrate 10b located near the protruding portion PT1, passes between the first portion 121 and the second portion 122 of the organic insulating layer 12, and reaches the ending point of the substrate 10b located near the protruding portion PT2.

[0115] The cut line CL2 is perpendicular to the straight line portion L2 of the protruding portion PT1. That is, the scribing direction CD is perpendicular to the straight line portion L2. The same is true for the protruding portion PT2.

[0116] 12 are used to align the scribe tool. The two alignment marks M1 on the main body 101 can also be used to check for deviations in the cutting position after the pad portion 102 is cut off.

[0117] Here, some advantages of this embodiment will be described. When the display elements DE1, DE2, DE3 are formed, the laminated films FL1, FL2, FL3 are also formed in the peripheral area SA and the pad section 102. The laminated films FL1, FL2, FL3 formed by vapor deposition have a low adhesion to the base, and therefore may peel off from the base during the manufacturing process of the display device DSP. If this peeling spreads, the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 thereon may peel off and become undesirable particles.

[0118] In the display area DA, the stacked films FL1, FL2, and FL3 are finely divided by the lattice-shaped partition wall 6A. Therefore, the stacked films FL1, FL2, and FL3 are unlikely to peel off from the base. In addition, as described below, in this embodiment, the partition wall 6B, the partition wall 6C, the slits 51, and the slits 52 suppress peeling of the stacked films FL1, FL2, and FL3 in the peripheral area SA and the pad portion 102.

[0119] 14 is a schematic cross-sectional view showing a part of the panel unit PP on which the laminated film FL1 is formed. The cross-section shown here is taken across the protrusion PT1, similarly to FIG.

[0120] The laminated film FL1 is divided by an overhanging partition wall 6B. Furthermore, in this embodiment, an overhang structure is formed by the slits 51 in the rib layer 5 and the grooves 120 in the organic insulating layer 12. Therefore, the laminated film FL1 is also divided by the slits 51.

[0121] 14, the laminated film FL1 is also divided by the partition wall 6C and the slit 52. In this manner, in the present embodiment, the laminated film FL1 is also divided in the peripheral area SA and the pad portion 102, so that the laminated film FL1 is less likely to peel off. The same is true for the laminated films FL2 and FL3.

[0122] The groove 120 can be formed by performing etching, after the slits 51 and 52 are formed, in which the etching rate for the organic insulating layer 12 is faster than the etching rate for the rib layer 5. This etching may be performed only for the purpose of forming the groove 120, or may be performed when forming the partition walls 6A, 6B, and 6C.

[0123] As shown in Fig. 11, if the slit 51 is formed along the outer shape of the panel portion PP, the laminated films FL1, FL2, FL3 formed on the panel portion PP can be entirely separated from the laminated films FL1, FL2, FL3 formed around it. Also, if a large number of partition walls 6B, 6C are arranged with gaps therebetween as shown in Fig. 8 and Fig. 12, the partition walls 6B, 6C are less likely to inhibit the spread of a patterning resist that is placed in a process after the formation of the partition walls 6B, 6C.

[0124] Fig. 15 is a diagram showing a comparative example of the present embodiment, and shows a schematic configuration in the vicinity of the protrusion PT1, similar to Fig. 13. In this comparative example, the protrusion PT1 connects the ends in the X direction of the first portion 121 and the second portion 122 of the organic insulating layer 12. As a result, the distance between the protrusion PT1 and the starting point ST is shorter than in the example of Fig. 13.

[0125] During the above-mentioned scribing, the scribe tool cuts off the protruding parts PT1 and PT2. The scribe tool is in the middle of accelerating near the starting point ST. If the scribe tool hits the protruding part PT1 in this state, the scribe tool may shake, and a good scribe line may not be formed.

[0126] In contrast, in this embodiment, the protrusion PT1 is separated from the end E1 of the second side S2. This ensures an acceleration distance until the scribing tool hits the protrusion PT1, and makes it possible to form a good scribe line by suppressing vibration of the scribing tool. As described above, if the distance Dx in the X direction between the end E1 of the second side S2 and the protrusion PT1 is, for example, 2 mm or more, a sufficient effect of suppressing vibration of the scribing tool can be obtained.

[0127] 16 and 17 are diagrams showing modifications of this embodiment, and show the schematic configuration in the vicinity of the protruding portion PT1 as in FIG. 13. In these modifications, the protruding portion PT1 is also spaced apart from the end portion E1. Therefore, the above-mentioned acceleration distance can be ensured, and a good scribe line can be formed. However, in these modifications, the second side S2 is generally linear. In other words, the second side S2 does not have the recessed portion V.

[0128] In the modification of FIG. 16, the second side S2 and the side (straight line portion L2) of the protrusion PT1 are perpendicular to each other. When the partition walls 6A, 6B, and 6C are formed, the materials of the bottom layer 63, the axis layer 64, and the upper portion 62 are formed over the entire substrate 10a shown in FIG. 9. The materials are then patterned into the shapes of the partition walls 6A, 6B, and 6C. When the second side S2 and the straight line portion L2 are perpendicular to each other as shown in FIG. 16, the materials of the partition walls 6A, 6B, and 6C cannot be completely removed from the corners formed by them, and tend to remain as residues 6x. The residues 6x are conductive and may be a cause of electrostatic breakdown.

[0129] In the modified example of FIG. 17, the side of the protrusion PT1 is an arc shape centered on the cut line CL2. With this configuration, residue 6x is less likely to be generated. However, if the scribing tool is even slightly misaligned from the cut line CL2 in the Y direction, the scribing tool will hit the side of the protrusion PT1 at an angle. In this case, there is a possibility that the scribing tool will shake.

[0130] In this embodiment, as shown in Fig. 6, the second side S2 has a recess V. Furthermore, all of the interior angles formed in the recess V are obtuse angles. Even with this configuration, residue 6x is unlikely to be generated, as in the modified example of Fig. 17.

[0131] Furthermore, in this embodiment, the recess V and the linear portions L1, L2, L3a, L3b, and L3c around it are connected by arc-shaped curved portions C1, C2, C3, and C4. With this configuration, the residue 6x can be more suitably suppressed.

[0132] In addition, in this embodiment, by providing the recessed portion V, a relatively long straight portion L2 can be formed on the side of the protruding portion PT1. This makes it easier for the scribing tool to perpendicularly contact the side of the protruding portion PT1 even if the scribing tool deviates from the cut line CL2. As a result, it is possible to suppress the shaking of the scribing tool.

[0133] In this way, the display device according to this embodiment can suppress the peeling of the laminated films FL1, FL2, and FL3 and electrostatic breakdown caused by the residue 6x, and can perform good cutting along the cut line CL2. As a result, the yield of the display device DSP is improved. In addition, various other advantageous effects can be obtained from this embodiment.

[0134] All display devices and manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display device and manufacturing method thereof described above as embodiments of the present invention belong to the scope of the present invention as long as they include the gist of the present invention.

[0135] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0136] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0137] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13...sealing layer, 5...rib layer, 51, 52...slit, 6A, 6B, 6C...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 12...organic insulating layer, 120...groove, PT1, PT2...convex part.

Claims

1. A substrate having a display area for displaying an image and a peripheral area surrounding the display area; an organic insulating layer formed of an organic insulating material and disposed above the substrate; a rib layer formed of an inorganic insulating material, covering the organic insulating layer, and having a plurality of pixel openings in the display region; a plurality of display elements respectively overlapping the plurality of pixel apertures; Equipped with the substrate has a first side; The organic insulating layer is a second side located between the first side and the display area in a plan view; a protrusion protruding from the second side toward the first side in a plan view and provided at a position away from an end of the second side; having The second side is a first straight line portion parallel to the first side; a recessed portion located between the first linear portion and the protruding portion and recessed in a direction away from the first side; The display device has

2. The side of the protrusion has a second straight line portion perpendicular to the first side. The display device according to claim 1 .

3. The recess has a plurality of third linear portions, Among the first straight line portion, the second straight line portion, and the plurality of third straight line portions, two adjacent straight line portions form an obtuse angle. The display device according to claim 2 .

4. Among the first straight line portion, the second straight line portion, and the plurality of third straight line portions, two adjacent straight line portions are connected by an arc-shaped curved portion. The display device according to claim 3 .

5. The rib layer has a first slit overlapping with the protrusion. The display device according to claim 1 .

6. The first slit surrounds the display area. The display device according to claim 5 .

7. the organic insulating layer has a groove overlapping with the first slit; The display device according to claim 5 .

8. An edge of the rib layer along the first slit protrudes above the groove. The display device according to claim 7.

9. Each of the plurality of display elements is A lower electrode; an upper electrode located above the lower electrode; an organic layer located between the lower electrode and the upper electrode, the organic layer emitting light in response to application of a voltage; Including, The display device according to claim 5 .

10. a first partition disposed between adjacent display elements in the display region; a plurality of second partitions arranged around the first slit in the peripheral region; Further equipped with Each of the first partition wall and the second partition wall has a conductive lower portion disposed above the rib layer; an upper portion having an end portion protruding from a side surface of the lower portion; Including, The display device according to claim 9.

11. the upper electrode is in contact with the lower portion of the first partition wall; The display device according to claim 10.

12. At least one of the plurality of second partition walls is located above the protrusion. The display device according to claim 10.

13. the organic insulating layer has a pair of the protrusions, The first slits overlap with the pair of protruding portions, The display device according to claim 5 .

14. a terminal portion located between the display area and the second side and on which an electronic component can be mounted, The display device according to claim 13.

15. a wiring having one end connected to the terminal portion and the other end located on the first side, the wiring intersects the second side between the pair of protrusions in a plan view, The display device according to claim 14.

16. The rib layer further includes a second slit having a lattice shape located between the second side and the display area. The display device according to claim 5 .

17. a first partition disposed between adjacent display elements in the display region; a third partition disposed in a region surrounded by the second slit in the peripheral region; Further equipped with Each of the first partition wall and the third partition wall has a conductive lower portion disposed above the rib layer; an upper portion having an end portion protruding from a side surface of the lower portion; Including, The display device according to claim 16.

18. The third partition has an opening. The display device according to claim 17.

19. Further comprising an alignment mark overlapping the second side. The display device according to claim 5 .

20. The first slit is bent along an alignment mark.

20. The display device according to claim 19.

Images