Nitride semiconductor device

Abstract

To reduce an on-resistance while maintaining a gate-drain breakdown voltage, in a bidirectional switch.SOLUTION: A nitride semiconductor device 10 includes a bidirectional switch 12. The bidirectional switch 12 includes a semiconductor substrate 40, a first nitride semiconductor layer 42, a second nitride semiconductor layer 44 having a bandgap larger than that of the first nitride semiconductor layer 42, a first drain electrode 28 and a second drain electrode 30 which contact the second nitride semiconductor layer 44, a third nitride semiconductor layer 50 containing acceptor-type impurities, and a gate electrode 26 located above the third nitride semiconductor layer 50. The third nitride semiconductor layer 50 includes a ridge part 54 contacting the gate electrode 26 and an extension part 56 thinner than the ridge part 54. The extension part 56 includes a first extension region 56A extending from the ridge part 54 toward the first drain electrode 28, and a second extension region 56b extending from the ridge part 54 toward the second drain electrode 30.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) and aluminum gallium nitride (AlGaN) are being commercialized. Patent Document 1 discloses an example of a normally-off HEMT using a nitride semiconductor.

[0003] In HEMTs, a two-dimensional electron gas (2DEG) formed near the heterojunction interface between an electron transport layer (e.g., a GaN layer) and an electron supply layer (e.g., an AlGaN layer) is used as a conductive path. In recent years, bidirectional switches using this HEMT structure have been proposed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73506

[0005] [overview] In bidirectional switches using a HEMT structure, it is desirable to reduce the on-resistance while maintaining the breakdown voltage.

[0006] A nitride semiconductor device according to one embodiment of the present disclosure includes a bidirectional switch. The bidirectional switch includes a semiconductor substrate, a first nitride semiconductor layer located above the semiconductor substrate, a second nitride semiconductor layer located on the first nitride semiconductor layer and having a bandgap larger than that of the first nitride semiconductor layer, first and second drain electrodes in contact with the second nitride semiconductor layer, a third nitride semiconductor layer located on the second nitride semiconductor layer between the first and second drain electrodes and containing acceptor-type impurities, and a gate electrode located on the third nitride semiconductor layer. The third nitride semiconductor layer includes a ridge portion located on the second nitride semiconductor layer and in contact with the gate electrode, and an extension portion located on the second nitride semiconductor layer and thinner than the ridge portion. The extension portion includes a first extension region extending from the ridge portion toward the first drain electrode and a second extension region extending from the ridge portion toward the second drain electrode.

[0007] Other features and aspects will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device including a bidirectional switch according to a first embodiment. [Figure 2] FIG. 2 is a schematic plan view illustrating an exemplary interconnect structure below the pads of the nitride semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic plan view showing the planar layout of the bidirectional switch according to the first embodiment. [Figure 4] FIG. 4 is an enlarged view of a portion of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the bidirectional switch according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view of a bidirectional switch according to the second embodiment. [Figure 7]FIG. 7 is a conceptual diagram of a bidirectional switch for explaining the influence on the breakdown voltage of a pn junction formed when a p-type semiconductor substrate is used. [Figure 8] FIG. 8 is a schematic cross-sectional view of a bidirectional switch according to a first modified example. [Figure 9] FIG. 9 is a schematic cross-sectional view of a bidirectional switch according to a second modification.

[0009] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0010] The following detailed description provides a comprehensive understanding of the described methods, devices, and / or systems. Modifications and equivalents of the described methods, devices, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a particular order, the order of operations is illustrative and may be changed as would be apparent to one skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. Example embodiments may have different forms and are not limited to the described examples.

[0011] First Embodiment (Schematic structure of nitride semiconductor device) An exemplary nitride semiconductor device 10 including a bidirectional switch according to a first embodiment will be described with reference to FIGS. 1 to 5. The nitride semiconductor device 10 may be configured as a semiconductor chip on which a bidirectional switch 12 is formed. FIG. 1 is a schematic plan view of the nitride semiconductor device 10. FIG. 2 is a schematic plan view showing an exemplary wiring structure below pads (e.g., gate pad 14, first drain pad 16, second drain pad 18, etc.) of the nitride semiconductor device 10 of FIG. 1. FIG. 3 is a schematic plan view showing the planar layout of the bidirectional switch 12. FIG. 4 is an enlarged view of a portion of FIG. 3. FIG. 5 is a schematic cross-sectional view of the bidirectional switch 12 taken along line F5-F5 in FIG. 4.

[0012] 1 to 5, the Z-axis direction of the mutually orthogonal X, Y, and Z axes is a direction that intersects (e.g., is perpendicular to) the surface of the semiconductor substrate 40 (see FIG. 5). As used herein, the term "plan view" refers to viewing the nitride semiconductor device 10 from above along the Z-axis direction, unless explicitly stated otherwise. In the present disclosure, the Y-axis direction may be referred to as the first direction, and the X-axis direction may be referred to as the second direction.

[0013] 1, the nitride semiconductor device 10 may include a gate pad 14, a first drain pad 16, and a second drain pad 18 formed on an upper surface 10A that is rectangular in plan view. The gate pad 14, the first drain pad 16, and the second drain pad 18 may be electrically connected to a gate electrode, a first drain electrode, and a second drain electrode (e.g., the gate electrode 26, the first drain electrode 28, and the second drain electrode 30 shown in FIGS. 3 to 5 ), respectively, of a bidirectional switch 12 formed in the nitride semiconductor device 10. The gate pad 14, the first drain pad 16, and the second drain pad 18 can be used for external connection of the nitride semiconductor device 10.

[0014] The gate pad 14 may be disposed near a corner of the top surface 10A of the nitride semiconductor device 10. The first drain pad 16 and the second drain pad 18 may be disposed spaced apart from each other in the Y-axis direction.

[0015] The gate pad 14, the first drain pad 16, and the second drain pad 18 may be formed of any conductive material. It should be understood that the layout of the nitride semiconductor device 10 shown in FIG. 1 is an example, and that different layouts may be employed depending on the desired design of the nitride semiconductor device 10.

[0016] 2, the nitride semiconductor device 10 may further include a gate wiring 20, a first drain wiring 22, and a second drain wiring 24 located below the gate pad 14, the first drain pad 16, and the second drain pad 18. An insulating layer (not shown) may be disposed between the gate wiring 20, the first drain wiring 22, and the second drain wiring 24 and the gate pad 14, the first drain pad 16, and the second drain pad 18.

[0017] The gate wiring 20 may at least partially overlap the gate pad 14 in a plan view. The gate wiring 20 is electrically connected to the gate pad 14, for example, via one or more vias (not shown). The first drain wiring 22 may at least partially overlap the first drain pad 16 in a plan view. The first drain wiring 22 is electrically connected to the first drain pad 16, for example, via one or more vias (not shown). The second drain wiring 24 may at least partially overlap the second drain pad 18 in a plan view. The second drain wiring 24 is electrically connected to the second drain pad 18, for example, via one or more vias (not shown).

[0018] 2, the nitride semiconductor device 10 includes a plurality of first drain wirings 22 and a plurality of second drain wirings 24. Each of the plurality of first drain wirings 22 may be arranged adjacent to at least one of the plurality of second drain wirings 24. The gate wiring 20 may extend so as to surround the plurality of first drain wirings 22 and the plurality of second drain wirings 24 in a plan view. The number of first drain wirings 22 and second drain wirings 24 can be determined appropriately depending on the desired design of the nitride semiconductor device 10.

[0019] (Structure of a two-way switch) Next, the structure of the bidirectional switch 12 will be described with reference to FIGS. 3, the bidirectional switch 12 includes a gate electrode 26, a first drain electrode 28, and a second drain electrode 30. The gate electrode 26, the first drain electrode 28, and the second drain electrode 30 may be located below the first drain wiring 22 and the second drain wiring 24. An insulating layer (not shown) may be disposed between the gate electrode 26, the first drain electrode 28, and the second drain electrode 30 and the first drain wiring 22 and the second drain wiring 24.

[0020] 3, the gate electrode 26, the first drain electrode 28, and the second drain electrode 30 extend in the X-axis direction. In a plan view, the gate electrode 26 is disposed between the first drain electrode 28 and the second drain electrode 30. The first drain electrode 28, the gate electrode 26, and the second drain electrode 30, which extend in the X-axis direction, may be aligned parallel to the Y-axis direction.

[0021] The unit structure of the bidirectional switch 12 includes a first drain electrode 28, a gate electrode 26, and a second drain electrode 30. In the nitride semiconductor device 10, this unit structure may be repeatedly arranged in the Y-axis direction. In this case, the first drain electrode 28 or the second drain electrode 30 may be shared by two unit structures adjacent to each other in the Y-axis direction.

[0022] The gate electrode 26 included in each unit structure may be connected to a gate electrode connection portion 32 extending in the Y-axis direction at the center of the nitride semiconductor device 10. The gate electrode connection portion 32 may be arranged so as to overlap with the gate wiring 20 in a plan view.

[0023] 4 is an enlarged view of the region indicated by F4 in FIG. 3. The gate electrode connection portion 32 is connected to the gate wiring 20 by at least one gate connection via 34. Therefore, the gate electrode 26 is electrically connected to the gate wiring 20. The first drain electrode 28 is connected to the first drain wiring 22 by at least one first drain connection via 36. The second drain electrode 30 is connected to the second drain wiring 24 by at least one second drain connection via 38. The number and arrangement of the vias 34, 36, 38 can be determined appropriately depending on the desired design of the nitride semiconductor device 10, and are not limited to the example shown in the figure.

[0024] FIG. 5 is a schematic cross-sectional view of the bidirectional switch 12 taken along line F5-F5 in FIG. 4. For simplification, the upper wiring structure is omitted from FIG. 5. As shown in FIG. 5, the bidirectional switch 12 includes a semiconductor substrate 40, a first nitride semiconductor layer 42 located above the semiconductor substrate 40, and a second nitride semiconductor layer 44 located on the first nitride semiconductor layer 42. The first nitride semiconductor layer 42 and the second nitride semiconductor layer 44 can also be referred to as an electron transit layer and an electron supply layer, respectively. The bidirectional switch 12 may further include a buffer layer 46 located between the semiconductor substrate 40 and the first nitride semiconductor layer 42.

[0025] The semiconductor substrate 40 may be n-type. The semiconductor substrate 40 may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 40 may be an n-type Si substrate. The thickness of the semiconductor substrate 40 may be, for example, not less than 100 μm and not more than 1500 μm. The semiconductor substrate 40 may be electrically connected to the first drain electrode 28. In another example, the semiconductor substrate 40 may be p-type.

[0026] The buffer layer 46 may include one or more nitride semiconductor layers. The buffer layer 46 may be made of any material capable of reducing warping or cracking of the nitride semiconductor device 10 due to differences in thermal expansion coefficients between the semiconductor substrate 40 and layers formed on the buffer layer 46 (e.g., the first nitride semiconductor layer 42, etc.). For example, the buffer layer 46 may include at least one of an aluminum nitride (AlN) layer, an AlGaN layer, and a graded AlGaN layer having a different aluminum (Al) composition. For example, the buffer layer 46 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0027] In one example, the buffer layer 46 may include a first buffer layer that is an AlN layer formed on the semiconductor substrate 40, and a second buffer layer that is an AlGaN layer formed on the AlN layer. The first buffer layer may be an AlN layer having a thickness of, for example, 100 nm to 300 nm, while the second buffer layer may include multiple AlGaN layers with different compositions, each having a thickness of 100 nm to 300 nm. Note that, in order to reduce leakage current in the buffer layer 46, impurities may be introduced into a portion of the buffer layer 46 to make the buffer layer 46 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0028] The first nitride semiconductor layer 42 may be located on the buffer layer 46. In this embodiment, the first nitride semiconductor layer 42 may be a GaN layer. The thickness of the first nitride semiconductor layer 42 may be, for example, 0.5 μm or more and 2 μm or less. In order to reduce leakage current in the first nitride semiconductor layer 42, impurities may be introduced into a part of the first nitride semiconductor layer 42 to make the first nitride semiconductor layer 42 semi-insulating except for the surface region thereof. In this case, the impurity may be, for example, C. The impurity concentration in the first nitride semiconductor layer 42 may be, for example, 4×10 16 cm -3 It can be more than that.

[0029] That is, the first nitride semiconductor layer 42 may include multiple GaN layers with different impurity concentrations, for example, a C-doped GaN layer and a non-doped GaN layer. In this case, the C-doped GaN layer may be in contact with the buffer layer 46. The C-doped GaN layer may have a thickness of 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be 5×10 17 cm -3 Over 9 x 10 19 cm -3 The undoped GaN layer may be formed on the C-doped GaN layer and have a thickness of 0.05 μm or more and 0.4 μm or less. The undoped GaN layer may be in contact with the second nitride semiconductor layer 44. In one example, the first nitride semiconductor layer 42 may include a C-doped GaN layer having a thickness of 0.4 μm and an undoped GaN layer having a thickness of 0.4 μm. The C concentration in the C-doped GaN layer may be about 2×10 19 cm -3 It may be.

[0030] The second nitride semiconductor layer 44 has a larger bandgap than the first nitride semiconductor layer 42. In this embodiment, the second nitride semiconductor layer 44 may be an AlGaN layer. In one example, the second nitride semiconductor layer 44 is an AlGaN layer. x Ga 1-xIt is composed of N, where 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The second nitride semiconductor layer 44 may have a thickness of 5 nm or more and 20 nm or less. In one example, the second nitride semiconductor layer 44 may have a thickness of 8 nm or more.

[0031] The first nitride semiconductor layer 42 (e.g., GaN layer) and the second nitride semiconductor layer 44 (e.g., AlGaN layer) have different lattice constants from each other. Therefore, the first nitride semiconductor layer 42 and the second nitride semiconductor layer 44 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the first nitride semiconductor layer 42 and the second nitride semiconductor layer 44 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the first nitride semiconductor layer 42 near the hetero-junction interface becomes lower than the Fermi level. As a result, the 2DEG 48 spreads in the first nitride semiconductor layer 42 at a position close to the hetero-junction interface between the first nitride semiconductor layer 42 and the second nitride semiconductor layer 44 (e.g., within a range of about several nm from the interface). The 2DEG 48 in the first nitride semiconductor layer 42 functions as a channel of the bidirectional switch 12. The sheet carrier density of the 2DEG 48 generated in the first nitride semiconductor layer 42 can be increased by increasing at least one of the Al composition and the thickness of the second nitride semiconductor layer 44.

[0032] The bidirectional switch 12 further includes a third nitride semiconductor layer 50 located on the second nitride semiconductor layer 44. The third nitride semiconductor layer 50 can also be called a gate layer. The third nitride semiconductor layer 50 may be in contact with a part of the second nitride semiconductor layer 44. The third nitride semiconductor layer 50 includes a bottom surface 50B in contact with the second nitride semiconductor layer 44 and an upper surface 50A opposite to the bottom surface 50B. Details of the shape of the third nitride semiconductor layer 50 will be described later.

[0033] The third nitride semiconductor layer 50 contains acceptor-type impurities. In this embodiment, the third nitride semiconductor layer 50 may be a GaN layer doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the third nitride semiconductor layer 50 is 7×10 18 cm -3 More than 1×10 20 cm -3 It can be as follows:

[0034] 4 and 5, the gate electrode 26 is located on the third nitride semiconductor layer 50. More specifically, the gate electrode 26 may be in contact with an upper surface 50A of the third nitride semiconductor layer 50.

[0035] The gate electrode 26 may be composed of one or more metal layers. In one example, the gate electrode 26 may be composed of titanium nitride (TiN). In another example, the gate electrode 26 may include a first metal layer composed of Ti and a second metal layer composed of TiN provided on the first metal layer. The gate electrode 26 can form a Schottky junction with the third nitride semiconductor layer 50. The thickness of the gate electrode 26 may be, for example, not less than 50 nm and not more than 200 nm.

[0036] The bidirectional switch 12 may further include a passivation layer 52 covering the second nitride semiconductor layer 44, the third nitride semiconductor layer 50, and the gate electrode 26. The passivation layer 52 has a first opening 52A and a second opening 52B that expose the second nitride semiconductor layer 44. In the example of FIG. 5 , the first opening 52A and the second opening 52B are spaced apart in the Y-axis direction. The gate electrode 26 and the third nitride semiconductor layer 50 are located between the first opening 52A and the second opening 52B in the Y-axis direction.

[0037] The passivation layer 52 may be formed of, for example, at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), aluminum oxide (AlO), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 52 may be, for example, 80 nm or more and 150 nm or less.

[0038] (First drain electrode and second drain electrode) The first drain electrode 28 and the second drain electrode 30 are spaced apart in the Y-axis direction in a plan view. The first drain electrode 28 and the second drain electrode 30 are in contact with the second nitride semiconductor layer 44. The third nitride semiconductor layer 50 is located on the second nitride semiconductor layer 44 between the first drain electrode 28 and the second drain electrode 30.

[0039] At least a portion of the first drain electrode 28 is filled in the first opening 52A of the passivation layer 52. Since the first opening 52A exposes the second nitride semiconductor layer 44, the first drain electrode 28 can come into contact with the second nitride semiconductor layer 44. Furthermore, at least a portion of the second drain electrode 30 is filled in the second opening 52B of the passivation layer 52. Since the second opening 52B exposes the second nitride semiconductor layer 44, the second drain electrode 30 can come into contact with the second nitride semiconductor layer 44.

[0040] The first drain electrode 28 can make ohmic contact with the 2DEG 48 immediately below the second nitride semiconductor layer 44, which is in contact with the first drain electrode 28. Similarly, the second drain electrode 30 can make ohmic contact with the 2DEG 48 immediately below the second nitride semiconductor layer 44, which is in contact with the second drain electrode 30.

[0041] In another example, the second nitride semiconductor layer 44 may have openings (not shown) that communicate with the first opening 52A and the second opening 52B of the passivation layer 52, respectively. The openings can expose the first nitride semiconductor layer 42. As a result, the first drain electrode 28 and the second drain electrode 30 can be in contact with the second nitride semiconductor layer 44 in the openings and also with the first nitride semiconductor layer 42 exposed by the openings.

[0042] The distance D1 between the first drain electrode 28 and the gate electrode 26 in the Y-axis direction may be equal to the distance D2 between the second drain electrode 30 and the gate electrode 26 in the Y-axis direction. Here, the distance D1 between the first drain electrode 28 and the gate electrode 26 may be the distance between the first drain electrode 28 filled in the first opening 52A and the gate electrode 26. Similarly, the distance D2 between the second drain electrode 30 and the gate electrode 26 may be the distance between the second drain electrode 30 filled in the second opening 52B and the gate electrode 26. In the present disclosure, two distances or dimensions being equal means that they are within a range of manufacturing variation (for example, ±20%).

[0043] The distance D1 may be, for example, less than 3.0 μm, less than 2.0 μm, less than 1.5 μm, or less than 1.0 μm. The distance D2 may be, for example, less than 3.0 μm, less than 2.0 μm, less than 1.5 μm, or less than 1.0 μm. In a preferred example, the distance D1 may be less than 1.5 μm, and the distance D2 may be less than 1.5 μm.

[0044] The first drain electrode 28 and the second drain electrode 30 may be formed of one or more metal layers (eg, any combination of a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and / or an AlCu layer, etc.).

[0045] (Cross-sectional shape of the third nitride semiconductor layer) 4 and 5, the third nitride semiconductor layer 50 is located on the second nitride semiconductor layer 44, between the first drain electrode 28 and the second drain electrode 30. The third nitride semiconductor layer 50 includes a ridge portion 54 located on the second nitride semiconductor layer 44 and in contact with the gate electrode 26, and an extension portion 56 located on the second nitride semiconductor layer 44 and thinner than the ridge portion 54. By providing the extension portion 56 around the bottom of the ridge portion 54, it is possible to alleviate electric field concentration near the end of the third nitride semiconductor layer 50 (for example, the lower corner of the ridge portion 54).

[0046] The ridge portion 54 may include the upper surface 50A of the third nitride semiconductor layer 50. As shown in FIG. 4, the extension portion 56 may extend outward from the ridge portion 54 in a plan view. The ridge portion 54 may be surrounded by the extension portion 56 and may be formed integrally with the extension portion 56. As shown in FIG. 5, the extension portion 56 is thinner than the ridge portion 54, and therefore is located lower than the upper surface 50A of the third nitride semiconductor layer 50 in the Z-axis direction. Due to the presence of the extension portion 56, the bottom surface 50B of the third nitride semiconductor layer 50 has a larger area than the upper surface 50A included in the ridge portion 54.

[0047] The ridge portion 54 corresponds to a relatively thick portion of the third nitride semiconductor layer 50. For example, the thickness of the ridge portion 54 may be not less than 50 nm and not more than 120 nm. On the other hand, the extension portion 56 may have a thickness that is not more than half the thickness of the ridge portion 54. For example, the thickness of the extension portion 56 may be not less than 10 nm and not more than 25 nm.

[0048] The extension portion 56 includes a first extension region 56A extending from the ridge portion 54 toward the first drain electrode 28, and a second extension region 56B extending from the ridge portion 54 toward the second drain electrode 30. The first extension region 56A may be a portion of the extension portion 56 located between the ridge portion 54 and the first drain electrode 28. Similarly, the second extension region 56B may be a portion of the extension portion 56 located between the ridge portion 54 and the second drain electrode 30.

[0049] The first extension region 56A extends from the ridge portion 54 toward the first opening 52A. The first extension region 56A partially covers the surface of the second nitride semiconductor layer 44 between the ridge portion 54 and the first opening 52A in a plan view. The first extension region 56A does not reach the first drain electrode 28 embedded in the first opening 52A.

[0050] The second extension region 56B extends from the ridge portion 54 toward the second opening 52B. The second extension region 56B partially covers the surface of the second nitride semiconductor layer 44 between the ridge portion 54 and the second opening 52B in a plan view. The second extension region 56B does not reach the second drain electrode 30 embedded in the second opening 52B.

[0051] 5, the first extension region 56A and the second extension region 56B extend in the Y-axis direction from the ridge portion 54 by equal lengths. That is, the length L1 of the first extension region 56A in the Y-axis direction is equal to the length L2 of the second extension region 56B in the Y-axis direction. The length L1 of the first extension region 56A in the Y-axis direction may be 0.1 μm or more and 0.3 μm or less. The length L2 of the second extension region 56B in the Y-axis direction may be 0.1 μm or more and 0.3 μm or less.

[0052] (Functions of nitride semiconductor devices) The operation of the nitride semiconductor device 10 including the bidirectional switch 12 according to this embodiment will now be described.

[0053] The bidirectional switch 12 includes a first drain electrode 28 and a second drain electrode 30 in contact with the second nitride semiconductor layer 44, a third nitride semiconductor layer 50 containing acceptor-type impurities and located between the first drain electrode 28 and the second drain electrode 30, and a gate electrode 26 located on the third nitride semiconductor layer 50.

[0054] When a voltage exceeding the gate threshold voltage is applied to the gate electrode 26 of the bidirectional switch 12, a channel is formed by the 2DEG 48 in the first nitride semiconductor layer 42. As a result, a current can flow between the first drain electrode 28 and the second drain electrode 30. Depending on the potentials of the first drain electrode 28 and the second drain electrode 30, the current can flow in a direction from the first drain electrode 28 to the second drain electrode 30 or in a direction from the second drain electrode 30 to the first drain electrode 28.

[0055] On the other hand, when a voltage lower than the gate threshold voltage is applied to the gate electrode 26 (including when no voltage is applied to the gate electrode 26), the 2DEG 48 is not formed in at least a part of the region of the first nitride semiconductor layer 42 located below the third nitride semiconductor layer 50. This is because the third nitride semiconductor layer 50 contains acceptor-type impurities, which raises the energy levels of the first nitride semiconductor layer 42 and the second nitride semiconductor layer 44, resulting in depletion of the 2DEG 48. This allows the bidirectional switch 12 to operate normally.

[0056] The third nitride semiconductor layer 50 includes a ridge portion 54 located on the second nitride semiconductor layer 44 and in contact with the gate electrode 26, and an extension portion 56 located on the second nitride semiconductor layer 44 and thinner than the ridge portion 54. The extension portion 56 includes a first extension region 56A extending from the ridge portion 54 toward the first drain electrode 28, and a second extension region 56B extending from the ridge portion 54 toward the second drain electrode 30.

[0057] The third nitride semiconductor layer 50 includes the first extension region 56A, which reduces the strength of the electric field between the gate electrode 26 and the first drain electrode 28 of the bidirectional switch 12. Similarly, the third nitride semiconductor layer 50 includes the second extension region 56B, which reduces the strength of the electric field between the gate electrode 26 and the second drain electrode 30 of the bidirectional switch 12. Therefore, by providing the bidirectional switch 12 with the first extension region 56A and the second extension region 56B, the gate-drain breakdown voltage of the bidirectional switch 12 can be improved.

[0058] Furthermore, since the first extension region 56A and the second extension region 56B are part of the third nitride semiconductor layer 50, it is easier to miniaturize the bidirectional switch compared to the case where a field plate made of metal or the like is separately provided in the bidirectional switch 12 to improve the breakdown voltage.

[0059] Therefore, according to this embodiment, it is possible to reduce the gate-drain dimension while maintaining the gate-drain breakdown voltage, and therefore the on-resistance of the bidirectional switch 12 can be reduced.

[0060] The nitride semiconductor device 10 of this embodiment has the following advantages. (1) The bidirectional switch 12 includes a first drain electrode 28 and a second drain electrode 30 in contact with the second nitride semiconductor layer 44, a third nitride semiconductor layer 50 located on the second nitride semiconductor layer 44 between the first drain electrode 28 and the second drain electrode 30, and a gate electrode 26 located on the third nitride semiconductor layer 50. The third nitride semiconductor layer 50 includes a ridge portion 54 located on the second nitride semiconductor layer 44 and in contact with the gate electrode 26, and an extension portion 56 located on the second nitride semiconductor layer 44 and thinner than the ridge portion 54. The extension portion 56 includes a first extension region 56A extending from the ridge portion 54 toward the first drain electrode 28 and a second extension region 56B extending from the ridge portion 54 toward the second drain electrode 30.

[0061] According to this configuration, the presence of the first extension region 56A and the second extension region 56B can reduce the strength of the electric field between the gate and the drain of the bidirectional switch 12. Therefore, it is possible to miniaturize the dimension between the gate and the drain while ensuring the withstand voltage between the gate and the drain, and ultimately to reduce the on-resistance of the bidirectional switch 12.

[0062] (2) The first drain electrode 28 and the second drain electrode 30 are spaced apart in a first direction in a planar view, and the first extension region 56A and the second extension region 56B may extend in the first direction by equal lengths from the ridge portion 54.

[0063] The bidirectional switch 12 has two extension regions 56A, 56B that extend symmetrically in the first direction with respect to the gate electrode 26. Therefore, the bidirectional switch 12 can achieve a uniform breakdown voltage in both directions.

[0064] (3) The first drain electrode 28 and the second drain electrode 30 are spaced apart in a first direction in a planar view, and the distance D1 between the first drain electrode 28 and the gate electrode 26 in the first direction may be equal to the distance D2 between the second drain electrode 30 and the gate electrode 26 in the first direction.

[0065] The bidirectional switch 12 has two drain electrodes 28 and 30 that are arranged symmetrically in the first direction with respect to the gate electrode 26. Therefore, the bidirectional switch 12 can achieve a uniform breakdown voltage in both directions.

[0066] (4) The first drain electrode 28 and the second drain electrode 30 are spaced apart in a first direction in a planar view, and the distance D1 between the first drain electrode 28 and the gate electrode 26 in the first direction may be less than 1.5 μm, and the distance D2 between the second drain electrode 30 and the gate electrode 26 in the first direction may be less than 1.5 μm.

[0067] In the bidirectional switch 12, the withstand voltage is improved by providing the first extension region 56A and the second extension region 56B, which are part of the third nitride semiconductor layer 50, so that the distances D1 and D2 can be made relatively small, which makes it easy to miniaturize the bidirectional switch 12.

[0068] (5) The thickness of the ridge portion 54 may be 50 nm or more and 120 nm or less, and the thickness of the extension portion 56 may be 10 nm or more and 25 nm or less. With this configuration, the withstand voltage of the bidirectional switch 12 can be improved while minimizing the increase in on-resistance due to the extension portion 56.

[0069] (6) The first drain electrode 28 and the second drain electrode 30 are spaced apart in the first direction in plan view, and the length L1 of the first extension region 56A in the first direction may be 0.1 μm or more and 0.3 μm or less, and the length L1 of the second extension region 56B in the first direction may be 0.1 μm or more and 0.3 μm or less. This configuration allows the bidirectional switch 12 to achieve both improved breakdown voltage and miniaturization.

[0070] Second Embodiment Next, with reference to FIGS. 6 and 7, a nitride semiconductor device 100 including an exemplary bidirectional switch 102 according to a second embodiment of the present disclosure will be described.

[0071] Fig. 6 is a schematic cross-sectional view of the bidirectional switch 102. In Fig. 6, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description of the same components as those in the first embodiment will be omitted.

[0072] The bidirectional switch 102 includes a semiconductor substrate 104. The semiconductor substrate 104 is p-type. The semiconductor substrate 104 may be formed of Si, SiC, GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 104 may be a p-type Si substrate. The thickness of the semiconductor substrate 104 may be, for example, 100 μm or more and 1500 μm or less. The semiconductor substrate 104 may be electrically connected to the first drain electrode 28. A buffer layer 46, a first nitride semiconductor layer 42, and a second nitride semiconductor layer 44, similar to those in the first embodiment, are formed on the semiconductor substrate 104.

[0073] 6, the third nitride semiconductor layer 50 includes a ridge portion 54 located on the second nitride semiconductor layer 44 and in contact with the gate electrode 26, and an extension portion 56 located on the second nitride semiconductor layer 44 and thinner than the ridge portion 54. The extension portion 56 includes a first extension region 56A extending from the ridge portion 54 toward the first drain electrode 28 and a second extension region 56B extending from the ridge portion 54 toward the second drain electrode 30. In the second embodiment, the second extension region 56B extends from the ridge portion 54 in the Y-axis direction by a length shorter than that of the first extension region 56A. That is, the length L2 of the second extension region 56B in the Y-axis direction is shorter than the length L1 of the first extension region 56A in the Y-axis direction.

[0074] 7 is a conceptual diagram of a bidirectional switch 150 for explaining the effect on the breakdown voltage of a pn junction formed when a p-type semiconductor substrate 104 is used. In FIG. 7, for ease of explanation, the buffer layer 46 and the first nitride semiconductor layer 42 formed on the semiconductor substrate 104 are shown as an integrated layer. The buffer layer 46 and the first nitride semiconductor layer 42 are n-type due to crystal defects or the like, even if they are not intentionally doped with n-type impurities. Therefore, the p-type semiconductor substrate and the n-type nitride semiconductor layer including the buffer layer 46 and the first nitride semiconductor layer 42 form a pn junction (indicated by a diode symbol in FIG. 7).

[0075] Here, the voltage applied to the first drain electrode 28 is designated as V1, and the voltage applied to the second drain electrode 30 is designated as V2. Since the first drain electrode 28 is electrically connected to the semiconductor substrate 104 via the electrode 152, in the following description, the voltage applied to the semiconductor substrate 104 is assumed to be approximately the same as the voltage V1.

[0076] For example, when +V volts is applied to the first drain electrode 28 and no voltage is applied to the second drain electrode 30 (V1=+V volts, V2=0 volts), the bidirectional switch 150 allows a current to flow in the direction from the first drain electrode 28 to the second drain electrode 30. At this time, the voltage applied to the semiconductor substrate 104 is +V volts and the voltage applied to the second drain electrode 30 is 0 volts, so that the pn junction below the second drain electrode 30 is forward biased. As a result, the depletion layer formed near the pn junction below the second drain electrode 30 narrows.

[0077] On the other hand, when no voltage is applied to the first drain electrode 28 and +V volts is applied to the second drain electrode 30 (V1=0 volts, V2=+V volts), the bidirectional switch 150 allows a current to flow in the direction from the second drain electrode 30 to the first drain electrode 28. At this time, the voltage applied to the semiconductor substrate 104 is 0 volts and the voltage applied to the second drain electrode 30 is +V volts, so the pn junction below the second drain electrode 30 is reverse biased. As a result, the depletion layer formed near the pn junction below the second drain electrode 30 expands.

[0078] When the depletion layer formed near the pn junction below the second drain electrode 30 expands, the strength of the electric field between the gate electrode 26 and the second drain electrode 30 of the bidirectional switch 150 is reduced. Therefore, when a current flows from the second drain electrode 30 to the first drain electrode 28, the withstand voltage of the bidirectional switch 150 is improved. On the other hand, when the depletion layer formed near the pn junction below the second drain electrode 30 narrows, the strength of the electric field between the gate electrode 26 and the second drain electrode 30 of the bidirectional switch 150 is not reduced. Therefore, when a current flows from the first drain electrode 28 to the second drain electrode 30, the withstand voltage of the bidirectional switch 150 is not improved. In this way, the bidirectional switch 150 including the p-type semiconductor substrate 104 can have different withstand voltages depending on the direction of the current.

[0079] In this embodiment, the withstand voltage of the bidirectional switch 102 when a current flows in a direction from the second drain electrode 30 to the first drain electrode 28 can be adjusted depending on the length of the second extension region 56B extending from the ridge portion 54. In the bidirectional switch 102, the second extension region 56B extends in the Y-axis direction from the ridge portion 54 by a length shorter than that of the first extension region 56A. Therefore, it is possible to reduce non-uniformity in the withstand voltage depending on the direction of the current, which can occur when a p-type semiconductor substrate 104 is used.

[0080] As described above, the nitride semiconductor device 100 of the second embodiment can achieve a uniform breakdown voltage in both directions in the bidirectional switch 102 including the p-type semiconductor substrate 104. In addition, the nitride semiconductor device 100 has advantages similar to the advantages (1) and (4) to (6) of the first embodiment.

[0081] <Example of change> The above embodiment can be modified as follows. A nitride semiconductor device 200 including an exemplary bidirectional switch 202 according to a first modified example will be described with reference to Fig. 8. In Fig. 8, the same components as those in the second embodiment are denoted by the same reference numerals. Further, detailed description of the same components as those in the second embodiment will be omitted.

[0082] As shown in FIG. 8 , the bidirectional switch 202 includes a p-type semiconductor substrate 104. Unlike the second embodiment, the bidirectional switch 202 has the first extension region 56A and the second extension region 56B, whose lengths L1 and L2 are equal. Instead, the bidirectional switch 202 has the second extension region 56A and the gate electrode 26, whose distance D2 in the Y-axis direction is smaller than the first drain electrode 28 and the gate electrode 26, whose distance D1 in the Y-axis direction is smaller than the first drain electrode 28 and the gate electrode 26. The withstand voltage of the bidirectional switch 202 when a current flows from the second drain electrode 30 to the first drain electrode 28 can be adjusted depending on the distance D2 between the second drain electrode 30 and the gate electrode 26. This reduces the non-uniformity of the withstand voltage depending on the current direction, which may occur when a p-type semiconductor substrate 104 is used.

[0083] As described above, according to the nitride semiconductor device 200 of the first modified example, a uniform breakdown voltage can be achieved in both directions in the bidirectional switch 202 including the p-type semiconductor substrate 104. In addition, the nitride semiconductor device 200 has advantages similar to the advantages (1) and (4) to (6) of the first embodiment.

[0084] A nitride semiconductor device 300 including an exemplary bidirectional switch 302 according to a second modified example will be described with reference to Fig. 9. In Fig. 9, the same components as those in the second embodiment are denoted by the same reference numerals. Further, detailed description of the same components as those in the second embodiment will be omitted.

[0085] As shown in FIG. 9 , the bidirectional switch 302 includes a p-type semiconductor substrate 104. In the bidirectional switch 302, as in the second embodiment, the length L2 of the second extension region 56B in the Y-axis direction is smaller than the length L1 of the first extension region 56A in the Y-axis direction. In addition, in the bidirectional switch 302, the distance D2 between the second drain electrode 30 and the gate electrode 26 in the Y-axis direction is smaller than the distance D1 between the first drain electrode 28 and the gate electrode 26 in the Y-axis direction. The withstand voltage of the bidirectional switch 302 when a current flows from the second drain electrode 30 to the first drain electrode 28 can be adjusted depending on the length of the second extension region 56B extending from the ridge portion 54 and the distance D2 between the second drain electrode 30 and the gate electrode 26. Therefore, non-uniformity in the withstand voltage depending on the direction of the current, which may occur when a p-type semiconductor substrate 104 is used, can be reduced.

[0086] As described above, according to the nitride semiconductor device 300 of the second modified example, a uniform breakdown voltage can be achieved in both directions in the bidirectional switch 302 including the p-type semiconductor substrate 104. In addition, the nitride semiconductor device 300 has advantages similar to the advantages (1) and (4) to (6) of the first embodiment.

[0087] In the first embodiment, the semiconductor substrate 40 is described as being electrically connected to the first drain electrode 28. However, in another example, the semiconductor substrate 40 may be selectively electrically connected to either the first drain electrode 28 or the second drain electrode 30. In this case, the nitride semiconductor device 10 may further include a control circuit (not shown) electrically connected to the semiconductor substrate 40, the first drain electrode 28, and the second drain electrode 30. The control circuit may be configured to selectively electrically connect the semiconductor substrate 40 to either the first drain electrode 28 or the second drain electrode 30. This allows the nitride semiconductor device 10 to switch which of the two drain electrodes 28, 30 is set to the same potential as the semiconductor substrate 40.

[0088] The control circuit may be formed in the chip on which the bidirectional switch 12 is formed (see FIG. 1 ), or may be formed in a chip different from the chip on which the bidirectional switch 12 is formed. When the control circuit is formed in the chip on which the bidirectional switch 12 is formed, the nitride semiconductor device 10 may be a system-on-chip (SoC) including the bidirectional switch 12 and the control circuit. When the control circuit is formed in a chip different from the chip on which the bidirectional switch 12 is formed, the nitride semiconductor device 10 may be a nitride semiconductor module including multiple chips.

[0089] A control circuit similar to the above-described control circuit can also be applied to the second embodiment, the first modified example, and the second modified example. That is, the nitride semiconductor device 100, 200, or 300 may further include a control circuit electrically connected to the semiconductor substrate 104, the first drain electrode 28, and the second drain electrode 30. The control circuit may be configured to selectively electrically connect the semiconductor substrate 104 to either the first drain electrode 28 or the second drain electrode 30.

[0090] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0091] The term "on" as used in this disclosure can mean both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0092] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0093] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0094] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0095] (Appendix 1) The bidirectional switch (12, 102, 202, 302) is provided, and the bidirectional switch (12, 102, 202, 302) a semiconductor substrate (40, 104); a first nitride semiconductor layer (42) located above the semiconductor substrate (40, 104); a second nitride semiconductor layer (44) located on the first nitride semiconductor layer (42) and having a band gap larger than that of the first nitride semiconductor layer (42); a first drain electrode (28) and a second drain electrode (30) in contact with the second nitride semiconductor layer (44); a third nitride semiconductor layer (50) located on the second nitride semiconductor layer (44) between the first drain electrode (28) and the second drain electrode (30), the third nitride semiconductor layer (50) containing acceptor-type impurities; a gate electrode (26) located on the third nitride semiconductor layer (50); Including, the third nitride semiconductor layer (50) includes a ridge portion (54) located on the second nitride semiconductor layer (44) and in contact with the gate electrode (26), and an extension portion (56) located on the second nitride semiconductor layer (44) and thinner than the ridge portion (54); The extension portion (56) includes a first extension region (56A) extending from the ridge portion (54) toward the first drain electrode (28), and a second extension region (56B) extending from the ridge portion (54) toward the second drain electrode (30).

[0096] (Appendix 2) The nitride semiconductor device according to claim 1, wherein the first drain electrode (28) and the second drain electrode (30) are spaced apart in a first direction in a planar view, and the first extension region (56A) and the second extension region (56B) extend in the first direction by equal lengths from the ridge portion (54).

[0097] (Appendix 3) 3. The nitride semiconductor device according to claim 1, wherein the semiconductor substrate (40) is an n-type, and the semiconductor substrate (40) is electrically connected to the first drain electrode (28).

[0098] (Appendix 4) The nitride semiconductor device according to claim 1, wherein the first drain electrode (28) and the second drain electrode (30) are spaced apart in a first direction in a planar view, and the second extension region (56B) extends from the ridge portion (54) in the first direction by a length shorter than that of the first extension region (56A).

[0099] (Appendix 5) 5. The nitride semiconductor device according to claim 1, wherein the semiconductor substrate (104) is p-type, and the semiconductor substrate (104) is electrically connected to the first drain electrode (28).

[0100] (Appendix 6) The nitride semiconductor device according to any one of appendixes 1 to 5, wherein the first drain electrode (28) and the second drain electrode (30) are spaced apart in a first direction in a planar view, and a distance (D1) between the first drain electrode (28) and the gate electrode (26) in the first direction is equal to a distance (D2) between the second drain electrode (30) and the gate electrode (26) in the first direction.

[0101] (Appendix 7) The nitride semiconductor device according to claim 2 or 4, wherein the first drain electrode (28) and the second drain electrode (30) are spaced apart in a first direction in a planar view, and a distance (D2) between the second drain electrode (30) and the gate electrode (26) in the first direction is smaller than a distance (D1) between the first drain electrode (28) and the gate electrode (26) in the first direction.

[0102] (Appendix 8) 8. The nitride semiconductor device according to claim 7, wherein the semiconductor substrate (104) is p-type, and the semiconductor substrate (104) is electrically connected to the first drain electrode (28).

[0103] (Appendix 9) The nitride semiconductor device according to any one of appendices 1 to 8, wherein the first drain electrode (28) and the second drain electrode (30) are spaced apart in a first direction in a planar view, a distance (D1) between the first drain electrode (28) and the gate electrode (26) in the first direction is less than 1.5 μm, and a distance (D2) between the second drain electrode (30) and the gate electrode (26) in the first direction is less than 1.5 μm.

[0104] (Appendix 10) 10. The nitride semiconductor device according to any one of claims 1 to 9, wherein the ridge portion (54) has a thickness of 50 nm or more and 120 nm or less, and the extension portion (56) has a thickness of 10 nm or more and 25 nm or less.

[0105] (Appendix 11) The nitride semiconductor device according to any one of Appendices 1 to 10, wherein the first drain electrode (28) and the second drain electrode (30) are spaced apart in a first direction in a planar view, the length (L1) of the first extension region (56A) in the first direction is not less than 0.1 μm and not more than 0.3 μm, and the length (L2) of the second extension region (56B) in the first direction is not less than 0.1 μm and not more than 0.3 μm.

[0106] (Appendix 12) a control circuit electrically connected to the semiconductor substrate (40; 104), the first drain electrode (28), and the second drain electrode (30); The nitride semiconductor device according to any one of appendices 1 to 11, wherein the control circuit is configured to selectively electrically connect the semiconductor substrate (40; 104) to either the first drain electrode (28) or the second drain electrode (30).

[0107] Various changes in form and detail may be made to the above-described examples without departing from the scope of the claims and their equivalents. The above-described examples are illustrative and not limiting. The description of a feature in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the sequential events are performed in a different order and / or if components within the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description, but by the claims and their equivalents. All variations within the scope of the claims and their equivalents are included herein. [Explanation of symbols]

[0108] 10, 100, 200, 300...Nitride semiconductor devices 10A…Top surface 12, 102, 150, 202, 302... Two-way switches 14...Gate pad 16...1st drain pad 18...Second drain pad 20...Gate wiring 22...First drain wiring 24...Second drain wiring 26...Gate electrode 28...First drain electrode 30...Second drain electrode 32...Gate electrode connection part 34…Gate connection via 36...First drain connection via 38...Second drain connection via 40,104...Semiconductor substrate 42...First nitride semiconductor layer 44...Second nitride semiconductor layer 46...Buffer layer 48...Two-dimensional electron gas (2DEG) 50...Third nitride semiconductor layer 52…Pathlon layer 52A…Opening 1 52B…Second opening 54…Ripbu 56…Yunzaibu 56A…1st extension area 56B…Second extension in the field 152…Electrode

Claims

1. a bidirectional switch, the bidirectional switch comprising: a semiconductor substrate; a first nitride semiconductor layer located above the semiconductor substrate; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first drain electrode and a second drain electrode in contact with the second nitride semiconductor layer; a third nitride semiconductor layer located on the second nitride semiconductor layer between the first drain electrode and the second drain electrode, the third nitride semiconductor layer including an acceptor-type impurity; a gate electrode located on the third nitride semiconductor layer; Including, the third nitride semiconductor layer includes a ridge portion located on the second nitride semiconductor layer and in contact with the gate electrode, and an extension portion located on the second nitride semiconductor layer and thinner than the ridge portion; the extension portion includes a first extension region extending from the ridge portion toward the first drain electrode, and a second extension region extending from the ridge portion toward the second drain electrode.

2. 2. The nitride semiconductor device according to claim 1, wherein the first drain electrode and the second drain electrode are spaced apart in a first direction in a plan view, and the first extension region and the second extension region extend in the first direction from the ridge portion by equal lengths.

3. The nitride semiconductor device according to claim 2 , wherein said semiconductor substrate is of n-type, and said semiconductor substrate is electrically connected to said first drain electrode.

4. 2. The nitride semiconductor device according to claim 1, wherein the first drain electrode and the second drain electrode are spaced apart in a first direction in a plan view, and the second extension region extends from the ridge portion in the first direction by a length shorter than that of the first extension region.

5. The nitride semiconductor device according to claim 4 , wherein said semiconductor substrate is of p-type, and said semiconductor substrate is electrically connected to said first drain electrode.

6. 6. The nitride semiconductor device according to claim 1, wherein the first drain electrode and the second drain electrode are spaced apart in a first direction in a planar view, and a distance between the first drain electrode and the gate electrode in the first direction is equal to a distance between the second drain electrode and the gate electrode in the first direction.

7. 5. The nitride semiconductor device according to claim 2, wherein the first drain electrode and the second drain electrode are spaced apart in a first direction in a plan view, and a distance between the second drain electrode and the gate electrode in the first direction is smaller than a distance between the first drain electrode and the gate electrode in the first direction.

8. The nitride semiconductor device according to claim 7 , wherein said semiconductor substrate is of p-type, and said semiconductor substrate is electrically connected to said first drain electrode.

9. 6. The nitride semiconductor device according to claim 1, wherein the first drain electrode and the second drain electrode are spaced apart in a first direction in a planar view, the distance between the first drain electrode and the gate electrode in the first direction is less than 1.5 μm, and the distance between the second drain electrode and the gate electrode in the first direction is less than 1.5 μm.

10. 6. The nitride semiconductor device according to claim 1, wherein the ridge portion has a thickness of 50 nm or more and 120 nm or less, and the extension portion has a thickness of 10 nm or more and 25 nm or less.

11. 6. The nitride semiconductor device according to claim 1, wherein the first drain electrode and the second drain electrode are spaced apart in a first direction in a planar view, the length of the first extension region in the first direction is 0.1 μm or more and 0.3 μm or less, and the length of the second extension region in the first direction is 0.1 μm or more and 0.3 μm or less.

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