Pseudo-random number generation device, pseudo-random number generation program, and pseudo-random number generation method

Abstract

To efficiently generate a floating-point pseudo-random number.SOLUTION: A first generation unit generates a first bit string that is random and has a bit length of a floating-point number. A second generation unit generates a second bit string that has the bit length of the first bit string, by using a predetermined sign bit, a predetermined bit string of an exponent part, and a bit string of a mantissa part included in the first bit string.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to pseudorandom number generation technology. [Background technology]

[0002] A Linear Feedback Shift Register (LFSR) is a shift register whose input bits are the exclusive OR (XOR) of a portion of the bit string that makes up its value. LFSRs are sometimes used to generate pseudorandom numbers.

[0003] As a method for generating pseudo-random numbers, a random number generation method for generating any M-sequence random number of K bits or less is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-352904 Summary of the Invention [Problem to be solved by the invention]

[0005] LFSR generates pseudorandom numbers by performing an operation called Xorshift, which is an operation that combines exclusive OR and bit shift, and is used to generate pseudorandom numbers with fixed-point numbers.

[0006] However, in recent AI (Artificial Intelligence) applications, floating-point random numbers are often used.

[0007] In addition, parallel computing systems including multiple processing elements (PEs) may use reconfigurable architectures such as CGRAs (Coarse Grained Reconfigurable Arrays) and systolic arrays. In reconfigurable architectures, PEs are interconnected by data paths to form a reconfigurable matrix. In such parallel computing systems, it is desirable to supply random floating-point numbers to each row or column of the reconfigurable matrix.

[0008] In one aspect, the present invention aims to efficiently generate pseudo-random floating-point numbers. [Means for solving the problem]

[0009] In one proposal, the pseudorandom number generator includes a first generator and a second generator. The first generator generates a random first bit string having the bit length of a floating-point number. The second generator generates a second bit string having the bit length of the first bit string using a predetermined sign bit, a predetermined bit string of an exponent, and a bit string of a mantissa included in the first bit string. [Effects of the Invention]

[0010] According to one aspect, pseudo-random floating-point numbers can be generated efficiently. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a functional configuration diagram of a pseudorandom number generation device according to an embodiment. [Figure 2] 10 is a flowchart of a random number generation process. [Figure 3] FIG. 2 is a hardware configuration diagram of a first pseudo-random number generation device. [Figure 4] FIG. 1 is a hardware configuration diagram of a first LFSR. [Figure 5] FIG. 10 is a hardware configuration diagram of a second LFSR. [Figure 6]FIG. 10 is a diagram illustrating the amount of hardware. [Figure 7] FIG. 10 is a diagram illustrating the distribution of pseudo-random numbers. [Figure 8] FIG. 10 is a hardware configuration diagram of a second pseudo-random number generation device. [Figure 9] FIG. 2 is a hardware configuration diagram of an information processing device. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings.

[0013] 1 shows an example of the functional configuration of a pseudorandom number generation device according to an embodiment. The pseudorandom number generation device 101 in FIG.

[0014] Fig. 2 is a flowchart showing an example of random number generation processing performed by the pseudorandom number generator 101 of Fig. 1. First, the first generation unit 111 generates a random first bit string having the bit length of a floating-point number (step 201). Next, the second generation unit 112 uses a predetermined sign bit, a predetermined bit string of the exponent part, and a bit string of the mantissa part included in the first bit string to generate a second bit string having the bit length of the first bit string (step 202).

[0015] The pseudorandom number generator 101 in FIG. 1 can efficiently generate floating-point pseudorandom numbers.

[0016] Fig. 3 shows an example of the hardware configuration of a first pseudorandom number generator. Pseudorandom number generator 301 in Fig. 3 corresponds to pseudorandom number generator 101 in Fig. 1 and generates pseudorandom floating-point numbers in the open interval (1.0; 2.0). Pseudorandom number generator 301 includes an LFSR 311, a mask circuit 312, and an adder circuit 313. LFSR 311, mask circuit 312, and adder circuit 313 are hardware components.

[0017] The LFSR 311 corresponds to the first generation unit 111 in FIG. 1, and the mask circuit 312 and the adder circuit 313 correspond to the second generation unit 112 in FIG.

[0018] The LFSR 311 stores a bit string having the bit length of a floating-point number and updates the bit string by Xorshift at a predetermined clock cycle. The LFSR 311 then outputs the updated bit string z to the mask circuit 312. The initial value (seed value) of the bit string is set by the user or an external device.

[0019] A different bit string can be generated for each clock cycle by using the LFSR 311. The updated bit string z is an example of a random first bit string.

[0020] Fig. 4 shows an example of the hardware configuration of the first LFSR 311. The LFSR 311 in Fig. 4 includes a shift register 411, an XOR circuit 412, an XOR circuit 413, and an XOR circuit 414. The shift register 411, the XOR circuit 412, the XOR circuit 413, and the XOR circuit 414 are hardware.

[0021] Shift register 411 stores a bit string having the bit length of a single-precision floating-point number defined by IEEE (Institute of Electrical and Electronics Engineers) 754. The bit length of a single-precision floating-point number is 32 bits. Of bits 0 to 31, bits 0 to 22 represent the mantissa, bits 23 to 30 represent the exponent, and bit 31 represents the sign.

[0022] The XOR circuit 412 outputs the exclusive OR of the bit value of bit 17 and the bit value of bit 31 of the shift register 411 to the XOR circuit 413. The XOR circuit 413 outputs the exclusive OR of the bit value of bit 13 of the shift register 411 and the output from the XOR circuit 412 to the XOR circuit 414.

[0023] The XOR circuit 414 outputs the exclusive OR of the bit value of bit 5 of the shift register 411 and the output from the XOR circuit 413 to bit 0 of the shift register 411. As a result, the bit value of bit i (i=0 to 30) before the update is shifted to bit i+1, and the shifted bits 0 to 31 are output as the bit string z.

[0024] The Xorshift performed by the LFSR 311 in FIG. 4 is described by, for example, the following equation.

[0025] z=z^z_13^z_17^z_5 (1)

[0026] z_i represents the bit value of bit i of the shift register 411, and "^" represents an exclusive OR.

[0027] The mask circuit 312 outputs the logical product P of the bit string z output from the LFSR 311 and the mask bit string M to the adder circuit 313. The value of each bit in the sign and exponent parts of the mask bit string M is logical 0, and the value of each bit in the mantissa part is logical 1. By generating the logical product P, the mask circuit 312 changes the value of each bit in the sign and exponent parts included in the bit string z to logical 0. The logical product P is an example of a third bit string, and the mask circuit 312 is an example of a change unit.

[0028] In the case of single-precision floating-point numbers, the mask bit string M is expressed by the following formula:

[0029] M=0000 0000 0111 1111 1111 1111 1111 1111 (2)

[0030] As an example, consider a bit string z as follows:

[0031] z=0100 1000 1111 0000 1110 1110 0000 0000 (3)

[0032] In this case, the logical product P is calculated by the following formula:

[0033] P=z&M =0000 0000 0111 0000 1110 1110 0000 0000 (4)

[0034] The adder circuit 313 adds a predetermined bit string L to the logical product P in floating-point format and outputs the addition result as a pseudo-random number R. The bit string L represents the endpoint 1.0 of the open interval (1.0; 2.0), and the value of each bit of the mantissa part of the bit string L is logical 0. By adding the bit string L to the logical product P, the adder circuit 313 replaces the sign and exponent part of the logical product P with the sign and exponent part of the bit string L.

[0035] The bit string L is an example of a fourth bit string, and the sign and exponent parts of the bit string L are an example of a bit string of a predetermined sign bit and a predetermined exponent part. The pseudorandom number R is an example of a second bit string, and the addition circuit 313 is an example of an addition unit.

[0036] In the case of single-precision floating-point numbers, the bit string L is expressed by the following formula:

[0037] L=0x3f800000 =0011 1111 1000 0000 0000 0000 0000 0000 (5)

[0038] When the logical product P is expressed by the formula (4), the pseudo-random number R is calculated by the following formula.

[0039] R=P+L =0011 1111 1111 0000 1110 1110 0000 0000 (6)

[0040] Fig. 5 shows an example of the hardware configuration of the second LFSR 311. The LFSR 311 in Fig. 5 includes a shift register 511, an XOR circuit 512, an XOR circuit 513, and an XOR circuit 514. The shift register 511, the XOR circuit 512, the XOR circuit 513, and the XOR circuit 514 are hardware components.

[0041] Shift register 511 stores a bit string having the bit length of a double-precision floating-point number defined by IEEE 754. The bit length of a double-precision floating-point number is 64 bits. Of bits 0 to 63, bits 0 to 51 represent the mantissa, bits 52 to 62 represent the exponent, and bit 63 represents the sign.

[0042] The XOR circuit 512 outputs the exclusive OR of the bit value of bit 17 and the bit value of bit 63 of the shift register 511 to the XOR circuit 513. The XOR circuit 513 outputs the exclusive OR of the bit value of bit 13 of the shift register 511 and the output from the XOR circuit 512 to the XOR circuit 514.

[0043] The XOR circuit 514 outputs the exclusive OR of the bit value of bit 7 of the shift register 511 and the output from the XOR circuit 513 to bit 0 of the shift register 511. As a result, the bit value of bit i (i=0 to 62) before the update is shifted to bit i+1, and bits 0 to 63 after the shift are output as the bit string z.

[0044] The Xorshift performed by the LFSR 311 in FIG. 5 is described by, for example, the following equation.

[0045] z=z^z_13^z_7^z_17 (7)

[0046] z_i represents the bit value of bit i of the shift register 511. In the case of double-precision floating-point numbers, the mask bit string M and the bit string L are expressed by the following equations.

[0047] M=0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 (8) L=0x3ff0000000000000 =0011 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 (9)

[0048] FIG. 6 shows an example of the amount of hardware required when the LFSR 311 in FIG. 4 is implemented using an FPGA (Field Programmable Gate Array). The number of LUTs (Lookup tables) used is 111, with a utilization rate of 0.11%. The number of FFs (flip-flops) used is 72, with a utilization rate of 0.04%. The operating clock period is 2.006 ns, and the clock frequency is 498.5 MHz. In this case, the LFSR 311 is implemented with an extremely small amount of hardware.

[0049] Figure 7 shows an example of the distribution of pseudorandom numbers generated using the hardware in Figure 6. In this example, one pseudorandom number is generated every 2.006 ns, for a total of 10,000 pseudorandom numbers. The horizontal axis represents the numerical value of the generated pseudorandom number, and the vertical axis represents the occurrence rate (%) of numbers falling within each numerical range. The open interval (1.0; 2.0) is divided into 10 numerical ranges with a width of 0.1.

[0050] The generated pseudorandom numbers are distributed almost uniformly across the 10 ranges, demonstrating sufficient randomness.

[0051] 3, pseudorandom numbers in the open interval (1.0; 2.0) can be efficiently generated using a small amount of hardware. Therefore, in a parallel computing system using a reconfigurable architecture such as a CGRA or a systolic array, the pseudorandom number generator 301 can be easily implemented for each row or column of a reconfigurable matrix.

[0052] The range of the generated pseudo-random numbers is not limited to the open interval (1.0;2.0) and may be specified by a user or an external device. As an example, a pseudo-random number generator that generates floating-point pseudo-random numbers in a specified open interval (a;b) will be described. a and b are real numbers, and a <bである。

[0053] Fig. 8 shows an example of the hardware configuration of a second pseudorandom number generation device. Pseudorandom number generation device 801 in Fig. 8 corresponds to pseudorandom number generation device 101 in Fig. 1, and has a configuration in which a subtraction circuit 811, a subtraction circuit 812, a multiplication circuit 813, and an addition circuit 814 are added to pseudorandom number generation device 301 in Fig. 3. The subtraction circuit 811, the subtraction circuit 812, the multiplication circuit 813, and the addition circuit 814 are hardware.

[0054] The adder circuit 313 outputs the addition result A of the logical product P and the bit string L to the subtracter circuit 811. The subtracter circuits 811, 812, multiplier circuit 813, and adder circuit 814 perform floating-point arithmetic as shown in the following equation to convert the pseudo-random number in the open interval (1.0;2.0) into the pseudo-random number R in the open interval (a;b).

[0055] R=a+(A-1.0)×((ba) / (2.0-1.0)) =a+(A-1.0)×(ba) (10)

[0056] The subtraction circuit 811 subtracts 1.0 from the addition result A in floating point format and outputs the subtraction result S1 to the multiplication circuit 813. The subtraction circuit 812 subtracts a from b in floating point format and outputs the subtraction result S2 to the multiplication circuit 813. The addition result A is an example of a fifth bit string.

[0057] The multiplication circuit 813 multiplies the subtraction result S1 by the subtraction result S2 in floating-point format and outputs the multiplication result U to the addition circuit 814. The addition circuit 814 adds a to the multiplication result U in floating-point format and outputs the addition result as a pseudo-random number R. The pseudo-random number R is an example of a second bit string, and the subtraction circuits 811, 812, multiplication circuit 813, and addition circuit 814 are examples of an arithmetic unit.

[0058] The pseudorandom number generator 801 in FIG. 8 can efficiently generate floating-point pseudorandom numbers in a specified open interval (a; b) using a small amount of hardware.

[0059] It is also possible to generate pseudorandom numbers using an information processing device (computer) instead of the pseudorandom number generation device 301 in FIG. 3 and the pseudorandom number generation device 801 in FIG.

[0060] Fig. 9 shows an example of the hardware configuration of an information processing device that operates as a pseudo-random number generator. The information processing device in Fig. 9 includes a CPU 901, a memory 902, an input device 903, an output device 904, an auxiliary storage device 905, a media drive device 906, and a network connection device 907. These components are hardware and are connected to each other via a bus 908.

[0061] The memory 902 is, for example, a semiconductor memory such as a read-only memory (ROM) or a random access memory (RAM), and stores programs and data used in processing. The memory 902 may store, as data, the bit string in the shift register 411 in Fig. 4 or the shift register 511 in Fig. 5.

[0062] The CPU 901 (processor) executes a program using the memory 902, for example, to perform processing similar to the operations of the LFSR 311, mask circuit 312, and adder circuit 313 in Figures 3 and 8. The CPU 901 executes a program using the memory 902, to perform processing similar to the operations of the subtractor circuit 811, subtractor circuit 812, multiplier circuit 813, and adder circuit 814 in Figure 8.

[0063] The CPU 901 executes a program using the memory 902 to perform processes similar to the operations of the shift register 411, the XOR circuit 412, the XOR circuit 413, and the XOR circuit 414 in Fig. 4. The CPU 901 executes a program using the memory 902 to perform processes similar to the operations of the shift register 511, the XOR circuit 512, the XOR circuit 513, and the XOR circuit 514 in Fig. 5.

[0064] The input device 903 is, for example, a keyboard, a pointing device, etc., and is used for inputting instructions or information from a user or operator. The output device 904 is, for example, a display device, a printer, a speaker, etc., and is used for outputting inquiries or processing results to a user or operator. The processing result may be a pseudorandom number R.

[0065] The auxiliary storage device 905 is, for example, a magnetic disk device, an optical disk device, a magneto-optical disk device, a tape device, etc. The auxiliary storage device 905 may be a hard disk drive or a solid state drive (SSD). The information processing device can store programs and data in the auxiliary storage device 905 and load them into the memory 902 for use.

[0066] The medium drive device 906 drives a portable recording medium 909 and accesses the recorded contents thereof. The portable recording medium 909 is a memory device, a flexible disk, an optical disk, a magneto-optical disk, etc. The portable recording medium 909 may be a CD-ROM (Compact Disk Read Only Memory), a DVD (Digital Versatile Disk), a USB (Universal Serial Bus) memory, etc. A user or operator can store programs and data in the portable recording medium 909 and load them into the memory 902 for use.

[0067] In this way, the computer-readable recording medium that stores the program and data used in the processing is a physical (non-transitory) recording medium such as the memory 902, the auxiliary storage device 905, or the portable recording medium 909.

[0068] The network connection device 907 is a communication device connected to a communication network such as a WAN (Wide Area Network) or a LAN (Local Area Network) and performs data conversion associated with communication. The information processing device receives programs and data from an external device via the network connection device 907 and loads them into the memory 902 for use.

[0069] The configurations of the pseudorandom number generator 101 in Fig. 1, the pseudorandom number generator 301 in Fig. 3, and the pseudorandom number generator 801 in Fig. 8 are merely examples, and some of the components may be omitted or changed depending on the application or conditions of the pseudorandom number generator. For example, the bit string z may be generated using another pseudorandom number generation circuit instead of the LFSR 311 in Fig. 3 and Fig. 8.

[0070] 4 and 5 are merely examples, and some of the components may be omitted or modified depending on the application or conditions of the pseudorandom number generator. For example, in LFSR 311 in Fig. 4, the bit values ​​of other bits in shift register 411 may be input to XOR circuit 412, XOR circuit 413, and XOR circuit 414. Also, in LFSR 311 in Fig. 5, the bit values ​​of other bits in shift register 511 may be input to XOR circuit 512, XOR circuit 513, and XOR circuit 514.

[0071] The flowchart in FIG. 2 is merely an example, and some of the processing may be omitted or changed depending on the application or conditions of the pseudorandom number generator.

[0072] The amount of hardware shown in Figure 6 and the distribution of pseudo-random numbers shown in Figure 7 are merely examples, and the amount of hardware of the pseudo-random number generator and the distribution of the generated pseudo-random numbers will vary depending on how the pseudo-random number generator is implemented.

[0073] 9 is merely an example, and some of the components may be omitted or changed depending on the application or conditions of the information processing device. For example, if an interface with a user or operator is not required, the input device 903 and the output device 904 may be omitted. If the portable recording medium 909 or a communication network is not used, the medium drive device 906 or the network connection device 907 may be omitted.

[0074] Equations (1) to (10) are merely examples, and the pseudorandom number generator may generate the pseudorandom number R based on another mathematical formula.

[0075] Although the disclosed embodiments and their advantages have been described in detail, those skilled in the art may make various modifications, additions, and omissions without departing from the scope of the invention as clearly set forth in the claims.

[0076] The following notes are further provided regarding the embodiment described with reference to FIGS. (Appendix 1) a first generator that generates a random first bit string having a bit length of a floating-point number; a second generator that generates a second bit string having the bit length using a predetermined sign bit, a predetermined bit string of an exponent part, and a bit string of a mantissa part included in the first bit string; A pseudorandom number generating device comprising: (Appendix 2) The second generation unit a modification unit that modifies the value of a sign bit and each bit of a bit string of an exponent part included in the first bit string to a logical value of 0, thereby generating a third bit string having the bit length from the first bit string; an adder that generates the second bit string by adding a fourth bit string including the predetermined sign bit, the predetermined bit string of the exponent part, and a predetermined bit string of the mantissa part to the third bit string; Including, 2. The pseudorandom number generating device according to claim 1, wherein the value of each bit included in the bit string of the predetermined mantissa is a logical value of 0. (Appendix 3) The second generation unit a modification unit that modifies the value of a sign bit and each bit of a bit string of an exponent part included in the first bit string to a logical value of 0, thereby generating a third bit string having the bit length from the first bit string; an adder that generates a fifth bit string having the bit length by adding a fourth bit string including the predetermined sign bit, the predetermined bit string of the exponent part, and a predetermined bit string of the mantissa part to the third bit string; a calculation unit that generates the second bit string by performing a floating-point calculation using the fifth bit string; Including, 2. The pseudorandom number generating device according to claim 1, wherein the value of each bit included in the bit string of the predetermined mantissa is a logical value of 0. (Appendix 4) 4. The pseudorandom number generator according to claim 1, wherein the first generation unit is a linear feedback shift register. (Appendix 5) generating a first random bit string having a bit length of a floating-point number; generating a second bit string having the bit length using a predetermined sign bit, a predetermined bit string of the exponent part, and a bit string of the mantissa part included in the first bit string; A pseudorandom number generating program that causes a computer to execute a process. (Appendix 6) The process of generating the third bit string includes: generating a third bit string having the bit length from the first bit string by changing the value of a sign bit and each bit of a bit string of an exponent part included in the first bit string to a logical value of 0; generating the second bit string by adding a fourth bit string including the predetermined sign bit, the predetermined bit string of the exponent part, and the predetermined bit string of the mantissa part to the third bit string; Including, The pseudorandom number generating program according to claim 5, wherein the value of each bit included in the bit string of the predetermined mantissa is a logical value of 0. (Appendix 7) The process of generating the third bit string includes: generating a third bit string having the bit length from the first bit string by changing the value of a sign bit and each bit of a bit string of an exponent part included in the first bit string to a logical value of 0; generating a fifth bit string having the bit length by adding a fourth bit string including the predetermined sign bit, the predetermined bit string of the exponent part, and the predetermined bit string of the mantissa part to the third bit string; generating the second bit string by performing a floating-point operation using the fifth bit string; Including, The pseudorandom number generating program according to claim 5, wherein the value of each bit included in the bit string of the predetermined mantissa is a logical value of 0. (Appendix 8) The pseudorandom number generator generating a first random bit string having a bit length of a floating-point number; generating a second bit string having the bit length using a predetermined sign bit, a predetermined bit string of the exponent part, and a bit string of the mantissa part included in the first bit string; A pseudorandom number generation method comprising: (Appendix 9) The process of generating the third bit string includes: generating a third bit string having the bit length from the first bit string by changing the value of a sign bit and each bit of a bit string of an exponent part included in the first bit string to a logical value of 0; generating the second bit string by adding a fourth bit string including the predetermined sign bit, the predetermined bit string of the exponent part, and the predetermined bit string of the mantissa part to the third bit string; Including, 9. The pseudorandom number generation method according to claim 8, wherein the value of each bit included in the bit string of the predetermined mantissa is a logical value of 0. (Appendix 10) The process of generating the third bit string includes: generating a third bit string having the bit length from the first bit string by changing the value of a sign bit and each bit of a bit string of an exponent part included in the first bit string to a logical value of 0; generating a fifth bit string having the bit length by adding a fourth bit string including the predetermined sign bit, the predetermined bit string of the exponent part, and the predetermined bit string of the mantissa part to the third bit string; generating the second bit string by performing a floating-point operation using the fifth bit string; Including, 9. The pseudorandom number generation method according to claim 8, wherein the value of each bit included in the bit string of the predetermined mantissa is a logical value of 0. [Explanation of symbols]

[0077] 101, 301, 801 pseudorandom number generator 111 1st generation part 112 Second generation part 311 LFSR 312 Mask Circuit 313, 814 Addition circuit 411, 511 shift registers 412~414, 512~514 XOR circuit 811, 812 Subtraction circuit 813 Multiplication Circuit 901 CPU 902 memory 903 Input Device 904 Output Device 905 Auxiliary storage device 906 Media drive unit 907 Network Connection Device 908 Bus 909 Portable recording media

Claims

1. a first generator that generates a random first bit string having a bit length of a floating-point number; a second generator that generates a second bit string having the bit length by using a predetermined sign bit, a predetermined bit string of an exponent part, and a bit string of a mantissa part included in the first bit string; A pseudorandom number generating device comprising:

2. The second generation unit a modification unit that modifies the value of a sign bit and each bit of a bit string of an exponent part included in the first bit string to a logical value of 0, thereby generating a third bit string having the bit length from the first bit string; an adder that generates the second bit string by adding a fourth bit string including the predetermined sign bit, the predetermined bit string of the exponent part, and a predetermined bit string of the mantissa part to the third bit string; Including, 2. The pseudorandom number generator according to claim 1, wherein the value of each bit included in the bit string of the predetermined mantissa is a logical value of 0.

3. The second generation unit a modification unit that modifies the value of a sign bit and each bit of a bit string of an exponent part included in the first bit string to a logical value of 0, thereby generating a third bit string having the bit length from the first bit string; an adder that generates a fifth bit string having the bit length by adding a fourth bit string including the predetermined sign bit, the predetermined bit string of the exponent part, and a predetermined bit string of the mantissa part to the third bit string; a calculation unit that generates the second bit string by performing a floating-point calculation using the fifth bit string; Including, 2. The pseudorandom number generator according to claim 1, wherein the value of each bit included in the bit string of the predetermined mantissa is a logical value of 0.

4. 4. The pseudorandom number generator according to claim 1, wherein the first generator is a linear feedback shift register.

5. generating a random first bit string having a bit length of a floating-point number; generating a second bit string having the bit length using a predetermined sign bit, a predetermined bit string of the exponent part, and a bit string of the mantissa part included in the first bit string; A pseudorandom number generating program that causes a computer to execute a process.

6. The pseudorandom number generator generating a random first bit string having a bit length of a floating-point number; generating a second bit string having the bit length using a predetermined sign bit, a predetermined bit string of the exponent part, and a bit string of the mantissa part included in the first bit string; A pseudorandom number generation method comprising:

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